JP2005140770A - Semiconductor testing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing circuit which can easily perform expected value comparison at the time of a monitoring operation, without making the stress decrease, at the burn-in time, and moreover, can decrease the number of necessary I/O terminals at the burn-in. <P>SOLUTION: A scan operating control signal for controlling the scanning operation, scan data for test, and a standard clock are supplied to a scan-designed semiconductor circuit. In the semiconductor test circuit, which performs the monitoring operation of an output of a final stage in a scan chain at the burn-in test, a scan shift operation and a scan-capturing operation are performed alternatively at the time of the burn-in, based on a monitoring control signal and a monitoring control signal input terminal which inputs the monitoring control signal which shows whether the monitoring operation is carried out from outside of the semiconductor test circuit. At monitoring of operation, a scan operation control signal selection output circuit, which outputs the scan operation control signal so that the scan shift operation is to be performed, is prepared. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor test circuit, and more particularly to a burn-in test.

  A conventional scan-designed semiconductor circuit inputs periodic scan data during a burn-in test and compares the output of the last stage of the scan chain with an expected value to determine whether to apply stress in the burn-in test. (For example, refer to Patent Document 1).

  In some cases, scan data is shared by each scan chain and a limited I / O terminal is effectively used (see, for example, Patent Document 2).

FIG. 9 shows a conventional semiconductor test circuit.
In FIG. 9, 900 is a conventional semiconductor test circuit, 910 is a scan-designed semiconductor circuit to be burn-in tested, 901 is a scan operation control signal input terminal for inputting a scan operation control signal for controlling the scan operation, and 902 is A reference clock input terminal for inputting a reference clock, 903 is a scan data input terminal for inputting scan data, 904 is a monitor control signal input terminal for inputting a monitor control signal indicating whether to monitor, 907 is based on the monitor control signal 905 is a monitor signal output terminal for outputting a monitor signal, and 905 is a monitor signal output terminal for outputting the output of the monitor signal output unit 907 from the semiconductor test circuit 900 to the outside.

The operation will be described below.
First, scan operation control is performed from a burn-in device (not shown) outside the semiconductor test circuit 900 via a scan operation control signal input terminal 901, a reference clock input terminal 902, a scan data input terminal 903, and a monitor control signal input terminal 904, respectively. A signal, a reference clock, scan data, and a monitor control signal are input, and stress is applied to the scan-designed semiconductor circuit 910.

The monitor signal output from the monitor signal output unit 907 via the monitor signal output terminal 905 is compared with a predetermined expected value by a burn-in device (not shown), and the quality of the scan-designed semiconductor circuit 910 is determined. The
JP 2001-183425 A Japanese Patent Laid-Open No. 2001-42010

  However, the conventional semiconductor test circuit requires five or more I / O terminals at the time of burn-in test, but it is necessary to reduce the number of I / O terminals due to rationalization of the semiconductor circuit and restrictions on the burn-in device. When the number of I / O terminals is reduced, the synchronization signal with the burn-in device is reduced. Therefore, the monitor signal at the time of monitoring becomes asynchronous with the burn-in device, and is necessary for determining the quality of the semiconductor circuit. There was a problem that it was difficult to compare the expected values.

  The present invention has been made to solve the above-mentioned conventional problems, and can reduce the number of I / O terminals required at the time of burn-in and monitor without reducing the stress at the time of burn-in. An object of the present invention is to provide a semiconductor test circuit capable of easily comparing expected values at the time.

  According to a first aspect of the present invention, a semiconductor test circuit supplies a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit, so that a final scan chain can be obtained. In a semiconductor test circuit performing a burn-in test for monitoring the output of the stage, based on the monitor control signal input terminal for inputting a monitor control signal indicating whether to monitor from the outside of the semiconductor test circuit, and the monitor control signal, A scan operation control signal selection output circuit is provided for outputting the scan operation control signal so that a scan shift operation and a scan capture operation are alternately performed at the time of burn-in and a scan shift operation is performed at the time of monitoring.

  A semiconductor test circuit according to a second aspect of the present invention is the semiconductor test circuit according to the first aspect, wherein the reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit and the reference clock are divided. And a frequency divider that outputs the scan data.

  A semiconductor test circuit according to a third aspect of the present invention is the semiconductor test circuit according to the first aspect, wherein a reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit, and the reference clock as an input, The scan data includes a scan data generator that alternately outputs different frequency divisions.

  According to a fourth aspect of the present invention, a semiconductor test circuit supplies a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit, so that a final scan chain can be obtained. In a semiconductor test circuit performing a burn-in test for monitoring the output of a stage, a reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit and a period for performing a scan shift operation based on the reference clock are determined. A scan shift period determining circuit for outputting a selection signal for selecting whether to perform a scan shift operation or a scan capture operation, and a scan operation control signal selection for outputting the scan operation control signal based on the selection signal And an output circuit.

  According to a fifth aspect of the present invention, a semiconductor test circuit supplies a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit, so that a final scan chain is obtained. In a semiconductor test circuit performing a burn-in test for monitoring the output of a stage, a monitor control signal input terminal for inputting a monitor control signal indicating whether or not to monitor from the outside of the semiconductor test circuit, and using the monitor control signal as a reset And a scan operation control signal output circuit for outputting the scan operation control signal.

  A semiconductor test circuit according to a sixth aspect of the present invention is the semiconductor test circuit according to the first aspect, wherein the monitor control signal is input, the scan indefinite period mask circuit is output, and the scan indefinite period mask circuit is output. And a monitor signal output unit that outputs a monitor signal from the scan-designed semiconductor circuit based on the output of the indefinite period mask circuit.

  A semiconductor test circuit according to a seventh aspect of the present invention is the semiconductor test circuit according to the first aspect, further comprising an oscillator that oscillates the reference clock.

  A semiconductor test circuit according to an eighth aspect of the present invention is the semiconductor test circuit according to the seventh aspect, further comprising a frequency divider that divides a reference clock oscillated by the oscillator and outputs the frequency as the scan data. is there.

  A semiconductor test circuit according to a ninth aspect of the present invention is the semiconductor test circuit according to the seventh aspect, further comprising an oscillation control circuit for controlling an oscillation frequency of the oscillator.

  A semiconductor test circuit according to the present invention supplies a scan operation control signal for controlling a scan operation, scan data for testing, and a reference clock to a scan-designed semiconductor circuit, and outputs the final stage of the scan chain. In a semiconductor test circuit that performs a burn-in test to be monitored, a scan operation control signal is internally supplied by the semiconductor test circuit, and during burn-in, a scan shift operation and a scan capture operation are alternately performed to apply stress to the semiconductor circuit. Since the scan output of the scan shift operation synchronized with the burn-in device is output as a monitor signal at the time of monitoring, the number of I / O terminals required at the time of burn-in can be reduced, and the stress at the time of burn-in can be reduced. Easily compare expected values when monitoring There is an effect that theft can be.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram showing a semiconductor test circuit according to the first embodiment.
In FIG. 1, 100 is a semiconductor test circuit according to the first embodiment, and 110 is a scan-designed semiconductor circuit to be burn-in tested.

  Reference numeral 2 is a reference clock input terminal for inputting a reference clock, 3 is a scan data input terminal for inputting scan data, 4 is a monitor control signal input terminal for inputting a monitor control signal indicating whether or not to monitor, and 6 is a monitor. Based on the control signal, the scan shift operation and scan capture operation are alternately switched during burn-in, and the scan operation is selected so that the scan shift operation is performed during monitoring. A circuit, 7 is a monitor signal output unit for outputting a monitor signal based on the monitor control signal, and 5 is a monitor signal output terminal for outputting the output of the monitor signal output unit 7 from the semiconductor test circuit 100 to the outside.

The operation will be described below.
First, at the time of burn-in, from a burn-in device (not shown) outside the semiconductor test circuit 100, the reference clock is input to the reference clock input terminal 2, the scan data is not monitored to the scan data input terminal 3, and the monitor control signal input terminal 4 is not monitored. A monitor control signal indicating this is supplied. At this time, the scan operation control signal selection output circuit 6 selectively outputs the scan operation control signal so that the scan shift operation and the scan capture operation are alternately switched. Here, the scan operation control signal selection output circuit 6 is a frequency divider that receives, for example, a reference clock, and uses a frequency-divided output having a period equal to or greater than the number of scan flip-flops. If the initial state of the frequency divider is not uniformly determined, the frequency-divided output is an asynchronous signal with the burn-in device, but there is no particular problem during burn-in.

  Next, at the time of monitoring for determining pass / fail of the scan designed semiconductor circuit 110, it indicates that the monitor control signal supplied from the monitor control signal input terminal 4 is monitored. At this time, the scan operation control signal selection output circuit 6 selectively outputs the scan operation control signal so that the scan shift operation is performed. Since the scan operation is fixed at the scan shift, the monitor signal output from the monitor signal output unit 7 becomes a signal synchronized with a burn-in device (not shown), and this monitor signal is output via the monitor signal output terminal 5. The burn-in apparatus that does not perform comparison with a predetermined expected value determines whether the scan-designed semiconductor circuit 110 is good or bad.

  As described above, the semiconductor test circuit according to the first embodiment supplies the scan operation control signal internally to the semiconductor test circuit, and alternately performs the scan shift operation and the scan capture operation at the time of burn-in. Since the stress is applied and the scan output of the scan shift operation synchronized with the burn-in device is output as the monitor signal at the time of monitoring, the number of I / O terminals required at the time of burn-in can be reduced and the stress at the time of burn-in The expected value at the time of monitoring can be easily compared without lowering.

(Embodiment 2)
FIG. 2 is a diagram showing a semiconductor test circuit according to the second embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 2, reference numeral 200 denotes a semiconductor test circuit according to the second embodiment, and reference numeral 8 denotes a frequency divider that divides and outputs a reference clock supplied to the reference clock input terminal 2.

The operation will be described below.
At the time of burn-in, a reference clock is supplied to the reference clock input terminal 2 and a monitor control signal indicating that monitoring is not performed to the monitor control signal input terminal 4 from a burn-in device (not shown) outside the semiconductor test circuit 200. At this time, the scan data is supplied by the frequency divider 8. The frequency divider 8 has a reference clock as an input, and its initial state is determined uniformly. For example, the frequency divider 8 divides the reference clock by four.
Other operations are the same as those in the first embodiment.

  As described above, since the semiconductor test circuit according to the second embodiment internally supplies the scan operation control signal and the scan data by the semiconductor test circuit, the scan operation control signal and the scan data from outside the semiconductor test circuit. Stress is applied to the semiconductor circuit without receiving supply, and the number of I / O terminals required at the time of burn-in can be reduced.

(Embodiment 3)
FIG. 3 is a diagram showing a semiconductor test circuit according to the third embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 3, reference numeral 300 denotes a semiconductor test circuit according to the third embodiment, and reference numeral 9 denotes a scan data generator which receives a reference clock supplied to the reference clock input terminal 2 and alternately outputs different frequency divisions. .

The operation will be described below.
At the time of burn-in, a reference clock is supplied to the reference clock input terminal 2 and a monitor control signal indicating that monitoring is not performed to the monitor control signal input terminal 4 from a burn-in device (not shown) outside the semiconductor test circuit 300. At this time, the scan data is supplied by the scan data generator 9. The scan data generator 9 has a reference clock as an input and has a frequency divider whose initial state is uniformly determined. For example, the reference clock divided by two and the reference clock divided by four are divided into eight reference clocks. The output is switched by a frequency dividing signal.
Other operations are the same as those in the first embodiment.

  As described above, since the semiconductor test circuit according to the third embodiment supplies the scan data at two kinds of frequencies, the stress at the time of burn-in can be further increased.

  In the third embodiment, the scan data generator is described as supplying two types of scan data. However, naturally three or more types may be used.

(Embodiment 4)
FIG. 4 is a diagram showing a semiconductor test circuit according to the fourth embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 4, reference numeral 400 denotes a semiconductor test circuit according to the fourth embodiment. Reference numeral 10 denotes the reference clock supplied to the reference clock input terminal 2 as an input, determines the period during which the scan shift operation is performed, and performs the scan shift operation. A scan shift period determination circuit that outputs a selection signal for selecting whether to perform a scan capture operation, and 11 is a scan shift operation or a scan capture operation based on a selection signal output from the scan shift period determination circuit 10 A scan operation control signal selection output circuit that selects which scan operation is performed and outputs a scan operation control signal.

The operation will be described below.
At the time of burn-in, the reference clock input terminal 2 does not monitor the reference clock, the scan data input terminal 3 scan data, and the monitor control signal input terminal 4 do not monitor from a burn-in device (not shown) outside the semiconductor test circuit 400. Each of the monitor control signals shown is supplied. At this time, the scan operation control signal selection output circuit 11 selects and outputs which scan operation to perform between the scan shift operation and the scan capture operation based on the selection signal output from the scan shift period determination circuit 10. To do. The scan shift period determination circuit 10 is a frequency divider that receives, for example, a reference clock and whose initial state is uniformly determined, and outputs a frequency-divided signal having a period equal to or greater than the number of scan flip-flops.
Other operations are the same as those in the first embodiment.

  As described above, since the semiconductor test circuit according to the fourth embodiment is configured to supply the scan operation control signal internally by the semiconductor test circuit, the number of I / O terminals required at the time of burn-in can be reduced, and It is possible to easily compare the expected value during monitoring without reducing the stress during burn-in.

(Embodiment 5)
FIG. 5 is a diagram showing a semiconductor test circuit according to the fifth embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 5, reference numeral 500 denotes a semiconductor test circuit according to the fifth embodiment, and reference numeral 12 denotes scan data in which a scan operation control signal for alternately switching between a scan shift operation and a scan capture operation is supplied to the scan data input terminal 3. And a scan operation control signal output circuit that uses a monitor control signal as a reset so as to synchronize with the reference clock supplied to the reference clock input terminal 2.

The operation will be described below.
At the time of burn-in, the reference clock input terminal 2 does not monitor the reference clock, the scan data input terminal 3 scan data, and the monitor control signal input terminal 4 do not monitor from a burn-in device (not shown) outside the semiconductor test circuit 500. Each of the monitor control signals shown is supplied. At this time, the scan operation control signal output circuit 12 outputs a scan operation control signal based on the monitor control signal so that the scan shift operation and the scan capture operation are alternately performed. Here, the scan operation control signal output circuit 12 is a frequency divider having a reset whose initial state is uniformly determined, and uses a frequency-divided output having a period equal to or greater than the number of scan flip-flops.

At the time of monitoring, the monitor control signal supplied from the monitor control signal input terminal 4 indicates that monitoring is performed. At this time, the scan operation control signal output circuit 12 is reset, and the monitor signal output unit 7 outputs a monitor signal synchronized with a burn-in device (not shown).
Other operations are the same as those in the first embodiment.

  As described above, since the semiconductor test circuit according to the fifth embodiment includes the scan operation control signal output circuit that uses the monitor control signal as the reset, it is easy to compare the expected value during monitoring without adding a reset terminal. Can be done.

(Embodiment 6)
FIG. 6 is a diagram showing a semiconductor test circuit according to the sixth embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 6, reference numeral 600 denotes a semiconductor test circuit according to the sixth embodiment, and reference numeral 13 denotes a scan indefinite period mask that receives the monitor control signal supplied to the monitor control signal input terminal 4 and outputs it by masking the scan indefinite period. Circuit.

The operation will be described below.
During burn-in, a reference clock is supplied to the reference clock input terminal 2 and a monitor control signal indicating that monitoring is not performed to the monitor control signal input terminal 4 from a burn-in device (not shown) outside the semiconductor test circuit 600.

At the time of monitoring, the monitor control signal supplied from the monitor control signal input terminal 4 indicates that monitoring is performed. At this time, the scan operation control signal selection output circuit 6 selectively outputs the scan operation control signal so that the scan shift operation is performed. The scan operation is fixed to scan shift, and the scan output accompanying this is output as a monitor signal, but the scan output for the length of the number of scan flip-flops until the scan data input for the first time is scanned out is undefined. Become. The scan indefinite period mask circuit 13 is a frequency divider that resets the monitor control signal, for example, and outputs a frequency division period equal to or greater than the number of scan flip-flops so that the monitor signal output unit 7 does not output a monitor signal during the scan indefinite period. Mask the monitor control signal with.
Other operations are the same as those in the first embodiment.

  As described above, since the semiconductor test circuit according to the sixth embodiment is configured not to output the monitor signal during the scan indefinite period, the expected value comparison at the time of monitoring can be performed more easily.

(Embodiment 7)
FIG. 7 is a diagram showing a semiconductor test circuit according to the seventh embodiment. Components similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 7, 700 is a semiconductor test circuit according to the seventh embodiment, 14 is an oscillator that oscillates a reference clock, 15 is a frequency divider that divides the reference clock oscillated by the oscillator 14 and outputs it as scan data. is there.

The operation will be described below.
Only a monitor control signal is supplied to the monitor control signal input terminal 4 from a burn-in circuit (not shown) outside the semiconductor test circuit 700. The scan-designed semiconductor circuit 110 is supplied with a reference clock oscillated by the oscillator 14 and scan data output by the frequency divider 15.
Other operations are the same as those in the second embodiment.

  As described above, the semiconductor test circuit according to the seventh embodiment includes the oscillator, and the reference clock is supplied internally by the semiconductor test circuit, so that the number of I / O terminals required at the time of burn-in can be reduced. .

  If the initial state of the frequency divider 15 is determined uniformly and the frequency division ratio of the oscillator 14 is divided by 2 or more, even if the initial oscillation value of the oscillator 14 is not uniformly determined, Since the H or L level signal is output in a specific section, the expected value comparison at the time of monitoring can be performed more easily.

(Embodiment 8)
FIG. 8 shows a semiconductor test circuit according to the eighth embodiment. In addition, the same code | symbol is attached | subjected to the thing similar to FIG. 7, and the description is abbreviate | omitted.

  In FIG. 8, reference numeral 800 denotes a semiconductor test circuit according to the eighth embodiment, and reference numeral 18 denotes an oscillation frequency of the oscillator 14 based on oscillation frequency setting data that can be input from outside the semiconductor test circuit 800 other than when a monitor signal is output. The oscillation control circuit 16 controls the output of the monitor signal and the monitor signal output terminal for inputting the oscillation frequency setting data. The monitor signal is output to the monitor signal output terminal 16 when the monitor signal is output based on the monitor control signal. The monitor signal output unit outputs a signal and outputs the oscillation frequency setting data to the oscillation control circuit 18 when the oscillation frequency setting data is input.

The operation will be described below.
At the time of burn-in, a monitor control signal indicating that monitoring is not performed is supplied from the monitor control signal input terminal 4. At this time, predetermined oscillation frequency setting data is input to the oscillation control circuit 18 from a burn-in device (not shown) outside the semiconductor test circuit 800 via the monitor signal output terminal 16 and the monitor signal output unit 17. 18 sets the oscillation frequency of the oscillator 14 based on the oscillation frequency setting data.
Other operations are the same as those in the seventh embodiment.

  As described above, the semiconductor test circuit according to the eighth embodiment sets the oscillation frequency of the oscillator based on the oscillation frequency setting data input through the monitor signal output terminal when the monitor signal is not output. The frequency of the operation clock during burn-in can be arbitrarily changed without increasing the number of terminals, and the operation current can be adjusted.

  The semiconductor test circuit according to the present invention can reduce the number of I / O terminals required at the time of burn-in, and can easily compare the expected value at the time of monitoring without reducing the stress at the time of burn-in. It is suitable for use in a burn-in test of a scan designed semiconductor circuit.

It is a figure which shows the semiconductor test circuit by Embodiment 1 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 2 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 3 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 4 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 5 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 6 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 7 of this invention. It is a figure which shows the semiconductor test circuit by Embodiment 8 of this invention. It is a figure which shows the conventional semiconductor test circuit.

Explanation of symbols

2,902 Reference clock input terminal 3,903 Scan data input terminal 4,904 Monitor control signal input terminal 5,16,905 Monitor signal output terminal 6,11 Scan operation control signal selection output circuit 7, 17, 907 Monitor signal output unit 8, 15 Frequency divider 9 Scan data generator 10 Scan shift period determination circuit 12 Scan operation control signal output circuit 13 Scan indefinite period mask circuit 14 Oscillator 18 Oscillation control circuit 100, 200, 300, 400, 500, 600, 700, 800, 900 Semiconductor test circuit 110, 910 Scan designed semiconductor circuit 901 Scan operation control signal input terminal

Claims (9)

A semiconductor test circuit for supplying a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit and performing a burn-in test for monitoring the output of the final stage of the scan chain In
A monitor control signal input terminal for inputting a monitor control signal indicating whether to monitor from the outside of the semiconductor test circuit;
Based on the monitor control signal, a scan operation control signal selection output circuit that outputs the scan operation control signal so that a scan shift operation and a scan capture operation are alternately performed during burn-in and a scan shift operation is performed during monitoring. Prepared,
A semiconductor test circuit. The semiconductor test circuit according to claim 1,
A reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit;
A frequency divider that divides the reference clock and outputs it as the scan data;
A semiconductor test circuit. The semiconductor test circuit according to claim 1,
A reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit;
A scan data generator that receives the reference clock as an input and alternately outputs different frequency divisions as the scan data;
A semiconductor test circuit. A semiconductor test circuit for supplying a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit and performing a burn-in test for monitoring the output of the final stage of the scan chain In
A reference clock input terminal for inputting the reference clock from the outside of the semiconductor test circuit;
A scan shift period determining circuit for determining a period for performing a scan shift operation based on the reference clock and outputting a selection signal for selecting whether to perform the scan shift operation or the scan capture operation;
A scan operation control signal selection output circuit that outputs the scan operation control signal based on the selection signal;
A semiconductor test circuit. A semiconductor test circuit for supplying a scan operation control signal for controlling a scan operation, test scan data, and a reference clock to a scan-designed semiconductor circuit and performing a burn-in test for monitoring the output of the final stage of the scan chain In
A monitor control signal input terminal for inputting a monitor control signal indicating whether to monitor from the outside of the semiconductor test circuit;
The monitor control signal is used as a reset, and includes a scan operation control signal output circuit that outputs the scan operation control signal.
A semiconductor test circuit. The semiconductor test circuit according to claim 1,
A scan indefinite period mask circuit that inputs the monitor control signal and masks and outputs the scan indefinite period;
A monitor signal output unit that outputs a monitor signal from the scan designed semiconductor circuit based on the output of the scan indefinite period mask circuit;
A semiconductor test circuit. The semiconductor test circuit according to claim 1,
An oscillator for oscillating the reference clock;
A semiconductor test circuit. The semiconductor test circuit according to claim 7,
A frequency divider for dividing the reference clock oscillated by the oscillator and outputting as the scan data is provided.
A semiconductor test circuit. The semiconductor test circuit according to claim 7,
An oscillation control circuit for controlling the oscillation frequency of the oscillator;
A semiconductor test circuit.

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