JP2005085206A - Semiconductor integrated circuit and scan path test circuit design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan path circuit design method or the like which allows a scan path test to be performed for a logic circuit designed by gated clock design. <P>SOLUTION: A scan latch unit is inserted (step st2) in logic design processing for designing a logic circuit on the latch base (step st1), and next, a clock gate for generating a gated clock in the logic circuit is searched (step st3). A gate control circuit which controls a prescribed control signal inputted to the clock gate is inserted on the basis of a search result (step st4), and thus the gate clock is controlled to perform a scan path test being a desired test operation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a scan path test circuit design method for executing a scan path test of a semiconductor integrated circuit, and a semiconductor integrated circuit having a logic configuration designed based on a latch based on the method.

  As ASIC (Application Specific Integrated Circuit) increases in scale, there is a method in which a test circuit for product inspection at the manufacturing stage is incorporated in the ASIC in advance and designed in addition to the original function intended for the ASIC. It is used. As one of the test methods, a test circuit that incorporates a test circuit capable of executing a test called a scan path test method is known.

  As an example, this scan path test method replaces a flip-flop circuit, which is a sequential circuit provided in a semiconductor integrated circuit, with a so-called scan flip-flop capable of scanning, inputs test data, and from the observed output result, the sequential circuit The test which judges the defect etc. of this is performed.

Alternatively, a latch circuit may be provided instead of the flip-flop as a sequential circuit from the viewpoint of ensuring the high-speed operation of the device. In Japanese Patent Application Laid-Open No. 8-273393, for the logic circuit designed on the latch base, A semiconductor integrated circuit that executes the scan path test method is disclosed.
JP-A-8-273393

  On the other hand, in current logic circuit design, in order to improve speed, reduce area, and increase functionality, multilayer clock design using multiple clock signals, gated clock design that processes clocks using gates, etc. Clock designs have been adopted.

  However, the logic circuit having these clock designs may be prohibited from incorporating the test circuit because of complicated control of the latch circuit and the like. For example, one of the typical logic circuit design constraints is the so-called “prohibition of gated clock”.

  Therefore, the scan path test method has not been executed in the logic circuit for which the gated clock design is performed.

  The object of the present invention is to solve the above-mentioned problems and execute the scan path test method even in the case of having a logic circuit designed by a latch base and designed by a gated clock design. A semiconductor integrated circuit and a scan path test circuit designing method capable of being provided.

  The semiconductor integrated circuit of the present invention includes a plurality of scan latch circuits, a plurality of latch circuits, and a plurality of logic circuits. The plurality of scan latch circuits latch and output one of the plurality of signals input based on the clock signals having the first and second logic levels. Each of the plurality of latch circuits is arranged so as to be alternately connected in series between the plurality of scan latch circuits, and the input signal is complementarily latched and output to the plurality of scan latch circuits. . Each of the plurality of logic circuits is provided so as to be alternately connected in series between each scan latch circuit and each adjacent latch circuit, and outputs a signal based on a predetermined logic operation operation according to one input. Output to the other. At least one scan latch circuit of the plurality of scan latch circuits latches and outputs one of the plurality of signals based on the input of the clock signal and a predetermined control signal. During the test, the predetermined control signal is fixed at one of the first and second logic levels.

  The scan path test circuit design method of the present invention includes a plurality of latch circuits that latch and output based on clock signals having first and second logic levels, and a plurality of latch circuits alternately in series. In a logic design process for designing a logic circuit configured by using a plurality of connected logic units, and in a logic circuit generated by the logic design process, each of a group of latch circuits among the plurality of latch circuits is the other A gated clock generated based on a combination of a predetermined control signal and a clock signal in the logic circuit, and a process of replacing the latch circuit with a scan latch circuit so as to be disposed between each logic unit and the logic circuit. A process for searching for a clock gate for generating a clock and a predetermined control signal input to the clock gate based on the search result. And a process of inserting the gate control circuit.

  As described above, according to the present invention, in a latch circuit that latches and outputs one of a plurality of signals based on the input of a clock signal and a predetermined control signal, the predetermined control signal is supplied to the first and second signals during a test. Fix to one of the logical levels. Thereby, at the time of the test, the latch circuit can execute the latch operation in synchronization with the clock signal, so that the scan path test which is a desired test operation can be executed.

  Also, in a logic design process for designing a logic circuit on a latch basis, a gate control circuit for controlling a predetermined control signal input to a clock gate based on a search result is inserted even in a logic design having a gated clock. Thus, a scan path test which is a desired test operation can be executed.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a flowchart showing a scan path test circuit design method for a semiconductor integrated circuit according to the first embodiment of the present invention.

  Referring to FIG. 1, a logic design process for designing a logic circuit on a latch basis is performed (step st1).

  FIG. 2 is an example of a logic circuit designed on a latch basis in step st1.

  2, this logic circuit includes logic units 1 to 3, 6 to 8, latch circuits L1, L2 #, L3, L4 #, and L5, and AND circuits 4 and 10.

  This logic circuit configuration is a sequential circuit in which high-through latch circuits and low-through latch circuits are alternately arranged in series across a logic unit. Here, a sequential circuit is shown as an example using the logic units 1 to 3 and 6 to 8, but a similar sequential circuit can be arranged in the preceding stage or the subsequent stage of this circuit.

  Specifically, the latch circuit L1 latches and outputs the input signal IN in synchronization with the clock signal CLK (“H” level). The logic unit 1 receives the output signal of the latch circuit L1, executes a predetermined logic operation, and outputs the result to the latch circuit L2 #. The latch circuit L2 # latches the output signal of the logic unit 1 in synchronization with the clock signal CLK (“L” level) and outputs it to the logic unit 2. The logic unit 2 receives the output signal of the latch circuit L2 #, executes a predetermined logic operation, and outputs the result to the latch circuit L3. The latch circuit L3 latches the output signal of the logic unit 2 that is input in synchronization with the output signal (“H” level) of the AND circuit 4 that is a processed clock signal (also referred to as a gated clock), to the logic unit 6. Output.

  Logic unit 6 receives the output signal of latch circuit L3, executes a predetermined logic operation, and outputs the result to latch circuit L4 #. The latch circuit L4 # latches the output signal of the logic unit 6 in synchronization with the clock signal CLK (“L” level) and outputs it to the logic unit 7. The logic unit 7 receives the output signal of the latch circuit L4 #, executes a predetermined logic operation, and outputs the result to the latch circuit L5. The latch circuit L5 latches the output signal of the logic unit 7 that is input in synchronization with the output signal (“H” level) of the AND circuit 10 that is the processed clock signal, and outputs it as the output signal OUT.

  The AND circuit 4 outputs an AND logic operation result to the latch circuit L3 based on the clock signal CLK and the output signal EN1 of the logic unit 3. The AND circuit 10 outputs an AND logic operation result to the latch circuit L5 based on the clock signal CLK and the output signal EN2 of the logic unit 8. The AND circuits 4 and 10 are also referred to as clock gates that control the clock signal CLK.

  An example of the operation of this logic circuit configuration will be described.

  Here, it is assumed that control signals EN1 and EN2 output from logical unit 3 and logical unit 8, respectively, are set to “H” level.

  In this case, based on the input of the input signal IN, each latch circuit sequentially latches and outputs the logical operation result via the logic unit in synchronization with the “H” level or “L” level of the clock signal CLK. To do. As a result, in this example, the output signal OUT in response to the input of the input signal IN is output from the latch circuit L5 in three clock cycles.

  Referring to FIG. 1 again, next, a process of inserting a scan latch circuit is executed to execute a scan path test (step st2). Specifically, a scan latch circuit is provided instead of the latch circuit.

  Next, a clock gate search process is executed (step st3). Specifically, the clock gate in the logic circuit is searched and detected.

  Next, a gate control circuit is inserted into the clock gate in the logic circuit (step st4). Specifically, a gate control circuit is inserted and set to perform mask processing on the control signal input to the clock gate during the test.

  FIG. 3 is a logic circuit configuration diagram of the semiconductor integrated circuit according to the first embodiment of the present invention in which the flowchart of FIG. 1 is applied to the logic circuit of FIG.

  First, the scan latch circuit insertion process will be described.

  Referring to FIG. 3, the logic circuit according to the first embodiment of the present invention includes scan latch circuits SKL1 to SKL3 replaced with latch circuits L1, L3, and L5, respectively, as compared with the logic circuit of FIG. Circuits 5 and 9 are further included. Since the other points are the same, detailed description thereof will not be repeated.

  Scan latch circuit SKL1 includes a selector SEL1 and latch circuits L1 and L1 #.

  Here, as a design method, the selector SEL1 is inserted in series with the latch circuit L1 so that the input signals of the latch circuit L1 and the selector SEL1 are common, and the input signal IN and the input signal SI are passed through the selector SEL1. The signal is selectively output to the latch circuit L1 in response to the control signal SE. Latch circuit L1 latches the output signal output from selector SEL1 in synchronization with clock signal CLK (“H” level), and outputs signal S1 to logic unit 1 and latch circuit L1 #. The latch circuit L1 # latches the signal S1 in synchronization with the clock signal CLK (“L” level) and outputs the signal S1 to the scan path line SPLSPL as the signal S1 #. The latch circuit L1 # transmits the signal S1 # to the next-stage scan latch circuit SKL via the scan path line SPL. A latch circuit that transmits a signal to the next-stage scan latch circuit via the scan path line SPL is also called a so-called slave latch circuit. The same applies to the following. In the present specification, it is simply referred to as a latch circuit.

  Scan latch circuit SKL2 includes a selector SEL2 and latch circuits L3 and L3 #.

  Here, as a design method, the selector SEL2 is inserted in series with the latch circuit L3 so that the input signals of the latch circuit L3 and the selector SEL2 are common, and the signal is passed through the selector SEL2 via the signal S2 and the scan path line SPL. The transmitted signal S1 # is selectively output to the latch circuit L3 in response to the control signal SE. The latch circuit L3 latches the output signal output from the selector SEL2 in synchronization with the output signal (“H” level) (gated clock) of the AND circuit 4, and the signal S3 is input to the logic unit 6 and the latch circuit L3 #. Output. The latch circuit L3 # latches the signal S3 in synchronization with the output signal (“L” level) of the AND circuit 4, and outputs the signal S3 to the scan path line SPL as the signal S3 #.

  Scan latch circuit SKL3 includes a selector SEL3 and latch circuits L5 and L5 #.

  Here, as a design method, the selector SEL3 is inserted in series with the latch circuit L5 so that the input signals of the latch circuit L5 and the selector SEL3 are common, and through the selector SEL3 via the signal S4 and the scan path line SPL. The transmitted signal S3 # is selectively output to the latch circuit L3 in response to the control signal SE. The latch circuit L5 latches the output signal output from the selector SEL3 in synchronization with the output signal (“H” level) (gated clock) of the AND circuit 10, and outputs the signal S5 as the output signal OUT. Latch circuit L5 # latches signal S5 in synchronization with the output signal ("L" level) of AND circuit 10 and outputs it as signal SO.

  The scan latch circuit SKL1 selects either the input signal IN or the input test data signal SI in response to the control signal SE and outputs the selected signal to the logic unit 1 and the scan path line SPL. Similarly, scan latch circuit SKL2 selects either input signal S2 from logic unit 2 or a signal transmitted from scan path line SPL in response to control signal SE to select logic unit 6 and scan path line SPL. Output to. Similarly, scan latch circuit SKL3 selects one of input signal S4 from logic unit 7 and the signal transmitted from scan path line SPL in response to control signal SE, and outputs it as output signal OUT and signal SO. To do. Accordingly, the scan latch circuit SKL is inserted into the logic circuit designed on the latch base shown in FIG.

  Next, a clock gate search process is executed. In this example, the AND circuits 4 and 10 are detected as clock gates, and the AND gates 4 and 10 that are the clock gates are gate control circuits that control the gates. Some OR circuits 5 and 9 are inserted.

  Specifically, the OR circuit 5 outputs the OR logic operation result to one of the input nodes of the AND circuit 4 based on the test mode signal TE and the control signal EN1. The OR circuit 9 outputs the OR logic operation result to one of the input nodes of the AND circuit 10 based on the test mode signal TE and the control signal EN2.

  The normal operation of this logic circuit will be described. Under normal conditions, the control signal SE is set to the “L” level, and the test mode signal TE is set to the “L” level.

  In this case, in the scan latch circuit SKL1, the selector SEL1 selects the input signal IN and outputs it to the latch circuit L1. Similarly for the other scan latch circuits SKL2 and SKL3, the selectors SEL2 and SEL3 select the input signals S2 and S4 and output them to the latch circuits L3 and L5, respectively.

  Therefore, in response to the input signal IN, the latch circuit L1-logic unit 1-latch circuit L2 # -logic unit 2-latch circuit L3-logic unit 6-latch circuit L4 # -logic unit 7-latch circuit L5 An output signal OUT is output via this. Therefore, in a normal time, a logic circuit having the same function as the logic circuit described in FIG. 2 is configured.

  Next, the operation during the test will be described.

  The scan path test method according to the first embodiment of the present invention will be described using the timing chart of FIG.

  The scan path test is a test in which test data is set in advance and a logical operation result output from the logical unit is observed to determine whether or not a desired logical operation (desired logical circuit configuration) is achieved. In this example, test data d1 and d2 are shown as signals used for the scan path test. The test data d3 is an output signal from another logic circuit arranged in the preceding stage of the logic circuit of FIG. 3 (not shown).

  Here, in Embodiment 1 of the present invention, test mode signal TE is set to the “H” level. Accordingly, the signal input to the input nodes of AND circuits 4 and 10 is always set to “H” level. Therefore, the AND circuits 4 and 10 output a gated clock synchronized with the clock signal CLK at the same logic level as the clock signal CLK. Therefore, the following description will be made assuming that the clock signal CLK.

  Referring to FIG. 4, in this example, the rising and falling edges of clock signal CLK are periodically input. Specifically, rising edges r1 to r6 of the clock signal CLK are shown, and falling edges f1 to f6 are shown.

  First, a scan path test using the test data d1 and d2 will be described.

  At time T1, which is the rising edge (r1) of the clock signal CLK, the scan latch circuit SKL1 latches (shifts in) the test data d1. Specifically, the selector SEL1 selects the test data signal d1 in response to the control signal SE (“H” level). Latch circuit L1 latches test data d1 in synchronization with clock signal CLK ("H" level) and outputs signal S1.

  Next, at time T2 which is the falling edge (f1) of the clock signal CLK, the latch circuit L1 # latches the signal S1 as the test data d1 in synchronization with the clock signal CLK (“L” level), Signal S1 # is transmitted to scan campus line SPL. At the same timing, the latch circuit L2 operates. That is, the output signal of the logic unit 1 is latched and output to the logic unit 2. The logic unit 2 receives the output signal from the latch circuit L2, generates a signal S2, and inputs it to the scan latch circuit SKL2.

  Scan latch circuit SKL2 selects signal S1 # from signals S2 and S1 # input in response to control signal SE ("H" level), and outputs the selected signal as signal S3i.

  The latch circuit L3 of the scan latch circuit SKL2 latches the signal S3i that is the test data d1 output from the selector SEL2 at time T3, which is the rising edge (r2) of the clock signal CLK. As a result, the test data d1 is set in the scan latch circuit SKL2.

  At time T4, which is the falling edge (f2) of the next clock signal CLK, the latch circuit L3 # latches the test data d1 that is the output signal of the latch circuit L3, and outputs it as the signal S3 #. At the same timing, the latch circuit L4 # operates, and the output signal S4 of the logic units 6 and 7 is input to the scan latch circuit SKL3.

  Next, the set of test data d2 will be described.

  At time T3 which is the rising edge (r2) of the clock signal CLK, the test data d1 is input to the scan latch circuit SKL1 (shift-in). Specifically, the selector SEL1 selects the test data signal d2 in response to the control signal SE (“H” level). The latch circuit L1 latches the test data d2 and outputs a signal S1. Thereby, the scan latch circuit SKL1 sets the test data d1.

  Next, at time T2, which is the falling edge (f2) of the clock signal CLK, the test data d2 is latched in the latch circuit L1 #, and the signal S1 # is output. At the same timing, the latch circuit L2 operates and the output signal S2 of the logic units 1 and 2 is input to the scan latch circuit SKL2.

  In the two test data d1 and d2 set in the scan latch circuits SKL1 and SKL2, the control signal SE is set to the “L” level, and the clock signal CLK is advanced by one clock cycle.

  In the selector SEL2, the scan latch circuit SKL2 selects and outputs the signal S2 in response to the control signal SE (“L” level) after the falling edge (f2) of the clock signal CLK. That is, the selector SEL2 outputs the signal S3i of the test data d2A. Similarly, scan latch circuit SKL3 selects and outputs signal S4 in selector SEL3 in response to control signal SE ("L" level). That is, the selector SEL3 outputs the signal S5i of the test data d1B.

  At time T6 which is the rising edge (r3) of the next clock signal CLK, the latch circuit L3 of the scan latch circuit SKL2 latches (captures) the test data d2A and outputs it as the signal S3. Similarly, the latch circuit L5 of the scan latch circuit SKL3 latches (captures) the test data d1B and outputs it as the signal S5, that is, the output signal OUT (shift out).

  At time T7 which is the falling edge (f3) of the next clock signal CLK, the latch circuit L3 # of the scan latch circuit SKL2 latches the signal S3 which is the test data d2A and outputs it as the signal S3 #. Similarly, the latch circuit L5 # of the scan latch circuit SKL3 latches the signal S5 that is the test data d1B and outputs it as the signal SO. As a result, the logical operation signal d1B passing through the logical units 6 and 7 can be observed according to the input test data d1.

  Next, the selector SEL3 of the scan latch circuit SKL3 selects the signal S3 # which is the test data d2A in response to the setting of the “H” level of the control signal SE after the falling edge (f3) of the clock signal CLK. Output as signal S5i.

  The latch circuit L5 of the scan latch circuit SKL3 latches the signal S3 #, which is the test data d2A, at time T8, which is the rising edge (r4) of the next clock signal CLK, and outputs it as the signal S5, that is, the output signal OUT ( Shift out).

  At time T9 which is the falling edge (f4) of the next clock signal CLK, the latch circuit L5 # of the scan latch circuit SKL3 latches the signal S5 which is the test data d2A and outputs it as the output signal SO. As a result, the logical operation signal d2A passing through the logical units 1 and 2 can be observed according to the input test data d2.

  Accordingly, two test data d1 and d2 are set in the shift latch circuits SKL1 and SKL2, respectively, and the set test data d1 and d2 are shifted in the next clock cycle. A signal d1B of a predetermined logic operation and a signal d2A of a predetermined logic operation based on the combination of the logic units 1 and 2 can be observed. That is, it is possible to test whether or not the logic circuit is a desired circuit by setting the test data d1 and d2 set in advance and obtaining the observation result.

  Furthermore, in this example, observation of test data d3 that is an output signal from another logic circuit arranged in the preceding stage of the logic circuit of FIG. 3 (not shown) will also be described.

  Test data d3 is input at time T4, which is the falling edge (f2) of the clock signal CLK. In this case, the latch circuit L1 of the scan latch circuit SKL1 latches the output signal of the selector SEL1 at time T6, which is the rising edge (r3) of the next clock signal CLK. In this case, the selector SEL1 selects the input signal IN which is the test data d3 in response to the control signal SE (“L” level). As a result, the latch circuit L1 latches the test data d3 and outputs the signal S1. At time T7 which is the falling edge (f3) of the next clock signal CLK, the latch circuit L1 # latches the signal S1 which is the test data d3 and outputs it as the signal S1 # to the scan path line SPL.

  At time T8 which is the rising edge (r4) of the next clock signal CLK, the latch circuit L3 of the scan latch circuit SKL2 latches the output signal S3i of the selector SEL2. At this time, the selector SEL2 selects the signal S1 # transmitted to the scan path line SPL in response to the control signal SE (“H” level). Thereby, the latch circuit L3 latches the signal S3i, which is the test data d3, and outputs it as the signal S3. At time T9 which is the falling edge (f4) of the next clock signal CLK, the latch circuit L3 # latches the signal S3 which is the test data d3 and outputs it as the signal S3 #.

  At the next rising edge (r6) of the clock signal CLK, the latch circuit L5 of the scan latch circuit SKL3 latches the output signal S5i of the selector SEL3. At that time, the selector SEL3 selects the signal S3 # transmitted to the scan path line SPL in response to the control signal SE (“H” level). Therefore, the latch circuit L5 latches the signal S5i, which is the test data d3, and outputs it as the signal S5. At time T11 which is the falling edge (f6) of the next clock signal CLK, the latch circuit L5 # latches the signal S5 which is the test data d3 and outputs it as the signal SO.

  Therefore, the data d3 given to the input signal IN is output as the signal SO at the same data level without using the logic unit using the scan path line SPL. Thereby, it is possible to observe an output signal based on the logical operation operation of another logic circuit arranged in the preceding stage of the logic circuit of FIG. 3 (not shown). By obtaining the observation result, it is possible to test whether another logic circuit in the previous stage is a desired circuit.

  In the timing chart, the symbol “A” at the end of the test data indicates the case of passing through the logical units 1 and 2, the symbol “B” indicates the case of passing through the logical units 6 and 7, and the symbol “AB” indicates a case in which the logical units 1 and 2 and the logical units 6 and 7 are passed.

  As described above, even in a logic circuit configuration having a clock gate, an OR circuit, which is a gate control circuit for controlling the clock gate, is inserted, and a fixed test mode signal TE (“H” level) is supplied during testing. input. As a result, during the test, the gated clock output from the clock gate outputs a signal having the same logic level and the same cycle as the clock signal CLK, and the scan path test is executed even in the logic circuit configuration having the clock gate. be able to.

(Modification of Embodiment 1)
In the first embodiment described above, the method of executing the scan path test by replacing the high-through latch circuit with the scan latch circuit has been described.

  In the modification of the first embodiment, a method of executing a scan path test by replacing a low-through latch circuit with a scan latch circuit will be described.

  FIG. 5 is another example of a logic circuit designed on a latch basis.

  Referring to FIG. 5, this logic circuit includes logic units 1 to 3, 6 to 8, latch circuits L1 #, L2, L3 #, L4 and L5 #, and AND circuits 4 and 10.

  The logic circuit of FIG. 5 has a configuration in which a high-through latch circuit and a low-latch latch circuit are interchanged as compared with the logic circuit of FIG. Specifically, the latch circuits L1 #, L3 #, and L5 # latch the input signal IN or the output signal of the logic unit in synchronization with the “L” level input signal. The latch circuits L2 and L4 latch the output signal of the logic unit in synchronization with the “H” level input signal.

  Therefore, only the clock signal CLK and the output signals of the AND circuits 4 and 10 when the signal is latched are inverted, and the operation of the logic circuit is the same as that of the first embodiment, so that the detailed description thereof will be given. Do not repeat.

  FIG. 6 is a logic circuit configuration diagram of a semiconductor integrated circuit according to a modification of the first embodiment of the present invention in which the flowchart of FIG. 1 is applied to the logic circuit of FIG.

  Referring to FIG. 6, the semiconductor integrated circuit according to the modification of the first embodiment of the present invention includes scan latch circuits SKL1 # to SKL3 #, logic units 1 to 3 and 6 to 8, latch circuits L2 and L4, AND circuits 4 and 10 and OR circuits 5 and 9 are included.

  The logic circuit of FIG. 6 differs from the logic circuit of FIG. 3 in that the low-through latch circuit is replaced with a scan latch circuit, but the processing procedure is the same.

  The scan latch circuit SKL1 # has a configuration in which the connection arrangement relationship between the latch circuits L1 and L1 # is switched compared to the scan latch circuit SKL1. Specifically, for example, the latch circuit L1 of the scan latch circuit SKL1 # latches the signal from the selector SEL1 in synchronization with the “L” level clock signal CLK. The latch circuit L1 # latches the signal S1 in synchronization with the “H” level clock signal CLK.

  The same applies to the other scan latch circuits SKL2 # and SKL3 #.

  A scan path test according to a modification of the first embodiment of the present invention will be described with reference to the timing chart of FIG.

  In this example, test data d1 and d2 are shown as signals used for the scan path test. Note that the test data d3 is an output signal from another logic circuit arranged in front of the logic circuit of FIG. 6 (not shown).

  Here, in the scan path test according to the modification of the first embodiment, test mode signal TE is set to the “H” level. Accordingly, one input to the input nodes of the AND circuits 4 and 10 is always set to the “H” level. Therefore, the AND circuits 4 and 10 output a gated clock synchronized with the clock signal CLK at the same logic level as the clock signal CLK. Therefore, the following description will be made assuming that the clock signal CLK.

  Referring to FIG. 7, in this example, the rising and falling edges of clock signal CLK are periodically input. Specifically, falling edges f1 to f6 of the clock signal CLK are shown, and rising edges r1 to r6 are shown.

  First, a scan path test using the test data d1 and d2 will be described.

  Compared with the test method described with reference to FIG. 4, this scan path test is similar to the test data d1, according to the same procedure as described with reference to FIG. 4 except that the logic level of the clock signal CLK at the time of latching is inverted. d2 is set. Specifically, at time T20 which is the falling edge (f1) of the clock signal CLK, the scan latch circuit SKL1 # latches the test data d1 (shift-in). At time T22 which is the falling edge (f2) of the next clock signal CLK, the scan latch circuit SKL2 # latches the test data d1. On the other hand, at time T22, the scan latch circuit SKL1 # receives and latches the next test data d1 (shift-in). Thereby, the test data d1 and d2 can be set.

  Next, the control signal SE is set to the “L” level and advanced by one clock cycle. Accordingly, the scan latch circuit SKL3 # latches the signal S4, which is the test data d1B that has passed through the logic units 6 and 7, in synchronization with the “L” level of the clock signal CLK according to the same procedure as in FIG. . The scan latch circuit SKL2 # latches the signal S2 that is the test data d2A that has passed through the logic units 1 and 2. Thereby, the signal SO is observed according to the same procedure as in FIG.

Therefore, two test data d1 and d2 are set in the shift latch circuits SKL1 # and SKL2 #, respectively, and the set test data d1 and d2 are shifted in the next clock cycle, thereby combining the logic units 6 and 7. A signal d1B of a predetermined logical operation operation based on the above and a signal d2A of a predetermined logical operation operation based on the combination of the logic units 1 and 2 can be observed. That is, it is possible to test whether or not the logic circuit is a desired circuit by setting the test data d1 and d2 set in advance and obtaining the observation result.

Further, in the timing chart of FIG. 7, the output signal is from another logic circuit arranged in the preceding stage of the logic circuit of FIG. 6 (not shown) according to the same procedure as described in FIG. By observing the test data d3, it is possible to test whether another logic circuit in the previous stage is a desired circuit. Also in this test, only the logic level of the clock signal CLK at the time of latching is inverted, and the operation procedure is the same as that in FIG.

  As described above, even in a logic circuit configuration having a clock gate according to the modification of the first embodiment, an OR circuit, which is a gate control circuit for controlling the clock gate, is inserted, and a fixed test mode is used at the time of testing. Input signal TE (“H” level). As a result, at the time of testing, the gated clock output from the clock gate is the same signal with the same logic level as the clock signal CLK, and the scan path test can be executed even in a logic circuit configuration having the clock gate. . In the present embodiment, the configuration using three scan latch circuits has been described. However, the present invention is not limited to this, and a plurality of logic units are provided, and a plurality of scan latch circuits are provided correspondingly. The present invention can also be applied in the configuration.

(Embodiment 2)
In the first embodiment described above, the method for executing the scan path test even in the logic circuit having the clock gate design has been described.

  In the configuration shown in FIG. 3 of the first embodiment, in the test mode, the test mode signal SE is fixed to the “H” level, so that the output signals of the logic units 3 and 8 cannot be observed. .

  In the second embodiment, a circuit configuration of a scan latch circuit capable of observing a control signal for controlling a gate in a logic circuit having a clock gate design will be described.

  FIG. 8 is a circuit configuration diagram of the scan latch circuit according to the second embodiment.

  FIG. 8A is a circuit configuration diagram of a scan latch circuit SKL3a that can be replaced with the scan latch circuit SKL3 of the first embodiment described in FIG.

  In this example, a circuit configuration for observing an output signal EN2 (hereinafter also referred to as a gate control signal EN2) that is a gate control signal output from the logic unit shown in FIGS. 3 and 6 will be described as an example.

  Referring to FIG. 8A, the scan latch circuit SKL3a is different from the scan latch circuit SKL3 in that a two-stage selector SEL4 and SEL5 that replace the selector SEL3 are provided.

  Here, as a design method, the selector SEL5 is inserted in series with the latch circuit L5 so that the input signals of the latch circuit L5 and the selector SEL5 are common, and the input signal IN and the control signal EN2 are transmitted through the selector SEL5. Selectively output in response to ENSEL. Further, a selector SEL4 is provided in series between the selector SEL5 and the latch circuit L5, and an output signal from the selector SEL5 and a signal SI transmitted via the scan path line SPL are selectively latched in response to the control signal SE. The signal is output to the circuit L5. The latch circuit L5 receives and latches the output signal of the selector SEL4 in synchronization with the output signal ("H" level) of the AND circuit 10. Latch circuit L5 # receives the output signal of latch circuit L5 and latches it in synchronization with the output signal ("L" level) of AND circuit 10.

  A normal operation will be described. Under normal conditions, control signal ENSEL is set to “L” level, and control signal SE is set to “L” level. Thereby, the selector SEL5 selects the input signal IN. The selector SEL4 selects the output signal of the selector SEL5, that is, the input signal IN, and outputs it to the latch circuit L5.

  Therefore, for normal operation, the scan latch circuit SKL3a has the same function as the latch circuit L5 described in FIG.

  On the other hand, the operation in the test mode will be described.

  For the scan path test other than detecting the gate control signal EN, the control signal ENSEL is set to the “L” level. Thereby, the input signal IN is selected in the selector SEL5. That is, the selector SEL4 selects either the input signal IN or the signal SI input via the scan path line SPL in response to the control signal SE, and the scan latch circuit SKL3a is the same as in the first embodiment. It has the same function as the scan latch circuit SKL3 described.

  On the other hand, for the scan path test for detecting the gate control signal EN, the control signal ENSEL is set to the “H” level. Thereby, in the selector SEL5, the gate control signal EN2 is selected and output to the selector SEL4.

  The selector SEL4 selects the gate control signal EN2 in response to the control signal SE (“L” level). Accordingly, the latch circuit L5 can latch the data included in the gate control signal EN2 and observe the gate control signal EN2 from the signal SO or the output signal OUT.

  FIG. 8B is a circuit configuration diagram of scan latch circuit SKL3 # a that can be replaced with scan latch circuit SKL3 according to the modification of the first embodiment described in FIG.

  The scan latch circuit SKL3 # a has a configuration in which the connection arrangement relationship between the latch circuit L5 and the latch circuit L5 # is switched compared to the scan latch circuit SKL3a. As for the specific operation, only the logic level at the time of latching is inverted and the other operations are the same, so that detailed description thereof will not be repeated.

  Therefore, by using the scan latch circuits SKL3a and SKL3 # a according to the second embodiment of the present invention, the gate control signal can also be observed, and an efficient scan path test can be executed.

(Modification of Embodiment 2)
FIG. 9 is a circuit configuration diagram of a scan latch circuit according to a modification of the second embodiment.

  FIG. 9A is a circuit configuration diagram of a scan latch circuit SKL3b that can replace the scan latch circuit SKL3 of the first embodiment described with reference to FIG.

  Referring to FIG. 9A, scan latch circuit SKL3b further includes two-stage selectors SEL6 and SEL7 that replace selector SEL3, OR circuit 11 and AND circuit 12 as compared with scan latch circuit SKL3. The point is different.

  Here, as a design method, the selector SEL7 is inserted in series with the latch circuit L5 so that the input signals of the latch circuit L5 and the selector SEL7 are common, and transmitted through the selector SEL7 via the scan path line SPL. The signal SI and the control signal EN2 are selectively output in response to the control signal SI. Further, a selector SEL6 is provided in series between the selector SEL7 and the latch circuit L5, and the output signal from the selector SEL7 and the input signal IN are selectively output to the latch circuit L5 in response to the output signal from the OR circuit 11. So that The latch circuit L5 receives the output signal of the selector SEL6 and latches it in synchronization with the output signal ("H" level) of the AND circuit 10. Latch circuit L5 # receives the output signal of latch circuit L5 and latches it in synchronization with the output signal ("L" level) of AND circuit 10. The AND circuit 12 receives the inverted signal of the control signal ENSEL and the inverted signal of the gate control signal EN2 and outputs the AND logic operation result to one of the input nodes of the OR circuit 11. The OR circuit 11 receives the output signal of the AND circuit 12 and the inverted signal of the test mode signal TE and outputs the OR logic operation result.

  A normal operation will be described.

  Since the test mode signal TE is set to the “L” level in the normal time, the OR circuit 11 outputs an “H” level signal in response to the input of the inverted signal of the test mode signal TE. Accordingly, the input signal IN is selected in the selector SEL6, and a normal shift operation is executed as described above.

  The operation in the test mode will be described.

  In this case, test mode signal TE is set to “H” level. Therefore, one of the input nodes of the OR circuit 11 is at the “L” level.

  For the scan path test other than detecting the gate control signal EN2, the control signal ENSEL is set to the “L” level and the control signal SE is set to the “H” level. Accordingly, in response to control signal SE (“H” level), signal SI is selected in selector SEL7. Further, since the inverted signal (“L” level) of the control signal SE is input to the AND circuit 12, the output signal of the AND circuit 12 becomes the “L” level. Therefore, the output signal of the OR circuit becomes “L” level. Accordingly, the selector SEL6 selects the output signal of the selector SEL7, that is, the control signal SI. Therefore, the selector SEL6 selects one of the input signal IN and the signal SI input through the scan path line SPL, and the scan latch circuit SKL3b is the scan latch circuit SKL3 described in the first embodiment. Has the same function.

  On the other hand, for the scan path test for detecting the gate control signal EN, the control signal ENSEL is set to the “H” level and the control signal SE is set to the “L” level. In response to the control signal SE (“L” level), the selector SEL7 selects the gate control signal signal EN. Further, since the inverted signal (“L” level) of the control signal ENSEL is input to the AND circuit 12, the output signal of the AND circuit 12 becomes the “L” level. Therefore, the output signal of the OR circuit becomes “L” level. Accordingly, the selector SEL6 selects the output signal of the selector SEL7, that is, the gate control signal EN2.

  The gate control signal EN2 can be observed by latching data in the latch circuit L5.

  In this configuration, the input signal IN passes through only one selector stage as compared with the scan latch circuit SKL3a in FIG. 8A, so that the delay period can be shortened and high-speed shift operation is executed. can do.

  FIG. 9B is a circuit configuration diagram of scan latch circuit SKL3 # b that can replace scan latch circuit SKL3 according to the modification of the first embodiment described in FIG.

  The configuration is the same as that described with reference to FIG. 9A, and the connection arrangement relationship between the latch circuit L5 and the latch circuit L5 # is switched. As for the specific operation, only the logic level at the time of latching is inverted and the other operations are the same, so that detailed description thereof will not be repeated.

  Therefore, by using scan latch circuits SKL3b and SKL3 # b according to the modification of the second embodiment of the present invention, an efficient scan path test is executed and the delay amount of input signal IN during normal operation is also reduced. Therefore, a high-speed shift operation can also be performed.

  In the present embodiment, the configuration of the scan latch circuit replaceable with the scan latch circuit SKL3 has been mainly described. However, the present invention is not limited to this, and can be applied to the scan latch circuit SKL2. It is also possible to apply to a latch circuit.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

FIG. 5 is a flowchart showing a scan path test circuit design method for a semiconductor integrated circuit according to the first embodiment of the present invention. It is an example figure which designed the logic circuit by the latch base. 1 is a logic circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a timing chart explaining a scan path test method according to the first embodiment of the present invention. It is another example figure which designed the logic circuit on the latch base. It is a logic circuit block diagram of the semiconductor integrated circuit according to the modification of Embodiment 1 of this invention. FIG. 10 is a timing chart illustrating a scan path test according to a modification of the first embodiment of the present invention. FIG. 10 is a circuit configuration diagram of a scan latch circuit according to the second embodiment. FIG. 10 is a circuit configuration diagram of a scan latch circuit according to a modification of the second embodiment.

Explanation of symbols

  1-3, 6-8 Logic unit, 4,10 AND circuit, 5,9 OR circuit, L1-L5, L1 # -L5 # latch circuit, SEL1-SEL3 selector, SKL1-SKL3, SKL1 # -SKL3 # scan latch circuit.

Claims (11)

A plurality of scan latch circuits that latch and output one of a plurality of signals input based on a clock signal having first and second logic levels;
A plurality of latch circuits which are arranged so as to be alternately connected in series between the plurality of scan latch circuits, and which latch and output an input signal complementary to the plurality of scan latch circuits. When,
Each is provided so as to be alternately connected in series between each of the scan latch circuits and each of the adjacent latch circuits, and a signal based on a predetermined logical operation operation according to one input is supplied to the other With a plurality of logic circuits to output,
At least one scan latch circuit of the plurality of scan latch circuits latches and outputs one of the plurality of signals based on the input of the clock signal and a predetermined control signal,
The semiconductor integrated circuit, wherein the predetermined control signal is fixed to one of the first and second logic levels during a test. The plurality of signals input to the first scan latch circuit among the plurality of scan latch circuits include a test data signal used during testing,
2. The semiconductor integrated circuit according to claim 1, wherein the plurality of signals input to another scan latch circuit among the plurality of scan latch circuits include an output signal latched in a preceding scan latch circuit. Each of the plurality of scan latch circuits includes a selector unit that selects one of the plurality of signals in response to a control signal;
The semiconductor integrated circuit according to claim 1, further comprising: a latch circuit that latches and outputs a signal selected by the selector unit based on at least one of the clock signal and the predetermined control signal. In the at least one scan latch circuit, the plurality of input signals include the predetermined control signal, an output signal of an adjacent logic circuit, and an output signal of a previous scan latch circuit,
The selector unit is
A first selector unit that selectively outputs the predetermined control signal and an output signal of the adjacent logic circuit based on a first control signal;
4. The semiconductor integrated circuit according to claim 3, further comprising: a second selector unit that selectively outputs an output signal of the first selector unit and an output signal of the preceding scan latch circuit based on a second control signal. . In the at least one scan latch circuit, the plurality of input signals include the predetermined control signal, an output signal of an adjacent logic circuit, and an output signal of a previous scan latch circuit,
The selector unit is
A first selector unit that selectively outputs the predetermined control signal and an output signal of the preceding scan latch circuit based on a first control signal;
4. The semiconductor integrated circuit according to claim 3, further comprising: a second selector unit that selectively outputs an output signal of the first selector unit and an output signal of the logic circuit in the previous stage based on a second control signal. Each includes a plurality of latch circuits that latch and output based on clock signals having first and second logic levels, and a plurality of logic units that are alternately connected in series with the plurality of latch circuits. A logic design process for designing a logic circuit;
In the logic circuit generated by the logic design process, the scan latch circuit is configured such that each of the group of latch circuits among the plurality of latch circuits is arranged with each of the other logic units sandwiching each logic unit. Replace and insert,
In the logic circuit, a process of searching for a clock gate that generates a gated clock generated based on a combination of a predetermined control signal and the clock signal;
And a process for inserting a gate control circuit for controlling the predetermined control signal input to the clock gate based on a search result.   The scan path test circuit design method according to claim 6, wherein the gate control circuit fixes the predetermined control signal to one of the first and second logic levels. The process of replacing each of the group of latch circuits with a scan latch circuit is inserted,
A process of inserting a selector in series with each latch circuit of the group of latch circuits;
A process in which the latch circuit of each of the group of latch circuits and the input signal of the inserted selector are made common, and the output signal of the preceding logic unit and the preceding scan latch circuit is selectively output through the selector. The scan path test circuit design method according to claim 6. The process of replacing each of the group of latch circuits with a scan latch circuit is inserted,
In the case where the scan latch circuit latches based on the gated clock,
A process of inserting a first selector in series with each latch circuit of the group of latch circuits;
A process in which input signals of the latch circuits of the group of latch circuits and the inserted first selector are made common, and a preceding logic unit and the predetermined control signal are selectively output through the first selector; ,
A process of inserting a second selector in series between the first selector and each latch circuit of the group of latch circuits;
The scan path test circuit design method according to claim 6, further comprising: a process of selectively outputting the output signal of the first selector and the output signal of the preceding scan latch circuit through the second selector. The process of replacing each of the group of latch circuits with a scan latch circuit is inserted,
In the case where the scan latch circuit latches based on the gated clock,
A process of inserting a first selector in series with each latch circuit of the group of latch circuits;
Processing for selectively outputting the predetermined control signal and the output signal of the preceding scan latch circuit through the first selector;
A process of inserting a second selector in series between the first selector and each latch circuit of the group of latch circuits;
The latch circuit of each of the group of latch circuits and the input signal of the inserted second selector are made common, and the output signal of the preceding stage logic circuit and the first selector is selectively output through the second selector. The scan path test circuit design method according to claim 6, further comprising: The process of replacing each of the group of latch circuits with a scan latch circuit is inserted,
11. The device according to claim 8, further comprising a process of inserting a slave latch circuit that latches an output signal of each latch circuit of the group of latch circuits and outputs the latched output signal to a subsequent scan latch circuit. Campus test circuit design method.

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