JP6988156B2 - Diagnostic circuit and control method of diagnostic circuit - Google Patents

Description

The present invention relates to a diagnostic circuit and a method for controlling the diagnostic circuit.

Boundary scan, which finds a failure by a plurality of flip-flops inserted in a boundary scan chain, is known as a failure diagnosis technique for semiconductor integrated circuits. Here, there is a technique for storing two data for one flip-flop circuit. For example, by inputting signals having opposite phases to the first latch portion and the second latch portion, the combination of the first latch portion and the second latch portion can be used as one scan flip-flop circuit. (For example, see Patent Document 1). Similarly, there is a technique of using two pulse latches as one flip-flop circuit (see, for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2005-3556 Japanese Patent Application Laid-Open No. 2003-255025

However, in the conventional technique, since the data of one latch overwrites the data of the other latch at the time of scan shift, the data stored in the other latch before the scan shift cannot be read correctly. As a result, it becomes difficult to determine whether or not the data stored before the scan shift was correctly written in the other latch.

Therefore, the present disclosure provides a diagnostic circuit and a method for controlling the diagnostic circuit, which enable the data stored in each latch in the scan chain to be correctly read out.

In one aspect of the disclosure,
It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a diagnostic circuit that scan-shifts the data
The first clock and the second clock in the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch. A clock control circuit that inverts the phases of the first clock and the second clock while maintaining the phase relationship with the clock in the opposite phase.
A spare latch, which is a latch different from the plurality of latches,
A switching circuit for switching whether or not to include the spare latch in the scan chain according to the first signal is provided between the first case and the second case.
The plurality of latches provide a diagnostic circuit that holds data selected according to a second signal different from the first signal.

Further, in one aspect of the present disclosure,
It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a control method of a diagnostic circuit that scan-shifts the data.
In the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch, the clock control circuit included in the diagnostic circuit is While maintaining the phase relationship between the first clock and the second clock in opposite phases, the phases of the first clock and the second clock are inverted.
Switched between when the first and when said second switching circuit, wherein the diagnostic circuitry is included in accordance with the first signal whether to include a pre-latch are different latch in the scan chain and the plurality of latches ,
The plurality of latches provide a method of controlling a diagnostic circuit that holds data selected according to a second signal different from the first signal.

According to the diagnostic circuit or the control method of the diagnostic circuit according to the present disclosure, the data stored in each latch in the scan chain can be correctly read out.

It is a figure which shows an example of the structure of the diagnostic circuit which concerns on this disclosure. It is a figure which shows an example of the structure of a clock control circuit. It is a time chart which shows an example of the operation when the data stored in the even-numbered latch is scan-shifted. It is a time chart which shows an example of the operation when the data stored in the odd-numbered latch is scan-shifted. It is a figure which shows an example of the structure of an integrated circuit. It is a figure which shows an example of the structure of the scan chain in which a plurality of scan flip-flops are connected. It is a time chart which shows an example of the operation of the scan chain in which a plurality of scan flip-flops are connected. It is a figure which shows an example of the structure of a register file. It is a figure which shows an example of the control method of the diagnostic circuit which concerns on this disclosure. It is a figure which shows another example of the structure of the diagnostic circuit which concerns on this disclosure.

Hereinafter, embodiments of the diagnostic circuit according to the present disclosure will be described with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of the diagnostic circuit according to the present disclosure. FIG. 1A is a diagram showing a circuit configuration of a diagnostic circuit including a plurality of latches connected in a scan chain. FIG. 1B is an operation image diagram in the case of scan-shifting the data stored in the even-numbered latch among the plurality of latches. FIG. 1 (c) is an operation image diagram in the case of scan-shifting the data stored in the odd-numbered latch among the plurality of latches. In FIGS. 1 (b) and 1 (c), M represents a master latch and S represents a slave latch.

The diagnostic circuit 11 shown in FIG. 1 is an example of a diagnostic circuit that scan-shifts the data stored in each of the plurality of latches. The diagnostic circuit 11 has a plurality of (four in the figure) latches 1 to 4, the same number of selectors 21 to 24 as the latches 1 to 4, a spare latch 41, and a selector 51.

The latches 1 to 4 and the spare latch 41 are circuits having an input terminal D, an output terminal M, and a clock terminal CK, respectively. Specific examples of the latches 1 to 4 and the spare latch 41 include a D latch.

In the present embodiment, the latches 1 to 4 and the spare latch 41 write the data input to the input terminal D when the level of the clock input to the clock terminal CK changes from the high level to the low level. Then, each of the latches 1 to 4 and the spare latch 41 write the data input to the input terminal D during the period when the clock level input to the clock terminal CK is low level, and the data input to the input terminal D. Is output from the output terminal M as it is. On the other hand, in each of the latches 1 to 4 and the spare latch 41, when the clock level input to the clock terminal CK changes from the low level to the high level, the data (or the transition thereof) input to the input terminal D at the time of the transition. The data output from the output terminal M at the time point) is held. Then, each of the latches 1 to 4 and the spare latch 41 output the retained data regardless of the logical level of the data input to the input terminal D during the period when the clock level input to the clock terminal CK is high level. Continuously output from terminal M.

The plurality of latches 1 to 4 latch the data selected by the selectors 21 to 24 provided in the preceding stage of each. When the low-level selection signal SE (SE = 0), which is an example of the first selection signal, is input, the selectors 21 to 24 are input data A1 which is not the output data of the latch provided in the preceding stage of each. ~ Select A4. On the other hand, when the high-level selection signal SE (SE = 1), which is an example of the second selection signal, is input, the selectors 21 to 24 select the output data of the latch provided in the preceding stage of each. ..

The selection signal SE is one of the signals input to the diagnostic circuit 11. The operation mode of the diagnostic circuit 11 is set to either the latch mode or the scan mode according to the selection signal SE. The latch mode represents a mode in which each of the latches 1 to 4 functions as a storage element for storing data. The scan mode represents a mode in which the scan test of the latches 1 to 4 is performed by passing the data for the scan test through the scan chain 10 including the latches 1 to 4.

When the level of the selection signal SE is the first level (for example, low level “0”, SE = 0), the operation mode of the diagnostic circuit 11 is set to the latch mode. On the other hand, when the level of the selection signal SE is the second level (for example, high level “1”, SE = 1), the operation mode of the diagnostic circuit 11 is set to the scan mode.

The selector 24 is provided in front of the latch 4. The selector 24 selects either the scan-in data input from the scan-in terminal SI or the first input data A1 based on the selection signal SE, and selects the selected signal as the input terminal D of the latch 4. Output to. When the level of the selection signal SE is a low level indicating the selection of the latch mode (SE = 0), the selector 24 selects the input data A1 and outputs the input data A1 to the input terminal D of the latch 4. On the other hand, when the level of the selection signal SE is a high level indicating the selection of the scan mode (SE = 1), the selector 24 selects the scan-in data input from the scan-in terminal SI and inputs the latch 4 to the input terminal D. Output to.

The latch 4 latches the output data of the selector 24 according to the clock CLK0. The latch 4 outputs the latched data from the output terminal M as output data M1 in synchronization with the clock CLK0. The latch 4 represents the fourth latch counting from the scanout terminal SO side.

The selector 23 is provided in front of the latch 3. The selector 23 selects either the output data M1 of the latch 4 or the second input data A2 based on the selection signal SE, and outputs the selected signal to the input terminal D of the latch 3. When the level of the selection signal SE is a low level indicating the selection of the latch mode (SE = 0), the selector 23 selects the input data A2 and outputs the input data A2 to the input terminal D of the latch 3. On the other hand, when the level of the selection signal SE is a high level indicating the selection of the scan mode (SE = 1), the selector 23 selects the output data M1 of the latch 4 and outputs it to the input terminal D of the latch 3.

The latch 3 latches the output data of the selector 23 according to the clock CLK1. The latch 3 outputs the latched data from the output terminal M as output data M2 in synchronization with the clock CLK1. Latch 3 represents the third latch counting from the scanout terminal SO side.

The selector 22 is provided in front of the latch 2. The selector 22 selects either the output data M2 of the latch 3 or the third input data A3 based on the selection signal SE, and outputs the selected signal to the input terminal D of the latch 2. When the level of the selection signal SE is a low level indicating the selection of the latch mode (SE = 0), the selector 22 selects the input data A3 and outputs the input data A3 to the input terminal D of the latch 2. On the other hand, when the level of the selection signal SE is a high level indicating the selection of the scan mode (SE = 1), the selector 22 selects the output data M2 of the latch 3 and outputs it to the input terminal D of the latch 2.

The latch 2 latches the output data of the selector 22 according to the clock CLK0. The latch 2 outputs the latched data from the output terminal M as output data M3 in synchronization with the clock CLK0. Latch 2 represents the second latch counting from the scanout terminal SO side.

The selector 21 is provided in front of the latch 1. The selector 21 selects either the output data M3 of the latch 2 or the fourth input data A4 based on the selection signal SE, and outputs the selected signal to the input terminal D of the latch 1. When the level of the selection signal SE is a low level indicating the selection of the latch mode (SE = 0), the selector 21 selects the input data A4 and outputs the input data A4 to the input terminal D of the latch 1. On the other hand, when the level of the selection signal SE is a high level indicating the selection of the scan mode (SE = 1), the selector 21 selects the output data M3 of the latch 2 and outputs it to the input terminal D of the latch 1.

The latch 1 latches the output data of the selector 21 according to the clock CLK1. The latch 1 outputs the latched data from the output terminal M as output data M4 in synchronization with the clock CLK1. Latch 1 represents the first latch counting from the scanout terminal SO side.

If all the latches 1 to 4 in the scan chain 10 operate according to the clocks having the same phase, the data will race from the latch 4 to the latch 1 when the scan shift is performed (during the scan operation). That is, the same data is written to all the latches 1 to 4 at once by one pulse of the clock. To prevent this, when the scan mode is selected, the clocks input to the adjacent latches in the scan chain 10 are set out of phase with each other. That is, when the scan mode is selected, the phase relationship between the clock CLK0 and the clock CLK1 is out of phase.

The diagnostic circuit 11 includes a spare latch 41 separate from the plurality of latches 1 to 4. The spare latch 41 is a circuit that latches the output data M4 of the latch 1 according to the clock CLK0. The spare latch 41 outputs the latched data from the output terminal M in synchronization with the clock CLK0.

The selector 51 scan-shifts the spare latch 41 in the case of scan-shifting the data stored in the even-numbered latches 2 and 4 and the case of scanning-shifting the data stored in the odd-numbered latches 1 and 3. Switch whether to include in. The selector 51 is an example of a switching circuit.

When the data stored in the even-numbered latches 2 and 4 is scan-shifted, the level of the scan selection signal OD becomes a low level (OD = 0). On the other hand, when the data stored in the odd-numbered latches 1 and 3 is scan-shifted, the level of the scan selection signal OD becomes a high level (OD = 1). The scan selection signal OD is one of the signals input to the diagnostic circuit 11.

Whether or not the selector 51 scans out the output data M4 of the first latch 1 in the last stage of the latches 1 to 4 via the spare latch 41 in the case of OD = 0 and the case of OD = 1. Switch between. When OD = 0, the selector 51 scans out the output data M4 of the first latch 1 without going through the spare latch 41. That is, when OD = 0, the selector 51 scans out the output data M4 as scanout data from the scanout terminal SO without passing it through the spare latch 41. On the other hand, when OD = 1, the selector 51 scans out the output data M4 of the first latch 1 via the spare latch 41. That is, when OD = 1, the selector 51 passes the output data M4 through the spare latch 41 and scans out the output data M4 from the scanout terminal SO as scanout data.

Diagnostic circuitry 11 includes a clock control circuit for controlling each of the phases of the clocks CLK1 and CLK 0.

FIG. 2 is a diagram showing an example of the configuration of the clock control circuit. Clock control circuit 30 shown in FIG. 2 controls each of phases of the clocks CLK1 and CLK 0. The clock control circuit 30 has selectors 31 and 32 and inverters 33 and 34.

The inverter 33 outputs a signal in which the logic of the clock CLK, which is one of the signals input to the diagnostic circuit 11, is inverted. The inverter 34 outputs a signal obtained by inverting the logic of the signal output from the selector 31.

When the level of the scan selection signal OD is low level (OD = 0), the selector 31 selects the clock CLK and outputs the clock CLK as the clock CLK0. On the other hand, when the level of the scan selection signal OD is high level (OD = 1), the selector 31 selects the output signal of the inverter 33 and outputs the output signal of the inverter 33 as the clock CLK0.

When the level of the selection signal SE is a low level indicating the selection of the latch mode (SE = 0), the selector 32 selects the output signal of the selector 31 and outputs the output signal of the selector 31 as the clock CLK1. On the other hand, when the level of the selection signal SE is a high level indicating the selection of the scan mode (SE = 1), the selector 32 selects the output signal of the inverter 34 and outputs the output signal of the inverter 34 as the clock CLK1.

That is, when the latch mode is selected (SE = 0), the clock control circuit 30 outputs clock CLK0 and clock CLK1 having the same phase. On the other hand, when the scan mode is selected and the data stored in the even-numbered latches 2 and 4 is scan-shifted (SE = 1 and OD = 0), the clock control circuit 30 has a phase relationship between the clock CLK0 and the clock CLK1. To be out of phase. On the other hand, when the scan mode is selected and the data stored in the odd-numbered latches 1 and 3 is scan-shifted (SE = 1 and OD = 1), the clock control circuit 30 has a phase relationship between the clock CLK0 and the clock CLK1. To be out of phase.

Thus, the clock control circuit 30 in the OD = 0 and OD = 1, while maintaining the phase relationship between the clock CLK0 and the clock CLK2 in opposite phase, to reverse the respective phases of the clock CLK1 and clock CLK 0 It is possible.

Next, an operation example of the diagnostic circuit 11 will be described.

FIG. 3 is a time chart showing an example of the operation of the diagnostic circuit when the even-numbered latch is scan-shifted. FIG. 3 shows an operation example in which the data stored in each of the even-numbered latches 2 and 4 counted from the scanout terminal SO shown in FIG. 1 is read from the scanout terminal SO. In FIG. 3, first, it is assumed that the data A, B, C, and D are stored in the latches 4, 3, 2, and 1, respectively. The operation shown in FIG. 3 will be described with reference to FIG.

At the timing t1 when the level of the selection signal SE transitions to the high level indicating the selection of the scan mode, the clock CLK0 is the high level. Therefore, the even-numbered latches 2 and 4 output the held data from the output terminal M regardless of the logical level of the data input to the input terminal D. On the other hand, since the clock CLK1 is low level at the timing t1, the odd-numbered latches 1 and 3 write the data input to the input terminal D and output the data input to the input terminal D as it is from the output terminal M. .. Therefore, at the timing t1, the data A pre-stored in the latch 4 is written in the latch 3, and the data C pre-stored in the latch 2 is written in the latch 1. Therefore, the data C stored in advance in the latch 2 is output from the scanout terminal SO via the latch 1 and the selector 51 to which the OD = 0 is input.

Next, since the clock CLK0 transitions to the low level at the timing t2, the even-numbered latches 2 and 4 write the data input to the input terminal D, and the data input to the input terminal D is directly transmitted from the output terminal M. Output. On the other hand, since the clock CLK1 transitions to the high level at the timing t2, the odd-numbered latches 1 and 3 output the held data from the output terminal M regardless of the logical level of the data input to the input terminal D. Therefore, the data A written in the latch 3 at the timing t1 is written in the latch 2.

Next, since the clock CLK1 transitions to the low level at the timing t3, the odd-numbered latch 1 writes the data input to the input terminal D and outputs the data input to the input terminal D as it is from the output terminal M. .. On the other hand, since the clock CLK0 transitions to the high level at the timing t3, the even-numbered latch 2 outputs the held data from the output terminal M regardless of the logical level of the data input to the input terminal D. Therefore, the data A written in the latch 2 at the timing t2 is written in the latch 1. Therefore, the data A stored in advance in the latch 4 is output from the scanout terminal SO via the latch 1 and the selector 51 to which the OD = 0 is input.

That is, according to the diagnostic circuit according to the present embodiment, it is possible to correctly read the data C and A stored in advance in the latches 2 and 4 from the scanout terminal SO.

FIG. 4 is a time chart showing an example of the operation of the diagnostic circuit when the odd-numbered latch is scan-shifted. FIG. 4 shows an operation example in which the data stored in each of the odd-numbered latches 1 and 3 counted from the scanout terminal SO shown in FIG. 1 is read from the scanout terminal SO. Also in FIG. 4, it is assumed that the data A, B, C, and D are stored in the latches 4, 3, 2, and 1, respectively. The operation shown in FIG. 4 will be described with reference to FIG.

At the timing t11 when the level of the selection signal SE transitions to the high level indicating the selection of the scan mode, the clock CLK0 is the low level. Therefore, the even-numbered latches 2 and 4 write the data input to the input terminal D, and output the data input to the input terminal D as it is from the output terminal M. On the other hand, since the clock CLK1 is at a high level at the timing t11, the odd-numbered latches 1 and 3 output the held data from the output terminal M regardless of the logical level of the data input to the input terminal D. Therefore, at the timing t11, the data B pre-stored in the latch 3 is written in the latch 2, and the data D pre-stored in the latch 1 is written in the spare latch 41. Since the clock CLK0 is low level, the spare latch 41 writes the data input to the input terminal D and outputs the data input to the input terminal D as it is from the output terminal M. Therefore, the data D stored in advance in the latch 1 is output from the scanout terminal SO via the spare latch 41 and the selector 51 to which the OD = 1 is input.

Next, since the clock CLK0 transitions to the high level at the timing t12, the even-numbered latches 2 and 4 output the retained data from the output terminal M regardless of the logical level of the data input to the input terminal D. .. On the other hand, since the clock CLK1 transitions to the low level at the timing t12, the odd-numbered latches 1 and 3 write the data input to the input terminal D and output the data input to the input terminal D as it is from the output terminal M. do. Therefore, the data B written in the latch 2 at the timing t11 is written in the latch 1.

Next, since the clock CLK1 transitions to the high level at the timing t13, the odd-numbered latch 1 outputs the retained data from the output terminal M regardless of the logical level of the data input to the input terminal D. On the other hand, since the clock CLK0 transitions to the low level at the timing t13, the spare latch 41 writes the data input to the input terminal D and outputs the data input to the input terminal D as it is from the output terminal M. Therefore, the data B written in the latch 1 at the timing t12 is written in the spare latch 41. Therefore, the data B stored in advance in the latch 3 is output from the scanout terminal SO via the spare latch 41 and the selector 51 to which the OD = 1 is input.

That is, according to the diagnostic circuit 11 according to the present embodiment, the data D and B stored in advance in each of the latches 1 and 3 can be correctly read out from the scanout terminal SO.

In this way, the diagnostic circuit 11 is stored in advance in the latches 1 to 4 by scanning-shifting the data stored in the even-numbered latch and the data stored in the odd-numbered latch in two steps. Data can be correctly scanned out from the scanout terminal SO. That is, when OD = 0 in FIG. 1 (b), even if the data stored in advance in the odd-numbered latch is overwritten by the data in the even-numbered latch in the previous stage at the time of scan shift, in FIG. 1 (c). When OD = 1, the data stored in advance in the odd-numbered latch can be correctly read out. Therefore, the data stored in each latch in the scan chain can be read correctly.

FIG. 5 is a diagram showing an example of the configuration of an integrated circuit. The integrated circuit 100 shown in FIG. 5 includes a register file 80, scan flip-flops (SFF) 61 to 64, and scan flip-flops (SFF) 71 to 74. Further, the integrated circuit 100 includes a plurality of external connection terminals. An inspection device (not shown) that scan-tests the integrated circuit 100 and / or the register file 80 is connected to these external connection terminals. The inspection device inputs the test data-in signal TDI, the clock CLK, the selection signal SE, and the scan selection signal OD via these external connection terminals. Further, the inspection device acquires the test data out signal TDO via the external connection terminal.

The test data-in signal TDI is data that is shifted in to the boundary scan chain including SFF61-64. The test data out signal TDO is data that is shifted out from the boundary scan chain including SFF71 to 74.

The test data-in signal TDI is input to the SFF64 as a scan-in signal, and the scanout data output from the SFF61 is input to the scan-in terminal of the register file 80. The scanout data output from the scanout terminal of the register file 80 is input to the SFF74, and the scanout data output from the SFF71 is output as a test data out signal TDO.

The storage element unit in the register file 80 has the same configuration as that in FIG. The SFF 61 to 64, 71 to 74 connected to the front and rear stages of the register file 80 have the same configuration as that of FIG. The SFF 61 to 64 in the first stage of FIG. 5 correspond to the SFF 101 to 104 of FIG. 6, respectively. SFF 71 to 74 in the latter part of FIG. 5 correspond to SFF 101 to 104 in FIG. 6, respectively.

FIG. 6 is a diagram showing an example of a configuration of a scan chain in which a plurality of scan flip-flops are connected. FIG. 6A is a diagram showing a circuit configuration of a boundary scan chain in which a plurality of SFFs are connected. FIG. 6B is an operation image diagram in the case of scan-shifting the data stored in each of the plurality of SFFs. In FIG. 6B, M represents a master latch and S represents a slave latch.

The scan chain shown in FIG. 6 has a plurality of (four in the illustration) SFF 101-104 and the same number of selectors 121-124 as the SFF 101-104.

SFF101 to 104 are circuits having an input terminal D, an output terminal M, and a clock terminal CK, respectively. Specific examples of SFF 101 to 104 include D flip-flops. The D flip-flop has a structure in which two D latches, a master latch and a slave latch, are connected.

The plurality of SFFs 101 to 104 latch the data selected by the selectors 121 to 124 provided in the preceding stage of each. When the low-level selection signal SE (SE = 0), which is an example of the first selection signal, is input, the selectors 121 to 124 are input data B1 which is not the output data of the latch provided in the preceding stage of each. Select ~ B4. On the other hand, when the high-level selection signal SE (SE = 1), which is an example of the second selection signal, is input, the selectors 121 to 124 select the output data of the latch provided in the preceding stage of each. ..

The SFF 104 latches the output data of the selector 124 according to the clock CLK. The SFF 104 outputs the latched data as output data Q1 from the output terminal M in synchronization with the clock CLK. Similarly, the SFF 103, 102, and 101 output the data latched by each of them as output data Q2, Q3, and Q4 from the output terminal M in synchronization with the clock CLK.

FIG. 7 is a time chart showing an example of the operation of a scan chain in which a plurality of scan flip-flops are connected. In FIG. 7, it is assumed that data A, B, C, and D are first stored in SFF 104, 103, 102, and 101, respectively. As is well known, the scan chain shown in FIG. 6 scans out data D, C, B, and A in this order according to the clock CLK.

FIG. 8 is a diagram showing an example of the structure of the register file. The register file 80 includes a latch unit 81, a read unit 82, a write unit 83, and a clock control circuit 30.

The latch unit 81 is an example of a storage unit having a configuration of (n + 1) bits × (m + 1) words. When the read access signal RA is active, the lead unit 82 reads out the data stored in the latch unit 81 and outputs the data to the read terminal RD. The lead unit 82 is, for example, a (m + 1) to 1 multiplexer. The write unit 83 makes the word data WD writable in one of the (m + 1) words. The clock control circuit 30 has the configuration shown in FIG.

The latch portion 81 has the same configuration as that of FIG. 1 although the number of latches is different, and has a configuration in which (n + 1) × (m + 1) latches are included in the scan chain. The write unit 83 is a circuit that calculates the logical product of (m + 1) decode circuit signals WA, clock CLK0, and clock CLK1. By operating this circuit configuration as shown in the flowchart of FIG. 9, it becomes possible to determine whether the lead unit 82 has failed or the write unit 83 has failed.

FIG. 9 is a diagram showing an example of a control method of the diagnostic circuit according to the present disclosure. The inspection device sets SE = 1 and OD = 0, and sets the value to be written in the register file 80 for SFF61 to 64 in the previous stage of the register file 80 as the test data-in signal TDI by inputting the clock CLK. (Steps S11 to S15).

The inspection device sets SE = 0 (step S21) and operates the clock CLK once (step S23). At this point, the value set in step S11 is written to the latch portion 81 in the register file 80. Further, the inspection device inputs the same set values to the preceding stages SFF61 to 64 (step S25No, step S11), and operates the clock CLK once (step S23). At this point, the value read from the register file 80 is written to SFF71 to 74 in the subsequent stage of the register file 80, and the same value is also written to the latch portion 81 in the register file 80 (step S25Yes).

The inspection device is set to SE = 1 (step S31). When scanning the even-numbered latches 2 and 4, the inspection device sets OD = 0 and inputs the necessary clocks CLK0 and CLK1 to perform a scan shift (steps S33Yes, S37). On the other hand, when scanning the odd-numbered latches 1 and 3, the inspection device sets OD = 1 and inputs the necessary clocks CLK0 and CLK1 to perform a scan shift (steps S33No, S35, S37). The inspection device compares the test data out signal TDO with the expected value (step S39).

The inspection device determines whether or not there is an error (failure) in the latches 1 to 4 in the register file 80 based on the comparison result (step S41), and determines that there is no error in the latches 1 to 4. , It is determined whether or not there is an error in SFF (step S43). When the inspection device determines that there is no error in SFF, the integrated circuit 100 determines that there is no failure (step S45), and when it determines that there is an error in SFF, it determines that there is an error in reading by the lead unit 82. ..

On the other hand, the inspection device determines whether or not there is an error (failure) in the latches 1 to 4 in the register file 80 based on the comparison result (step S41), and determines that there is an error in the latches 1 to 4. If so, the process of step S49 is executed. In step S49, the inspection device determines whether or not there is an error other than the error in the latches 1 to 4. When the inspection device determines that there is no error other than the error in the latches 1 to 4, it determines that there is an error in the writing by the write unit 83 (step S51). On the other hand, when the inspection device determines that there is an error other than the error in the latches 1 to 4, it determines that there is an error in both the writing by the write unit 83 and the reading by the read unit 82 (step S55).

In this way, the inspection device can determine whether the failure occurs at the time of writing the register file 80 or at the time of reading the register file 80. In addition, since the failure of the write part and the lead part can be isolated, the time until the remake can be shortened, and the cost can be reduced. Further, since a simple latch is used instead of the SFF for the storage element that does not require data setting in boundary scan, there is an effect of reducing the size and power consumption.

FIG. 10 is a diagram showing another example of the configuration of the diagnostic circuit according to the present disclosure. FIG. 10A is a diagram showing a circuit configuration of a diagnostic circuit including a plurality of latches connected in a scan chain. FIG. 10B is an operation image diagram in the case of scan-shifting the data stored in the even-numbered latch among the plurality of latches. FIG. 10C is an operation image diagram in the case of scan-shifting the data stored in the odd-numbered latch among the plurality of latches. In FIGS. 10 (b) and 10 (c), M represents a master latch and S represents a slave latch.

As shown in FIG. 10, the diagnostic circuit 12 includes a spare latch 41 and a selector 51 provided in the rear stage of the last stage latch 1 and a spare latch 42 and a selector 52 provided in the front stage of the front stage latch 4. To prepare for.

The spare latch 42 is a circuit that latches the scan-in data input from the scan-in terminal according to the clock CLK1. The spare latch 42 outputs the latched data from the output terminal M in synchronization with the clock CLK1. The selector 52 scan-shifts the spare latch 42 in the case of scan-shifting the data stored in the even-numbered latches 2 and 4 and the case of scanning-shifting the data stored in the odd-numbered latches 1 and 3. Switch whether to include in. The selector 52 is an example of the second switching circuit.

Even with such a configuration, the data stored in advance in the latches 1 to 4 can be correctly scanned out from the scanout terminal SO as in FIG. 1.

Although the diagnostic circuit and the control method of the diagnostic circuit have been described above by the embodiment, the present invention is not limited to the above embodiment. Various modifications and improvements, such as combinations and substitutions with some or all of the other embodiments, are possible within the scope of the present invention.

Further, the following additional notes will be disclosed with respect to the above embodiments.
(Appendix 1)
It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a diagnostic circuit that scan-shifts the data
The first clock and the second clock in the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch. A clock control circuit that inverts the phases of the first clock and the second clock while maintaining the phase relationship with the clock in the opposite phase.
A spare latch, which is a latch different from the plurality of latches,
A diagnostic circuit comprising a switching circuit for switching whether or not to include the spare latch in the scan chain between the first case and the second case.
(Appendix 2)
The spare latch holds data according to the first clock.
The switching circuit determines whether or not to output the output data of the first latch in the last stage of the plurality of latches via the spare latch in the first case and the second case. The diagnostic circuit according to Appendix 1 for switching.
(Appendix 3)
In the first case, the switching circuit outputs the output data of the first latch without passing through the spare latch, and in the second case, the output data of the first latch is output of the spare latch. The diagnostic circuit according to Appendix 2, which outputs data via.
(Appendix 4)
The plurality of latches hold the data selected by the selector provided in front of each latch.
The selector selects the input data that does not scan shift when the first selection signal is input, and selects the data that scan shifts when the second selection signal is input, from Appendix 1. The diagnostic circuit according to any one of 3.
(Appendix 5)
The diagnostic circuit according to any one of Supplementary note 1 to 4, wherein the latch is a D latch.
(Appendix 6)
It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a control method of a diagnostic circuit that scan-shifts the data.
In the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch, the clock control circuit included in the diagnostic circuit is While maintaining the phase relationship between the first clock and the second clock in opposite phases, the phases of the first clock and the second clock are inverted.
In the diagnostic circuit, in the first case and the second case, the switching circuit included in the diagnostic circuit switches whether or not a spare latch, which is a latch different from the plurality of latches, is included in the scan chain. Control method.
(Appendix 7)
The spare latch holds data according to the first clock.
In Appendix 6, the output data of the first latch in the last stage of the plurality of latches is switched between the first case and the second case, and whether or not the output data of the first latch in the last stage is output via the spare latch. The method of controlling the diagnostic circuit described.
(Appendix 8)
In the first case, the output data of the first latch is output without passing through the spare latch, and in the second case, the output data of the first latch is output via the spare latch. The method for controlling the diagnostic circuit according to Appendix 7.
(Appendix 9)
The plurality of latches hold the data selected by the selector provided in front of each latch.
The selector selects the input data that does not scan shift when the first selection signal is input, and selects the data that scan shifts when the second selection signal is input, from Appendix 6. 8. The method for controlling a diagnostic circuit according to any one of 8.
(Appendix 10)
The method for controlling a diagnostic circuit according to any one of Supplementary note 6 to 9, wherein the latch is a D latch.

1-4 Latch 10 Scan chain 11 Diagnostic circuit 21-24 Selector 30 Clock control circuit 41 Spare latch 51 Selector 80 Register file 81 Latch 100 Integrated circuit

Claims (9)

It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a diagnostic circuit that scan-shifts the data
The first clock and the second clock in the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch. A clock control circuit that inverts the phases of the first clock and the second clock while maintaining the phase relationship with the clock in the opposite phase.
A spare latch, which is a latch different from the plurality of latches,
A switching circuit for switching whether or not to include the spare latch in the scan chain according to the first signal is provided between the first case and the second case.
The plurality of latches are diagnostic circuits that hold data selected according to a second signal different from the first signal. The diagnostic circuit according to claim 1, wherein the plurality of latches hold the output data of the latches provided in the preceding stage according to the second signal. The diagnostic circuit according to claim 1, wherein the plurality of latches hold data selected according to the second signal by a selector provided in the preceding stage of each. The selector selects input data that is not the output data of the latch provided in each pre-stage when the second signal is at the first level, and when the second signal is at the second level, each pre-stage. The diagnostic circuit according to claim 3, wherein the output data of the latch provided in the above is selected. The diagnosis according to any one of claims 1 to 4, wherein the clock control circuit controls the phases of the first clock and the second clock according to the first signal and the second signal. circuit. The clock control circuit outputs the first clock and the second clock in the same phase when the second signal is at the first level, and when the second signal is at the second level, the first clock is output. The diagnostic circuit according to any one of claims 1 to 5, which outputs the clock of 1 and the second clock in opposite phases. The spare latch holds data according to the first clock.
The switching circuit determines whether or not to output the output data of the first latch in the last stage of the plurality of latches via the spare latch in the first case and the second case. The diagnostic circuit according to any one of claims 1 to 6, which is switched. In the first case, the switching circuit outputs the output data of the first latch without passing through the spare latch, and in the second case, the output data of the first latch is output of the spare latch. The diagnostic circuit according to claim 7 , wherein the data is output via the above. It comprises a scan chain including an even-numbered latch that holds data according to a first clock and an odd-numbered latch that holds data according to a second clock, and is held by each of a plurality of latches included in the scan chain. It is a control method of a diagnostic circuit that scan-shifts the data.
In the first case of scan-shifting the data held in the even-numbered latch and the second case of scanning-shifting the data held in the odd-numbered latch, the clock control circuit included in the diagnostic circuit is While maintaining the phase relationship between the first clock and the second clock in opposite phases, the phases of the first clock and the second clock are inverted.
Switched between when the first and when said second switching circuit, wherein the diagnostic circuitry is included in accordance with the first signal whether to include a pre-latch are different latch in the scan chain and the plurality of latches ,
A method of controlling a diagnostic circuit , wherein the plurality of latches hold data selected according to a second signal different from the first signal.

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