WO2016068573A1

WO2016068573A1 - Chip test time minimizing method and device therefor

Info

Publication number: WO2016068573A1
Application number: PCT/KR2015/011374
Authority: WO
Inventors: 송재훈
Original assignee: (주)이노티오
Priority date: 2014-10-29
Filing date: 2015-10-27
Publication date: 2016-05-06
Also published as: TW201625973A

Abstract

Disclosed is a scan test time minimizing method and a device therefor. The scan test time minimizing device splits a plurality of scan patterns into at least two or more scan sections, and for each scan section, identifies a first shift frequency by which, through the increase/decrease of the shift frequency, a scan chain output pattern differs from a prediction pattern, and then the device sets a second shift frequency that is smaller than the first shift frequency as the shift frequency of each scan section. Further, the present invention has the effect of minimizing a burn-in test time and increasing the quality of the burn-in test.

Description

Method and apparatus for minimizing chip test time

The present invention relates to integrated circuit (IC) chip testing, and more particularly, to a method and apparatus for minimizing time of chip testing by optimizing scan shift frequency.

The most common way to test an IC chip is to apply test data to the IC chip's input and compare the observed value at the IC chip's output with a known predicted value. However, if you want to test an IC chip that contains a sequential logic with storage elements such as flip-flop, externally apply the desired value to the flip-flop in the IC chip or the value of the flip-flop. It is very difficult to observe from outside. There is a scan design method to solve this problem.

The scan design method is one of the design for testability (DFT) methods considering the test used to increase the controllability and observability of the circuit. Using the scan design method, a small but high fault coverage test is performed using the Automatic Test Pattern Generator (ATPG) software, which automatically generates test patterns based on the structural information of the circuit. Data can be obtained.

In other words, the scan design turns sequential logic into combinational logic during the scan test, making it easier to control and observe the circuit outside the chip, and minimize the size of the test data through ATPG. have. Test data obtained through scan design and ATPG software consists of at least one scan pattern. In general, scan patterns are ordered in the performance of scan tests. The test pattern set consists of one or more scan patterns.

1 is a diagram illustrating an example of an IC chip to which a conventional scan design method is applied.

Referring to FIG. 1, the IC chip 100 is a sequential logic composed of at least one combination circuit 110 and a plurality of flip-

flops

120, 130, and 140. In the case of FIG. 1, the flip-

flops

120, 130, and 140 may be a scan flip-flop of a multiplexer (MUX) method, or various other methods.

The IC chip 100 may include a primary input (PI) port 150, a primary output (PO) port 152, a scan enable (SE) port 160, and a scan input port 162. ), A clock input port 164, a scan output port 166, and the like. The scan activation port 160 and the clock input port 164 are connected to the flip-

flops

120, 130, and 140, respectively. Each flip-

flop

120, 130, 140 may be connected to the combination circuit 110 to output a value stored in each flip-flop to the combination circuit, and receive a value output from the combination circuit.

The main input port 150 and the main output port 152 are ports for inputting and outputting data during normal operation of the IC chip.

The scan activation port 160 is a port for inputting a scan enable signal or a scan disable signal, and according to the scan enable signal or the scan disable signal, the IC chip enters a normal or functional mode in which a normal operation is performed. The scan mode is tested to test the IC chip.

The scan input port 162 is a port for inputting a scan pattern for testing the IC chip 100, and the scan output port 166 is a port for outputting a test result based on the scan pattern. The bit pattern output through the scan output port is called an output scan pattern or an output pattern, and may be, for example, a scan test result pattern.

The clock input port 164 shifts and loads a scan pattern input through the scan input port 162 to the flip-

flops

120, 130, and 140, or captures the output of the combination circuit 110 on the flip-

flops

120, 130, and 140. It is a port to input clock signal for triggering. For example, the flip-

flops

120, 130, and 140 are triggered by the rising edge or the falling edge of the clock signal input through the clock input port 164 to store or capture an input value.

A path (dashed path) connected to the scan output port 166 through the plurality of flip-

flops

120, 130, and 140 from the scan input port 162 is called a scan chain or a scan path. 1 illustrates a single scan chain, a plurality of scan chains may be used.

In the functional mode, the combination circuit 110 performs a normal operation of receiving data through the main input port 150 and outputting a result through the main output port 152. In addition, in the function mode, the flip-

flops

120, 130, and 140 receive an output value of the combination circuit 110 according to the clock signal, and this operation is called scan capture during the scan test.

In scan mode, each bit of the scan pattern is sequentially shifted-in to flip-

flops

120, 130, and 140 present on the scan path in accordance with the clock signal, and sequentially through the scan output port 166. It is shifted out. Here, a state in which the scan pattern is shifted-in to the flip-

flops

120, 130, and 140 is called a load, and an unloaded state in which the value stored in the flip-

flop

120, 130, and 140 is shifted out through the scan output port 166 is unloaded. ).

For example, if the number of flip-

flops

120, 130, 140 on the scan chain in the IC chip is three, the length of each scan pattern consists of three bits of length equal to the number of flip-flops on the scan chain, and the three-bit scan pattern is The shift signals are sequentially shifted into the flip-

flops

120, 130 and 140 on the scan chain according to the clock signal. That is, when a value is stored in the flip-flop on the rising edge of the clock signal, the first bit of the scan pattern is input and stored in the first flip-flop 140 on one rising edge of the clock signal, and then stored in the next clock signal. The output value of the first flip-flop 140 is stored in the second flip-flop 130, and the second flip-flop 140 stores the second bit value of the scan pattern. In the next clock signal, the output value of the second flip-flop 130 is stored in the third flip-flop 120, and the output value of the first flip-flop 140 is stored in the second flip-flop 130, and the first The third flip-flop 140 stores the third bit value of the scan pattern. Therefore, one scan pattern is loaded into the flip-

flops

120, 130 and 140 on the scan chain with three clock signals. Similarly, with the three clock signals, the values of the flip-

flops

120, 130 and 140 on the scan chain are unloaded through the scan output port 166.

In more detail, the general scan test process is as follows.

(1) Main input test data is applied to the main input port 150 of the IC chip 100.

(2) The scan activation signal is applied to the scan activation port 160 to make the chip 100 in the scan mode.

(3) Shift-in the scan pattern to the scan input port 162 to load the scan pattern to the flip-

flops

120, 130 and 140 on the scan chain. The scan pattern loaded in the scan chain is applied to the combination circuit 110. After the scan pattern is applied to the combination circuit, the result output through the main output port 152 is compared with the predicted main output value. If the comparison result is different, the IC chip is defective.

(4) The scan deactivation signal is applied to the scan activation port 160 to switch the chip 100 from the scan mode to the function mode. In the functional mode, when a clock signal is applied, the flip-

flops

120, 130, and 140 capture the output values of the combination circuit 110, and this operation is called scan capture, and this mode is also called a scan capture mode.

(5) The scan activation signal is applied to the scan activation port 160 to switch the chip back from the functional mode to the scan mode.

(6) Then, the values captured in the flip-

flops

120, 130, and 140 on the scan chain are shifted out through the scan output port 166 and unloaded.

(7) The unloaded output pattern is compared with a known prediction pattern to determine whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern that is output through the scan output port 166 after applying the main input test data and the scan pattern and performing the scan capture operation when the IC chip is normal, and is a value known before the test. That is, if the comparison result in step (3) and the comparison result in step (7) are the same, that is, if the test result is pass, the IC chip is good and the IC chip is defective.

There are two types of scan tests: stuck-at-fault tests and delay fault tests. Here, the fixing failure refers to a problem in which a signal line on the IC chip is inadvertently stuck to a logic 0 or logic 1 value, and the delay failure refers to any signal line or path on the IC chip. When passing the signal value through the path, it means a failure that does not meet the specifications of the IC chip due to the delay time.

Types of delay failure tests also include transition delay tests and path delay tests. The transition delay test is to test whether a specific node or signal line on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay problem. The path delay test is to test whether a particular path on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem.

Representative methods for delay failure testing include launch-on-capture and launch-on-shift methods, which also scan the scan pattern for delay failure testing. It consists of a load operation that shifts in on the chain and an unload operation that shifts out the delayed test results that are captured by flip-flops on the scan chain.

In the conventional scan test, since the number of clock pulses for shifting the number of flip-flops on the scan chain is required, there is a problem in that it takes a lot of time due to the shift-in and shift-out operations. However, you can't simply increase the clock signal's frequency, or shift frequency, to reduce test time.

For example, simply increasing the scan shift frequency may cause an overkill problem in which a good product is judged to be defective due to a power consumption or a critical path delay time.

In addition to deep sub-micron (DSM) microprocessing and low-power processes, as well as lower power designs, IC chips are becoming more power-lower, and the impact of power supply noise on IC chip operating frequencies is higher. In particular, since the IC chip generates more switching operation in scan mode than in function mode, the additional delay of the signal line caused by power supply noise due to switching operation can cause delay test overkill, which simply increases the shift frequency. There is a limit.

In addition, the issue of signal integrity due to signal crosstalk on IC chips has become more important as the DSM fine process proceeds. More switching behavior occurs in scan mode, resulting in more interference between signal lines. Therefore, an additional delay occurring in the signal line due to the interference between the signal lines during the delay test may cause the delay test overkill.

In addition, when the shift frequency is found based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the IC chip specification, due to the influence of excessive circuit switching operation and process variation on the IC chip due to the scan test characteristics, the IR Scan test error problems can occur due to -drop or ground-bounce. For example, in a delay test using a scan pattern, the effects of IR-drop, or voltage drop, can cause additional delays on certain signal lines, which can cause delay test overkill. In contrast, even if the power consumption of the scan pattern exceeds the specifications of the IC chip, IR-drop or ground-bounce problems may not occur due to the process and design characteristics of the chip. Therefore, there is a limit to finding the optimal shift frequency for the IC chip with only the power consumption value. In addition, in the case of finding the maximum shift frequency using only the power consumption value of the scan pattern, the critical shift timing problem may occur on the scan chain due to the increased shift frequency even if the power consumption value does not exceed the IC chip specification. have.

In addition, increasing the shift frequency may cause a critical path timing problem on the scan chain, but may not cause a logical problem due to the scan pattern. In other words, depending on the state of the bit value on the critical path of the scan chain, the case of a false critical path may occur in a particular scan shift cycle.

In addition, low-power IC chips that use multiple voltage island or voltage domain or region techniques provide high voltages for design areas that require high speed performance, and relatively low voltages for areas that do not. As a result, the permissible power consumption is different for each voltage region.

SUMMARY OF THE INVENTION The present invention provides a method for minimizing chip test time by optimizing a shift frequency used to shift-in or shift-out a scan pattern into a scan chain for each scan section to minimize scan test time or burn-in test time. To provide the device.

An example of the chip test time minimization method according to the present invention for achieving the above technical problem, for each of the at least two or more scan sections, the output pattern of the scan chain obtained by increasing or decreasing the shift frequency or the period of the shift frequency Determining a first shift frequency based on a result of comparing a to a prediction pattern, wherein the shift frequency or the period of the shift frequency is the frequency or frequency of the shift-in or shift-out of the scan section.

Another example of the method for minimizing chip test time according to the present invention for achieving the above technical problem includes determining a different shift frequency for each of the at least two scan sections; for each scan section The determined shift frequency is characterized in that the output pattern of the scan chain is smaller than the shift frequency which is different from the prediction pattern.

In order to achieve the above technical problem, an example of an apparatus for minimizing chip test time according to the present invention may include: a frequency increase and decrease unit configured to increase or decrease a scan shift frequency; A pattern input unit configured to input a scan pattern including at least one scan section into a scan chain; A pattern comparison unit to determine whether an output pattern of the scan chain is identical to a prediction pattern; And a frequency grading unit that grasps a shift frequency smaller than a shift frequency at a point in time at which the output pattern and the prediction pattern are different as possible shift frequencies of the scan section, wherein each of the shift frequencies identified for at least two scan sections is included. Some or all of them are different from each other.

Another example of a method for minimizing chip test time according to the present invention for achieving the above technical problem is power consumption or consumption when shifting a scan section in a scan chain at a predetermined initial shift frequency among at least two scan sections. And determining, for at least one scan section whose current is above or above a predetermined threshold, an output frequency of the scan chain is equal to a prediction pattern.

Another example of the method for minimizing chip test time according to the present invention for achieving the above technical problem is that the power consumption or current consumption when shifting the first scan section and the second scan section in the scan chain is a preset threshold. Determining a first shift frequency and a second shift frequency that are above or above a value; And determining a third shift frequency and a fourth shift frequency when the power consumption or current consumption when shifting the third scan section and the fourth scan section to the scan chain is less than or equal to the threshold value. The first shift frequency and the second shift frequency are different from each other, and the third shift frequency and the fourth shift frequency are the same.

According to another aspect of the present invention, there is provided a chip test time minimizing apparatus, including: a power detector configured to detect power consumption or current consumption when shifting a scan section to a scan chain at a first shift frequency; A first frequency grasp for identifying or determining the first shift frequency or less as a possible shift frequency of the scan section for at least one or more scan sections whose power consumption or current consumption by the first shift frequency is below or below a predetermined threshold; part; And identifying or determining at least one second shift frequency for at least one scan section in which power consumption or current draw is above or above the threshold, the output pattern of the scan chain being equal to a prediction pattern. 2 frequency grasping unit; includes.

In order to achieve the above technical problem, an example of a method of minimizing chip test time according to the present invention includes shifting the scan sections to a scan chain using different shift frequencies assigned to each of at least two or more scan sections. step; And performing a burn-in test together with the shifting.

In order to achieve the above technical problem, an example of an apparatus for minimizing chip test time according to the present invention may include: a chamber controller configured to control a supplied voltage and a temperature; And a shifting unit configured to shift the scan section to the scan chain while the voltage and the temperature are supplied, and shift the scan section to the scan chain using different shift frequencies for each of the at least two scan sections. .

According to the present invention, an optimum shift frequency for each scan pattern, scan section or section group is provided. In addition, when increasing the shift frequency by considering only power consumption or critical path delay time, scan test time can be minimized while solving an over kill problem in which a good product is judged to be defective due to an overshift frequency. Find the optimal shift frequency.

In addition, the optimum shift frequency can be found by considering the influence of power supply noise and interference between signal lines. In addition, the optimum shift frequency can be found by reflecting the effects of IR-drop or ground-bounce that may be caused by excessive circuit switching behavior, process variation, microprocessing, low-power processes, or low-power designs caused by scan tests. Can be.

In addition, the optimum shift frequency can be found by considering the influence of the critical path timing on the scan chain that may occur when the shift frequency is increased.

In addition, if the critical path of the scan chain becomes a false critical path according to the bit value on the scan chain, it ignores the critical timing constraint and maximizes the scan shift frequency within the range where the IC chip can operate normally. Can be minimized.

In addition, for low-power IC chips using multiple voltage island or voltage region or region techniques, the optimal shift frequency can be found by reflecting the power consumption allowed for each voltage island or voltage region.

In addition, the circuit design information of the IC chip is not needed to find the optimal shift frequency of the scan pattern or scan section. Therefore, even if the chip design information is lost or lost, only the chip and scan pattern set is required. Find the frequency.

In addition, a predetermined predetermined shift frequency, such as a nominal shift frequency, is initially assigned to all scan sections, and then a process of finding an optimal shift frequency for a scan pattern or scan section in which the power consumption or current consumption of each scan section is a certain level or more is performed. This can save time compared to finding the optimal shift frequency for each full scan pattern or scan section.

Scan patterns can also be used to further accelerate aging, reducing burn-in test time. In addition, a burn test and a scan pattern using a scan pattern can be performed simultaneously, thereby reducing the overall test time for the IC chip. It also has the effect of improving the quality of the burn-in test.

1 is a diagram illustrating an example of an IC chip to which a conventional scan design method is applied;

2 and 3 are views each showing the configuration of an embodiment of a chip test apparatus according to the present invention;

4 is a view showing an example of a scan pattern that can be applied to the method of minimizing scan test time according to the present invention to reduce scan test time;

5 illustrates an example of a scan section according to the present invention;

6 is a diagram illustrating an example of allocating a shift frequency for each scan section in order to minimize scan test time according to the present invention;

7 illustrates an example of a method for finding a shift frequency for minimizing scan test time according to the present invention;

8 is a flowchart illustrating an example of a method for minimizing scan test time according to the present invention;

9 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

10 is a flowchart illustrating a more specific process of a scan test time minimization method according to the present invention;

11 is a flowchart illustrating a specific process of identifying a normal shift-in in a scan test time minimization method according to the present invention;

12 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

13 is a view showing the configuration of an embodiment of an apparatus for minimizing scan test time according to the present invention;

14 illustrates another example of a method for allocating an optimum shift frequency for each scan section according to the present invention;

15 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

16 is a view showing another example of an apparatus for minimizing scan test time according to the present invention;

17 illustrates an example of a method of repositioning a scan pattern for minimizing scan test time according to the present invention;

18 and 19 are views illustrating a configuration of another embodiment of a chip test apparatus according to the present invention;

20 illustrates an example of a temperature effect on an IC chip when performing a burn-in test using a single scan shift frequency according to the present invention;

21 is a view showing an example of the temperature effect on the IC chip when performing the burn-in test using the optimal frequency for each scan pattern according to the present invention,

FIG. 22 is a view showing another example of a method using an optimal shift frequency for each scan section to minimize time of a burn-in test according to the present invention; FIG.

23 is a view showing an example of a burn-in test time minimization apparatus according to the present invention;

24 to 26 are diagrams showing an example of a pattern input to a scan chain for shift frequency determination according to the present invention;

FIG. 27 is a diagram illustrating experimental results of a shift frequency when the scan power is approached to a threshold power consumption of an IC chip and a shift frequency optimized by a shift frequency increase / decrease method for each scan pattern.

Hereinafter, a method and apparatus for minimizing scan test time according to the present invention will be described in detail with reference to the accompanying drawings.

2 and 3 are diagrams illustrating the configuration of an embodiment of an IC chip test apparatus, that is, a scan test apparatus, generally called an automatic test equipment (ATE) to which the present invention is applied.

2 and 3, the scan test apparatus includes

host computers

200 and 300,

tester bodies

210 and 310, test heads 220 and 320, and

interface boards

230 and 330. The device under test (DUT) 240 and 340 positioned on the interface board for the test may be an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it may further include a prober 350. Hereinafter, an IC chip or a packaged IC chip on a wafer is collectively called an IC chip.

The

tester bodies

210 and 310 control the scan test as a whole. For example, the tester body controls the overall process of setting up for the DUT test, generating the electrical signal for the DUT test, and observing and measuring the DUT test result signal. The

test bodies

210 and 310 may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and according to an embodiment, a device power supply device for supplying power to the

DUTs

240 and 340. It may further include a power supply). In addition, the tester

main body

210 or 310 controls a signal processing processor (DSP) (not shown) for processing various digital signals and the test heads 220 and 320, and a controller and a signal for applying a signal to the

DUTs

240 and 340. It may include dedicated hardware such as a generator, software or firmware.

Tester bodies

210 and 310 may also be called mainframes or servers.

The

host computers

200 and 300 may be computers, such as workstations, and are devices that allow a user to execute a test program, control a test process, and analyze test results. In general, the

host computer

200 or 300 may include a central processing unit, a storage device such as a memory or a hard disk, a user interface, and the like, and may be connected to the

tester bodies

210 and 310 by wire or wireless communication. The

host computers

200 and 300 may include dedicated hardware, software or firmware for controlling the test. In the present embodiment, the host computer and the tester main body are illustrated separately, but the

host computer

200 and 300 and the tester

main body

210 and 310 may be implemented as a single device.

An example of memory of the tester

main body

210 or 310 or the

host computer

200 or 300 may be a DRAM, an SRAM, a flash memory, or the like, and a program and data for performing a DUT test may be stored in the memory.

Software or firmware of the tester

main body

210 or 310 or the

host computer

200 or 300 is a device driver program for operating a scan test, an operating system (OS) program, a program for performing a DUT test, and performs setup for a DUT test and a DUT test. The signal may be stored in a memory in the form of an instruction code for generation of a signal, an observation analysis of a DUT test result signal, or the like, and may be performed by a central processing unit. Thus, the scan test pattern can be applied to the DUT by this program. In addition, reporting and analysis data for DUT tests and test results can be obtained automatically through the program. The language used in the program may be various languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The central processing unit of the

tester body

210 or 310 or the

host computer

200 or 300 is a processor and executes code of software or a program stored in a memory. For example, when a user command is received through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes it through software or a program, and then outputs the result to a user interface such as a speaker, a printer, or a monitor. To the user through.

The user interface of the

tester body

210, 310 or the

host computer

200, 300 allows the user and the device to exchange information and communicate commands. For example, an interface device for user input such as a keyboard, a touch screen, a mouse, and the like, and an output interface device such as a speaker, a printer, a monitor, and the like.

The test heads 220 and 320 include a channel for transmitting an electrical signal between the

tester bodies

210 and 310 and the

DUTs

240 and 340.

Interface boards

230 and 330 are provided on the test heads 220 and 320. An interface board used for testing a packaged IC chip is generally called a load board, and an interface board used for testing an IC chip on a wafer is generally called a probe card.

2 and 3 is only one example for better understanding of the present invention, and may be implemented in one piece by integrating each component, or in one embodiment by dividing one configuration into a plurality of configurations. Various design changes are possible according to this.

4 is a diagram illustrating an example of a scan pattern that can be applied to a method for minimizing scan test time according to the present invention to reduce scan test time.

Referring to FIG. 4, the shift-in and shift-out operations are simultaneously performed to reduce the time required when the shift-in operation and the shift-out operation are performed in the scan mode. In other words, the load and unload operations are performed at the same time.

For example, when the k-th input scan pattern 430 is loaded shift-in through the scan input port into the scan chain, the test results by the k-1 th input scan pattern 400 simultaneously shift the scan output port. -Out and unload. In this case, the unloaded output pattern is compared with the predicted output scan pattern 440 for the k-1 th input scan pattern 400 managed in pairs with the k th input scan pattern 430.

Predictions for the k-th input scan pattern 430 and the k-1 th input scan pattern 400 that are shifted-in through the scan input port in order to scan scan by overlapping the shift-in and shift-out operation. The output scan pattern 440 is managed in pairs. Thus, the scan patterns can be in order with each other. Scan patterns can also be rearranged in various ways.

When the first scan pattern is shifted in to the scan chain, the output pattern that is shifted out at the same time may be a Don't-care pattern or a scan chain state value by resetting the chip under test.

Another way to minimize scan test time is to reduce the total number of scan patterns for the scan test and to increase the scan shift speed. Here, increasing the scan shift rate means increasing the shift frequency of the shift-in or shift-out or decreasing the time interval (ie, shift period) between each bit of the scan pattern input or output in the scan chain. For example, lowering the scan shift rate may mean lowering the shift frequency or increasing the shift period. In addition, optimizing the scan shift rate means optimizing the shift frequency or optimizing the shift period. Since the increase and decrease of the shift frequency and the increase and decrease of the shift period are substantially the same, a method of minimizing the scan test time in terms of the increase and decrease of the shift frequency will be described below for convenience of description. The shift period may also be referred to as a shift frequency.

5 is a diagram illustrating an example of dividing the scan patterns on the scan pattern set into scan sections in order to minimize the time of the scan test according to the present invention.

Referring to FIG. 5, a plurality of scan patterns may be used for testing an IC chip. The scan section may consist of at least one scan pattern or part of a scan pattern, and further reduce scan test time by finding an optimum shift frequency for each scan section and applying the scan section.

According to a first embodiment, the scan section 500 may be configured as one scan pattern and correspond one-to-one with the scan pattern. That is, the scan pattern may soon be a scan section.

In a second embodiment, the scan section 510 may include two scan patterns. The number of scan patterns included in the scan section may be variously changed according to an embodiment.

In a third embodiment, the scan section 520 may be configured as part of the first scan pattern and part of the second scan pattern.

In a fourth embodiment, the scan section 530 may be configured as part of one scan pattern.

According to a fifth embodiment, one scan pattern may be divided into two

scan sections

540 and 550. The number of scan sections included in one scan pattern may be variously changed according to embodiments.

One or more scan patterns may be divided by any one of the

various embodiments

500, 510, 520, 530, 540, and 550 previously described, and the scan patterns may be divided by applying two or more of these embodiments. For example, a scan pattern set consisting of N scan patterns of FIG. 5 includes a first scan section 500 including one scan pattern, a second scan section 510 including two scan patterns, and one scan. It may be divided into third and

fourth scan sections

540 and 550 that include part of the pattern.

In addition, various methods of dividing the scan pattern set into scan sections may be applied, and the present invention is not limited to the scan section shown in FIG. 5.

6 is a diagram illustrating an example of allocating a shift frequency for each scan section to minimize scan test time according to the present invention.

Referring to FIG. 6, a plurality of shift frequencies are assigned to each scan section. In the case of the conventional scan test, it uses a constant scan shift frequency that can normally shift all scan patterns for testing the IC chip to the scan chain of the IC chip, which is nominal. Also called shift frequency.

In general, the nominal shift frequency can be the shift frequency used when creating a scan pattern with ATPG software, or a slightly adjusted shift frequency based on it, and all scan patterns for testing the IC chip will normally shift in the scan chain of the IC chip. It is a single shift frequency that can be quite low.

Therefore, if the nominal shift frequency is used as it is for several thousand to tens of thousands or more scan patterns of the IC chip to be tested, the scan test time is very large, especially during the mass production test of the IC chip, the IC chip cost and time to market. can have a significant impact on the market. For example, assuming that it takes 2 seconds to test one IC chip, testing 10 million chips sequentially takes about 5,556 hours, or about 231 days. Even if you test several chips at the same time using expensive equipment, it takes a lot of test time. IC chip test service companies usually charge in proportion to the number of test equipment used and the test time, so chip test time has a significant effect on chip cost.

However, if you increase the nominal shift frequency, the power dissipation of shift-in or shift-out of the scan pattern will be beyond the power range required by the IC chip, making it impossible to perform normal scan tests. In addition, the overshift frequency may cause an overkill problem in which good quality is determined as a defective product due to a critical path delay time problem, a deep power supply noise effect, a deep interference effect between signal lines, and the like. This can affect yield and cost, which are very important for IC chip production.

Therefore, the present embodiment does not apply a single shift frequency such as a nominal shift frequency to the entire scan pattern, but allocates an optimal shift frequency that can be normally shifted in the scan chain for each scan section. A process of finding an optimum shift frequency for each scan section will be described in more detail with reference to FIG. 7. Here, the optimal shift frequency may be the maximum allowable shift frequency for the scan section or a shift frequency smaller than this.

Referring back to FIG. 6, the first scan section is assigned a shift frequency A, and the second scan section is assigned a shift frequency B. And the third scan section is assigned the same shift frequency A as the first scan section. As such, each scan section may be assigned the same shift frequency or different shift frequencies.

For example, when one scan pattern is divided into a plurality of scan sections, a plurality of shift frequencies may be assigned to one scan pattern. Referring to FIG. 5, two

scan sections

540 and 550 belonging to one scan pattern may be assigned different shift frequencies. That is, two shift frequencies are allocated to one scan pattern.

Each scan section assigned a shift frequency may be integrated into a section group according to an embodiment. For example, the second scan section and the third scan section may be grouped into a section group, and a smaller shift frequency or less than the shift frequencies A and B of each scan section may be assigned to the corresponding section group.

Applying test data to the main input port of the general scan test procedure described in the background technology of the present invention and observing the test result at the main output after inputting the scan pattern to the scan chain may be applied to the general scan test procedure in the following embodiment .

For convenience of explanation of the present invention, the relationship between the input pattern, the scan section, the scan pattern, and the output pattern will be described as follows.

The input pattern is a bit pattern that is input to the scan chain. For example, referring to FIG. 7, the k th scan section 704 that is the current shift frequency determination object corresponds one-to-one with the k th input pattern 704, and the k th scan section 704 (= k th input pattern 704). ) Is the k-1 th input pattern 702, and the input pattern after the k th scan section 704 (= k th input pattern 704) is the k + 1 th input pattern 706.

(Input pattern when the scan section and the scan pattern correspond one-to-one) When the k-th scan section 704 that is the shift frequency determination target corresponds one-to-one with the k-th scan pattern, the k-1 th input pattern 702 and the k-th The input pattern 704 and the k + 1 th input pattern 706 may correspond one-to-one with the k-1 th scan pattern, the k th scan pattern, and the k + 1 th scan pattern, respectively.

(Output pattern K when scan section and scan pattern correspond one-to-one) k-th scan section 704 (= k-th) when k-th scan section 704 that is the shift frequency determination object corresponds one-to-one with k-th scan pattern The output pattern of the scan chain for input pattern 704 corresponds to the output pattern of the scan chain for the k th scan pattern. The output pattern of the scan chain for the k-th scan pattern may be a scan capture result pattern for the k-th scan pattern or a pattern in which the k-th scan pattern is output directly from the scan chain.

(Output pattern K-1 when the scan section and the scan pattern correspond one-to-one) When the k-th scan section 704 that is the shift frequency determination object corresponds one-to-one with the k-th scan pattern, the k-1 th input pattern 702 The output pattern of the scan chain for s corresponds to the output pattern of the scan chain for the k-1 th scan pattern. The output pattern of the scan chain for the k−1 th scan pattern may be a scan capture result for the k−1 th scan pattern or a pattern in which the k−1 th scan pattern is output directly from the scan chain.

(Output pattern K + 1 when the scan section and the scan pattern correspond one-to-one) When the k-th scan section to be shifted frequency determination corresponds one-to-one with the k-th scan pattern, the scan for the k + 1 th input pattern 706 is performed. The output pattern of the chain is the output pattern of the scan chain for the k + 1th scan pattern. The output pattern of the scan chain for the k + 1 th scan pattern may be a scan capture result pattern for the k + 1 th scan pattern or a pattern in which the k + 1 th scan pattern is output as it is from the scan chain.

(Input patterns K-1 and K + 1 when the scan section is part of the scan pattern) For example, referring to FIG. 25, when the k-th scan section 704 that is the shift frequency determination target is part of the k-th scan pattern. The k-th input pattern 702 may include a portion of the k-th scan pattern including the k-th scan pattern and the k-th scan section 704 except for the k-th scan section. The k + 1 th input pattern 706 may include a portion except the k th scan section 704 in the k th scan pattern including the k + 1 th scan pattern and the k th scan section 704.

(Output pattern K when scan section is part of scan pattern) Scanning for k-th scan section 704 when the k-th scan section 704 that is the shift frequency determination target is a part of k-th scan pattern as shown in FIG. The output pattern of the chain may be a scan capture result pattern for the k th scan section 704 or a scan capture result pattern for the k th scan pattern that includes the k th scan section. Alternatively, the output pattern of the scan chain for the k-th scan section may be a pattern in which the k-th scan section 704 is output directly from the scan chain or the k-th scan pattern including the k-th scan section 704 is output directly from the scan chain. It may be a pattern.

(Output patterns K-1 and K + 1 when the scan section is part of the scan pattern) When the k-th scan section 704 that is the shift frequency determination target is a part of the k-th scan pattern as shown in FIG. The output pattern of the scan chain for the input pattern 702 may be an output pattern for the k−1 th scan pattern or an output pattern for the k−1 th scan pattern and a portion of the k th scan pattern. Also, the output pattern of the scan chain for the k + 1 th input pattern 706 may be an output pattern for the k + 1 th scan pattern or an output pattern for a portion of the k + 1 th scan pattern and the k th scan pattern. . As another example, the output pattern of the scan chain for a portion of the k th scan pattern included in the k-1 th input pattern 702 or the k + 1 th input pattern 706 may include the k th scan section 704. Can be reflected in the output pattern of the scan chain for the k-th scan pattern.

(When the scan section spans a plurality of scan patterns) For example, referring to FIG. 26, a k-th scan section 704 that is a shift frequency determination object may span a plurality of scan patterns. In this case, the k-1 th input pattern 702 may include a portion of the k-1 th scan pattern except the k th scan section 704, and the k + 1 th input pattern 706 is the k th scan section. It may include a portion of the k + 1 th scan pattern except 704. In this case, it is possible to separately determine the optimum shift frequency for each part of the kth scan section 704 spanning each scan pattern, and to determine the single shift frequency assignable for the kth scan section 704. .

The above is an example for aiding the understanding of the present invention, and the present invention is not limited to this example. In addition, the scan pattern may be divided into various types of scan sections, as described in FIG. The form may also vary. That is, the k-1 th input pattern 702 or the k + 1 th input pattern 706 may be composed of at least one scan section.

7 illustrates an example of a method for finding a shift frequency for minimizing scan test time according to the present invention.

FIG. 7 illustrates an example of a method for minimizing scan test time when the shift-in and the shift-out described in FIG. 4 are performed by overlapping. FIG. 7 illustrates one example according to the present invention, and the present invention is not limited to the case where the shift-in and the shift-out described in FIG. 4 are performed at the same time.

The scan test of the IC chip compares the test result pattern of the input scan pattern with the prediction pattern to determine whether the test is normal. That is, after loading the input scan pattern into the scan chain, the result pattern obtained by performing the capture operation is unloaded, and the test pattern is determined by comparing the predicted pattern with the unloaded result pattern.

In the present embodiment, for shift frequency optimization for a scan pattern or a scan section, when the shift frequency optimization target scan pattern or the scan section is shifted in the scan chain, whether the output pattern shifted out simultaneously (or sequentially) is also normal. It is desirable to. For example, even if the scan pattern to be shifted frequency optimized or the scan section is normally shifted in to the scan chain with an increased shift frequency, the test result pattern for the previous input scan pattern shifted out with the increased shift frequency will cause an error. Because it may.

Referring to FIG. 7, the k−1 th input pattern 702 and the k + 1 th input are used to determine whether the k th scan section 704 that is the current shift frequency determination target is properly shifted into the scan chain at a specific shift frequency. The pattern 706 can be used together. That is, each time the k-th scan section 704, which is the current shift frequency determination target, is repeatedly input to the scan chain, a k-1 th input pattern 702 capable of initializing the scan chain into a constant bit pattern may be used. Also, whenever the output pattern of the scan chain for the k th scan section 704 is repeatedly shifted out, a k + 1 th input pattern 702 which is shifted in the scan chain with a constant bit pattern may be used.

If the k-th scan section 704 has a one-to-one correspondence with the k-th scan pattern, the k-th input pattern 702 is the k-1th used for the actual scan test located in front of the k-th scan section 704. It may be a scan pattern or a prediction pattern for a result pattern obtained by scanning and capturing the k-1 th scan pattern in a scan chain.

As another example, when the k th scan section 704 that is the current shift frequency determination object is part of the k th scan pattern as shown in FIG. 25, the k−1 th input pattern 702 is positioned in front of the k th scan section 704. The k-1 th scan pattern or the k-1 th scan pattern used for the actual test may include a prediction pattern for a result pattern obtained by scanning a scan loaded in a scan chain. Also, the k−1 th input pattern 702 may include a portion of the k th scan pattern except for the k th scan section. Here, a part of the k-th scan pattern except for the k-th scan section may be a part of the bit pattern used for the actual scan test.

As another example, the k-1 th input pattern 702 is composed of bit '0' or '1' oriented or consecutive bit '0' or '1' oriented so as to reduce switching operation on the scan chain. It may be a pattern of.

As another example, the k−1 th input pattern 702 may include at least one scan section as shown in FIG. 24.

If the k th scan section 704 has a one-to-one correspondence with the k th scan pattern, the k + 1 th input pattern 706 is the k + 1 th scan used for the actual scan test located behind the k th scan section 704. It may be a pattern or a prediction pattern for a result pattern obtained by scanning and capturing a K + 1th scan pattern into a scan chain.

As another example, when the k th scan section 704 that is the current shift frequency determination object is part of the k th scan pattern as shown in FIG. 25, the k + 1 th input pattern 706 is located after the k th scan section 704. The k + 1 th scan pattern or the k + 1 th scan pattern used for the actual scan test located in the scan chain may be included in the prediction pattern for the result pattern obtained by scanning capture. Also, the k + 1 th input pattern 706 may include a portion of the k th scan pattern except the k th scan section 704. Here, a part except the k-th scan section 704 may be a part of a bit pattern used for the actual scan test.

As another example, the k + 1 th input pattern 706 is composed of bit '0' or '1' oriented or consecutive bit '0' or '1' oriented so as to reduce switching operation on the scan chain. It may be a pattern of.

As another example, the k + 1 th input pattern 702 may include at least one scan section as shown in FIG. 24.

In the scan test, the input scan pattern, which is located before the first scan section and after the last scan section, is composed of bit '0' or '1' oriented or consecutive bit '0' to reduce switching operation on the scan chain. Alternatively, the pattern may be any predetermined pattern composed mainly of '1'. In addition, the input scan pattern located in front of the first scan section may be a value on the scan chain when the chip under test is in the reset state.

The k-1 th input pattern 702 or the k + 1 th input pattern 706 may each consist of one or more scan sections, the shift frequency of which is the k th scan section 704 of the current shift frequency determination target. It is desirable not to constrain the search for the maximum shift frequency.

For example, the k-1 th input pattern 702 can normally shift-in up to 30 MHz in the scan chain and the k-th scan section 704 subject to shift frequency determination can normally shift-in up to 50 MHz in the scan chain. Let's say In this case, the k-1 th input pattern 702 and the k th scan section 704 are sequentially shifted into the scan chain while increasing the shift frequency, and the output pattern for the scan chain is compared with the predictive pattern k. The maximum shift frequency that can be found for the first scan section 704 is constrained to 30 MHz. That is, when the shift frequency exceeds 30 MHz, the output pattern and the prediction pattern for the k-1 th input pattern 702 may be different.

Therefore, in order to avoid such a constraint situation, it is preferable that the shift frequency of the k-1 th input pattern 702 or the k + 1 th input pattern 706 does not exceed a preset shift frequency (30 MHz in the above example). .

For example, the shift frequency of the k-1 th input pattern 702 or the k + 1 th input pattern 706 is fixed to a preset shift frequency (30 MHz or less in the above example), and the k th scan section 704 is performed. By increasing or decreasing only the shift frequency of, the maximum shift frequency for the kth scan section 704 can be found.

As another example, the shift frequency together with the preset shift frequency (30 MHz or less in the above example) for the k-1 th input pattern 702, the k th scan section 704, and the k + 1 th input pattern 704 together. If the increase and decrease of the predetermined shift frequency is applied, only the shift frequency of the k-th scan section 704 may be increased or decreased. In other words, the shift frequency of the k-th scan section 704 and the shift frequency of the remaining

input patterns

702 and 706 may be controlled differently. Of course, if the maximum allowable shift frequency of the k-1 th input pattern 702 or the k + 1 th input pattern 706 is greater than the maximum shift frequency of the k th scan section, then the k th scan section 704 and the remaining

input patterns

702, 706. Can be increased or decreased in the same manner. Here, the preset shift frequency may be variously changed according to an exemplary embodiment such as a nominal shift frequency, a shift frequency adjusted with a nominal shift frequency, or a preset value or a user set value for each test device. It is not limited.

As another example, when the optimal shift frequency has already been determined for the k-1 th input pattern 702 or the k + 1 th input pattern 706 by the method according to the present invention, k- is applied by applying below the optimal shift frequency. The first input pattern 702 or the k + 1th input pattern 706 may be shifted in to the scan chain.

For example, when the method according to the present invention is sequentially applied to the scan patterns, at least one scan constituting the k-1 th input pattern before the shift frequency determination process of the k th scan section, which is the current shift frequency determination target. The optimal shift frequency for the section can be predetermined. Therefore, the scan test time minimization apparatus uses the optimal shift frequency for each scan section of the k-1 th input pattern, and shifts the nominal shift frequency or the smooth shift frequency for each scan section for the k + 1 th input pattern. Frequency can be used.

And while increasing or decreasing the shift frequency for the scan section to find the optimum shift frequency of the k-th scan pattern, sequentially input the k-1, k, k + 1st scan pattern to the scan chain 710 to the actual output pattern ( Determine if 720 is the same as the prediction pattern 730. In this case, a scan capture operation may be performed on at least one scan pattern among k-1, k, or k + 1th scan patterns.

For example, the scan test time minimization apparatus uses the nominal shift frequency as the initial shift frequency, and increases the shift frequency in units of variation of the shift frequency preset in the scan test time minimization apparatus. That is, after shifting-in the k-1 th input pattern 702 with a preset shift frequency equal to the nominal frequency in the scan chain, the k th scan section 704 has a shift frequency of "Initial Shift Frequency + Incremental Unit Increment". Shift-in to the low scan chain, and simultaneously shift-out the test result (i.e., output pattern K-1) 722 by the k-th input pattern 702 to know the predicted pattern K-1 (732) in advance. Is equal to). In this case, the preset shift frequency of at least one scan section included in the k-1 th input pattern 702 or the k-1 th input pattern 702 may be different from the initial shift frequency of the k th scan section 704. have. Then, at the same time as the shift-in of the k + 1 th input pattern 706, the prediction pattern K 734 knowing in advance the output pattern K 724 obtained by shifting out the test result by the k th scan pattern 704. Compare with. In this case, when the k th scan section 704 is a part of the scan pattern as shown in FIG. 25, the k-1 th input pattern 702, the k th scan section 704, the k + 1 th input pattern 706, and these The output pattern for each is as described above.

The above-described preset shift frequency preferably does not limit the search for the optimal shift frequency of the k-th scan section 704 that is the current shift frequency determination target. Therefore, the shift frequency of the k-1 th input pattern 702 or the k + 1 th input pattern 706 does not increase or decrease with the shift frequency of the k th scan section 704 or is different from the k th scan section 704. In this case, it is preferable to use a shift frequency capable of normally inputting the scan section of the k-1 th input pattern 702 or the k + 1 th input pattern 706 into the scan chain. According to an embodiment, the preset shift frequency may be variously changed according to an embodiment, such as a value adjusted to a nominal shift frequency in addition to the nominal shift frequency, a value set in the device by a program, or a value set by a user. It is not necessarily limited to.

If the output pattern K-1 722 and the prediction pattern K-1 732 are the same, and the output pattern K 724 and the prediction pattern K 734 are the same, the k-th scan section 704 that is the current shift frequency determination target The shift frequency available for. The scan test time minimization apparatus again increases the shift frequency for scan section K 704 to find the optimal shift frequency by a predetermined amount, and again inputs the scan chain from the k-1 th input scan pattern 702 as described above. The process of comparing the output pattern 720 and the prediction pattern 730 is performed again.

As such, the shift frequency for the k th scan section 704 is continuously increased to the point where the output pattern 720 and the prediction pattern 730 are different, and the shift frequency before the point is less than or equal to the k th scan section. The optimal shift frequency can be determined.

Although the above embodiment mainly describes a method of finding an optimum shift frequency by increasing the shift frequency, in another embodiment, the shift frequency is different from the output pattern 720 and the prediction pattern 730 of the k-th scan section 704. It is also possible to find a point where the output pattern 720 and the prediction pattern 730 are equalized by repetitively decreasing from a high frequency, and determining below the shift frequency of that point as the optimal shift frequency of the kth scan section 704.

In addition, when the output pattern for the scan section or the scan pattern is repeatedly compared with the prediction pattern while increasing or decreasing the shift frequency, the shift frequency may be increased or decreased within the range set in the scan test time minimizing apparatus. If the pattern 720 and the prediction pattern 730 are the same and different or different and find the same point, the increase and decrease of the shift frequency can be stopped to reduce the time required to find the maximum possible shift frequency for each scan section.

According to an embodiment, the initial shift frequency for finding the optimal shift frequency for the kth scan section may be set in addition to the nominal frequency, and may not be increased at a low shift frequency, but may be increased at different output patterns and prediction patterns. You can also find the shift frequency at the point where the output pattern and the prediction pattern are the same, starting with the shift frequency and decreasing the shift frequency. In addition, instead of sequentially increasing or decreasing the shift frequency of the k-th scan section, various algorithms may be used to change the shift frequency to find an optimal shift frequency at a faster time.

For example, you can use a binary search algorithm. For example, if the shift frequency is a test success at 10 MHz and fails at 20 MHz, the next shift frequency tries 15 MHz in between. If the test is successful, try between 15MHz and 20MHz. If this fails, try between 10MHz and 15MHz.

In the example of FIG. 7, scan section K 704 to find the optimal shift frequency corresponds one to one with scan pattern K 704, but k-th scan section 704 of FIG. 25 or scan section 530 of FIG. 5. It may be configured as part of the scan pattern as shown. That is, the length of the current scan frequency determination target scan section may be shorter than the length of the scan chain. In this case, in the scan pattern including the scan section selected to find the optimal shift frequency, the shift frequency of the portion except the scan section is not limited to finding the optimal shift frequency of the scan section. To this end, the shift frequency of the portion excluding the selected scan section may not increase or decrease with the shift frequency of the selected scan section, or a shift frequency different from the selected scan section may be used. In addition, the shift frequency of the portion excluding the selected scan section may preferably use a shift frequency capable of normally inputting the portion excluding the selected scan section to the scan chain.

In one embodiment, the shift frequency applied to the portion other than the selected scan section to find the optimal shift frequency is less than the nominal shift frequency or for the portion except the selected scan section, the optimal shift frequency is already determined by the method according to the present invention. In this case, a predetermined shift frequency may be used, such as less than or equal to the optimum shift frequency. For the scan section selected to find the optimal shift frequency, the optimum frequency is found by shifting the frequency up or down as described above. The preset shift frequency may be variously changed according to an exemplary embodiment, such as a value of adjusting a nominal shift frequency, a value set in a device by a program, or a value set by a user, but is not necessarily limited to the above example.

FIG. 7 illustrates a method of finding an optimum shift frequency of a k-th scan section by using a k-1 th input pattern together, but is not necessarily limited thereto. According to an embodiment, only the k-th scan section may be input to the scan chain without a k-1 th input pattern or a k + 1 th input pattern, and the output pattern may be compared with a prediction pattern to find an optimal shift frequency.

8 is a flowchart illustrating an example of a method for minimizing scan test time according to the present invention.

Referring to FIG. 8, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (S800).

In the dividing step, the data for the scan section or the group of sections divided into thousands or tens of thousands or more scan patterns for testing the IC chip, or the file containing the data, may be batched using a computer program or software. Can be handled as

For example, a computer program or software divides a scan pattern set into scan sections or section groups by using information related to the scan section division such as the number, length, and position of the scan sections, and the data for the divided scan sections or section groups. Alternatively, files containing these data can be created in a batch.

Information related to the scan section division may be obtained through a user interface device such as a keyboard, mouse, or voice recognition device, or information data code or file containing information related to the scan section division, or through a data communication network. Can be used by.

As an example of division of the scan pattern, the method illustrated in FIG. 5 may be used. The scan test time minimization apparatus allocates a plurality of shift frequencies to each scan section (S810). Here, the shift frequency assigned to each scan section is less than or equal to the shift frequency before the output pattern of the scan chain is different from the prediction pattern. The division of the scan pattern into scan sections (S800) and the scan section allocation of the shift frequency (S810) may be performed in the same device or different devices, respectively, according to embodiments. It may also be performed.

That is, the scan test time minimization apparatus searches for the maximum shift frequency that can be allocated to the scan section immediately before the output pattern and the prediction pattern are changed according to the increase or decrease of the shift frequency. According to an embodiment, each scan section may be assigned a shift frequency smaller than the maximum shift frequency found by increasing or decreasing the shift frequency.

9 is a diagram illustrating another example of a method of determining an optimal shift frequency for each scan section in order to minimize scan test time according to the present invention.

Referring to FIG. 9, the scan test time minimization apparatus divides one or more scan patterns into at least two scan sections (S900).

The scan test time minimization apparatus detects the shift frequency at the time when the output pattern is different from the prediction pattern while increasing or decreasing the frequency shifting-in the scan section to the scan chain (S910). Chips used to find the optimal shift frequency are preferably chips that have been tested for good quality in advance. For example, as a result of a scan test using a nominal shift frequency, an optimal shift frequency is searched according to the present embodiment using a good chip. The same is true in other embodiments below.

In operation S920, the scan test time minimization apparatus determines a shift frequency before a time point at which the output pattern and the prediction pattern differ from each other in the scan section. The former shift frequency also includes a smaller shift frequency.

For example, when the output pattern and the prediction pattern are the same at the first shift frequency, but the output pattern and the prediction pattern of the scan chain are different at the second shift frequency in which the first shift frequency is increased by a certain amount, the scan test time minimization apparatus Two shift frequencies, or smaller, may be determined as the shift frequency of the scan section or may provide information that may be determined.

The magnitude of the increase and decrease in order to find the optimal shift frequency is preset in the scan test apparatus, and the increase and decrease size may be changed by the user.

The present embodiment describes a method of finding an optimal shift frequency for each scan section by increasing or decreasing the shift frequency for convenience of description, but according to the exemplary embodiment, the optimum shift frequency is increased while increasing or decreasing the shift-out frequency. You can find it. The same applies to the following examples.

Each step described with reference to FIG. 9 may be performed in another apparatus such as a computer, rather than all performed in the apparatus for minimizing scan test time, according to an exemplary embodiment.

10 is an embodiment of a flowchart illustrating a more detailed process of the scan test time minimization method according to the present invention.

Referring to FIG. 10, the apparatus for minimizing scan test time divides one or more scan patterns into a plurality of scan sections (S1000).

The scan test time minimization apparatus selects one scan section of which no shift frequency is determined according to the present exemplary embodiment among the scan sections (S1010). For example, if a predetermined order is defined between scan patterns for the scan test, the scan test time minimizing apparatus may sequentially select from the first scan section. Alternatively, the user may select a scan section for which the shift frequency is to be optimized, and the scan test time minimization apparatus may perform the shift frequency optimization for the selected scan section. In addition, there are various ways to select the scan section for which the shift frequency is to be optimized.

The scan test time minimization apparatus increases or decreases the shift frequency (S1020). For example, the scan test time minimization apparatus may variously set the initial shift frequency to a nominal shift frequency.

The scan test time minimization apparatus determines whether the scan section can normally be shifted-in to the scan chain at the increased shift frequency starting from the initial shift frequency (S1030). An example of a specific method of determining whether the selected shift frequency determination target scan section can normally shift-in to the current shift frequency will be described with reference to FIG. 11.

If the normal shift-in of the scan section is possible (S1040), the scan test time minimization apparatus increases or decreases the shift frequency (S1020) and repeats the process of determining whether normal shift-in is possible (S1030).

If the shift section does not normally shift-in the scan section due to the increase or decrease of the shift frequency (S1040), the scan test time minimization apparatus scans below the shift frequency before the current shift frequency where the scan section is not normally shifted-in. Information that can be determined or determined by the shift frequency of the section can be stored in a computer-readable recording medium (S1050). The above process is repeated until shift frequencies for all scan sections are determined or information that can be determined is stored in a computer-readable recording medium (S1060). Here, as an example of the information stored in the recording medium, it may be information about a shift or a test pass or fail for each shift frequency.

The apparatus for minimizing scan test time may group scan sections into section groups as necessary (S1070). For example, if the scan test device that performs the actual scan test has constraints such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required for the shift frequency change, the scan test time The minimization apparatus may group scan sections in such a way that the number of scan sections satisfies the above constraints, and may consider the total scan test time to be minimized. In this case, the lowest shift frequency among the optimal shift frequencies of at least two scan sections included in one scan section group may be determined as the shift frequency of the corresponding section group. The step S1070 of grouping the sections into groups may be omitted according to an embodiment.

For example, if the maximum number of shift frequency changes supported by the scan test device is 5, the scan test time minimizer divides the scan sections into 5 or less section groups if the current number of scan sections exceeds 5, and each section The lower or lower optimal shift frequency among the optimal shift frequencies of the sections in the group may be determined as the shift frequency of the corresponding section group. As a method of grouping into section groups, there may be various methods such as grouping by section groups having similar optimal shift frequencies, and it is desirable to minimize the total scan test time.

The embodiments discussed so far have mainly been a process of finding an optimal shift frequency in consideration of only the increase and decrease of the shift frequency. However, the chip is also affected by supply voltage and ambient temperature, so it is necessary to find the optimal shift frequency to reflect these environmental conditions.

Therefore, the scan test time minimizing apparatus may perform a process of finding an optimum shift frequency while changing conditions such as supply voltage and external temperature.

For example, the scan test time minimization apparatus may increase or decrease the voltage supplied to the chip in consideration of a specification range of the chip or quality related policies such as QA (Quality Assurance) and QC (Quality Control). In addition, the scan test time minimization apparatus finds an optimal shift frequency for each scan section according to an embodiment of the present invention at each increased or decreased supply voltage. If there are a plurality of optimal shift frequencies found for each supply voltage of the selected scan section, the scan test time minimization apparatus may determine a shift frequency of the selected scan section below the lowest optimal shift frequency among them (S1050). In addition, the process of finding the optimal shift frequency may be repeated for temperature increase or decrease and various other conditions, and the lower than the lowest optimal shift frequency may be determined as the shift frequency of the corresponding scan section.

Here, to grasp the characteristics such as the operating frequency range of the IC chip while changing the supply voltage or ambient temperature of the IC chip, generally referred to as electrical testing or shiming, electrical characteristics testing or Making a plot of characteristic information by making a drawing is called 'smooth plotting'. The plot is called a shmoo plot.

Each step of FIG. 10 may be performed by another apparatus such as a computer as well as a scan test time minimization apparatus.

11 is a flowchart illustrating an embodiment of a specific process of identifying a normal shift-in in the scan test time minimization method according to the present invention. That is, FIG. 11 corresponds to step S1030 of FIG. 10.

Referring to FIG. 11, the scan test time minimization apparatus shifts-in the k-1 th input pattern positioned in front of the k th scan section, which is the currently selected shift frequency determination target, to the scan chain as shown in FIG. 7 (S1100). The k-1th input pattern is located in front of the kth scan section and is either the k-1th input pattern used for the actual scan test, or the resulting pattern that appears when the k-1th input pattern is loaded into the scan chain and then captured. May be a prediction pattern. The k-th input pattern may be included in any one scan section or may include one or more scan sections.

(1) If the k-1 th input pattern is the k-1 th scan pattern used for the actual scan test, the scan test time minimization apparatus loads the k-1 th scan pattern into the scan chain and performs a scan capture process. do. In this case, there is an advantage of reflecting the actual scan test operation.

(2) When the k-1 th input pattern is a predictive pattern for a result pattern that appears when the k-1 th scan pattern used for the actual scan test is loaded after the scan capture, the apparatus for minimizing the scan test time is performed. Since the input pattern is loaded into the scan chain, there is no need to perform a separate scan capture process, thereby reducing the time required for clock capture and thus, the time required to find the optimal shift frequency.

After the scan test time minimization apparatus loads the k-1 th input pattern, the apparatus shifts the selected shift frequency determination target scan section (k th scan section) into the scan chain at the increased or decreased shift frequency (S1110). If the scan section K selected to find the optimal shift frequency is shorter than the length of the scan chain as part of the scan pattern, such as

scan sections

530, 540 and 550 of FIG. 5, then the input scan pattern comprising the scan section K is added to the scan chain. Shift-in

In this case, it is preferable that the shift frequency of the scan pattern portion except for the selected shift frequency target scan section K does not limit the search for the optimal shift frequency of the scan section K. It is preferable to use a shift frequency that does not increase or decrease with the shift frequency of K, or that a frequency different from the scan section K can be used, and that a portion other than the scan section K can be normally input into the scan chain. In an embodiment, the shift frequency of the portion excluding the scan section K may use a preset shift frequency, such as a nominal shift frequency or less, or when the optimal shift frequency is already determined through the method according to the present invention. Can be. Then shift out the value stored on the scan chain. The preset shift frequency may be variously changed according to an exemplary embodiment, such as a value of adjusting a nominal shift frequency, a value set in a device by a program, or a value set by a user, but is not necessarily limited to the above example.

For example, when the k-1 th input pattern is a k-1 th scan pattern used for an actual scan test, the output pattern shifted out is a scan capture result with the k-1 th scan pattern loaded. to be. In the case where the k-1 th input pattern is a predictive pattern for scan capture by the k-1 th scan pattern used in the actual scan test, the output pattern is a result output as is from the scan chain without a scan capture operation.

The scan test time minimization apparatus compares the output pattern with the prediction pattern (S1120). If the output pattern and the prediction pattern are not the same (S1120), the scan test time minimization apparatus determines that the k-th scan section which is the current shift frequency determination target cannot be normally shifted-in to the scan section at the current shift frequency (S1170).

If the output pattern and the prediction pattern are the same, the scan test time minimization apparatus shifts out the k-th scan section which is the target of the shift frequency determination currently located on the scan chain, or captures the scan after the k-th scan section is loaded. The result is shifted out (S1140). When performing scan capture, there is an advantage that can reflect the actual scan test operation process. The shift-out of the k th scan section without scan capture has the advantage of reducing the time required to find the optimal shift frequency by reducing the time required for scan capture.

The scan test time minimization apparatus compares the shifted-out output pattern and the prediction pattern (S1150). For example, when the k-th scan section to be shifted frequency determination is shifted out as it is, the scan test apparatus compares the k-th section in the output pattern. In the case of outputting the scan capture result for the k-th scan section, the scan test time minimization apparatus compares the output pattern with the predicted scan capture pattern that is known in advance for the k-th scan section.

The scan test time minimizing apparatus determines that the k-th scan section can be normally shifted-in into the scan chain at the current shift frequency when the output pattern and the prediction pattern for the k-th scan section which are the shift frequency determination targets are the same (S1160). . That is, it is desirable to find an optimal shift frequency for the k-th scan section by comparing the output pattern for the k-th scan section, which is the current shift frequency determination target, as well as the output pattern for the scan section or the scan pattern located in front of the prediction pattern. Do.

12 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention.

Depending on the type and state of a process, process variations between IC chips on different wafers or between IC chips on the same wafer may occur, which may greatly affect the operating frequency and power consumption of the IC chip. have. In particular, micro processes and low power processes have more influence. 12 is an example for finding an optimal scan shift frequency and reflecting the same.

Referring to FIG. 12, the scan test time minimizing apparatus performs a process of determining an optimal frequency for each salping scan section for a plurality of chips (S1200). Here, the plurality of chips may be IC chips on the same wafer or IC chips on different wafers, and chips that have been inspected with good quality in advance are preferable.

The scan test time minimization apparatus may determine the optimal shift frequency of the corresponding scan section, or determine the shift frequency below the lowest shift frequency among the plurality of optimal shift frequencies found through the plurality of IC chips for one scan section. The information may be stored in a computer-readable recording medium (S1210), and this may be performed for each scan section. Here, as an example of the information stored in the recording medium, it may be information about the pass or fail of the shift or test for each shift frequency.

For example, assume that the shift frequency of the k-th scan section of the first chip is A and the shift frequency of the k-th scan section of the second chip is B. If the shift frequency A is less than the shift frequency B, the scan test apparatus may select A or less as the shift frequency of the k-th scan section, or store the selectable information in a computer-readable recording medium.

Each step of FIG. 12 may be performed in another apparatus such as a computer as well as an apparatus for minimizing scan test time by using the scan pattern set and the shift frequency information identified for each scan section for a plurality of chips.

In addition, the scan test time minimization apparatus can reduce the time required to find or determine the optimal shift frequency by finding or determining the optimal shift frequency of different scan sections together for each of the plurality of IC chips. In one embodiment, the plurality of scan test devices together find or determine the optimal shift frequency of different scan sections, or in one scan test device, the optimum shift frequency of different scan sections for each of the plurality of IC chips. You can find or decide together.

13 is a diagram showing the configuration of an embodiment of a scan test apparatus according to the present invention.

The scan test time minimization apparatus of FIG. 13 may perform the above-described method of the present invention for optimizing the shift frequency of each scan section, and may apply some or all of the methods of FIGS. 7 to 12 as an example.

Referring to FIG. 13, the apparatus for minimizing scan test time includes a condition setting unit 1300, a pattern dividing unit 1305, a pattern input unit 1310, a pattern comparing unit 1320, and a frequency grasping unit 1330. The condition setting unit 1300 again includes a frequency increasing unit 1302, a supply voltage increasing unit 1304, a temperature increasing unit 1306, and the like.

First, the condition setting unit 1300 sets various conditions for finding an optimal shift frequency for each scan section. In detail, the frequency increase / decrease unit 1302 increases or decreases the shift frequency, the supply voltage increase / decrease unit 1304 increases or decreases the voltage supplied to the chip, and the temperature increase / decrease unit 1306 increases or decreases the ambient temperature of the test environment. The condition setting unit 1300 may set conditions such as a supply voltage and an ambient temperature and increase or decrease the shift frequency.

The pattern divider 1305 divides one or more scan patterns into a plurality of scan sections.

The pattern input unit 1310 shifts-in the scan section into the scan chain under the condition set by the condition setting unit 1300. More specifically, the pattern input unit 1310 may sequentially shift-in the scan pattern or the scan section respectively located in front of and behind the scan section for which the optimum scan shift frequency is to be searched together with the scan section.

The pattern comparison unit 1320 compares the shift-in of the pattern input unit 1310 with the output pattern shifted out at the same time as the prediction pattern. As the shift frequency is increased or decreased by the condition setting unit 1300, there may be a time point in which the output pattern and the prediction pattern are the same and different or different and the same.

The frequency determiner 1330 may find or determine a shift frequency of the output pattern before or after the output pattern differs from the prediction pattern by using the comparison result information by the pattern comparison unit 1320 or the comparison result. The shift frequency information may be stored in a computer-readable recording medium. The information may also be used to determine an optimal shift frequency of the scan section. According to an embodiment, the frequency determiner 1330 may determine a shift frequency when at least the scan section located in front of the current shift frequency determination target scan section and the output pattern for the determination target scan section are equal to the prediction pattern. Available shift frequency information may be stored on a computer readable recording medium. Also, in FIG. 13, two or more parts may be integrated into one module or may be further subdivided.

When shifting scan sections into the scan chain, the power consumed by the IC chip can vary depending on the magnitude of the shift frequency. For example, the higher the shift frequency, the more power is consumed by the chip. Also, even with the same shift frequency, the number of circuit switching on the IC chip or the part of the circuit to be switched may vary according to the bit value of each scan section.

14 is a diagram illustrating another example of a method for finding or determining an optimal shift frequency for each scan section according to the present invention.

Referring to FIG. 14, when the power consumption when the IC chip is inspected using the scan shift frequency pre-allocated in the scan section does not exceed the power consumption limit for the normal operation of the IC chip, the power consumption is pre-allocated. Use the scan shift frequency. On the other hand, if the power consumption when using the scan shift frequency pre-assigned to the scan section exceeds the threshold power consumption, the shift frequency is optimized for the corresponding scan section. That is, the shift frequency optimization may be performed only on the scan section selectively selected based on the power consumption to reduce the time required to find or determine the shift frequency. The shift frequency optimization may use the method described above with reference to FIGS. 7 to 12. In the threshold power consumption-based method, the time required for measuring or estimating the power consumption of the scan section is less than the time required for shift frequency optimization by shift frequency increase and decrease, and consumes power below or below the threshold power consumption of the IC chip. This can be effective if you can test the IC chip normally with a scan section.

To further reduce the test time of the IC chip, shift frequency optimization can also be performed on scan sections below the threshold power consumption. For example, shift frequency optimization may be additionally performed on a scan section in which power consumption is less than or equal to a predetermined reference.

Referring back to FIG. 14, when the scan sections are shifted to the initial shift frequency, the average power consumption is divided into a first scan section group having a value above or above a predetermined threshold and a second scan section group having a value below or below a threshold. Here, the initial shift frequency is preferably a shift frequency equal to or greater than the nominal shift frequency, and the scan test time based on the shift frequency set in the scan pattern information or the scan section information data or the shift frequency determined through the empirical value or various previous experimental data. It may be a value set by the user in the minimization device or set automatically by a program. For example, use a single shift frequency such that the average power dissipated by the scan sections is close to the average power dissipation allowed by the IC chip, or use a different shift frequency as the initial shift frequency for at least two or more scan sections. Can also be used. In addition, the threshold power consumption may be an average power, a peak power, or a value larger or smaller than the allowable value of the IC chip, and various values may be applied according to embodiments.

Referring to FIG. 14, the scan test time minimization apparatus allocates an initial shift frequency as it is to scan sections that are less than or less than a threshold. For example, in FIG. 14,

scan sections

1 and 3 that have an average power consumption less than a threshold value may all be allocated the same or different initial shift frequencies. That is, for scan sections having an average power consumption of less than or equal to a threshold value, the process of searching for an optimal shift frequency as illustrated in FIGS. 7 to 12 may be omitted, thereby saving time for searching for a shift frequency for each scan section.

On the other hand, in FIG. 14,

scan sections

2, 4, and 5 that have average power consumptions above or above the threshold power consumption are allocated shift frequencies through shift frequency increases and decreases. In this case, the above-described method of the present invention can be used, and examples are FIGS. 7 to 12.

The shift frequencies allocated to each scan section may be the same or different. If the initial shift frequency is high or the threshold power consumption is low, all scan sections may exceed the threshold power consumption, in which case the scan test time minimizer will find the optimal shift frequency by shifting the frequency up or down for all scan sections. The process can be performed.

As another example, a method of using peak power consumption instead of average power consumption as a value of the vertical axis of FIG. 14 and finding an optimal shift frequency through shift frequency increase and decrease based on the magnitude of the peak power consumption will be performed. Scan sections can be distinguished from scan sections that are not. The shift frequency optimization method of the scan section using the shift frequency increase and decrease may use the above-described method of the present invention.

15 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention.

Referring to FIG. 15, the scan test time minimizing apparatus divides the scan pattern into at least one scan section (S1500). The dividing step S1500 may be performed in a separate device such as a computer as well as a scan test time minimizing device.

The scan test time minimization apparatus measures or calculates power consumption for each scan section when the scan section is shifted to a preset initial shift frequency (S1510). The calculating step S1510 may be performed by a separate device such as a power consumption measuring device or a computer as well as a scan test time minimizing device. In FIG. 15, power consumption may be, for example, average power consumption or peak power consumption.

When the power consumption of the scan section is less than or less than the preset threshold (S1520), the scan test time minimizing apparatus allocates a shift frequency that is less than or equal to the initial shift frequency or adjusts the initial shift frequency as the shift frequency of the corresponding scan section (S1560). .

On the other hand, if the power consumption of the scan section is greater than or greater than the threshold (S1520), the scan test time minimization apparatus performs a process of finding an optimal shift frequency for the scan section (S1530 to S1550).

As such, if the power consumption of each scan section is above or above a threshold, the process of finding an optimal shift frequency is additionally performed. If the power consumption is below or below a threshold, an additional shift frequency is searched for an additional shift frequency below or below the initial shift frequency. The shift frequency adjusted by may be determined as the shift frequency of the corresponding scan section.

Looking at the method for finding the optimal shift frequency in more detail with reference to Figure 15, the scan test time minimizing device increases and decreases the shift frequency (S1530). The initial value of the shift frequency increased or decreased may be a nominal shift frequency, a shift frequency preset in scan pattern information or scan section information data, a value preset by a user in the scan test time minimization apparatus, or automatically set by a program.

The apparatus for minimizing the scan test time determines whether the scan section is shiftable in the scan chain based on the increased or decreased shift frequency (S1540). The determination of the identity of the output pattern and the prediction pattern may be performed by the method described with reference to FIG. 7. For example, referring to FIG. 7, in the case of finding an optimal shift frequency for the current k th scan section, the scan test time minimization apparatus includes an output pattern and a k th scan section for the k-1 th scan pattern. The output pattern for the k th scan pattern is compared with each prediction pattern to determine whether normal shift is possible.

If the output pattern and the prediction pattern are the same (S1540), the process proceeds to step S1530 of increasing or decreasing the shift frequency and repeats the above steps (S1530, S1540). If the output pattern and the prediction pattern are different (S1540), the scan test time minimization apparatus determines the shift frequency of the scan section below the shift frequency before increasing or decreasing (S1550). The scan test time minimization apparatus may determine the maximum allowable shift frequency as the optimal shift frequency of the corresponding scan section or the lower shift frequency as the optimal shift frequency before the output pattern and the prediction pattern are different.

Some steps of FIGS. 14 and 15 may be performed in a separate device such as a computer as well as a scan test time minimization device.

16 illustrates another example of an apparatus for minimizing scan test time according to the present invention.

Referring to FIG. 16, an apparatus for minimizing scan test time includes a pattern divider 1600, a power detector 1610, a first frequency determiner 1620, and a second frequency determiner 1630. In addition, the second frequency grasping unit 1630 includes a frequency increasing / decreasing unit 1632, a pattern comparing unit 1634, and a grasping unit 1634.

The pattern divider 1600 divides one or more scan patterns into at least two scan sections.

The power detector 1610 detects power consumption when the scan section is shifted in the scan chain at a preset shift frequency. For example, the power detector 1610 detects average power consumption or peak power consumption during the shift to load or unload the scan section to the scan chain at the initial shift frequency.

The first frequency determiner 1620 may determine or determine a shift frequency that is less than or equal to the initial shift frequency or adjusts the initial shift frequency as scan scan frequencies for the sections for the scan sections whose power consumption is less than or less than a preset threshold. do. The power consumption may be average or peak power consumption.

The second frequency grading unit 1630 performs a process of finding an optimal shift frequency for scan sections whose power consumption is greater than or greater than a threshold. Here, the power consumption may be average or peak power consumption.

In detail, the frequency increasing / decreasing unit 1632 selects a scan section of which scan power whose power consumption is above or above a threshold is not yet determined or determined, and selects an optimal shift frequency for the selected scan section. Increase or decrease the shift frequency to find. The initial value of the shift frequency increased or decreased may be a nominal shift frequency.

The pattern comparison unit 1634 determines whether the scan section normally shifts in to the scan chain at the shift frequency increased or decreased by the frequency increase / decrease unit 1632. The above-described method of the present invention may be used to determine whether a normal shift-in is achieved. For example, the method of FIG. 7 may be applied to compare an output pattern and a prediction pattern. That is, the pattern comparison unit 1634 compares whether the output pattern and the prediction pattern are the same when shifting the scan section with the increased or decreased shift frequency, and stores the comparison result information in a computer-readable recording medium. If the comparison result is the same, it is determined that the normal shift is possible, and if it is different, it may be determined that the normal shift is impossible.

The grasping unit 1636 may grasp the maximum shift frequency that can be normally shifted based on the determination result of the pattern comparator 1634, or may store information for determining an optimum shift frequency in a computer-readable recording medium.

That is, when the grasp 1636 grasps the shift frequency at the point where the output pattern and the prediction pattern are different by the pattern comparator 1634, the grasp 1636 determines the shift frequency before the difference, that is, the shift frequency before or after the increase or decrease. The maximum shift frequency of the selected scan section may be determined, or information for determining the shift frequency may be stored in a computer-readable recording medium. Information stored on the recording medium may be used to determine or determine the optimum shift frequency of the scan section.

The salping scan test time minimizing device may be implemented in various forms using hardware or software. In addition, all or some of the scan test time minimizing devices may be implemented in the salping scan test device in FIGS. May be implemented in other devices.

Each embodiment described with reference to FIGS. 14 to 16 discloses a method and apparatus for finding an optimal shift frequency based on power consumption. However, the embodiment is not necessarily limited to the use of power consumption, and includes all cases of using other measurement values having a constant proportionality with power consumption.

For example, since the power consumption is proportional to the current consumption, an optimal shift frequency can be found based on the current consumption.

Referring back to the embodiment of FIG. 16 in terms of power consumption, the power detector 1610 detects power consumption (average current consumption or peak current consumption), and detects the first frequency detector 1620 and the second frequency detector ( 1630 may find and determine an optimal shift frequency for each scan section by using the current consumption and the current consumption threshold instead of power consumption. Other embodiments may use the current consumption and current consumption thresholds instead of power consumption.

17 is a diagram illustrating an example of a method of repositioning a scan pattern for minimizing scan test time according to the present invention.

Referring to FIG. 17, the scan patterns on the scan pattern set for the scan test have a certain order. However, the order of these scan patterns is not fixed but can be rearranged to reduce the overall scan test time by assigning higher shift frequencies for each scan section. For example, as shown in FIG. 17, the order of the second scan pattern and the third scan pattern on the original scan pattern set may be changed. This also changes the order of the predictive output scan pattern.

When rearranging the order of the scan patterns shifted in the scan chain, the scan shift may change the switched portion of the circuit and the number of switching operations on the IC chip, and thus the power consumption is changed so that the scan pattern (or scan section) The shift frequency that can be assigned to the channel can be increased. Therefore, after rearranging the scan pattern using this property, the overall scan test time can be further reduced by finding or determining the optimal shift frequency for each scan section by using the embodiment of the present invention which is previously described.

As a repositioning method of scan patterns, at least one scan pattern on an original scan pattern set is randomly rearranged, and an optimal shift frequency is identified for each relocated scan pattern set according to a prior embodiment, so that scan test time is minimal. There are a variety of methods such as determining what is required as the arrangement of the scan patterns, or arranging the scan patterns having the smallest bit pattern difference between the scan patterns next to each other.

As another example of repositioning the scan pattern, it is possible to have the highest shift frequency by sequentially looking for the optimal shift frequency by first placing the unordered scan patterns sequentially after the K (integer one or more) th scan pattern. The scan pattern can be determined as the next pattern of the Kth scan pattern.

Some or all of the operations for rearranging the order of the scan patterns may be performed by hardware and firmware or software such as a processor included in the IC chip test apparatus, or may be performed by a separate device such as a computer.

In addition, when it may take a long time to find the optimal scan pattern arrangement, there may be constraints such as the maximum number of scan pattern relocation or the time required to find the optimal scan pattern arrangement.

In addition, the present invention can reduce the stress test or burn-in test time and increase the test quality of the IC chip by using the optimum shift frequency for each scan pattern or scan section. The optimal shift frequency for can be found by the method of minimizing scan test time according to the present invention.

The stress test or burn-in test here generally refers to IC chip quality by stressing the IC chip by operating the IC chip for a long time or by accelerating aging by applying high voltage and high temperature to the IC chip, or testing an initial bad IC chip. To discover. Typically tens of hours of burn-in tests are conducted in high temperature environments above 100 ° C. Hereinafter, the stress test or burn-in test is collectively referred to as burn-in test.

For example, the scan test time minimization apparatus may perform a scan test using a scan pattern during the burn-in test of the IC chip. More circuit switching operation occurs in the scan mode than in the IC chip's functional mode.As the scan shift frequency increases, the power consumption of the IC chip increases in proportion, and the heat generation of the IC chip also increases. Can be accelerated. In addition, depending on the bit pattern of the scan pattern, the portion of the circuit to be activated may vary, and in general, in the scan mode of the IC chip, switching operations may be performed on more portions of the circuit than in the functional mode. Therefore, in the present invention, the scan test time minimization apparatus may use the maximum shift frequency that can be assigned to each scan section previously previewed to further reduce the burn-in test time by further accelerating aging during the burn-in test.

In addition, burn-in tests using the maximum shift frequency that can be assigned to each scan section can reduce the likelihood of aging only certain parts of the circuit due to specific scan patterns. In other words, it is possible to improve the quality of the burn-in test by applying the maximum stress to the IC chip as a whole, and the smaller the bit pattern length of the scan section, the higher the effect. A test device capable of performing such a burn-in test is also called a burn-in test device.

18 and 19 are diagrams showing the configuration of an embodiment of a burn-in test apparatus according to the present invention.

18 and 19, the burn-in test apparatus includes a

host computer

1800 and 1900,

tester bodies

1810 and 1910,

test heads

1820 and 1920, interface boards 1830 and 1930, and a temperature controller 1860. 1970),

chambers

1850 and 1960, and prober 1950.

The device under test (DUT) placed on the interface board for testing is an IC on the wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it may further include a prober. Hereinafter, an IC chip or a packaged IC chip on a wafer is collectively called an IC chip.

The

tester bodies

1810 and 1910 control the scan test and burn-in test as a whole. For example, the tester body controls the overall process of setting up for the DUT test, generating an electrical signal for the DUT test, observing and measuring the DUT test result signal, and controlling the temperature of the chamber through the temperature control unit. The tester body may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and further include a device power supply for supplying power to the DUT according to an embodiment. You may. In addition, the tester main body controls a signal processing processor (DSP) (not shown) for processing various digital signals, a test head, and a controller and a signal generator for applying signals to the

DUTs

1840 and 1940. Hardware, software or firmware. The tester body is also called the mainframe or server.

The

host computers

1800 and 1900 may be computers, such as workstations, and are devices that allow a user to execute a test program, control a test process, and analyze test results. In general, the host computer may include a configuration such as a central processing unit, a storage device such as a memory or a hard disk, a user interface, and the like, and may be connected to the tester main body by wire or wireless communication. The host computer may include dedicated hardware, software, firmware, and the like for controlling the test. In the present embodiment, the host computer and the tester main body are illustrated separately, but the host computer and the tester main body may be implemented as a single device.

As an example of memory of the tester main body or the host computer, DRAM, SRAM, flash memory, and the like may be used, and the memory and the program and data for performing the DUT test may be stored.

The software or firmware of the tester main unit or host computer is a device driver program for operating burn-in and scan tests, an operating system (OS) program, and a program for performing DUT tests. It may be stored in a memory in the form of an instruction code for the generation, observation analysis of the DUT test result signal, etc. and may be performed by the central processing unit. Thus, the scan test pattern can be applied to the DUT by this program. In addition, reporting and analysis data for DUT tests and test results can be obtained automatically through the program. The language used in the program may be various languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The central processing unit of the tester main body or host computer is a processor and executes code of software or programs stored in a memory. For example, when a user command is received through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes it through software or a program, and then outputs the result to a user interface such as a speaker, a printer, or a monitor. To the user through.

The user interface of the tester body or host computer allows the user and device to exchange information and communicate commands. For example, an interface device for user input such as a keyboard, a touch screen, a mouse, a voice recognition device, and the like, and an output interface device such as a speaker, a printer, a monitor, and the like.

The test heads 1820 and 1920 include a channel for transmitting an electrical signal between the tester body and the DUT. The interface board is provided on the test head. The interface board used for testing a packaged IC chip is generally called a load board, and the interface board used for testing an IC chip on a wafer is called a probe card.

The

chambers

1850 and 1960 are spaces capable of applying aging to the DUT, and the chamber controls the temperature of the DUT located in the chamber under the control of the temperature controller. The temperature controller may also be included in the tester body or host computer. The tester body or host computer can also control burn-in test time and voltage.

The burn-in test apparatus of FIGS. 18 and 19 is only one example for better understanding of the present invention, and each component may be integrally implemented by integrating each component, or one configuration may be separately implemented into a plurality of configurations. Various designs can be changed according to the design.

18 and 19 may be implemented to simultaneously perform a burn-in test and a scan test, or only one of them.

According to an embodiment of the present disclosure, the burn-in test apparatus may perform the burn-in test together with the scan test using the optimal shift frequency for each scan pattern or scan section as described above. The IC chip switches more IC chip circuitry in the scan mode than in the functional mode, thus further reducing the burn-in test time by accelerating aging through scan test. In addition, the burn-in test using the maximum shift frequency that can be assigned to each divided scan section further reduces burn-in test time, and also reduces the aging of only a certain part of the circuit due to a specific scan pattern. . In other words, it is possible to improve the quality of the burn-in test by applying the maximum stress to the IC chip as a whole, and the smaller the length of the scan section using the optimized shift frequency, the higher the effect can be.

In addition, the present invention is not limited to the case of simultaneously performing the scan test together with the burn-in test, and may include only the process of shifting the scan pattern during the burn-in test and may not perform the scan test itself.

20 is a diagram illustrating an example of a temperature effect on an IC chip when a burn-in test is performed using a single scan shift frequency according to the present invention.

Referring to FIG. 20, a plurality of scan patterns are all shifted to a scan chain of an IC chip using the same scan shift frequency (eg, 25 MHz). The main part where the IC chip is activated by each scan pattern may be different. For example, the main portion 2010 of the IC chip activated by the scan pattern 1 2030 and the main portion 2020 of the IC chip activated by the scan pattern 2 2032 may be different from each other.

In addition, the heat generated on the IC chip by each scan pattern may vary depending on the scan shift frequency or the number of switching circuits according to the scan pattern. For example, the temperature of the main portion 2010 of the IC chip activated by the scan pattern 1 may be a ° C., and the temperature of the main portion 2020 of the IC chip activated by the scan pattern 2 may be b ° C.

The shift frequency can be increased to generate more heat in the IC chip to accelerate the aging of the burn-in test. However, excessively increasing the shift frequency may cause an overkill problem in which a normal IC chip is judged as defective. On the contrary, when the shift frequency is lowered, heat generated in the IC chip is insufficient, which does not effectively accelerate the aging of the burn-in test.

21 is a view showing an example of the temperature effect on the IC chip when performing the burn-in test using the optimum frequency for each scan pattern, according to the present invention, Figures 20 and 21 are the same IC chip This is an example of using a scan pattern.

Referring to FIG. 21, the burn-in test time of the IC chip may be reduced by shifting the scan chain using an optimal shift frequency for each scan pattern.

Burn-in tests are typically performed for dozens of hours or more in high-temperature environments above 100 ° C, resulting in increased power consumption during burn-in tests. Therefore, reducing burn-in test time is very important in reducing test cost. It is also very important for the time entry time of the product.

For example, if the maximum possible scan shift frequency of scan pattern 1 2030 of FIG. 20 is 25 MHz and the shift frequency of scan pattern 2 2032 can be further increased, as shown in FIG. By optimizing and increasing the shift frequency, the aging of the IC chip can be further accelerated by the temperature (c ° C.) higher than the temperature (b ° C.) of FIG. 20.

20 and 21 illustrate a case in which a shift frequency is assigned to a scan pattern and shifted in a scan chain for convenience of description, but as shown in FIGS. 5 and 6, the scan pattern is divided into at least two scan sections and different shifts are performed. You can shift in the scan chain by frequency.

FIG. 22 is a diagram illustrating an example of a method of finding an optimal shift frequency for each scan section in order to minimize time of a burn-in test according to the present invention.

Referring to FIG. 22, the burn-in test time minimizing apparatus divides one or more scan patterns into at least two scan sections (S2200). As an example of division of the scan pattern, the method illustrated in FIG. 5 may be used. The burn-in test time minimizing apparatus allocates a plurality of shift frequencies to each scan section (S2210). Here, the value of the shift frequency assigned to each scan section is a value smaller than the shift frequency at which the output pattern of the scan chain is different from the prediction pattern. The burn-in test time minimization apparatus performs the burn-in test while shifting the corresponding scan section by using the shift frequency allocated to each scan section (S2220).

The division of the scan pattern as the scan section (S2200), the allocation of the scan section of the shift frequency (S2210), the performance of the burn-in test (S2220), and the like may be performed in the same device or different devices, respectively.

The burn-in test time minimizer can identify the shift frequency just before the output pattern and the prediction pattern as the shift frequency increases or decreases as the maximum shift frequency that can be assigned to the corresponding scan section. According to an embodiment, each scan section may be assigned a shift frequency smaller than the maximum shift frequency found through the increase and decrease of the shift frequency.

In order to find the optimal shift frequency for each scan section for the burn-in test of the present invention, various embodiments described above may be used. For example, the burn-in test time minimization apparatus may perform the method illustrated in FIGS. 7 to 12 to find an optimal shift frequency for each scan section. Alternatively, the burn-in test time minimization apparatus may find an optimal shift frequency for each scan section by performing the method illustrated in FIGS. 14 and 15. In addition, the method of changing the arrangement order of the scan patterns shown in FIG. 17 may also be applied for reducing burn-in test time and improving burn-in test quality.

23 is a diagram illustrating an example of a burn-in test time minimization apparatus according to the present invention.

Referring to FIG. 23, an apparatus for minimizing burn-in test time includes a chamber controller 2300, a shifting unit 2310, and a shift frequency determining unit 2320.

The chamber controller 2300 controls the voltage, temperature, burn-in test time, etc., supplied to the inspection target IC chip.

The shift frequency determiner 2320 determines the optimum shift frequency shifted to the scan chain of the IC chip for each scan section during the burn-in test. For example, the shift frequency determiner 2320 may determine an optimal shift frequency for each scan section based on at least one or more of the various embodiments described above. In addition, the optimum shift frequency may be determined or determined by a separate device as well as the burn-in test time minimization apparatus, and the checked or determined shift frequency may be used by the shift frequency determiner 2320.

The shifting unit 2310 minimizes the burn-in test time by shifting the scan section in the scan chain by using the optimal shift frequency determined by the shift frequency determining unit 2320 while the burn-in test is performed by the chamber controller 2300. do.

Minimize burn-in test time The device can perform both a burn-in test and a salping scan test simultaneously. The burn-in test time minimization apparatus may be implemented as part of the salping burn-in test apparatus in FIGS. 18 and 19. For example, a burn-in test may be performed using only a scan pattern set assigned an optimized shift frequency for each scan section, or a burn-in test and a scan test may be performed together.

The burn-in test time minimization apparatus may rearrange the order of the scan patterns shifted in the scan chain by using the repositioning method of the scan pattern illustrated in FIG. 17. In this case, the switching part of the circuit and the number of switching operations of the circuit on the IC chip may be changed by the shift of the scan pattern, and thus the operation characteristics of the circuit, such as power consumption, may be changed and thus may be allocated to the scan pattern (or scan section). The shift frequency can be high. Therefore, after rearranging the scan pattern using this property, the entire shift-in test time may be further reduced by finding or determining an optimal shift frequency for each scan section by using the embodiment of the present invention which is previously described. In addition, the rearrangement of the scan pattern may be performed by a separate device as well as a burn-in test time minimization apparatus, and used by the burn-in test time minimization apparatus.

FIG. 27 is a diagram illustrating experimental results of a shift frequency when the scan power is approached to a threshold power consumption of an IC chip and a shift frequency optimized by a shift frequency increase / decrease method for each scan pattern. Referring to FIG. 27, the optimization of the shift frequency increase and decrease uses the method of FIG. 7.

Referring to FIG. 27, it can be seen that the shift frequency when approaching the threshold power consumption of the IC chip can be further optimized for each scan pattern through a shift frequency increase and decrease method.

FIG. 27 illustrates an experiment result using a microcontrol unit (IC) processor IC chip and a test pattern of the IC chip, and the scan frequency target scan section corresponds one to one scan pattern. 27 is a power-limit-based method for finding the maximum possible shift frequency without the power consumption consumed by the scan pattern exceeding the allowable power consumption of the IC chip, and the shift frequency increase and decrease of the present invention described above. The maximum shift frequency found for each scan pattern is shown through a shift-frequency-scailing-based method.

The power consumption limit of FIG. 27 is a functional average power consumption when the IC chip is operated in a functional mode at 80 MHz, which is the functional frequency limit of the IC chip.

In general, the functional frequency limits and the frequency limits at which the IC chip can be damaged are different. This is because the functional frequency limit may be subject to various constraints such as critical timing path and signal crosstalk by the circuit structure.

The first column of FIG. 27 is a scan pattern number, the second column is power consumption due to leakage current of the IC chip, the third column is dynamic power consumption consumed by the scan shift, and the fourth column is the second column. The power consumption per scan pattern, which is the sum of the third column, does not exceed the power consumption limit. The fifth column is the shift frequency corresponding to the power consumption of the fourth column, which is the maximum possible shift frequency of each scan pattern without exceeding the power consumption limit.

The sixth column represents the test pass or fail as a result of the IC chip test when tested at the fifth frequency shift frequency for each scan pattern.

The seventh column is the maximum shift frequency found through the shift frequency increase and decrease by the above-described method of the present invention, all of which pass the test result.

The eighth column is for the seventh column's incremental magnitude as a result of the shift-frequency-scailing-based method compared to the fifth column, which is the result of the power-limit-based method. Show percentage change.

As described in the fifth, seventh and eighth columns of FIG. 27, the above-described present invention is used even if the maximum shift frequency is used as the initial shift frequency such that the power consumption consumed by the scan pattern does not exceed the allowable power consumption of the IC chip. It can be seen that the shift frequency can be further optimized by using the shift frequency increase / decrease method. That is, FIG. 27 shows that the result by the power-limit-based method can be further improved by the shift-freq.-scailing-based method.

In addition, in FIG. 27, even when the shift frequency is used so that power consumption consumed by the scan pattern does not exceed the allowable power consumption of the IC chip, the IC chip may not be normally tested. As shown in FIG. 27, the difference between the shift frequency result by the power-limit-based method and the shift-frequency-scailing-based method is different from that of the actual IC chip and the test environment. In addition to the power consumption of the circuit, there are circuit structures and features that can affect the shift frequency, and various physical conditions and environments.

In addition, even if the bit value of a scan section or scan pattern is inadvertently changed while being loaded into the scan chain during shift-in in determining the optimum shift frequency through shift frequency increase and decrease, the value of the scan capture according to the structure of the IC chip circuit This may appear as a normal result pattern. Therefore, before loading the scan section and scanning capture in the scan chain through shift frequency increase and decrease, the output result of the main output port of the IC chip is compared with the predicted result to confirm that the output result is a pass. Can be found.

The function for carrying out the present invention and the scan shift frequency information obtained by performing the present invention or the scan section information reflecting the information can be embodied as computer readable codes or data on a computer readable recording medium. An example of the code is an executable computer program or software. The code or data may be executed or used on a device such as a scan test device, burn-in test device or computer. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include various types of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, optical data storage device, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code or data is stored and executed in a distributed fashion. In one embodiment, the computer program code or data may be stored in a server computer and the client computer may access the server computer to use the code or data, or download and store or use the code or data on the client computer. For example, the program code may be executed on a server computer or a client computer.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

Claims

For each of the at least two scan sections, identifying a first shift frequency based on a result of comparing the shift pattern or the output pattern of the scan chain obtained through the increase or decrease of the period of the shift frequency with a prediction pattern,

Wherein the shift frequency or period of the shift frequency is a frequency of the shift-in or shift-out frequency or frequency of the scan section.
The method of claim 1, wherein the determining of the first shift frequency comprises:

Selecting a scan section for which a shift frequency is not determined;

Increasing or decreasing the shift frequency;

Inputting the scan section into a scan chain using the increased shift frequency;

Moving to the step of increasing or decreasing the shift frequency if the output pattern of the scan chain is the same as the predictive pattern; And

And identifying a shift frequency when the output pattern is different from the prediction pattern as the first shift frequency.
The method of claim 1, wherein the determining of the first shift frequency comprises:

Selecting a scan section for which a shift frequency is not determined;

When a first input pattern located in front of the selected scan section, the selected scan section, and a second input pattern located behind the selected scan section are sequentially input to the scan chain, and the output pattern of the scan chain is different from the prediction pattern. Determining a shift frequency of the first shift frequency of the chip test time;
The method of claim 3, wherein

The shift frequency of the scan section belonging to the first input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the first input pattern,

The shift frequency of the scan section belonging to the second input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the second input pattern.

And shifting the shift frequency of the selected scan section until the output pattern differs from the prediction pattern.
The method of claim 3, wherein

The first input pattern is an actual first input pattern located in front of the selected scan section in an actual test or a prediction pattern of scan capture by the first input pattern,

And wherein the second input pattern is an actual second input pattern or dummy pattern located behind the selected scan section in an actual test.
The method of claim 3, wherein the determining of the first shift frequency comprises:

The shift frequency at a point in time at which the output pattern of the scan chain for the first input pattern is different from the first prediction pattern or the output pattern of the scan chain for the selected scan section is different from the second prediction pattern is identified as the first shift frequency. And minimizing chip test time.
The method of claim 6,

And wherein the second prediction pattern is a prediction pattern for scan capture performed while the selected scan section is loaded in the scan chain.
The method of claim 1, wherein the determining of the first shift frequency comprises:

Combining the increase or decrease of the supply frequency with the increase or decrease of the shift frequency to identify a first shift frequency at a point in time at which the output pattern and the prediction pattern are different for each scan section; Minimization method.
The method of claim 1,

Determining a second shift frequency smaller than the first shift frequency as the shift frequency of each scan section.
The method of claim 9, wherein the determining step,

Determining a second shift frequency for each scan section for a plurality of chips;

And determining a shift frequency of a corresponding scan section, which is equal to or smaller than the smallest value among the plurality of second shift frequencies determined for each scan section, for the plurality of chips.
The method of claim 1,

Grouping the at least two or more scan sections into at least one section group based on at least one or more constraints including a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time resulting from a scan shift frequency change; And

And determining a shift frequency of the section group, which is less than or equal to the smallest value among the determined shift frequencies of each scan section belonging to the section group.
The method of claim 1,

And performing a burn-in test and a scan test while increasing the temperature of the test chip using the shift frequency determined for the scan section.
The method of claim 2, wherein the inputting to the scan chain comprises:

And inputting the selected scan section to the scan chain in a state in which at least one of a shift frequency, a supply voltage, and an external temperature is reflected every time the repetition is performed.
The method of claim 1,

And rearranging and rearranging patterns on the scan pattern set including the scan section.
Determining a different shift frequency for each of the at least two scan sections;

Wherein the shift frequency determined for each scan section is a value smaller than the shift frequency at which the output pattern of the scan chain differs from the prediction pattern.
The method of claim 15, wherein the determining step,

Selecting a scan section for which a shift frequency is not determined;

The process of sequentially inputting a first input pattern located in front of the selected scan section, the selected scan section, and a second input pattern located behind the selected scan section into a scan chain, wherein the first input pattern and the first input pattern are repeatedly performed. Inputting a second input pattern into the scan chain at a preset shift frequency and inputting the selected scan section to the scan chain at an increased or decreased shift frequency at each iteration; And

And determining a shift frequency of the selected scan section as a shift frequency of which the output pattern of the scan chain is smaller than the shift frequency of a time point different from the predicted pattern.
The method of claim 16,

And the output pattern is unloaded by shifting out a result pattern of scan capture when at least one of the first input pattern and the selected scan section is loaded.
The method of claim 16, wherein the inputting to the scan chain comprises:

And inputting the selected scan section to the scan chain in a state in which at least one of a shift frequency, a supply voltage, and an external temperature is reflected every time the repetition is performed.
The method of claim 15,

And performing a burn-in test and a scan test while increasing the temperature of the test chip using the shift frequency determined for the scan section.
The method of claim 15,

And rearranging and rearranging patterns on the scan pattern set including the scan section.
The method of claim 15,

The determining of the shift frequency may include determining a shift frequency divided by a shift frequency of a predetermined magnitude that may be increased or decreased by scan test equipment as a shift frequency of each scan section. Minimization method.
The method of claim 15, wherein the determining step,

Determining a shift frequency of each scan section for a plurality of chips; And

And determining a shift frequency of the corresponding scan section, which is less than the smallest value among the plurality of shift frequencies determined for each scan section, for the plurality of chips.
The method of claim 15,

Grouping the at least two or more scan sections into at least one section group based on at least one or more constraints including a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time resulting from a scan shift frequency change; And

And determining a shift frequency of the section group, which is less than or equal to the smallest value among the determined shift frequencies of each scan section belonging to the section group.
The method of claim 16, wherein the inputting to the scan chain comprises:

And inputting the selected scan section to the scan chain in a state in which at least one of a shift frequency, a supply voltage, and an external temperature is reflected every time the repetition is performed.
A frequency increase / decrease unit for increasing or decreasing a scan shift frequency;

A pattern input unit configured to input at least one scan section into a scan chain;

A pattern comparison unit to determine whether an output pattern of the scan chain is identical to a prediction pattern; And

And a frequency grasp unit for identifying a shift frequency smaller than a shift frequency at a time point at which the output pattern and the prediction pattern are different as possible shift frequencies of the scan section.

Chip test time minimizing device, characterized in that some or all of the shift frequencies respectively identified for at least two scan sections are different from each other.
The method of claim 25,

And a pattern divider for dividing one or more scan patterns into at least two scan sections.
The method of claim 25, wherein the frequency grasping unit,

Repeating the step of inputting a scan section and a scan pattern located in front of the scan section into the scan chain, the scan pattern located in front of the scan section is input to the scan chain at a preset shift frequency, the scan section is repeated The chip test time is characterized by inputting the scan chain with the shift frequency increased or decreased every time, and identifying the shift frequency in which the output pattern of the scan chain is smaller than the shift frequency at a time point different from the prediction pattern. Minimize device.
An output pattern of the scan chain for at least one scan section in which power consumption or current consumption when shifting the scan section in the scan chain at a preset initial shift frequency of at least two scan sections is above or above a preset threshold; Determining a shift frequency equal to the prediction pattern.
The method of claim 28,

Allocating below the initial shift frequency for at least one or more scan sections where power consumption or current consumption is below or below the threshold.
The method of claim 28,

Determining a first shift frequency for a first scan section in which power consumption or current consumption is above or above the threshold; And

Determining a second shift frequency for a second scan section where power consumption or current consumption is below or below the threshold;

And the first shift frequency and the second shift frequency are different from each other.
The method of claim 28,

Shift frequencies of some or all of the scan sections whose power consumption or current is below or below the threshold are equal to each other,

At least some of the scan sections whose power consumption or current is above or above the threshold are different in shift frequency from each other.
The method of claim 28, wherein determining the shift frequency,

Selecting a scan section in which a shift frequency is not determined among scan sections in which power consumption or current consumption is above or above a preset threshold;

Increasing or decreasing the shift frequency;

Shifting the selected scan section into a scan chain at the increased or decreased shift frequency;

Comparing whether the output pattern and the prediction pattern of the scan chain are the same;

Moving to the step of increasing or decreasing the shift frequency if the output pattern and the prediction pattern are the same; And

And determining the shift frequency of the selected scan section to be equal to or less than the shift frequency before the output pattern and the prediction pattern are different from each other. 2.
The method of claim 28,

And performing a burn-in test and a scan test by increasing the temperature of the chip to be tested using the shift frequency determined or determined for the scan section and the corresponding scan section.
The method of claim 28,

And rearranging and reordering the scan patterns.
Determining a first shift frequency and a second shift frequency at which power consumption or current consumption when shifting the first scan section and the second scan section into the scan chain is above or above a preset threshold; And

Determining a third shift frequency and a fourth shift frequency when power consumption or current consumption when shifting a third scan section and a fourth scan section to the scan chain is less than or less than the threshold;

The first shift frequency and the second shift frequency are different from each other,

And the third shift frequency and the fourth shift frequency are the same.
36. The method of claim 35, wherein determining the first shift frequency and the second shift frequency comprises:

Identifying a first scan section and a second scan section whose power consumption or current consumption when shifting the scan section to the scan chain at a preset initial shift frequency is above or above the threshold;

For each of the first scan section and the second scan section, determining a shift frequency in which the output pattern of the scan chain is equal to a prediction pattern as the first shift frequency and the second shift frequency, respectively, by increasing or decreasing the shift frequency; Chip test time minimizing method comprising a.
36. The method of claim 35, wherein determining the third shift frequency and the fourth shift frequency comprises:

Identifying a third scan section and a fourth scan section whose power consumption or current consumption when shifting the scan section to the scan chain at a preset initial shift frequency is less than or equal to or less than the threshold;

And determining, for the third scan section and the fourth scan section, the initial shift frequency or less as the third shift frequency and the fourth shift frequency.
The method of claim 35, wherein

And performing a burn-in test and a scan test by increasing the temperature of the chip to be tested using the shift frequency determined or determined for the scan section and the corresponding scan section.
The method of claim 35, wherein

And rearranging and reordering the scan patterns.
A power detector for detecting power consumption or current consumption when the scan section is shifted in the scan chain at a first shift frequency;

A first frequency grasp for identifying or determining the first shift frequency or less as a possible shift frequency of the scan section for at least one or more scan sections whose power consumption or current consumption by the first shift frequency is below or below a predetermined threshold; part; And

A second for identifying or determining at least one second shift frequency for at least one scan section where power consumption or current draw is above or above the threshold, the output pattern of the scan chain being equal to a prediction pattern Chip test time minimizing apparatus comprising a; frequency grasping unit.
The method of claim 40,

And a pattern dividing unit dividing the scan pattern into at least two scan sections.
The method of claim 40,

Shift frequencies of some or all of the scan sections whose power consumption or current is below or below the threshold are equal to each other,

And some or all of the scan sections whose power consumption is above or above the threshold are different in shift frequency from each other.
A computer-readable recording medium having recorded thereon a program for performing the method of claim 1.
A computer-readable recording medium storing shift frequency information determined or determined for a scan section by performing the method of claim 1, or scanning section information reflecting the shift frequency information.
A computer-readable recording medium having recorded thereon a program for performing the method of claim 15.
A computer-readable recording medium storing shift frequency information determined or determined for a scan section by performing the method described in claim 15 or scan section information reflecting the shift frequency information.
A computer-readable recording medium having recorded thereon a program for performing the method of claim 28.
29. A computer-readable recording medium having recorded thereon the shift frequency information or the scan section information reflecting the shift frequency information, which is determined or determined for the scan section by performing the method of claim 28.
A computer-readable recording medium having recorded thereon a program for performing the method of claim 35.
A computer-readable recording medium storing shift frequency information determined or determined for a scan section or scan section information reflecting the shift frequency information by performing the method of claim 35.
Shifting the scan section into a scan chain using different shift frequencies assigned for each of at least two scan sections; And

And performing a burn-in test together with the shifting.
The method of claim 51, wherein the shift frequency allocated to each scan section,

For each scan section, identifying a first shift frequency at which the output pattern of the scan chain differs from the prediction pattern by increasing or decreasing the shift frequency; And

Determining a second shift frequency smaller than the first shift frequency as a shift frequency of each scan section.
53. The method of claim 52, wherein identifying the first shift frequency comprises:

Selecting a scan section for which a shift frequency is not determined; And

When a first input pattern located in front of the selected scan section, the selected scan section, and a second input pattern located behind the selected scan section are sequentially input to the scan chain, and the output pattern of the scan chain is different from the prediction pattern. Determining a shift frequency of the first shift frequency of the chip test time;
The method of claim 53,

The shift frequency of the scan section belonging to the first input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the first input pattern,

The shift frequency of the scan section belonging to the second input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the second input pattern.

And shifting the shift frequency of the selected scan section until the output pattern differs from the prediction pattern.
The method of claim 53,

The first input pattern is an actual first input pattern located in front of the selected scan section in an actual test or a prediction pattern of scan capture by the first input pattern,

And wherein the second input pattern is an actual second input pattern or dummy pattern located behind the selected scan section in an actual test.
54. The method of claim 53, wherein identifying the first shift frequency comprises:

The shift frequency at a point in time at which the output pattern of the scan chain for the first input pattern is different from the first prediction pattern or the output pattern of the scan chain for the selected scan section is different from the second prediction pattern is identified as the first shift frequency. And minimizing chip test time.
The method of claim 51,

And a shift frequency allocated to each scan section is determined based on power consumption or current consumption of each scan section.
The method of claim 51,

Some or all of the shift frequencies assigned to the scan sections in which the power consumption or the current consumption when shifting the scan section in the scan chain at the preset initial shift frequency are equal to or less than each other are equal to each other,

And some or all of the shift frequencies assigned to the scan sections whose power consumption or current is above or above the threshold are different from each other.
The method of claim 51,

Grouping the at least two or more scan sections into at least one section group based on at least one or more constraints including a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time resulting from a scan shift frequency change; And

And determining a shift frequency of the section group, which is less than or equal to the smallest value among the determined shift frequencies of each scan section belonging to the section group.
62. The method of claim 61,

And rearranging and rearranging patterns on the scan pattern set including the scan section.
A chamber controller for controlling the supplied voltage and temperature; And

And a shifting unit configured to shift the scan section in the scan chain while the voltage and the temperature are supplied.

A chip test time minimization apparatus, wherein the scan sections are shifted in the scan chain using different shift frequencies for each of the at least two scan sections.
The method of claim 61, wherein the shifting unit,

Chip test time minimization device, comprising dividing one or more scan patterns into at least two scan sections.
The method of claim 61, wherein the shifting unit,

The chip test time minimizing device, characterized in that for shifting the scan section in the scan chain by using the shift frequency determined based on the power consumption or current consumption during the shifting for each scan section.
A computer-readable recording medium having recorded thereon a program for performing the method of claim 51.
A computer readable recording medium having recorded thereon shift frequency information or scan section information reflecting the shift frequency, by performing the method of claim 51.