KR101618822B1 - Method for minimizing scan test time and apparatus therefor - Google Patents

Abstract

Disclosed are a method for minimizing a scan test time by optimizing a shift frequency by scan sections, and an apparatus therefor. The apparatus divides scan patterns into two or more scan sections, and determines a second shift frequency lower than a first shift frequency as the shift frequency of each of the scan selections after the first shift frequency where the output pattern of a scan chain is different from a prediction pattern is recognized by an increase/decrease in a shift frequency, for each of the scan sections.

Description

[0001] The present invention relates to a method for minimizing scan test time,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to IC (Integrated Circuit) chip scan test, and more particularly, to a method and apparatus for optimizing a shift frequency to minimize the time of a scan test.

The most common method for testing an IC chip is to apply test data to the input of the IC chip and compare the observed value at the output of the IC chip with a predicted value that is known in advance. However, when an IC chip including a sequential logic having a storage element such as a flip-flop is to be tested, a desired value may be externally applied to the flip-flop in the IC chip or a value of the flip- It is very difficult to observe from outside. To solve this problem, there is a scan design method.

The scan design method is one of the design-for-testability (DFT) methods used to increase the controllability and observability of the circuit. Using the scan design method, the ATPG (Automatic Test Pattern Generator) software, which automatically generates test patterns based on the structural information of the circuit, is used to test small size and high fault coverage Data can be obtained.

In other words, the scan design allows sequential logic to be combinational logic during scan test so that the circuit can be easily controlled and observed outside the chip, and the size of test data can be minimized through ATPG have. The test data obtained through the scan design and the ATPG software are composed of at least one scan pattern. In general, the scan patterns have an order in performing the scan test. The set of test patterns consists of one or more scan patterns.

1 is a view illustrating an example of an IC chip to which a conventional scan design method is applied.

1, the IC chip 100 is a sequential logic circuit including at least one combination circuit 110 and a plurality of flip-flops 120, 130 and 140. In the case of FIG. 1, the flip-flops 120, 130 and 140 may be implemented by a multiplexer (MUX) type scan flip-flop or various other methods.

The IC chip 100 includes a primary input port (PI) 150, a primary output port 152, a scan enable (SE) port 160, a scan input port 162 A clock input port 164, a scan output port 166, and the like. The scan enable port 160 and the clock input port 164 are connected to the flip-flops 120, 130 and 140, respectively. Each of the flip-flops 120, 130, and 140 is connected to the combinational circuit 110 to output the values stored in the respective flip-flops to the combinational circuit, and receives the value output from the combinational circuit.

The main input port 150 and the main output port 152 are ports for inputting and outputting data during normal operation of the IC chip, respectively.

The scan enable port 160 is a port for inputting a scan enable signal or a scan disable signal. In response to a scan enable signal or a scan disable signal, the IC chip is in a normal mode, that is, a functional mode The scan mode for testing the IC chip becomes the scan mode.

The scan input port 162 is a port for inputting a scan pattern for testing the IC chip 100 and the scan output port 166 is a port for outputting a test result based on a scan pattern. The test result output through the scan output port is called an output pattern.

The clock input port 164 may be triggered to load the scan pattern input through the scan input port 162 to the flip flops 120, 130 and 140 or to capture the output of the combinational circuit 110 to the flip flops 120, 130, ) Is a port for inputting a clock signal. For example, the flip-flops 120, 130, and 140 are triggered by a rising edge or a falling edge of a clock signal input through a clock input port 164 to store or capture an input value.

A path (dotted line path) connected from the scan input port 162 to the scan output port 166 through the plurality of flip flops 120, 130 and 140 is referred to as a scan chain or a scan path. Although a single scan chain is shown in FIG. 1, a plurality of scan chains can be used.

In the functional mode, the combinational circuit 110 performs the normal operation of receiving data through the main input port 150 and outputting the result through the main output port 152. [ In addition, in the functional mode, the flip-flops 120, 130 and 140 receive the output value of the combinational circuit 110 according to the clock signal, and during the scan test, this operation is called scan capture.

In the scan mode, each bit of the scan pattern is sequentially shifted in accordance with the clock signal to the flip-flops 120, 130 and 140 existing in the scan path, and sequentially through the scan output port 166 And is shifted out. A state in which the scan pattern is shifted to the flip-flops 120, 130 and 140 is referred to as a load and a state in which the values stored in the flip-flops 120, 130 and 140 are shifted out through the scan output port 166 is unloaded ).

For example, if the number of flip-flops 120, 130, 140 on the scan chain in the IC chip is three, the length of each scan pattern is made up of 3 bits of the same length as the number of flip flops on the scan chain, And are sequentially shifted to the flip-flops 120, 130 and 140 on the scan chain according to the clock signal. That is, when the value is stored in the flip-flop at the rising edge of the clock signal, the first bit of the scan pattern is stored in the first flip-flop 140 on one rising edge of the clock signal, The output value of the first flip flop 140 is stored in the second flip flop 130 and the second bit value of the scan pattern is stored in the first flip flop 140. In the next clock signal, the output value of the second flip-flop 130 is stored in the third flip-flop 120, the output value of the first flip-flop 140 is stored in the second flip-flop 130, Th flip-flop 140 stores the third bit value of the scan pattern. Thus, one scan pattern is loaded into the flip-flops 120, 130, and 140 on the scan chain with three clock signals. Similarly, the values of the flip-flops 120, 130 and 140 on the scan chain are unloaded through the scan output port 166 with three clock signals.

The general scan test process will be described in more detail as follows.

(1) Main input test data is applied to the main input port 150 of the IC chip 100.

(2) A scan enable signal is applied to the scan enable port 160 to put the chip 100 into a scan mode.

(3) Load the scan pattern into the flip-flops 120, 130 and 140 on the scan chain by shifting the scan pattern to the scan input port 162. The scan pattern loaded in the scan chain is applied to the combinational circuit 110. After the scan pattern is applied to the combinational circuit, the result output through the main output port 152 is compared with the predicted main output value, and if the comparison result is different, the IC chip is a defective product.

(4) The scan enable signal is applied to the scan enable port 160 to switch the chip 100 from the scan mode to the functional mode. In the functional mode, when the clock signal is applied, the flip-flops 120, 130 and 140 capture the output value of the combinational circuit 110, and this operation is called scan capture.

(5) The scan enable signal is applied to the scan enable port 160 to switch the chip back from the functional mode to the scan mode.

(6) Then, the values captured in the flip-flops 120, 130 and 140 on the scan chain are shifted out through the scan output port 166 and unloaded.

(7) The unloaded output pattern is compared with a predicted pattern that is known beforehand to determine whether the IC chip is operating normally. Here, the predictive pattern is a scan pattern output through the scan output port 166 after the main input test data and the scan pattern are applied and the scan capture operation is performed when the IC chip is normal. That is, if the comparison result in the step (3) and the comparison result in the step (7) are both the same, the IC chip is a good product, otherwise, the IC chip is a defective product.

The types of scan tests are divided into stuck-at-fault test and delay fault test. Here, the stuck-at fault means that a signal line on the IC chip is inadvertently stuck to a logic 0 (logic 0) or a logic 1 (logic 1) value, and a delay fault refers to a signal line or path path) of the IC chip due to the delay time when the signal value is transmitted through the IC chip.

Types of delayed fault tests also include transition delay tests and path delay tests. The transition delay test is to test whether a specific node or signal line on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem. The path delay test is to test whether a particular path on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem.

On-Capture and Launch-On-Shift methods are representative methods for delay fault test, and these methods also scan scan patterns for delay fault test A load operation that shifts in on the chain, and an unload operation that shifts out the delay fault test results captured by the flip flops on the scan chain.

In the conventional scan test, since the number of clock pulses required to shift the number of flip-flops on the scan chain is required, it takes a long time to perform the shift-in and shift-out operations. However, the frequency of the clock signal, that is, the shift frequency, can not simply be increased to reduce the test time.

For example, when the scan shift frequency is simply increased, there is a problem of over kill in which a good product is determined as a defective product due to a power consumption or a problem of a cirtical path delay time.

In addition, as the IC chip is further reduced in power due to the low-power design as well as the deep sub-micron (DSM) microprocessing and low-power process, the influence of the power supply noise on the IC chip operating frequency is further increased. In particular, since the IC chip generates more switching operation than the scan mode in the functional mode, additional delay of the signal line due to the power supply noise due to the switching operation can cause delay test overkill, There is a limit to it.

In addition, the problem of signal integrity due to signal crosstalk on the IC chip has become more important as it goes to DSM microprocessing. Switching operation, which occurs more frequently than in scan mode, increases the inter-signal interference. Therefore, additional delay in the signal line due to inter-signal line interference in the delay test may cause delay test overkill.

In the case of finding the shift frequency based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, due to the influence of excessive circuit switching operation and process variation on the IC chip, -drop or Ground-bounce may cause scan test failure problems. For example, in a delay test using a scan pattern, an additional delay may occur in a particular signal line due to the influence of IR-drop, i.e., voltage drop, which may cause a delay test overrun. Conversely, even if the power consumption of the scan pattern exceeds the specification of the IC chip, IR-drop or ground-bounce problem may not occur due to the process and design characteristics of the chip. Therefore, there is a limit to finding the optimal shift frequency for the IC chip by simply using the power consumption value. In addition, when finding the maximum shift frequency only by the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, a critical path timing problem may occur on the scan chain due to the increased Schmitt frequency. have.

Also, increasing the shift frequency may cause a critical path timing problem on the scan chain, but logical problems due to the scan pattern may not occur. In other words, depending on the state of the bit value on the critical path of the scan chain, a false critical path case may occur in a particular scan shift cycle.

In addition, a low-power IC chip using a voltage island or voltage domain technique provides a high voltage in a design area for high speed performance and a relatively low voltage in a non- As a result, the allowable power consumption differs for each voltage region.

Patent Publication No. 2012-0102876

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for minimizing a scan test time by optimizing a shift frequency used for shift-in or shift-out of a scan pattern into a scan chain for each scan section have.

According to another aspect of the present invention, there is provided a method of minimizing a scan test time, the method comprising the steps of: increasing / decreasing a shift frequency for each of at least two scan sections, Determining a first shift frequency; And determining a shift frequency of each scan section as a second shift frequency smaller than the first shift frequency.

According to another aspect of the present invention, there is provided a method of minimizing scan test time, the method comprising: determining different shift frequencies for at least two scan sections; And the determined shift frequency is a value smaller than a shift frequency at which the output pattern of the scan chain is different from the predicted pattern.

According to an aspect of the present invention, there is provided an apparatus for minimizing a scan test time comprising: a frequency adjuster for increasing or decreasing a scan shift frequency; A pattern input unit for inputting a scan pattern including at least one scan section into a scan chain; A pattern comparison unit for determining whether an output pattern of the scan chain is the same as a predicted pattern; And a frequency detector for detecting a shift frequency smaller than a shift frequency at a time when the output pattern and the predicted pattern are different from each other as a possible shift frequency of the scan section, Some or all of which are different from each other.

According to the present invention, an optimal shift frequency is provided for each scan pattern, scan section, or section group. In addition, when the shift frequency is increased by considering only the power consumption or the cirtical path delay time, it is possible to minimize the scan test time while solving the over kill problem of determining the good product as defective due to the overshift frequency An optimal shift frequency can be found.

In addition, the optimum shift frequency can be found by taking into consideration the influence of power supply noise and the influence of interference between signal lines. It also finds the optimal shift frequency to reflect the effects of IR-drop or ground-bounce, which can be caused by excessive circuit switching behavior, process variation, fine processing, low power processes, or low power design caused by scan tests. .

Also, the optimum shift frequency can be found by considering the influence of the critical path timing on the scan chain, which may occur when the shift frequency is increased.

Also, when the critical path of the scan chain becomes a false critical path state according to the bit value on the scan chain, the critical timing constraint is ignored and the scan shift frequency is maximized within the range in which the IC chip can operate normally, Can be minimized.

In the case of a low power IC chip using a voltage island or a voltage doamin or region technique, an optimal shift frequency can be found by reflecting the power consumption allowed for each voltage island or voltage region.

In addition, since the circuit design information of the IC chip is not required in finding the optimal shift frequency of the scan pattern or the scan section, even if the circuit design information of the chip is lost or lost, You can find the frequency. You can also reduce the burn-in test time.

1 is a view showing an example of an IC chip to which a conventional scan designing method is applied,
FIG. 2 and FIG. 3 are views each showing a configuration of an embodiment of a scan test apparatus to which the present invention is applied,
4 is a diagram illustrating an example of a scan pattern that can be applied to a scan test time minimization method according to the present invention to reduce a scan test time.
5 is a view illustrating an example of a scan section according to the present invention.
6 is a diagram illustrating an example of assigning a shift frequency to each scan section in order to minimize a scan test time according to the present invention.
7 is a diagram illustrating an example of a method for finding a shift frequency for minimizing a scan test time according to the present invention.
8 is a flowchart illustrating an example of a scan test time minimization method according to the present invention.
FIG. 9 is a flowchart illustrating another example of a scan test time minimization method according to the present invention;
FIG. 10 is a diagram showing a more detailed process of the scan test time minimization method according to the present invention.
FIG. 11 is a flowchart illustrating a specific procedure for determining a normal shift-in in the scan test time minimization method according to the present invention.
FIG. 12 is a flowchart illustrating another example of a scan test time minimization method according to the present invention;
13 is a diagram illustrating a configuration of an apparatus for minimizing a scan test time according to an embodiment of the present invention,
FIG. 14 is a diagram illustrating an example of a method of relocating a scan pattern for minimizing a scan test time according to the present invention.

Hereinafter, a method and apparatus for minimizing scan test time according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 2 and 3 are views each showing the configuration of an IC chip test apparatus, that is, a scan test apparatus, which is generally called ATE (Automatic Test Equipment) to which the present invention is applied.

2 and 3, the scan test apparatus includes a host computer 200 and 300, a tester main body 210 and 310, test heads 220 and 320, and interface boards 230 and 330. A device under test (DUT) (240, 340) located on an interface board for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on the wafer, it may further include a prober 350. Hereinafter, an IC chip on a wafer or a packaged IC chip is collectively referred to as an IC chip.

The tester bodies 210 and 310 control the scan test as a whole. For example, the tester body controls overall processes such as setup for DUT testing, generation of electrical signals for DUT testing, observation and measurement of DUT test result signals, and the like. The test bodies 210 and 310 may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and may include a device power supply device Power Supply). The tester main bodies 210 and 310 include a controller for controlling a signal processing processor (DSP) (not shown) for processing various digital signals and the test heads 220 and 320, a controller for applying a signal to the DUTs 240 and 340, Dedicated hardware, such as a generator, software or firmware, and the like. The test bodies 210 and 310 are also referred to as mainframes or servers.

The host computer 200, 300 may be a computer, such as a workstation, and is a device that allows a user to run a test program, control the test process, and analyze test results. In general, the host computers 200 and 300 may include a central processing unit, a storage unit such as a memory or a hard disk, a user interface, and the like, and may be connected to the tester bodies 210 and 310 through wired or wireless communication. The host computer 200, 300 may include dedicated hardware, software, firmware, etc. for controlling the test. Although the host computer 200 and the test main body 200 are separately shown in the present embodiment, the host computers 200 and 300 and the test main bodies 210 and 310 may be implemented as a single device.

An example of the memory of the tester main body 210 or 310 or the host computer 200 or 300 may be a DRAM, an SRAM, a flash memory, or the like, and the memory may store programs and data for performing the DUT test.

Software or firmware of the tester main body 210 or 310 or the host computer 200 or 300 is a device driver program, an operating system (OS) program for a scan test, a program for performing a DUT test, a setup for a DUT test, a DUT test And the like, and may be stored in a memory in the form of an instruction code for performing observation analysis of the DUT test result signal, and may be performed by the central processing unit. Thus, the scan test pattern can be applied to the DUT by such a program. It is also possible to obtain the DUT test and the reporting and analysis data of the test result automatically through the program. The language used in the program can be a variety of languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, a magnetic tape or a flash memory.

The central processing unit of the tester main body 210, 310 or the host computer 200, 300 is a processor which executes the code of the software or program stored in the memory. For example, when receiving a user command through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes the command through a software or a program, and outputs the result to a user interface such as a speaker, To the user.

The user interface of the tester main body 210, 310 or the host computer 200, 300 allows information to be communicated between the user and the device and to communicate commands. For example, there are an interface device for user input such as a keyboard, a touch screen, a mouse and the like, and an output interface device such as a speaker, a printer, and a monitor.

The test heads 220 and 320 include channels for electrical signal transmission between the tester main bodies 210 and 310 and the DUTs 240 and 340. Interface boards 230 and 330 are provided on the test heads 220 and 320, respectively. The interface board used to test packaged IC chips is generally called a load board, and the interface board used for testing IC chips on a wafer is called a probe card.

The test apparatuses shown in FIGS. 2 and 3 are merely examples for facilitating understanding of the present invention, and each of the configurations may be integrated into one unit, or one unit may be divided into a plurality of units. Various design changes are possible.

FIG. 4 is a diagram illustrating an example of a scan pattern that can be applied to a scan test time minimization method according to the present invention to reduce a scan test time.

Referring to FIG. 4, shift-in and shift-out operations are simultaneously performed in order to reduce the time required for performing the shift-in operation and the shift-out operation in the scan mode, respectively. That is, the load and unload operations are performed simultaneously.

For example, when the k-th input scan pattern 430 is loaded in the scan chain via the scan input port, the test result by the (k-1) -th input scan pattern 400 shifts the scan output port simultaneously - Out and unloaded. At this time, the unloaded output pattern is compared with the predicted output scan pattern 440 for the (k-1) th input scan pattern 400 managed in pairs with the kth input scan pattern 430.

In order to perform a scan test by overlapping shift-in and shift-out operations, a prediction for a k-th input scan pattern 430 shifted through the scan input port and a k-1 input scan pattern 400 And the output scan patterns 440 are managed in pairs. Thus, the scan patterns can be in sequence with each other. The scan patterns can also be rearranged in various ways.

The output pattern that is shifted out simultaneously when shifting the first scan pattern to the scan chain may be a don't-care pattern or a scan chain state value due to a reset of the chip under test.

Another way to minimize scan test time is to reduce the amount of scan patterns for scan test and to increase the shift frequency to quickly apply scan patterns to the IC chip. In the following, the present invention mainly explains a method of increasing the shift frequency to minimize the scan test time.

5 is a diagram illustrating an example of dividing a scan pattern into scan sections in order to minimize the time of the scan test according to the present invention.

Referring to FIG. 5, a set of scan patterns composed of one or more input scan patterns is divided into at least two scan sections. That is, the scan section may be constituted by at least one scan pattern or a part of the scan pattern, and an optimal shift frequency may be found for each scan section to further save the scan test time.

In the first embodiment, the scan section 500 is composed of one scan pattern and may correspond one-to-one with the scan pattern. That is, the scan pattern may be a scan section.

In a second embodiment, the scan section 510 may include two scan patterns. The number of scan patterns included in the scan section may be variously changed according to the embodiment.

In the third embodiment, the scan section 520 may be composed of a part of the first scan pattern and a part of the second scan pattern.

In the fourth embodiment, the scan section 530 may be configured as a part of one scan pattern.

In a fifth embodiment, one scan pattern may be divided into two scan sections 540, 550. The number of scan sections included in one scan pattern can be variously changed according to the embodiment.

The one or more scan patterns can be divided into any one of the above-described embodiments 500, 510, 520, 530, 540, and 550, and the scan patterns can be divided by applying two or more of these embodiments. For example, the set of scan patterns having N scan patterns shown in FIG. 5 includes a first scan section 500 including one scan pattern, a second scan section 510 including two scan patterns, And the third and fourth scan sections 540 and 550 including a part of the pattern.

In addition, various methods of dividing a set of scan patterns into scan sections can be applied, and the present invention is not limited to the scan section shown in Fig.

6 is a diagram illustrating an example of assigning a shift frequency to each scan section in order to minimize scan test time according to the present invention.

Referring to FIG. 6, a plurality of shift frequencies are allocated to each scan section. In the case of a conventional scan test, a fixed scan shift frequency is used in advance according to the IC chip, and this single frequency is referred to as a nominal shift frequency.

The nominal shift frequency is the shift frequency used when making the scan pattern with the ATPG software, or a significantly lower frequency with a slightly adjusted shift frequency based on this. Therefore, if these frequencies can be used as they are, the scan test time will be long.

However, when the nominal shift frequency is increased, the power consumption occurring when the shift-in and shift-out is performed according to the scan pattern is out of the power range required by the IC chip, so that the normal scan test can not be performed. In addition, due to the overshift frequency, there may occur an over kill problem in which a good product is determined as a defective product due to a cirtical path delay time problem, an increase in power supply noise influence, and an increase in influence of interference between signal lines.

Therefore, the present invention does not apply a single shift frequency such as the nominal shift frequency to the entire scan pattern, but allocates an optimal shift frequency that can be normally shifted to the scan chain for each scan section. The process of finding an optimal shift frequency for each scan section will be described in more detail with reference to FIG. Here, the optimal shift frequency may be an allowable maximum shift frequency or a shift frequency less than the allowable maximum shift frequency.

Referring again to FIG. 6, the first scan section is assigned a shift frequency A and the second scan section is assigned a shift frequency B. FIG. And the third scan section is assigned the same shift frequency A as the first scan section. As such, each scan section may be assigned the same shift frequency or may be assigned a different shift frequency.

For example, in the case where one scan pattern is divided into a plurality of scan sections, a plurality of sweep frequencies may be assigned to one scan pattern. Referring to FIG. 5, two scan sections 540 and 550 belonging to one scan pattern may be assigned different shift frequencies. That is, two shift frequencies are assigned to one scan pattern.

Each scan section assigned shift frequency may be integrated into a section group according to an embodiment. For example, the second scan section and the third scan section may be grouped into a section group, and a smaller shift frequency of the shift frequencies A and B of each scan section or less may be assigned to the corresponding section group.
The test data can be applied to the main input port of the general scan test process described in the background art and the test result observation at the main output after the scan pattern input to the scan chain can be applied as a general scan test process .

FIG. 7 is a diagram illustrating an example of a method for finding a shift frequency for minimizing a scan test time according to the present invention.

FIG. 7 illustrates an example of a method for minimizing a scan test time when the shift-in and shift-out operations illustrated in FIG. 4 are performed in a superposed manner. FIG. 7 illustrates one example according to the present invention, and is not limited to the case where the shift-in and shift-out described in FIG. 4 are simultaneously performed.

For convenience of explanation, it is assumed that a kth scan section 704 is a section for searching for an optimal scan shift frequency, and a kth scan section 704 is a one-to-one correspondence with a kth input scan pattern. Of course, the kth scan section 704 may be a part of the scan pattern or a plurality of scan patterns as described with reference to FIG.

Referring to FIG. 7, a k-1-th input pattern 702 and a (k + 1) -th input pattern 706 are used to check whether a kth scan section 704 is normally shifted- Is required.

The (k-1) th input pattern 702 may be a (k-1) th scan pattern used in an actual scan test located in front of the kth scan section 704, And may be a prediction pattern obtained when capturing. The (k + 1) -th input pattern 706 may be a (k + 1) th scan pattern used in an actual scan test located behind the kth scan section 704 or a bit pattern of '0' or '1' Quot; 0 " or " 1 " based on consecutive bits or consecutive bits.

In the scan test, the input scan patterns located respectively before and after the first scan section of the first scan section are composed of bits '0' or '1' in order to reduce the switching operation on the scan chain, Or " 1 ", respectively. The input scan pattern located before the first scan section may be a value on the scan chain when the chip under test is in the reset state.

Each of the (k-1) -th input pattern 702 or the (k + 1) -th input pattern 706 may be constituted by one or more scan sections, and these sections may be optimized (K + 1) th input pattern 702 or (k + 1) -th input pattern 706 is applied to the corresponding section by applying a predetermined shift frequency equal to or less than the optimum shift frequency to the corresponding section, . The predetermined shift frequency may be a nominal shift frequency or more, a preset value for each device, or a value set by a user, and the present invention is not limited thereto.

For example, when the method according to the present invention is applied to scan patterns sequentially, an optimal shift of a scan section for a k-th scan pattern is performed before a shift frequency of a scan section for a k < th & The frequency is predetermined. Therefore, the apparatus for minimizing the scan test time may use the determined optimum shift frequency for the scan section of the (k-1) th scan pattern and use a nominal shift frequency for the scan section for the (k + 1) th scan pattern.

Then, the k-th scan pattern is sequentially input to the scan chain 710 while increasing / decreasing the shift frequency with respect to the section for which the optimum shift frequency of the kth scan pattern is to be searched, ) Is the same as the prediction pattern 730.

For example, the apparatus for minimizing the scan test time sets the initial shift frequency to the nominal shift frequency, and increases the shift frequency in units of a predetermined shift frequency in the scan test time minimizing apparatus. That is, after loading the (k-1) -th input scan pattern 702 into the scan chain with a predetermined shift frequency such as a nominal frequency, the kth scan section 704 is shifted to the "initial shift frequency + (I.e., the output pattern K-1) 722 by the (k-1) -th input scan pattern 702 to shift-out the predicted pattern K-1 (732). The output pattern K 724 obtained by shifting out the test result by the kth scan pattern 704 is shifted to the predicted pattern K 734 ).

The predetermined shift frequency mentioned above may be variously changed according to the embodiment such as a nominal shift frequency, a nominal shift frequency higher or lower than the nominal shift frequency, a preset value for each apparatus or a value set by the user. It is not.

When the output pattern K-1 722 and the predicted pattern K-1 732 are the same and the output pattern K 724 and the predicted pattern K 734 are the same, the apparatus for minimizing the scan test time finds the optimal shift frequency The shift frequency for the scan section K 704 is increased by a predetermined magnitude and input to the scan chain from the (k-1) -th input scan pattern 702 again as described above to generate the output pattern 720 and the prediction The pattern comparison process of the pattern 730 is performed again.

The shift frequency for the kth scan section 704 is continuously increased to the point where the output pattern 720 and the predicted pattern 730 are different from each other. The optimum shift frequency is determined.

According to an embodiment, various values can be set in addition to the nominal frequency for the initial shift frequency for finding the optimal shift frequency for the kth scan section, and a high value for varying the output pattern and the predicted pattern, It is possible to find the shift frequency at the point where the output pattern and the predicted pattern become the same while lowering the shift frequency. In addition, it is possible not to increase or decrease the shift frequency of the k-th scan section sequentially, but to change it in various ways through various algorithms to find an optimal shift frequency in a shorter time.

For example, a binary search algorithm can be used. For example, if the shift frequency is successful at 10 MHz and fails at 20 MHz, try the next shift frequency between them, 15 MHz. And if it is successful, try between 15MHz and 20MHz, and if it fails, try between 10MHz and 15MHz.

In the example of FIG. 7, the scan section K 704 for finding the optimal shift frequency corresponds one-to-one to the scan pattern K 704, but may be configured as a part of the scan pattern as the scan section 530 of FIG. In this case, in a scan pattern including a selected scan section to find an optimal shift frequency, if an optimum shift frequency is already determined at a nominal shift frequency or less according to the method of the present invention, Frequency A predefined shift frequency can be used as follows. For the selected scan section to find the optimal shift frequency, an optimal frequency is searched for by increasing or decreasing the shift frequency as described above. The predetermined shift frequency may be a nominal shift frequency or more, a preset value for each device, or a value set by a user, and the present invention is not limited thereto.

FIG. 8 is a flowchart illustrating an example of a scan test time minimization method according to the present invention.

Referring to FIG. 8, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (S800). As an example of the division of the scan pattern, the method shown in Fig. 5 can be used. The scan test time minimizing apparatus allocates a plurality of shift frequencies to each scan section (S810). Here, the shift frequency assigned to each scan section is smaller than the shift frequency at which the output pattern of the scan chain is different from the predicted pattern. The division (S800) of the scan pattern as the scan section and the scan section allocation (S810) of the shift frequency may be performed in the same device or in different devices, respectively, according to the embodiment.

That is, the scan test time minimizing apparatus recognizes the shift frequency immediately before the output pattern and the predicted pattern are changed as the maximum shift frequency that can be allocated to the scan section according to the increase / decrease of the shift frequency. According to an embodiment, each scan section may be assigned a shift frequency that is smaller than the maximum shift frequency determined by increasing or decreasing the shift frequency.

9 is a diagram illustrating another example of a method using an optimal shift frequency for each scan section in order to minimize the scan test time according to the present invention.

Referring to FIG. 9, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (S900).

In step S910, the scan test time minimizing device obtains a shift frequency at a time point at which the output pattern is different from the predicted pattern while increasing or decreasing the frequency of shifting the scan section to the scan chain. It is desirable to use a chip that has been previously tested with a good product to find the optimum shift frequency. For example, as a result of performing a scan test using a nominal shift frequency, an optimal shift frequency is searched for according to the present embodiment using a good chip. The same is true in the following other embodiments.

In operation S920, the apparatus for minimizing the scan test time determines a shift frequency of the scan section before the point at which the output pattern and the predicted pattern differ from each other. The previous shift frequency also includes a shift frequency smaller than the shift frequency.

For example, if the output pattern and the predicted pattern are the same at the first shift frequency but the output pattern and predicted pattern of the scan chain are different at the second shift frequency where the first shift frequency is increased by a certain magnitude, 2 Shift frequency or less shift frequency is determined as the shift frequency of the scan section.

In order to find the optimum shift frequency, the increase / decrease size is preset in the scan test apparatus, and the increase / decrease size may be changed by the user.

The steps described in FIG. 9 are not all performed in the apparatus for minimizing the scan test time according to the embodiment, but may be performed dispersedly in various apparatuses.

FIG. 10 is a flowchart illustrating a method for minimizing a scan test time according to the present invention.

Referring to FIG. 10, the apparatus for minimizing scan test time divides one or more scan patterns into a plurality of scan sections (S1000).

The scan test time minimization apparatus selects one scan section in which the shift frequency is not determined according to the present embodiment among the scan sections (S1010). For example, if a certain order is set between the scan patterns for the scan test, the apparatus for minimizing the scan test time can sequentially select from the first scan section.

The scan test time minimizing device increases or decreases the shift frequency (S1020). For example, the scan test time minimizing device can set the initial shift frequency to various nominal shift frequencies.

The scan test time minimizing apparatus starts from the initial shift frequency and determines whether the scan section can be normally shifted to the scan chain at the increased or decreased shift frequency (S1030). An example of a specific method of determining whether the selected scan section can be normally shifted to the current shift frequency will be described with reference to FIG.

If the normal shift-in of the scan section is possible (S1040), the scan test time minimizing apparatus repeats the process of increasing or decreasing the shift frequency again (S1020) and determining whether normal shift-in is possible (S1030).

If it is determined that the scan section can not be normally shifted in accordance with the increase / decrease of the shift frequency (S1040), the scan test time minimizing apparatus scans the shift frequency lower than the shift frequency before the current shift frequency, Section as the shift frequency of the section (S1050). The above process is repeated until the shift frequency for all scan sections is determined (S1060).

Minimizing scan test time The apparatus can group scan sections into section groups as required (S1070). For example, when the scan test apparatus performing the actual scan test has constraints such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required for changing the shift frequency, The minimization device can group the scan sections so that the number of scan sections meets the above constraints, which can be considered to minimize the overall scan test time. At this time, the shift frequency of the corresponding section group may be determined to be the lowest shift frequency or less among the optimal shift frequencies of at least two scan sections included in one section group. The process of grouping into a section group (S1070) may be omitted according to the embodiment.

For example, when the maximum number of shift frequency changes that can be supported by the scan test apparatus is 5, the scan test time minimizing apparatus divides scan sections into five or less section groups when the number of current scan sections exceeds 5, The shift frequency of the section group can be determined to be equal to or less than the lowest optimal shift frequency of the optimal shift frequency of the intra-group section. There are various methods such as a method of grouping into a section group and a method of grouping by section group having a similar optimal shift frequency, and it is desirable that the whole scan test time can be minimized.

In the embodiments discussed so far, only an increase / decrease of the shift frequency is mainly considered, and an optimum shift frequency is found. However, since the chip is also influenced by the supply voltage and ambient temperature, it is necessary to find the optimal shift frequency by reflecting such environmental conditions.

Accordingly, the apparatus for minimizing the scan test time can perform the process of finding the optimum shift frequency while changing conditions such as the supply voltage and the external temperature.

For example, the apparatus for minimizing the scan test time may increase or decrease the voltage supplied to the chip in consideration of the standard range of the chip or the quality-related policies such as QA (Quality Assurance) and QC (S1020). And the scan test time minimization device finds the optimum shift frequency for each scan section according to the embodiment of the present invention at each incremental supply voltage. If there is a plurality of optimal shift frequencies found for each supply voltage of the selected scan section, the scan test time minimizing apparatus determines the shift frequency of the selected scan section as the shift frequency of the lowest optimal shift frequency among the plurality of shift frequencies. The process of finding the optimum shift frequency for each of the other temperature conditions and other various conditions is repeated, and the shift frequency of the scan section below the lowest optimal shift frequency can be determined.

Here, it is generally referred to as electrical testing or shmooing to determine the characteristics such as the operating frequency range of the IC chip while changing the supply voltage or ambient temperature of the IC chip, It is called shmoo plotting to make a diagram of the characteristic information by moiting. The plot is called a shmoo plot.

10 may be performed in a separate apparatus as well as the scan test time minimizing apparatus using the set of scan patterns and constraint information of the shift frequency and scan test time minimizing apparatus that are grasped for each scan section.

FIG. 11 is a flowchart illustrating a specific procedure for determining a normal shift-in in the scan test time minimization method according to the present invention. That is, Fig. 11 corresponds to step S1030 of Fig.

Referring to FIG. 11, the scan test time minimizing apparatus shifts the (k-1) th input pattern located in front of the currently selected kth scan section to the scan chain as shown in FIG. 7 (S1100). The (k-1) -th input pattern may be a (k-1) -th input scan pattern located in front of the k-th scan section and used in an actual scan test, or a prediction Pattern.

(1) When the (k-1) -th input pattern is the (k-1) -th scan pattern used in the actual scan test, the scan test time minimizing device loads the k-th scan pattern into the scan chain and performs scan capturing do. In this case, there is an advantage that the actual scan test operation can be reflected as it is.

(2) If the (k-1) -th input pattern is a prediction pattern appearing when the scan pattern is captured after the (k-1) -th scan pattern used in the actual scan test, the scan test time minimizing apparatus scans the Since there is no need to perform a separate scan capture process after loading into the chain, the time required for the clock for scan capture can be reduced.

The scan test time minimizing device shifts the selected scan section (kth scan section) to the scan section with the increased shift frequency after loading the (k-1) th input pattern at step S1110. If the selected scan section K to find the optimal shift frequency is part of the scan pattern, such as the scan sections 530, 540, 550 of FIG. 5, the scan pattern portion, excluding the scan section K, When the optimum shift frequency is already determined through the method according to the present invention, shift-in can be performed using a predetermined shift frequency equal to or less than the optimum shift frequency. And simultaneously shift-out the values stored on the scan chain. The predetermined shift frequency may be a nominal shift frequency or more, a preset value for each device, or a value set by a user, and the present invention is not limited thereto.

For example, when the (k-1) -th input pattern is the (k-1) -th scan pattern itself used in the actual scan test, the shift- This is a result. When the (k-1) -th input pattern is a predictive pattern for scan capture by the (k-1) -th scan pattern used in the actual scan test, the output pattern is a result of being output from the scan chain without scan capture.

The scan test time minimizing apparatus compares the output pattern with the predicted pattern (S1120). If the output pattern and the predicted pattern are not the same (S1120), the scan test time minimizing device determines that the kth scan section can not be normally shifted to the scan section at the current shift frequency (S1170).

If the output pattern and the predicted pattern are the same, the scan test time minimizing device shifts out the kth scan section existing on the current scan chain as it is, or shifts the result after the scan capture in the state where the kth scan section is loaded (S1140). In case of performing scan capture, there is an advantage that it can reflect the actual scan test operation process. If the kth scan section is directly shifted out without scan capture, the time required for scan capture can be reduced.

The scan test time minimizing device compares the shift-out output pattern with the prediction pattern (S1150). For example, when the kth scan section is shifted out as it is, the scan test apparatus compares the output pattern with the kth scan section. In the case of outputting the scan capture result for the kth scan section, the scan test time minimization device compares the output pattern with the predicted scan capture pattern that is known in advance for the kth scan section.

If the output pattern and the predicted pattern for the kth scan section are the same, the scan test time minimizing apparatus determines that the scan section can be normally shifted to the scan chain at the current shift frequency (S1160).

12 is a flowchart illustrating another example of a scan test time minimization method according to the present invention.

Process variations between IC chips on different wafers or between IC chips on the same wafer may occur depending on the type and state of the process and this may have a great influence on the operation frequency and power consumption of the IC chip have. Especially in micro and low power processes. FIG. 12 is an example for reflecting an optimal scan shift frequency.

Referring to FIG. 12, in step S1200, the apparatus for minimizing scan test time determines a frequency optimum for each scan section for a plurality of chips. The plurality of chips may be chips on the same wafer or chips on different wafers, and a chip that has been inspected with good products in advance is preferable.

The scan test time minimizing apparatus can determine the optimal shift frequency of the scan section to be less than or equal to the lowest shift frequency among a plurality of optimal shift frequencies obtained through a plurality of chips for one scan section (S1210) Can be performed on the scan section.

For example, assume that the shift frequency of the kth scan section of the first chip is A and the shift frequency of the kth scan section of the second chip is B. If the shift frequency A is smaller than the shift frequency B, the scan test apparatus selects A or less at the shift frequency of the kth scan section.

Each step of FIG. 12 may be performed not only in a scan test time minimizing apparatus but also in a separate apparatus using a set of scan patterns and shift frequency information obtained for each scan section for a plurality of chips.

In addition to the method described above, the apparatus for minimizing the scan test time can perform a burn-in test using the optimal shift frequency found for each scan section. Here, the burn-in test is to find an initially defective IC chip by accelerating aging by applying high voltage and high temperature to the IC chip. Generally, burn-in test is conducted for several hours or more in a high-temperature environment exceeding 100 ° C.

Minimizing the scan test time The device can perform the scan test using the scan pattern during the burn-in test. More switching operation occurs in the scan mode than in the functional mode. As the scan shift frequency increases, the power consumption of the IC chip increases proportionally. Further, since the heat generation of the IC chip is increased in proportion to the power consumption, the deterioration of the IC chip is further accelerated. Therefore, the scan test time minimization device can use the maximum shift frequency that can be assigned to each scan section to reduce the burn-in test time by accelerating aging in the burn-in test. Also, a test apparatus capable of performing such a burn-in test is called a burn-in test apparatus.

13 is a diagram showing the configuration of an embodiment of a scan test apparatus according to the present invention.

13, the scan test time minimizing apparatus includes a condition setting unit 1300, a pattern dividing unit 1305, a pattern input unit 1310, a pattern comparing unit 1320, and a frequency determining unit 1330. The condition setting unit 1300 further includes a frequency adjuster 1302, a supply voltage adjuster 1304, a temperature adjuster 1306, and the like.

First, the condition setting unit 1300 sets various conditions for finding the optimal shift frequency for each scan section. Specifically, the frequency adjuster 1302 increases or decreases the shift frequency, the supply voltage adjuster 1304 increases or decreases the voltage supplied to the chip, and the temperature adjuster 1306 increases or decreases the ambient temperature of the test environment. The condition setting unit 1300 sets conditions such as the supply voltage and the ambient temperature and increases or decreases the shift frequency.

The pattern dividing unit 1305 divides one or more scan patterns into a plurality of scan sections.

The pattern input unit 1310 shifts the scan section to the scan chain under the condition set by the condition setting unit 1300. [ More specifically, the pattern input unit 1310 sequentially shifts the scan patterns, which are located before and after the scan section to which the optimum scan shift frequency is to be sought, along with the scan section to the scan chain.

The pattern comparison unit 1320 determines whether the output pattern shifted out simultaneously with the shift-in by the pattern input unit 1310 is the same as the predicted pattern. There is a point at which the output pattern and the predicted pattern become different from each other as the shift frequency is increased or decreased by the condition setting unit 1300. [

Using the result of the pattern comparison unit 1330, the frequency determination unit 1330 determines a frequency lower than the shift frequency when the output pattern and the prediction pattern are different from each other as a possible shift frequency of the scan section, And the like. The shift frequency thus determined can be used to determine the optimal shift frequency of the scan section.

FIG. 14 is a diagram illustrating an example of a method of relocating a scan pattern for minimizing a scan test time according to the present invention.

Referring to FIG. 14, scan patterns on a set of scan patterns for a scan test have a predetermined order. However, the order of these scan patterns is not fixed, but can be rearranged to allocate a higher shift frequency for each scan section to reduce the entire scan test time. For example, as shown in FIG. 14, the order of the second scan pattern and the third scan pattern on the original set of scan patterns can be changed. Accordingly, the order of the predicted output scan patterns is also changed.

In the case of rearranging the order of the scan patterns shifted to the scan chain, the portion to be switched on the IC chip and the number of switching operations can be changed by the scan shifting, so that the power consumption is changed, The shift frequency that can be achieved can be increased. Accordingly, by using the above-described property, the optimal scan frequency for each scan section can be found or determined by using the embodiment of the present invention, which is described above after rearranging the scan pattern, thereby reducing the overall scan test time.

In the method of rearranging scan patterns, the scan patterns on the original set of scan patterns are arbitrarily rearranged one or more times, and the optimum shift frequency is grasped according to the preceding embodiment for each set of rearranged scan patterns, There are various methods such as determining the required amount of the scan pattern or arranging the scan patterns having the smallest bit pattern difference between the scan patterns next to each other.

As another example of the scan pattern rearrangement, it is possible to have the highest shift frequency by sequentially substituting the scan patterns that are not sequenced after K (one or more integer) scan patterns and sequentially searching for the optimal shift frequency It is possible to determine the scan pattern as the next pattern of the Kth scan pattern.

Some or all of the operations of rearranging the order of the scan patterns may be performed by hardware and firmware such as a processor included in the IC chip testing apparatus, software, or may be performed in another separate apparatus such as a computer.

Also, when it takes a long time to find the optimal scan pattern arrangement, constraints such as the number of scan pattern relocation times or the time required to try to find the optimal scan pattern arrangement can be set.

The scan shift frequency information obtained by carrying out the present invention and the present invention or the scan section information reflecting the information may also be embodied as computer readable codes or data on a computer readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include various types of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, optical data storage, and the like. The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (27)

Determining, for each of at least two scan sections, a shift frequency that is different or identical to an output pattern of the scan chain by increasing or decreasing the shift frequency of shifting the scan section in the scan chain; Including,
Wherein the step of determining the shift frequency comprises shifting the input pattern located in front of the scan section and the scan section to a different shift frequency in the scan chain to compare the output pattern with the predicted pattern. How to minimize test time. The method of claim 1, wherein the step of determining the shift frequency comprises:
Increasing or decreasing the shift frequency;
Inputting the scan section into a scan chain using the increased and decreased shift frequencies;
Increasing the shift frequency if the output pattern of the scan chain is the same as the predicted pattern or decreasing the shift frequency if the output pattern of the scan chain is different from the predicted pattern; And
And estimating a shift frequency when the output pattern is the same as or different from the predicted pattern. The method of claim 1, wherein the step of determining the shift frequency comprises:
The first input pattern located in front of the scan section, the scan section, and the second input pattern located after the scan section are sequentially input to the scan chain, and the shift frequency when the output pattern of the scan chain is the same as or different from the predicted pattern is grasped The method comprising the steps of: The method of claim 3,
Wherein the shift frequency of the scan section belonging to the first input pattern is below a nominal shift frequency or below a predetermined shift frequency for a scan section belonging to the first input pattern,
Wherein the shift frequency of the scan section belonging to the second input pattern is below a nominal shift frequency or below a predetermined shift frequency for a scan section belonging to the second input pattern,
Wherein the shift frequency of the scanning section to be shifted frequency is increased or decreased until the output pattern is different from the prediction pattern. The method of claim 3,
The first input pattern is a bit pattern positioned before a scan section in an actual test or a prediction pattern for a result obtained when performing scan capturing in a state where the bit pattern is loaded in a scan chain,
Wherein the second input pattern is a bit pattern or a dummy pattern positioned after a scan section in an actual test. 4. The method of claim 3, wherein the step of determining the shift frequency comprises:
Determining a shift frequency at a time point when the output pattern of the scan chain for the first input pattern is the same as or different from the first predicted pattern or when the output pattern of the scan chain for the scan section is equal to or different from the second predicted pattern The method comprising the steps of: The method according to claim 6,
Wherein the second prediction pattern is a prediction pattern for a result obtained when performing scan capturing performed while the scan section is loaded in the scan chain. The method of claim 1, wherein the step of determining the shift frequency comprises:
And combining the increase or decrease of the shift frequency and the increase or decrease of the supply voltage or the ambient temperature to determine a shift frequency at a time point when the output pattern and the predicted pattern are the same or different for each scan section How to minimize. Determining or determining, for each of the at least two scan sections, the different shift frequencies that shift-in or shift-out the scan section into the scan chain,
The shift frequency determined or determined for each scan section is a value smaller than the shift frequency at which the output pattern of the scan chain is different from the predicted pattern,
The step of determining or determining the shift frequency may include shifting the input pattern located in front of the scan section and the scan section to a different shift frequency in the scan chain to compare the output pattern and the predicted pattern, Wherein the shift frequency of the section is determined or determined. 10. The method of claim 9,
A first input pattern, a scan section, and a second input pattern positioned after the scan section are sequentially input to the scan chain, wherein the first input pattern and the second input pattern are set in advance Inputting the scan signal into the scan chain at a shift frequency, and inputting the scan section to the scan chain at a shift frequency that is increased at each iteration,
And determining or determining the shift frequency as a shift frequency of the scan section, wherein the shift frequency is smaller than a shift frequency of a point at which the output pattern of the scan chain is different from the predicted pattern. How to minimize time. 11. The method of claim 10,
Wherein the output pattern is shifted out of a result pattern of scan capture in a state where at least one of the first input pattern and the scan section is loaded, and is unloaded. The method of claim 2 or 10, wherein the step of inputting to the scan chain comprises:
And inputting the scan section into the scan chain in a state in which the scan section reflects an increase or decrease of at least one of a shift frequency, a supply voltage, and an external temperature. 10. The method of claim 1 or 9,
Determining or determining a shift frequency for each scan section for a plurality of chips; And
And determining or determining a shift frequency of a corresponding scan section to a value less than a smallest value among a plurality of shift frequencies determined for each scan section for a plurality of chips. 10. The method of claim 1 or 9,
Grouping the at least two scan sections into at least one or more section groups on the basis of at least one constraint among a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time corresponding to a scan shift frequency change; And
And determining a shift frequency of the section group to be less than or equal to a smallest shift frequency among the shift frequencies determined for each scan section belonging to the section group. 10. The method of claim 1 or 9,
And performing a burn-in test while increasing the temperature of the test chip using the shift frequency determined for the scan section. 10. The method of claim 1 or 9,
And rearranging the patterns of the set of patterns on the set of scan patterns including the scan section. 10. The method of claim 1 or 9,
Determining a shift frequency of the scan section divided by a shift frequency of a predetermined size that can be increased or decreased by the scan test equipment. A frequency increasing / decreasing section for increasing / decreasing a shift frequency of shifting the scan section to the scan chain by shift-in or shift-out;
A pattern input unit for inputting a scan pattern including at least one scan section into a scan chain; And
And a pattern comparison unit for determining whether the output pattern of the scan chain is the same as the predicted pattern,
Some or all of the shift frequencies respectively grasped for at least two scan sections are different from each other,
Wherein the pattern input unit inputs the input pattern located in front of the scan section and the scan section at different shift frequencies in the scan chain. 19. The method of claim 18,
Further comprising a pattern division unit dividing the at least one scan pattern into at least two scan sections. 19. The method of claim 18,
The pattern input unit repeatedly inputs a scan section and an input pattern located in front of the scan section into a scan chain, inputs an input pattern located in front of the scan section into the scan chain at a predetermined shift frequency, Each time a section is repeatedly input to the scan chain at a shifted shift frequency,
Wherein the frequency determining unit determines a shift frequency that is smaller than a shift frequency of a point of time when the output pattern of the scan chain is different from a predicted pattern as a possible shift frequency of the scan section. A computer-readable recording medium having recorded thereon a program for performing the method according to claim 1 or 9. A computer-readable recording medium having recorded thereon the shift frequency information, which is determined or determined for a scan section by performing the method according to claim 1 or 9, or the scan section information in which the shift frequency is reflected. 10. The method of claim 1 or 9,
Comparing an output pattern of the input pattern with a predicted pattern; And
And comparing the output pattern of the scan section with the predicted pattern,
The output pattern for the scan pattern belonging to the input pattern or a part of the output pattern is shifted out at a shift frequency equal to the shift-in frequency of the scan section,
Wherein the output pattern of the scan section is shifted out to a shift frequency different from the shift-in frequency. 24. The method of claim 23,
The output pattern of the input pattern is a pattern obtained by loading a scan pattern or a scan pattern into a scan chain and then performing a scan capture,
Wherein the output pattern of the scan section is a pattern obtained by capturing a scan scan section or a scan section loaded in a scan chain. 19. The method of claim 18,
The pattern comparison unit compares the output pattern of the input pattern with the predicted pattern, compares the output pattern of the scan section with the predicted pattern,
The output pattern for the scan pattern belonging to the input pattern or a part of the output pattern is shifted out at a shift frequency equal to the shift-in frequency of the scan section,
Wherein the output pattern for the scan section is shifted out to a shift frequency different from the shift-in frequency. 26. The method of claim 25,
The output pattern of the input pattern is a pattern obtained by loading a scan pattern or a scan pattern into a scan chain and then performing a scan capture,
Wherein the output pattern of the scan section is a pattern obtained by scanning the scan section or the scan section after loading the scan section into the scan chain. 9. A computer-readable recording medium having recorded thereon an input pattern or a scan section used for carrying out the method of claim 1 or 9.

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