KR102373560B1 - Method and apparatus for generating search-data for searching optimal shift frequency of test data for IC chip scan test - Google Patents

Abstract

Disclosed are a method for generating search-data for finding a usable shift frequency of a scan section for an IC chip scan test and an apparatus thereof. The apparatus for generating search-data separates an input scan pattern into at least two segments including at least one scan section and generates a plurality of pieces of search-data corresponding to the number of segments if the number of frequency or timing identifiers that can be controlled or set by an IC chip test device is smaller than the number of scan sections of the input scan pattern.

Description

Method and apparatus for generating search-data for searching optimal shift frequency of test data for IC chip scan test

An embodiment of the present invention relates to a method and apparatus for generating search data for finding a shift frequency that can be used for each scan section of test data for an integrated circuit (IC) chip scan test, and an apparatus therefor.

The most common way to test an IC chip is to apply test data to the input of the IC chip and compare the output value of the IC chip with a preset predicted value or predicted result (for example, , see Patent Document 1). However, in the case of an IC chip including a sequential circuit having a storage element such as a flip-flop, a desired value is applied to the flip-flop in the IC chip from the outside, or the value of the flip-flop is externally applied. It is not easy to detect in

The scan design method is one of design for testability (DFT) methods that consider a test used to increase controllability and observability of a circuit. When using the scan design method, it uses ATPG (Automatic Test Pattern Generator), a software that automatically generates a test pattern based on the structural information of the circuit, which has a small size and high fault coverage. Test data can be obtained.

In other words, the scan design converts sequential logic into a combinatorial circuit during the scan test so that the circuit can be easily controlled and observed from outside the chip, and the size of the test data can be minimized through ATPG. there is. The scan design and test data obtained through ATPG software consist of at least one or more scan patterns. The scan patterns may have an order in the performance of the scan test.

The general scan test process is as follows.

(1) Apply the main input test data to the main input port of the IC chip.

(2) Apply a scan enable signal to the scan enable port to set the IC chip to scan mode.

(3) Shift the scan pattern in the scan input port to load the scan pattern onto the flip-flop on the scan path. In this specification, shift-in to the scan input port or shift-out from the scan output port is sometimes referred to simply as "shift". In addition, the time interval (period) for shifting the scan pattern and the shift frequency are inversely related. The scan pattern loaded into the scan path is applied to the combinational circuit. After the scan pattern is applied to the combination circuit, the result output through the main output port is compared with the predicted main output value, and if the comparison result is different, the IC chip is determined as defective.

(4) Apply the scan disable signal to the scan enable port to change the IC chip from scan mode to function mode. In the function mode, when a clock signal is applied, the flip-flop captures the output value of the combinational circuit, and this operation is called scan capture, and this mode is also called scan capture mode.

(5) Apply the scan enable signal to the scan enable port to switch the IC chip back from the function mode to the scan mode.

(6) Then, the value captured in the flip-flop on the scan path is shifted out through the scan output port and unloaded.

(7) By comparing the unloaded output pattern with the predicted pattern known in advance, it is determined whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern output through a scan output port after applying the main input test data and a scan pattern and performing a scan capture operation when the IC chip is normal, and is a value known in advance or a predicted result pattern before the test. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the test result is pass and the IC chip is good, otherwise the IC chip is defective. A test pass means a case in which it is determined that the IC chip is fault-free, and a test failure means a case in which it is determined that there is an error in the IC chip.

The scan test is largely divided into a stuck-at-fault test and a delay fault test. Here, the stuck failure refers to a state in which a signal line on the IC chip is unintentionally fixed with a logic 0 or logic 1 value, and the delayed failure refers to a certain signal line or path ( path) means a state in which the specification of the IC chip is not satisfied due to the delay time when transmitting the signal value.

The delay failure test includes a transition delay test and a path delay test, also called an at-speed test. The transition delay test is to test whether a specific node or signal line on an IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem. The path delay test tests whether a specific signal path on an IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem.

A typical method for delayed failure testing includes a launch-on-capture method and a launch-on-shift method. These methods also scan a scan pattern for delayed failure testing. It consists of a load operation that shifts in on the path and an unload operation that shifts out the delayed failure test result captured in the flip-flop on the scan path.

In such a scan test, the number of clock pulses for shifting by the number of flip-flops on the scan path is required. Accordingly, there is a problem in that a lot of time is required for the shift-in and shift-out operations. However, in order to reduce the test time, it is not possible to simply increase the frequency of the clock signal for shifting the scan pattern to the scan path, that is, the shift frequency.

For example, simply increasing the scan shift frequency may cause an overkill problem of determining a good product as a defective product due to power consumption or a critical path delay time problem.

In addition, as the IC chip is further reduced in power due to the low-power design as well as the deep sub-micron (DSM) micro-manufacturing process and low-power manufacturing process, the influence of power supply noise on the operating frequency of the IC chip has increased. In particular, since IC chips generate more switching operations in scan mode than in functional mode, additional delay in signal lines caused by power supply noise caused by switching operations can cause delay test overkill, so simply increase the shift frequency. There is a limit to

In addition, the problem of signal integrity due to signal crosstalk on the IC chip became more important as the DSM microprocessing progressed. Interference between signal lines may become more severe due to a switching operation that occurs frequently in the scan mode. Therefore, during the delay test, an additional delay occurring in the signal lines due to the interference between the signal lines may cause the delay test overkill.

In addition, when the shift frequency is found based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the specifications of the IC chip, due to the characteristics of the scan test, excessive circuit switching operation on the IC chip and the influence of manufacturing process variation This can cause scan test errors due to IR-drop or ground-bounce.

For example, during a delay test using a scan pattern, an additional delay may occur in a specific signal line due to the effect of IR-drop, that is, a voltage drop, which may cause delay test overkill. Conversely, even when the power consumption of the scan pattern exceeds the specification of the IC chip, the IR-drop or ground-bounce problem may not occur due to the manufacturing process and design characteristics of the IC chip. Therefore, there is a limit to finding the optimal shift frequency for the IC chip simply by using the power consumption value. In addition, when the maximum shift frequency is found only with the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, a critical path timing problem may occur on the scan path due to the increased shift frequency. there is.

In addition, if the shift frequency is increased, a critical path timing problem may occur on the scan path, but a logical problem due to the scan pattern may not occur in some cases. In other words, a case of a false critical path may occur in a specific scan shift cycle depending on the state of a bit value on the critical path of the scan path.

For example, when two consecutive logic-0 bit values are shifted and stored in two flip-flops constituting a critical path on the scan path, and then shifted with a high shift frequency, they are stored in the flip-flops at the beginning of the critical path. A critical pass latency problem can arise where a signal for a logical 0 bit value cannot reach the next flip-flop within the normal time. However, there may be a case of a false critical path in which a logical problem of bit values stored in two flip-flops constituting the critical path does not occur due to the shift operation.

In addition, in the case of a low-power IC chip using a multiple voltage island or voltage domain or region technique, a high voltage is supplied to a design area that requires high speed performance, and a relatively low voltage is applied to other areas. Therefore, the power consumption allowed for each voltage region is different.

Patent Document 1: Korean Patent Publication No. 10-2012-0102876

The technical problem to be achieved by the present invention is to optimize the frequency for each scan section of the test data to reduce the test time and to improve the test quality and yield. To provide a method and an apparatus for the same.

An example of a method for generating search data according to an embodiment of the present invention for achieving the above technical problem is a method of generating search data used to find an usable shift frequency of a scan section used for IC chip testing In the following, when the number of frequency or timing identifiers that can be set or controlled by the IC chip test apparatus is smaller than the number of scan sections dividing the input scan pattern, the input scan pattern is set to at least two including at least one scan section. dividing into more than one segment; and generating a plurality of search data corresponding to the number of segments, wherein the input scan pattern included in each of the plurality of search data includes a frequency or control that an IC chip test apparatus can set or control. It consists of at least two or more scan sections to which timing identifiers less than or equal to the number of timing identifiers are assigned, and timing identifiers assigned to each of the available frequency search target scan sections included in the input scan pattern in each of the plurality of search data are mutually exclusive. different, and in each of the plurality of data for search, a timing identifier assigned to a scan section other than the available frequency search target scan section included in the input scan pattern is different from a timing identifier assigned to the target scan section, and the data for search The shift frequency or period of the shift frequency of the scan section included in ? can be set or changed using the timing identifier assigned to the scan section.

In a computer-readable recording medium recording a plurality of search data according to an embodiment of the present invention for achieving the above technical problem, each usable shift of a plurality of scan sections dividing one input scan pattern The number of search data used to find the frequency is the input scan pattern determined based on the difference between the number of frequency or timing identifiers that can be set or controlled by the IC chip test equipment and the number of scan sections dividing the input scan pattern first data equal to the number of segments of ; and second data including information on a plurality of timing identifiers allocated to the plurality of scan sections, wherein different timing identifiers allocated to the scan sections included in the input scan pattern in each of the plurality of search data The number of is less than or equal to the number of frequencies or timing identifiers that can be set or controlled by the IC chip test device, and the timing identifier assigned to the target scan section to find the shift frequency usable in the search data and the front of the target scan section Alternatively, the timing identifiers of the scan sections located later are different from each other, and the shift frequency or period of the shift frequency of the scan section included in the search data can be set or changed using the timing identifier assigned to the scan section.

In order to achieve the above technical problem, an example of a data generating apparatus for search according to an embodiment of the present invention is that the number of frequency or timing identifiers that can be set or controlled by the IC chip test apparatus divides the input scan pattern. a segment generator that divides the input scan pattern into at least two segments including at least one scan section when the number of scan sections is less than the number of scan sections; and a data generator that generates a plurality of data for search corresponding to the number of segments, wherein the input scan pattern included in each of the plurality of data for search may be set or controlled by an IC chip test apparatus. It consists of at least two scan sections to which a frequency or timing identifier equal to or less than the number of timing identifiers is assigned, and a timing identifier assigned to each available frequency search target scan section included in the input scan pattern in each of the plurality of search data. is different from each other, and in each of the plurality of search data, a timing identifier assigned to a scan section other than the available frequency search target scan section included in the input scan pattern is different from a timing identifier assigned to the target scan section, and The shift frequency or period of the shift frequency of the scan section included in the data for use can be set or changed using the timing identifier assigned to the scan section.

According to an embodiment of the present invention, it is possible to reduce the number of search data for finding usable frequencies for each scan section of test data for a scan test of an IC chip test apparatus. In addition, the storage capacity of the storage medium for storing the entire search data can be saved, and the compilation time of the entire search data can be reduced.

In another embodiment, when the shift frequency is increased in consideration of only power consumption or critical path delay time for each scan pattern, scan section, or section group during IC chip testing, a non-defective product is judged as a defective product due to the over-shift frequency. It is possible to provide an optimal shift frequency that can reduce the scan test time while solving the overkill problem.

In addition, it is possible to provide an optimal shift frequency in consideration of the influence of power supply noise and interference between signal lines during IC chip testing.

In addition, during IC chip testing, excessive circuit switching operation by scan test, manufacturing process variation, microfabrication process, low power manufacturing process, or low power design influence of IR-drop or ground-bounce It is possible to provide an optimal shift frequency by reflecting the influence.

In addition, an optimal shift frequency may be provided in consideration of the critical path timing effect on the scan path that may occur when the shift frequency is increased during IC chip testing.

Also, when the critical path of the scan path becomes false according to the bit value on the scan path during IC chip testing, the critical timing constraint is ignored and the scan shift is within the range where the IC chip can operate normally. Test time can be minimized by maximizing the frequency.

In addition, it is possible to enable the use of a higher shift frequency by don't-care bits on the scan pattern set during IC chip testing. A money-care bit means a bit that does not affect the result of the scan test.

In addition, in the case of a low-power IC chip that uses multiple voltage island or voltage domain or region techniques during IC chip testing, the optimal shift frequency is reflected by considering the power consumption allowed for each voltage island or voltage region. can provide

In addition, since the circuit design information of the IC chip is not required to find the optimal shift frequency of the scan pattern or scan section during IC chip testing, only the chip and scan pattern set are optimal for each scan pattern or scan section, even without the circuit design information of the chip. It can provide a shift frequency of .

In addition, it is possible to suppress an increase in test time in order to solve a fail hole problem in which an abnormal test fail occurs within the range of a shift frequency that should be a test pass during IC chip testing. In order to solve the fail hole problem, it is possible to suppress the occurrence of a chip's fault coverage or field escape problem.

It can also reduce test time and improve test quality in stress or burn-in tests that further accelerate chip aging. In addition, the accuracy of the prediction time required for the stress or burn-in test can be increased, and the quality of the stress or burn-in test can be improved.

In addition, information for improving the yield can be found or the yield can be improved through the IC chip test.

In addition, it is possible to reduce the size of data for searching to find the optimal shift frequency of a scan pattern or scan section used for IC chip testing.

In addition, it is possible to reduce the number of data files for searching for an optimal shift frequency of a scan pattern or scan section used for IC chip testing.

In addition, it is possible to reduce the time to find the optimal shift frequency of the scan pattern or scan section used for IC chip testing.

1 is a conceptual diagram illustrating an example of an IC chip to which a scan design method is applied.
2 and 3 are block diagrams illustrating the configuration of a chip test system according to at least one embodiment of the present invention.
4 is a conceptual diagram illustrating an example of a scan pattern according to at least one embodiment of the present invention.
5 to 9 are conceptual diagrams illustrating a method of dividing test data according to at least one embodiment of the present invention.
10 is a graph illustrating a relationship between the number of scan sections and a scan test time reduction rate according to at least one embodiment of the present invention.
11 is a conceptual diagram illustrating an example of allocating a shift frequency to each scan section in order to minimize the time of a chip test according to at least one embodiment of the present invention.
12 is a conceptual diagram illustrating an example of a method of finding a shift frequency in order to minimize a chip test time according to at least one embodiment of the present invention.
13 to 15 are conceptual diagrams illustrating an example of a pattern input to a scan path for determining a shift frequency according to at least one embodiment of the present invention.
16 is a graph illustrating an example of a method of finding a usable shift frequency of a scan pattern according to at least one embodiment of the present invention.
17 is a graph illustrating a case in which a test result of another scan pattern fails when increasing or decreasing a shift frequency of a scan pattern to find an optimal shift frequency according to at least one embodiment of the present invention.
18 to 20 are conceptual diagrams illustrating an example of a configuration of a scan pattern, a scan section, and shift frequency information necessary to find an optimal shift frequency according to at least one embodiment of the present invention.
21 to 28 are conceptual diagrams illustrating various examples of a method for generating search data according to at least one embodiment of the present invention.
29 is a flowchart illustrating an example of a method for minimizing the time of a chip test according to at least one embodiment of the present invention.
30 is a flowchart illustrating another example of a method of determining an optimal shift frequency for each scan section in order to minimize a chip test time according to at least one embodiment of the present invention.
31 is a flowchart illustrating an example of a more detailed process of a method for minimizing the time of a chip test according to at least one embodiment of the present invention.
32 is a flowchart illustrating an example of a specific process of determining whether a test is normal in a method for minimizing a chip test time according to at least one embodiment of the present invention.
33 is a flowchart illustrating another example of a method for minimizing a time of a chip test according to at least one embodiment of the present invention.
34 is a block diagram illustrating a configuration of an apparatus for minimizing a chip test time according to at least one embodiment of the present invention.
35 is a conceptual diagram illustrating an example of a method of finding or determining optimal shift frequencies of a plurality of scan sections in parallel according to at least one embodiment of the present invention.
36 is a conceptual diagram illustrating an example of a method of rearranging a scan pattern in order to minimize a chip test time according to at least one embodiment of the present invention.
37 and 38 are block diagrams illustrating a configuration of a burn-in test system according to at least one embodiment of the present invention.
39 is a conceptual diagram illustrating an example of the effect of temperature on an IC chip when a burn-in test is performed using a single scan shift frequency according to at least one embodiment of the present invention.
40 is a conceptual diagram illustrating an example of the effect of temperature on an IC chip when a burn-in test is performed using an optimal shift frequency for each scan pattern according to at least one embodiment of the present invention.
41 is a thermal image showing the heat generation state of the IC chip during the scan shift operation when the shift frequency for each scan section is not optimized and when the shift frequency is optimized.
42 is a graph illustrating an example of power consumption occurring during a burn-in test before power consumption of test data is adjusted.
43 is a graph illustrating an example of power consumption occurring during a burn-in test after power consumption of test data is adjusted.
44 is a flowchart illustrating an example of a method of finding an optimal shift frequency for each scan section in order to minimize a burn-in test time according to at least one embodiment of the present invention.
45 is a block diagram illustrating an example of an apparatus for minimizing burn-in test time according to at least one embodiment of the present invention.
46 is a table showing the comparison of experimental results for shift frequencies optimized through the shift frequency increase/decrease method with a shift frequency when approaching the critical power consumption of the IC chip for each scan pattern.
47 is a graph illustrating an example of a test fail hole that may occur during an IC chip test.
48 is a graph illustrating an example of a method for solving a test fail hole problem according to the present invention.
49 is a flowchart of a method for resolving a fail hole problem in accordance with at least one embodiment of the present invention.
50 is a graph illustrating another example of a method for solving a fail hole problem according to at least one embodiment of the present invention.
51 is a graph illustrating a method of finding a shift frequency for reducing test time and improving yield according to at least one embodiment of the present invention.
52 is a diagram illustrating an example of test data according to an embodiment of the present invention.
53 and 54 are diagrams illustrating an example of search data according to an embodiment of the present invention.
55 and 56 are diagrams illustrating another example of search data according to an embodiment of the present invention.
57 is a flowchart illustrating an example of a method for generating search data according to an embodiment of the present invention.
58 is a diagram illustrating an example of a data file for search according to an embodiment of the present invention.
59 is a diagram illustrating an example of an apparatus for generating data for search according to an embodiment of the present invention.
60 is a diagram illustrating an example of a method for finding a failure location candidate of an IC chip based on shift frequency information for each scan section according to an embodiment of the present invention.
61 is a diagram illustrating an example of a method of visualizing and displaying a circuit part of an IC chip activated by a scan section according to an embodiment of the present invention.
62 is a diagram illustrating a configuration of an example of a chip analysis apparatus according to an embodiment of the present invention.

Hereinafter, a method and apparatus for minimizing scan test time according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an example of an IC chip to which a scan design method is applied.

In the example of FIG. 1 , the IC chip 100 includes a combination circuit 110 and a sequential circuit (Sequential Logic). The sequential circuit (Sequential Logic) is composed of a plurality of flip-flops (120, 130, 140). Each of the flip-flops 120 , 130 , and 140 may be implemented in various ways, including a multiplexer (MUX) type scan flip-flop.

The IC chip 100 includes a primary input (PI) port 150 , a primary output (PO, Primary Output) port 152 , a scan enable (SE, Scan Enable) port 160 , and a scan input port 162 . ), a clock input port 164 , and a scan output port 166 . The scan activation port 160 and the clock input port 164 are connected to the flip-flops 120 , 130 , and 140 . Each flip-flop 120 , 130 , 140 may be connected to the combination circuit 110 to output a value stored in each flip-flop to the combination circuit, and receive a value output from the combination circuit.

The main input port 150 and the main output port 152 are ports for inputting and outputting data during the normal operation of the IC chip, respectively.

The scan enable port 160 is a port for inputting a scan enable signal or scan deactivation signal, and the IC chip performs a normal operation according to the scan enable signal or scan deactivation signal in a normal mode (or functional mode) ) or the scan mode to test the IC chip.

The scan input port 162 is a port for inputting a scan pattern for testing the IC chip 100 , and the scan output port 166 is a port for outputting a test result based on the scan pattern. The bit pattern output through the scan output port is called an output scan pattern, output pattern, or scan test result pattern.

The clock input port 164 shifts and loads the scan pattern input through the scan input port 162 to the flip-flops 120, 130, 140, or captures the output of the combination circuit 110 to the flip-flops 120, 130, 140. It is a port for inputting a clock signal for triggering so that it can be stored. For example, the flip-flops 120 , 130 , and 140 are triggered by a rising edge or a falling edge of a clock signal input through the clock input port 164 .

A path (dotted line path) connected from the scan input port 162 to the scan output port 166 via the plurality of flip-flops 120 , 130 , 140 is referred to as a scan chain or a scan path. Although a single scan path is illustrated in FIG. 1 , a plurality of scan paths may be used.

In the case of the function mode, the combination circuit 110 receives data through the main input port 150 and outputs the result through the main output port 152 . In addition, in the functional mode, the flip-flops 120, 130, and 140 receive the output value of the combination circuit 110 according to the clock signal, and during the scan test, this operation is called scan capture.

In the scan mode, each bit of the scan pattern is sequentially shifted in to the flip-flops 120 , 130 , 140 existing on the scan path according to the clock signal, and is also sequentially shifted through the scan output port 166 . Shift-Out. Here, the state in which the scan pattern is shifted in to the flip-flops 120, 130, and 140 is called load, and the state in which the values stored in the flip-flops 120, 130, and 140 are shifted out through the scan output port 166 is called unload. do.

For example, if the number of flip-flops 120, 130, and 140 on the scan path in the IC chip is three, the length of each scan pattern consists of a length of 3 bits equal to the number of flip-flops on the scan path, and the 3-bit scan pattern is a clock According to the signal, it is sequentially shifted in to the flip-flops 120, 130, and 140 on the scan path.

That is, when a value is stored in the flip-flop at the rising edge of the clock signal, the first bit of the scan pattern is input to and stored in the first flip-flop 140 at the rising edge of the first clock signal, and the second clock signal At the rising edge of , the output value of the first flip-flop 140 is stored in the second flip-flop 130 , and the second bit value of the scan pattern is stored in the first flip-flop 140 . At the rising edge of the third clock signal, the output value of the second flip-flop 130 is stored in the third flip-flop 120 , and the output value of the first flip-flop 140 is stored in the second flip-flop 130 . and the third bit value of the scan pattern is stored in the first flip-flop 140 . Accordingly, one scan pattern is loaded into the flip-flops 120, 130, and 140 on the scan path with three clock signals. Similarly, the values of the flip-flops 120 , 130 , and 140 on the scan path are unloaded through the scan output port 166 with three clock signals.

The scan test process will be described in more detail as follows.

(1) The main input test data is applied to the main input port 150 of the IC chip 100 .

(2) The IC chip 100 is set to a scan mode by applying a scan activation signal to the scan activation port 160 .

(3) By shifting the scan pattern into the scan input port 162, the scan pattern is loaded into the flip-flops 120, 130, and 140 on the scan path. The scan pattern loaded in the scan path is applied to the combination circuit 110 . After the scan pattern is applied to the combination circuit, the result output through the main output port 152 is compared with the predicted main output value, and if the comparison result is different, the IC chip is determined as defective.

(4) The IC chip 100 is switched from the scan mode to the function mode by applying a scan deactivation signal to the scan enable port 160 . In the functional mode, when a clock signal is applied, the flip-flops 120, 130, and 140 capture the output value of the combination circuit 110, and this operation is called scan capture, and this mode is also called scan capture mode.

(5) By applying a scan activation signal to the scan activation port 160, the IC chip is switched from the function mode to the scan mode again.

(6) Then, the values captured by the flip-flops 120, 130, and 140 on the scan path are shifted out through the scan output port 166 and unloaded.

(7) By comparing the unloaded output pattern with the predicted pattern known in advance, it is determined whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern output through the scan output port 166 after applying the main input test data and the scan pattern and performing a scan capture operation when the IC chip is normal. A value known in advance or a predicted result pattern before the test. am. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the test result is pass and the IC chip is good, otherwise the IC chip is defective. A test pass means a case in which it is determined that the IC chip is fault-free, and a test failure means a case in which it is determined that there is an error in the IC chip.

2 and 3 are block diagrams each showing the configuration of an embodiment of an IC chip test system called ATE (Automatic Test Equipment) to which the present invention is applied.

2 and 3 , the chip test system includes host computers 200 and 300 , tester bodies 210 and 310 , test heads 220 and 320 , and interface boards 230 and 330 . For testing, the device under test (DUT) 240 and 340 positioned on the interface board may be an IC on a wafer or a packaged IC chip. When the DUT is an IC chip on a wafer, it may further include a prober 350 . Hereinafter, an IC circuit, an IC chip on a wafer, or a packaged IC chip is collectively referred to as an IC chip or chip for convenience of description.

The tester bodies 210 and 310 overall control the scan test. For example, the tester body controls overall processes such as setup for DUT testing, generation of electrical signals for DUT testing, and observation and measurement of DUT test result signals. The tester body 210 and 310 may be implemented as a computer including a central processing unit (CPU), memory, hard disk, user interface, and the like, and according to an embodiment, a device power supply for supplying power to the DUTs 240 and 340 . Power Supply) may be further included.

In addition, the tester body 210,310 controls a signal processing processor (DSP, Digital Signal Processor) (not shown) that processes various digital signals and the test heads 220 and 320, and applies a signal to the DUTs 240 and 340. A controller and a signal It may include dedicated hardware such as a generator, software, or firmware. The tester bodies 210 and 310 are also called main frames or servers.

The host computers 200 and 300 may be computers such as personal computers and workstations, and are devices that allow a user to execute a test program, control a test process, and analyze test results. In general, the host computers 200 and 300 may include a central processing unit, a storage device such as a memory or hard disk, a user interface, and the like, and may be connected to the tester body 210 or 310 through wired or wireless communication. The host computers 200 and 300 may include dedicated hardware, software, or firmware for controlling the test. Although the present embodiment shows the host computer and the tester body separately, the host computers 200 and 300 and the tester body 210 and 310 may be implemented as a single device.

As an example of the memory of the tester body 210 , 310 or the host computer 200 , 300 , DRAM, SRAM, or flash memory may be used, and a program and data for performing a DUT test may be stored in the memory.

The software or firmware of the tester body 210 or 310 or the host computer 200 or 300 is a device driver program for scan test, an operating system (OS) program, and a program for performing DUT tests, and performs setup and DUT tests for DUT tests. It may be stored in the memory in the form of an instruction code for generation of a signal for a signal, observation analysis of a DUT test result signal, and the like, and executed by the central processing unit. Therefore, the scan pattern can be applied to the DUT by such a program. In addition, reporting and analysis data for DUT tests and test results can be obtained by automatically performing through the program. As a language used for the program, various languages such as C, C++, and Java may be used. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The tester body 210 or 310 or the central processing unit of the host computer 200 or 300 is a processor and executes software or program codes stored in a memory. For example, when a user command is received through a user interface such as a keyboard or mouse, the central processing unit analyzes the user's command, executes it through software or a program, and displays the result through a user interface such as a speaker, printer, monitor, etc. provided to users through

The user interface of the tester body 210 or 310 or the host computer 200 or 300 allows information to be exchanged between the user and the device and commands to be transmitted. For example, there are an interface device for user input such as a keyboard, a touch screen, and a mouse, and an output interface device such as a speaker, a printer, and a monitor.

The test heads 220 and 320 include channels for transmitting electrical signals between the tester bodies 210 and 310 and the DUTs 240 and 340 . Interface boards 230 and 330 are provided on the test heads 220 and 320 . An interface board used for testing a packaged IC chip is generally called a load board, and an interface board used for testing an IC chip on a wafer is generally called a probe card.

In at least one embodiment of the present invention, the host computer 200,300 comprises an IC chip test device.

In at least one embodiment of the present invention, the IC chip test apparatus shifts the target scan section to search for usable shift frequencies among at least two or more scan sections included in the scan pattern set to the scan path so that the scan test result is and a shift frequency search unit that searches for a normal or failed shift frequency.

The shift frequency search unit increases or decreases or sets a shift frequency different from at least one scan section among other scan sections that shift the shift frequency of the target scan section to the scan path when the shift frequency is searched for the target scan section. Search for the shift frequency for which the scan test result is normal or failed.

The shift frequency search unit searches for a shift frequency in an area in which a scan test result changes from normal to failure or from failing to normal while increasing or decreasing the shift frequency of the target scan section when searching for available shift frequencies for the target scan section. do.

The shift frequency search unit, when searching for available shift frequencies for the target scan section, includes a first scan test result obtained by using the first shift frequency for the target scan section and a second scan section before the target scan section. When the results of the second scan test obtained by using the second shift frequency different from the first shift frequency are all normal, the first shift frequency is determined as a shift frequency usable for the target scan section.

In at least one embodiment of the present invention, the IC chip test apparatus performs a test by shifting a first scan pattern including a first scan section to a scan path to perform a test and a second test step after the first scan section and a shift frequency search unit configured to search for a usable shift frequency for the second scan section by performing a second test step of performing a test by shifting the second scan pattern including the scan section to the scan path.

The shift frequency search unit shifts the first scan section to the scan path with a first shift frequency in the first test step, and shifts the second scan section to the scan path with a second shift frequency different from the first shift frequency in the second test step. When the shift frequency available for the second scan section is searched, when the first scan test result of the first test step and the second scan test result of the second test step are both normal, the second shift frequency is set to the second Determines the available shift frequency for the scan section.

In at least one embodiment of the present invention, the first scan section is or is part of a first scan pattern and the second scan section is or is part of a second scan pattern.

The shift frequency search unit, when searching for available shift frequencies for the second scan section, increases or decreases differently from at least one scan section among other scan sections that shift the second shift frequency to the scan path, or sets it to a different frequency to search the shift frequency for the second scan section.

2 and 3, the IC chip test apparatus is described as being included in the host computers 200 and 300, but this is only an example, and is included in a separate computer with a processor to include the host computers 200 and 300 or the tester bodies 210 and 310 ) to perform a function.

The test system of FIGS. 2 and 3 is only one example for helping the understanding of the present invention, and each configuration can be integrated into an integrated form, or one configuration can be implemented by separating it into a plurality of configurations. Various design modifications are possible according to it.

The scan pattern means a bit pattern input to a scan path for a scan test or a bit pattern output from the scan path.

In addition, the bit length of the scan pattern is the length of the bit pattern required for one scan test operation. For example, the bit length of the scan pattern may be the same as the bit length of the bit pattern shifted in the scan path before the scan capture operation is performed. As another example, the bit length of the scan pattern may be equal to the number of bit storage elements, such as flip-flops, on the scan path. The bit length of the scan pattern is not limited to the above description and may be variously set according to the scan test circuit.

Embodiments of the present invention may be applied to not only the IC chip of FIG. 1 but also various types of chips that shift a bit pattern in a scan path and shift an output pattern out of a scan path.

For example, embodiments of the present invention are applied to various types of chips including circuits capable of performing an operation of shifting a scan pattern into a scan path, a scan capture operation, and an operation of shifting out a captured bit pattern. can be applied.

4 is a conceptual diagram illustrating an example of a scan pattern applicable to a chip test according to at least one embodiment of the present invention.

Referring to FIG. 4 , the shift-in and shift-out operations are simultaneously performed in order to reduce the time required to respectively perform the shift-in operation and the shift-out operation in the scan mode. That is, the load and unload operations are performed simultaneously.

For example, when the input pattern K 430 is shifted in to the scan path through the scan input port and loaded, the test result by the input pattern K-1 400 is simultaneously shifted out through the scan output port and unloaded. . At this time, the unloaded output pattern is compared with the prediction pattern K-1 (440) for the input pattern K-1 (400). In general, the prediction pattern K-1 440 and the input pattern K 430 for the input pattern K-1 400 may be managed as a pair in test data or a file.

In at least one embodiment of the present invention, in order to perform a scan test by overlapping shift-in and shift-out operations, an input pattern K 430 and an input pattern K-1 400 that are shifted in through a scan input port ), the prediction pattern K-1 (440) is managed in pairs. In this way, the scan patterns may have an order with each other. According to an embodiment, the scan patterns may be rearranged in various ways without an order.

In at least one embodiment of the present invention, when the first scan pattern is shifted in to the scan path, the output pattern shifted out at the same time is a Don't-care pattern or the scan path state by resetting the chip under test can be a value.

Another method for minimizing the scan test time includes a method of reducing the total number of scan patterns for the scan test and a method of increasing the scan shift speed.

Here, increasing the scan shift speed means increasing the shift frequency of the shift-in or shift-out of the scan pattern, or decreasing the period of the shift frequency. Reducing the scan shift speed means lowering the shift frequency or increasing the period of the shift frequency. Also, optimizing the scan shift speed means optimizing the shift frequency or optimizing the period of the shift frequency.

Since the increase or decrease of the shift frequency is substantially the same as the decrease or increase of the period of the shift frequency, a method of minimizing the scan test time will be mainly described in terms of the increase or decrease of the shift frequency for convenience of description. Therefore, even if there is no explicit description hereinafter, an increase or decrease in the frequency may be interpreted as a decrease or increase in the period of the frequency, and the decrease or increase in the period of the frequency may be interpreted as an increase or decrease in the frequency. Also, the period of the frequency may be simply referred to as a period or may be referred to as a clock period of an input clock.

5 to 9 are conceptual views illustrating various examples of a method of dividing test data into at least one scan section in order to minimize the time of a chip test according to at least one embodiment of the present invention.

Referring to FIG. 5, the bit pattern of the test data 500 shifted in the scan path for testing the IC chip is divided into a plurality of scan sections 510,512,514,516,518, and the optimal shift frequency for each scan section 510,512,514,516,518 is found It can be applied at the time of scan test to save scan test time.

In at least one embodiment of the present invention, the bit pattern 500 of the test data may include a plurality of scan patterns as shown in FIG. 6 .

Referring to FIG. 6 , a plurality of scan patterns may be used for testing an IC chip. The scan section may be composed of at least one scan pattern or a part of the scan pattern, and the scan test time can be further saved by finding an optimal shift frequency for each scan section and applying it during the scan test.

In the first embodiment, the scan section 600 is configured with one scan pattern and may correspond to the scan pattern one-to-one. That is, a scan pattern may become a scan section.

In a second embodiment, the scan section 610 may include two scan patterns. The number of scan patterns included in the scan section may be variously changed according to an embodiment.

As a third embodiment, the scan section 620 may be configured as a part of the first scan pattern and a part of the second scan pattern.

As a fourth embodiment, the scan section 630 may be configured as a part of one scan pattern.

As a fifth embodiment, one scan pattern may be divided into two scan sections 640 and 650 . The number of scan sections included in one scan pattern may be variously changed according to an embodiment.

The test data may be divided by any one of the above salpin various embodiments (600, 610, 620, 630, 640, 650) as well as divided by applying two or more of these embodiments. For example, the test data composed of N scan patterns of FIG. 6 includes a first scan section 600 including one scan pattern, a second scan section 610 including two scan patterns, and one scan pattern. It may be divided into third and fourth scan sections 640 and 650 including a portion of .

Referring to FIG. 7 , a section having the same and continuous bit values in the bit pattern of the test data 700 may be divided into scan sections 702 , 704 , 706 , 708 and 710 . When the same bit values are successively shifted in the scan path, bit value switching activities of the scan path are reduced and power consumption is reduced, so that a high shift frequency can be allocated to a scan section having consecutive bit values.

For example, based on a boundary at which a bit value in the bit pattern of the test data 700 changes from 0 to 1, or from 1 to 0, the test data 700 can be divided into at least one or more scan sections 702,704,706,708,710. . Alternatively, M (M is an integer) bits may be bundled and divided into scan sections 720 and 722 within the section 710 of the bit pattern in which bit values of 0 or 1 are continuous.

As another example, if the length of a section having the same and continuous bit values in the bit pattern of the test data is shorter than a certain length, the section is not divided into scan sections, but at least two sections 702 and 704 are bundled together to form one scan section (703).

Referring to FIG. 8 , the scan section 810 may be further divided into a plurality of sub scan sections 812 and 814 . For example, the scan section 810 having a relatively low optimal shift frequency among the optimal shift frequencies found for each scan section 810 and 820 is again divided into a plurality of sub-scan sections 812 and 814, and the divided sub-scan sections 812 and 814 are divided into sub-scan sections 812 and 814. The optimal shift frequency can be found again for .

Referring to FIG. 9 , the number of scan sections into which the test data is to be divided in consideration of the expected time (hereinafter referred to as 'expected time required') required to find the optimal shift frequency to be applied to each scan section of the test data 900 and 910 can be decided As the number of scan sections increases, the estimated time required to find the optimal shift frequency of the entire scan section increases. The expected required time may be calculated by a preset formula representing the relationship between the number of scan sections and the expected required time.

In the example of FIG. 9 , if there is a constraint of time A that can be used to find the optimal shift frequency, the number N of scan sections into which the test data 900 is divided is determined so that the expected required time is less than or equal to A time. If there is a constraint of time B (A > B) that can be used to find the optimal shift frequency, the number of scan sections into which the test data 910 is divided so that the estimated time required is less than or equal to B time M (N > M) this is decided

When it is determined that the number of divisions of the test data 900 is N, the test data 900 is divided into the determined N number of scan sections. For example, a method of dividing the test data 900 into N scan sections having an equal bit length, as shown in FIG. 7 , a section having the same and continuous bit values is divided into scan sections, but the number of sections is N Various methods can be applied, such as a method of dividing only up to a number.

The following information can be used to calculate the estimated required time.

- Start frequency to find the optimal shift frequency

- End frequency to find the optimal shift frequency

- Increase/decrease unit of frequency to find the optimal shift frequency

- Frequency increase/decrease method to find the optimal shift frequency (continuous increase/decrease frequency or increase/decrease by binary search method)

- Number of scan patterns included in test data (SPN)

- bit length of scan pattern (SBL)

- Method or criteria for dividing the test data into scan sections (segmentation by a certain bit length unit, partitioning into a certain number, or partitioning based on a boundary at which bit values change, etc.)

- Number of scan sections (SSN)

- The performance of the device in which the method of finding the optimal shift frequency is implemented (for example, processor performance (CPU speed, etc.), memory or hard disk capacity and speed, etc.)

- Other margin time considering the data input/output time of the device in which the method of finding the optimal shift frequency is implemented

In at least one embodiment of the present invention, assuming that a method of sequentially increasing at regular intervals from the start frequency to the end frequency is used to find the optimal shift frequency, an example of a formula for calculating the expected required time is the following math same as expression

Here, SSN is the number of scan sections, SPN is the number of scan patterns, SBL is the bit length of the scan pattern, SFP is the period of the shift frequency, and FN is the number of times the shift frequency is increased to find the optimal shift frequency per scan section.

In Equation 1, given the expected required time, it is possible to determine the number of scan sections by satisfying this requirement.

10 is a graph illustrating a relationship between the number of scan sections and a scan test time reduction rate according to at least one embodiment of the present invention.

Referring to FIG. 10 , the number of divided scan sections of the test data may be determined using transition information of the scan test time reduction rate according to the number of scan sections or a method of dividing the scan sections. As the number of scan sections for which the shift frequency is optimized increases, a time reduction rate of a scan test using test data may increase.

In FIG. 10 , the vertical axis represents the reduction rate of the scan test time required when using the optimal shift frequency for each scan section compared to the scan test time required when a single constant shift frequency is used for the entire test data. The horizontal axis means the number of scan sections for which the shift frequency is optimized.

As the number of scan sections dividing the test data increases, the average bit length of the scan sections becomes shorter. In addition, as the bit length of the scan section becomes shorter, the optimal shift frequency becomes higher, so that the scan test time can be shortened.

The various division methods of the salpin scan section in the above are only various embodiments to help the understanding of the present invention, but the present invention is not limited to each method of FIGS. 5 to 10 . In addition to the method shown in FIGS. 5 to 10 , various methods of dividing test data may be applied.

11 is a conceptual diagram illustrating an example of allocating a shift frequency to each scan section in order to minimize a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 11 , a plurality of shift frequencies are allocated to each scan section. In the case of the conventional scan test, a single shift frequency capable of normally shifting all scan patterns of the test data to the scan path of the IC chip is used, and this single shift frequency is also referred to as a nominal shift frequency.

In general, the nominal shift frequency may be the shift frequency used when creating a scan pattern with ATPG software, or it may be a slightly adjusted shift frequency based on this. It is a fairly low (eg, about 5 MHz) frequency as a single frequency that can be

Therefore, when the nominal shift frequency is used as it is for thousands to tens of thousands of scan patterns constituting the test data, it takes a considerable amount of time for the scan test. market) can have a significant impact. For example, assuming that it takes 2 seconds to test one IC chip, testing 10 million chips sequentially takes about 5,556 hours, or about 231 days. Even if several chips are tested simultaneously using expensive equipment, a considerable amount of test time is required. Typically, IC chip test service companies charge a fee in proportion to the number of test equipment used and test time, so the time required for chip test can have a significant impact on chip cost.

However, if the nominal shift frequency is increased, the power consumption generated when the scan pattern is shifted in or out is out of the range of power consumption allowed by the IC chip, so that a normal scan test cannot be performed. In addition, due to the over-shift frequency, an over-kill problem of determining a good product as a defective product may occur due to a critical path delay time problem, a deepening effect of power supply noise, and a deepening of interference between signal lines. This can affect the yield and cost, which are very important in mass production of IC chips.

Therefore, in the present embodiment, instead of applying a single shift frequency such as a nominal shift frequency to the entire scan pattern, an optimal shift frequency that can be normally shifted is allocated to the scan path for each scan section. The process of finding the optimal shift frequency for each scan section will be described in more detail with reference to FIG. 12 or less. The optimal shift frequency means the maximum shift frequency that can be used for the scan section or a shift frequency smaller than this.

In the example of FIG. 11 , scan section 1 is assigned a shift frequency A, and scan section 2 is assigned a shift frequency B. And the scan section 3 is allocated the same shift frequency A as the scan section 1. In this way, each scan section may be allocated the same shift frequency or may be allocated different shift frequencies.

For example, when one scan pattern is divided into a plurality of scan sections, a plurality of shift frequencies may be allocated to one scan pattern. Referring to FIG. 6 , two scan sections 640 and 650 belonging to one scan pattern may be assigned different shift frequencies. That is, two shift frequencies are allocated to one scan pattern.

Each scan section to which a shift frequency is assigned may be integrated into a section group according to an embodiment. For example, the second scan section and the third scan section may be grouped into a section group, and a smaller shift frequency or less among shift frequencies A and B of each scan section may be assigned to the corresponding section group.

In the scan test process, the application of the main input test data to the main input port and the observation of the test result at the main output after the scan pattern is input to the scan path may or may not be applied to the chip test process of the following embodiments.

12 is a conceptual diagram illustrating an example of a method of finding a shift frequency for minimizing a scan test time according to at least one embodiment of the present invention.

First, the relationship between the input pattern, the scan section, the scan pattern, and the output pattern will be described.

The input patterns 1202 , 1204 , and 1206 are bit patterns input to the scan path 1210 . In FIG. 12 , the scan section K, which is the current shift frequency determination target, corresponds one-to-one with the input pattern K 1204 . The bit pattern located before or after the input pattern K 1204 containing the scan section K (hereinafter, target scan section K) for which you want to find or determine the optimal shift frequency is the sub-scan section or sub-bit for the target scan section. It can be called a pattern.

(Input pattern when scan section and scan pattern are one-to-one correspondence)

When the target scan section K 1204 corresponds one-to-one with the scan pattern M, the input pattern K-1 1202, the input pattern K 1204, and the input pattern K+1 1206 each correspond to the scan pattern M-1, The scan pattern M and the scan pattern M+1 may correspond one-to-one.

(Output pattern K when scan section and scan pattern are one-to-one correspondence)

In the case where the target scan section K 1204 has a one-to-one correspondence with the scan pattern M, the output pattern of the scan path 1210 for the target scan section K 1204 is the output pattern K of the scan path 1210 for the scan pattern M (1224). The output pattern K 1224 may be a scan capture result pattern for the target scan section K 1204 or a pattern in which the scan pattern M is directly output from the scan path.

(Output pattern K-1 when scan section and scan pattern match one-to-one)

When the target scan section K 1204 has a one-to-one correspondence with the scan pattern M, the output pattern of the scan path for the input pattern K-1 1202 is the output pattern K-1 ( 1222). The output pattern K-1 1222 may be a scan capture result for the scan pattern M-1 or a pattern in which the scan pattern M-1 is directly output from the scan path.

(Output pattern K+1 when scan section and scan pattern match one-to-one)

When the target scan section K 1204 has a one-to-one correspondence with the scan pattern M, the output pattern of the scan path for the input pattern K+1 (1206) is the output pattern K+1 of the scan path for the scan pattern M+1 . The output pattern K+1 may be a scan capture result pattern for the scan pattern M+1 or a pattern in which the scan pattern M+1 is directly output from the scan path.

(Input patterns K-1, K+1 when the scan section is part of the scan pattern)

For example, referring to FIG. 14 , when the target scan section K 1204 is a part of a scan pattern M, the input pattern K-1 1202 is a scan pattern M-1 and a scan section K ( 1204) and other parts. The input pattern K+1 (1206) may include a portion other than the scan section K (1204) in the scan pattern M+1 and the scan pattern M.

(Output pattern K when the scan section is part of the scan pattern)

If the target scan section K 1204 is part of a scan pattern M as in FIG. 14 , the output pattern K 1224 of the scan path for the target scan section K 1204 is the scan capture for the target scan section 1204 . It may be a result pattern or a scan capture result pattern for scan pattern M containing scan section K. Alternatively, the output pattern K 1224 may be a pattern in which the scan section K 1204 is directly output from the scan path, or the scan pattern M including the scan section K 1204 is output directly from the scan path.

(Output patterns K-1, K+1 when the scan section is part of the scan pattern)

In the case where the target scan section K 1204 is a part of the scan pattern M as shown in FIG. 14 , the output pattern K-1 1222 of the scan path for the input pattern K-1 1202 is for the scan pattern M-1. It may be an output pattern or an output pattern for the scan pattern M-1 and a part of the scan pattern M. Also, the output pattern K+1 of the scan path for the input pattern K+1 (1206) may be an output pattern for the scan pattern M+1 or an output pattern for the scan pattern M+1 and a portion of the scan pattern M. As another example, the output pattern of the scan path for the portion of the scan pattern M included in the input pattern K-1 (1202) or the input pattern K+1 (1206) is the scan pattern M including the target scan section K (1204). It can be reflected in the output pattern of the scan path for . As another example, the output pattern for the input pattern K-1 (1202) or the input pattern K+1 (1206) is the output pattern of the input pattern K-1 (1202) or the input pattern K+1 (1206) as it is output from the scan path. It can be a pattern.

(If the scan section spans multiple scan patterns)

For example, referring to FIG. 15 , the target scan section K 1204 may span multiple scan patterns. In this case, the input pattern K-1 (1202) may include a portion of the scan pattern M-1 excluding the portion of the target scan section K (1204), and the input pattern K+1 (1206) is the scan pattern M+1 may include a portion excluding the portion of the target scan section K 1204 in . In this case, the optimal shift frequency for each portion of the target scan section K 1204 that spans each scan pattern can be separately identified, and the optimal shift frequency assignable to the target scan section K 1204 can be determined. .

The above corresponds to an example for helping understanding of the present invention, and the present invention is not limited to this example. In addition, the scan pattern may be divided into various types of scan sections as described with reference to FIGS. 5 to 10 , and depending on the division shape of the scan section, the input pattern K and the input pattern K-1 or input pattern K+1 located before and after the input pattern K may also vary in shape. That is, the input pattern K-1 1202 or the input pattern K+1 1206 may include at least one scan section.

12 illustrates an example of a method for minimizing a scan test time when shift-in and shift-out described in FIG. 4 are overlapped. 12 is for explaining an example according to the present invention, and the present invention is not limited to the case in which the shift-in and the shift-out described in FIG. 4 are simultaneously performed.

In the scan test of the IC chip, the test result pattern 1220 for the input pattern 1200 is compared with the prediction pattern 1230 to determine whether the test is normal. That is, after the input pattern 1200 is loaded into the scan path 1210 and the result pattern 1220 obtained by performing the capture operation is unloaded or the input pattern is loaded and then unloaded without a capture operation, the prediction pattern 1230 and the unloaded The result pattern 1220 is compared to determine whether the test is normal.

In at least one embodiment of the present invention, in order to optimize the shift frequency for the scan pattern or scan section, the output pattern shifted out simultaneously (or sequentially) when the target scan pattern or the target scan section is shifted in the scan path is also normal make sure it is For example, even if the target scan pattern or target scan section is normally shifted in the scan path with the increased shift frequency, an error may occur in the test result pattern for the previous input pattern shifted out with the increased shift frequency.

In the example of FIG. 12 , in order to check whether the scan section K 1204 , which is the current shift frequency determination target, is normally shifted into the scan path with a specific shift frequency, input pattern K-1 1202 and input pattern K+1 1206 can be used together. That is, each time the target scan section K 1204 is repeatedly input to the scan path 1210 , the input pattern K-1 1202 can be used to initialize the scan path to a constant bit pattern. Also, whenever the output pattern of the scan path for the k-th scan section 1204 is repeatedly shifted out, an input pattern K+1 ( 1206 ) that is shifted in to the scan path with a constant bit pattern may be used.

When the target scan section K 1204 corresponds to the scan pattern M one-to-one, the input pattern K-1 1202 is the scan pattern M-1 used for the actual scan test located in front of the target scan section K 1204, or , it may be a predictive pattern for the result pattern obtained by scan-capture after loading the scan pattern M-1 into the scan path.

As another example, when the target scan section K 1204 is a part of the scan pattern M as shown in FIG. 14 , the input pattern K-1 1202 is a scan pattern used for an actual test located in front of the target scan section K 1204 . After loading M-1 or scan pattern M-1 into the scan path, it may include a prediction pattern for the result pattern obtained by scan capture. Also, the input pattern K-1 (1202) may include a portion of the scan pattern M except for the target scan section K (1204). Here, a portion of the scan pattern M except for the target scan section K may be a part of a bit pattern used for an actual scan test.

As another example, the input pattern K-1 1202 may be configured based on bit '0' or '1' in order to reduce the switching operation of the scan path, or may be configured based on consecutive bits '0' or '1', etc. It could be a pattern.

As another example, the input pattern K-1 1202 may include at least one scan section as shown in FIG. 13 .

In the case where the target scan section K 1204 has a one-to-one correspondence with the scan pattern M, the k+1th input pattern 1206 is the scan pattern M+1 used for the actual scan test located after the scan section K 1204 or the scan After loading the pattern M+1 into the scan path, it may be a predictive pattern for the result pattern obtained by scan-capture.

As another example, when the target scan section K 1204 is a part of the scan pattern M as shown in FIG. 14 , the input pattern K+1 1206 is used for the actual scan test located behind the target scan section K 1204 . It may include a scan pattern M+1, and the like. Also, the input pattern K+1 (1206) may include a portion of the scan pattern M except for the target scan section K (1204). Here, a portion other than the target scan section K 1204 may be a part of a bit pattern used for an actual scan test.

As another example, the input pattern K+1 (1206) is composed of bit '0' or '1' mainly in order to reduce the switching operation on the scan path, or is composed mainly of consecutive bits '0' or '1', etc. It can be a pattern.

As another example, the input pattern K+1 (1206) may include at least one scan section as shown in FIG. 13 .

And, in the scan test, the input patterns positioned before the first scan section and after the last scan section, respectively, are mainly composed of bit '0' or '1' in order to reduce the switching operation of the scan path, or consecutive bit '0' or It may be a preset arbitrary pattern, such as mainly composed of '1'. Also, the input pattern positioned in front of the first scan section may be a value on the scan path when the chip under test is in the reset state.

In at least one embodiment of the present invention, the input pattern K-1 1202 or the input pattern K+1 1206 may each consist of one or more scan sections, the shift frequencies of these sections being the current shift frequency determination target. There may be no restrictions on finding the maximum shift frequency of the scan section K 1204 .

For example, it is assumed that the input pattern K-1 1202 can be normally shifted in the scan path up to 30 MHz, and the target scan section K 1204 can be normally shifted in the scan path up to 50 MHz. If the input pattern K-1 (1202) and the target scan section K (1204) are sequentially shifted into the scan path with the same shift frequency while increasing the shift frequency, the maximum shift frequency that can be found for the target scan section K (1204) is limited to 30 MHz. That is, when the shift frequency exceeds 30 MHz, the output pattern and the prediction pattern for the input pattern K-1 1202 may be different. Also, even if the input pattern K+1 (1206) is normally shiftable in the scan path up to 30 MHz, the maximum shift frequency that can be found for the target scan section K (1204) may be limited to 30 MHz.

Therefore, in order to avoid such a constraint, in at least one embodiment of the present invention, the shift frequency of the input pattern K-1 (1202) or the input pattern K+1 (1206) is a preset shift frequency (30 MHz in the above example) may not be exceeded.

For example, the shift frequency of the input pattern K-1 (1202) or the input pattern K+1 (1206) is fixed to a preset shift frequency (30 MHz or less in the above example), and the shift of the target scan section K (1204) By increasing or decreasing only the frequency, it is possible to find the maximum shift frequency usable for the target scan section K 1204 .

As another example, up to the preset shift frequency (in the above example, 30 MHz or less) for the input pattern K-1 (1202), the target scan section K (1204), and the input pattern K+1 (1206), the shift frequency increases or decreases together , and when out of the preset shift frequency, only the shift frequency of the target scan section K 1204 may be increased or decreased.

In other words, the shift frequency of the target scan section K 1204 and the shift frequency of the remaining input patterns 1202 and 1206 can be controlled differently. Of course, if the maximum allowable shift frequency of the input pattern K-1 (1202) or the input pattern K+1 (1206) is greater than the maximum shift frequency of the target scan section K (1204), then the target scan section K (1204) and the remaining input pattern ( 1202 and 1206) may be increased or decreased in the same manner. Here, the preset shift frequency may be a nominal shift frequency, a shift frequency adjusted with the nominal shift frequency, a value preset in the test device by a program, or a value preset by a user, etc. It can be variously changed according to an embodiment. It is not necessarily limited to the above example.

In at least one embodiment of the present invention, when the optimal shift frequency has already been determined for the input pattern K-1 ( 1202 ) or the input pattern K+1 ( 1206 ) through the method according to the embodiment of the present invention, the optimal shift The input pattern K-1 (1202) or the input pattern K+1 (1206) may be shifted in to the scan path by applying the frequency or less.

For example, when the method according to the present invention is sequentially applied to scan patterns, at least one scan section constituting the input pattern K-1 is performed before the shift frequency determination process of the target scan section K 1204. An optimal shift frequency may be predetermined. Therefore, the scan test time minimization device uses the optimal shift frequency for each scan section of the input pattern K-1 (1202), and for the input pattern K+1 (1206), the nominal shift frequency or the shift frequency adjusted by the nominal shift frequency can be applied.

And while increasing or decreasing the shift frequency of the target scan pattern K, input patterns 1202, 1204, and 1206 are sequentially input to the scan path 1210 to determine whether the actual output pattern 1220 is the same as the predicted pattern 1230 . In this case, if necessary, a scan capture operation may be performed on at least one of the input patterns 1202 , 1204 , and 1206 .

For example, the scan test time minimization apparatus uses a nominal shift frequency as the initial shift frequency, and increases the shift frequency in a unit of change of a shift frequency preset in the scan test time minimization apparatus. That is, after loading the input pattern K-1 (1202) by shifting it into the scan path with a preset shift frequency such as the nominal frequency, the target scan section K (1204) is set to the shift frequency of “initial shift frequency + increment” in the scan path , and at the same time, the test result (ie, output pattern K-1) 1222 by the input pattern K-1 (1202) is shifted out to compare whether it is the same as the known prediction pattern K-1 (1232). .

In this case, a shift frequency preset for at least one scan section included in the input pattern K-1 1202 or the input pattern K-1 1202 may be different from an initial shift frequency of the target scan section K 1204 . And again, at the same time as the shift of the input pattern K+1 (1206), the output pattern K (1224) obtained by shifting out the test result for the target scan section K (1204) is the same as the prediction pattern K (1234) known in advance compare it At this time, when the target scan section K 1204 is a part of the scan pattern as shown in FIG. 14 , the input pattern K-1 1202, the target scan section K 1204, the input pattern K+1 1206, and each of these The output pattern for this is as described above.

In at least one embodiment of the present invention, the above-mentioned preset shift frequency may not limit the search for the optimal shift frequency of the target scan section K 1204 . In at least one embodiment of the present invention, the shift frequency of input pattern K-1 1202 or input pattern K+1 1206 does not increase or decrease with the shift frequency of target scan section K 1204 or A different frequency than K 1204 can be used, in which case a shift frequency that can normally input the scan section of input pattern K-1 1202 or input pattern K+1 1206 into the scan path is used.

In at least one embodiment of the present invention, the preset shift frequency may be a value obtained by adjusting the nominal shift frequency in addition to the nominal shift frequency, a value set in the device by a program, or a value set by a user, etc. It can be changed in any way and is not necessarily limited to the above example.

If the output pattern K-1 (1222) and the prediction pattern K-1 (1232) are the same, and the output pattern K (1224) and the prediction pattern K (1234) are the same, the current shift frequency is in the target scan section K (1204). It is the available shift frequency for The scan test time minimization device increases the shift frequency for the target scan section K (1204) by a certain amount again, and as described above, while performing the process of inputting the input pattern K-1 (1202) into the scan path again, the output pattern ( 1220) and the prediction pattern 1230 are compared again.

In this way, the shift frequency for the target scan section K 1204 is continuously increased to the point where the output pattern 1220 and the prediction pattern 1230 are different, and the shift frequency or less before that point is set to the target scan section K ( 1204) can be determined as the optimal shift frequency.

Although the previous embodiment mainly describes a method of finding the optimal shift frequency by increasing the shift frequency, in another embodiment, the output pattern 1220 of the target scan section K 1204 and the prediction pattern 1230 are different for the shift frequency. It is possible to find a point at which the output pattern 1220 and the prediction pattern 1230 become the same by repeatedly decreasing from a high frequency. In addition, a shift frequency less than or equal to a point at which the output pattern 1220 and the prediction pattern 1230 become the same may be determined as the optimal shift frequency of the target scan section K 1204 .

In addition, as an embodiment of the increase/decrease range of the shift frequency when the output pattern for the scan section or scan pattern is repeatedly compared with the predicted pattern while increasing or decreasing the shift frequency, increase or decrease within the range set in the scan test time minimization device or output When the pattern 1220 and the prediction pattern 1230 are the same and then different, or when a point at which the pattern 1220 and the prediction pattern 1230 become the same is found, the increase or decrease of the shift frequency can be stopped. In this case, the time required to find the maximum usable shift frequency for each scan section can be reduced.

According to an embodiment, the initial shift frequency for finding the optimal shift frequency for the target scan section K 1204 may be set to various values other than the nominal frequency, and the output pattern and the prediction pattern are not increased at a low shift frequency. It is also possible to find the shift frequency at the point where the output pattern and the prediction pattern become the same as the shift frequency is decreased starting from this different high shift frequency. In addition, instead of sequentially increasing or decreasing the change in the shift frequency of the target scan section K 1204, it is possible to find the optimal shift frequency in a faster time by changing it in various ways through various algorithms.

In at least one embodiment of the present invention, a binary search algorithm may be used. For example, if the shift frequency is test ok at 10 MHz and the test fails at 20 MHz, try the next shift frequency of 15 MHz in between. And if the test is normal, try between 15MHz and 20MHz, and if it fails, try between 10MHz and 15MHz. The test normal means that the test target chip is determined as a good product, and the test failure means that the test target chip is judged as a defective product.

Binary search has the effect of reducing the time it takes to find a frequency that is the boundary between test success and failure or an usable frequency range where test is normal, compared to when performing a linear search. For example, if you use a linear search to find the maximum frequency at which the test is normal with N frequency increases and decreases, then you can use the binary search to find the maximum frequency at which the test is normal with about log ₂ (N) times. The effect of reducing the search time of the maximum frequency that is tested using binary search is more effective than the linear search method as the number of whole scan sections and the unit value of the frequency increased or decreased by the test equipment are small.

As another embodiment, an optimal frequency or period may be found or determined in consideration of a variation margin of a supply voltage supplied to a test target chip. For example, you can quickly find the optimal frequency or period within the range of voltages supplied to the chip under test by using the following steps.

Step 1

The scan test time minimization device finds the maximum shift frequency or shift frequency range in which the test result of the test data is normal for each voltage while changing the voltage supplied to the test target chip in a certain unit. That is, instead of finding the shift frequency for each scan section in which the test data is divided, the maximum shift frequency or shift frequency range that can be used for the entire test data is found.

Step 2

From the result of step 1, the scan test time minimization device selects a specific voltage to be supplied to the chip under test. Here, the specific voltage to be supplied to the test target chip is a voltage representing the lowest maximum shift frequency among the maximum shift frequencies for each voltage found in step 1 or a voltage adjacent to the voltage. In addition, the voltage supplied to the test target chip may be selected in consideration of a test setup, a manufacturing process, or a test process.

Step 3

The scan test time minimization device supplies the specific voltage selected in step 2 to the chip under test. In addition, the scan test time minimization device detects normal or failed tests for each shift frequency of each scan section while increasing or decreasing the shift frequency for each scan section while a specific voltage is supplied.

Step 4

The scan test time minimization apparatus finds or determines the optimal shift frequency for each scan section by using the shift frequency information to which the results of test normal or failure for each scan section found in step 3 are mapped.

Step 5

The scan test time minimization device checks whether the test result is normal by using the optimal shift frequency for each scan section found or determined in step 4 while changing the supply voltage to the chip under test.

In at least one embodiment of the present invention, the range of change of voltage in step 5 may be the same as the range of change of voltage in step 1. Alternatively, the change range of the voltage in step 5 may be a range in which the change range in step 1 is adjusted in consideration of a test setup, a manufacturing process, or a test process. While changing the voltage within the range of voltage change, check whether the scan test result using the optimal shift frequency of each scan section found or determined in step 4 is normal. If each scan section is all tested within the voltage change range, the shift frequency is normally optimized. In addition, there may be various criteria for determining that the shift frequency for each scan section is normally optimized in consideration of a test setup, a manufacturing process, a test process, and the like. For example, certain voltages may allow the test to fail.

If it is necessary to find the optimal frequency in consideration of the variation margin of the supply voltage to the chip under test, use the same method as in the previous step to find the method while changing the voltage and frequency for all scan sections, respectively. When used, the optimum shift frequency or period of the shift frequency can be quickly found or determined.

For example, it is assumed that SN (number of scan sections) = 1,000, VN (number of voltage changes) = 10, and FN (number of frequency changes) = 10.

case 1

Number of searches required to find a test good or failed, varying voltage and frequency respectively for every scan section = SN x VN x FN = 100,000

case 2

Number of searches required to find a test normal or failed using steps 1-5 above = (step 1) VN x FN + (step 3) SN x FN + (step 5) VN = (VN + SN) x FN + VN = 10,110

It can be seen that the number of cases in case 2 is reduced by about 10% compared to case 1.

The scan section K 1204 for finding the optimal shift frequency may be configured as a part of the scan pattern M as shown in FIG. 14 . That is, the length of the target scan section K 1204 may be shorter than the length of the scan path. In this case, in the scan pattern M including the target scan section K 1204 , the shift frequency of a portion excluding the target scan section 1204 does not limit the search for the optimal shift frequency of the target scan section K 1204 .

For example, the shift frequency of a portion of the scan pattern M except for the target scan section K 1204 does not increase or decrease with the shift frequency of the target scan section K 1204, or a shift frequency different from the target scan section K 1204 can be used In at least one embodiment of the present invention, the shift frequency of the portion excluding the target scan section K 1204 in the scan pattern M is a shift frequency that can normally input the portion except the target scan section K 1204 into the scan path. can be used

In another embodiment, the shift frequency applied to a portion other than the target scan section K 1204 in the scan pattern M is less than or equal to the nominal shift frequency, or for a portion other than the target scan section K 1204 according to an embodiment of the present invention When the optimal shift frequency has already been determined through the method, a preset shift frequency such as less than or equal to the optimal shift frequency may be used. And, as described above, for the target scan section K 1204, an optimal frequency is found by increasing or decreasing the shift frequency. The preset shift frequency may be variously changed according to embodiments, such as a value obtained by adjusting the nominal shift frequency, a value set in the device by a program, or a value set by a user, and is not necessarily limited to the above example.

12 illustrates a method of finding the optimal shift frequency of the target scan section K 1204 using the input pattern K-1 1202 together, but is not limited thereto. According to an embodiment, the optimal shift frequency may be found or determined by comparing only the target scan section K 1204 or the output pattern of the scan path for the scan pattern including the target scan section K 1204 with the prediction pattern.

(Considering the comparison of the output pattern with the previous input pattern)

In at least one embodiment of the present invention, when trying to find or determine the optimal shift frequency of the target scan section K ( 1204 ), the input pattern K-1 ( 1202 ) located immediately before the target scan section K ( 1204 ) is The output pattern or the output pattern for the scan pattern immediately preceding the scan pattern containing the target scan section K 1204 can also be compared with the predicted pattern.

For example, if the output pattern of the scan path for the target scan section K 1204 is the same as the prediction pattern, but also the output pattern for the input pattern K-1 1202 is the same as the prediction pattern, then the target scan section K The shift frequency used when shifting 1204 to the scan path may be identified as an usable shift frequency of the target scan section K 1204 .

As another example, when the target scan section K 1204 is part of the scan pattern as shown in FIG. 14 , the output pattern K 1224 of the scan path for the scan pattern M including the target scan section K 1204 is the predicted pattern K Same as (1234) and when the output pattern K-1 (1222) of the scan path for the scan pattern M-1 located in front of the scan pattern M is the same as the prediction pattern K-1 (1232), the target scan section K The shift frequency used when shifting 1204 to the scan path may be identified as an usable shift frequency of the target scan section K 1204 .

As such, the reason for comparing the output pattern 1222 and the prediction pattern 1232 for the input pattern 1202 positioned before the target scan section K 1204 as well as the target scan section K 1204 is the input pattern positioned before the target scan section K 1204 . This is because the output pattern of the scan path for (or part of the input pattern) may be affected by the shift-in frequency of the target scan section K 1204 . Here, the shift-out output pattern for the input pattern is a pattern obtained by performing a scan capture operation after an input pattern (or a part of an input pattern) located in front of the target scan section K 1204 is input to a scan path, or a scan capture operation It may be a pattern output from the scan path without

16 is a graph showing an example of a method of finding a usable shift frequency of a scan pattern according to at least one embodiment of the present invention, and FIG. 17 is a method for finding an optimal shift frequency according to at least one embodiment of the present invention. This is a graph showing a case in which the test result of another scan pattern fails when the shift frequency of the scan pattern is increased or decreased.

Referring to FIG. 16 , in order to find the optimal shift frequency of the second scan pattern, the first scan pattern, the second scan pattern, and the third scan pattern are sequentially input to the scan path. In at least one embodiment of the present invention, a shift frequency (eg, 5 MHz) capable of normally inputting the first scan pattern into a scan path is used for shift-in of the first scan pattern. In other words, a shift frequency at which a scan test result based on the first scan pattern can become normal is used for shifting the first scan pattern.

When the shift frequency of the second scan pattern is sequentially increased from 5 MHz to 25 MHz, both the test results of the first scan pattern and the second scan pattern are normal. In this case, all shift frequencies of 25 MHz or less are shift frequencies usable for the second scan pattern.

Referring to FIG. 17 , when the shift frequency of the second scan pattern is increased to 30 MHz, the test result of the second scan pattern is normal, but the test result of the first scan pattern is a failure. This is because the test result of the shifted-out first scan pattern is affected by the shift frequency of the second scan pattern. Accordingly, in at least one embodiment of the present invention, the shift frequency when the test result of the first scan pattern that is the input pattern before the second scan pattern as well as the second scan pattern to find the optimal shift frequency is normal is the second scan pattern is the available frequency of

A scan section for which an optimal shift frequency is to be found may be part of a scan pattern. At this time, as described above, the shift frequency when the test results of the first scan pattern as well as the second scan pattern including the target scan section for which the optimum shift frequency is to be found are all normal is the usable frequency of the target scan section. For bit patterns except for the target scan section, a shift frequency that can normally input the bit pattern into the scan path is used.

For the third scan pattern, a shift frequency that is normally shifted in the scan path and capable of normally shifting the test result for the second scan pattern out at the same time is used.

In order to find the optimal shift frequency of the scan section or to reduce the mass-production test time of the chip, when the first and second scan sections adjacent to each other are sequentially input into the scan path of the chip, the shift frequency of the first scan section and the second 2 The scan test can be performed by differentiating the shift frequencies of the scan sections. For example, each different shift frequency used in the two scan sections may be less than or equal to a shift frequency value at which a scan test using the two scan sections becomes normal.

The scan test may be performed with respect to the first scan section and the second scan section adjacent to each other by making the shift frequency of the second scan section larger or smaller than the shift frequency of the first scan section. At this time, when the test result for a fault-free chip is normal, each shift frequency or less of two adjacent scan sections is used to reduce the mass-production test time of the chip. That is, the influence of neighboring scan sections on each other during the scan test should be considered.

For example, when the first scan section and the second scan section have adjacent scan patterns, the effect of the shift frequency of the subsequently input second scan section is considered when the scan capture result by the first scan section is shifted out should be For example, when the scan capture result pattern is shifted out, the bit value of the result pattern may change according to the shift frequency.

As another example, when neighboring first and second scan sections are included in one scan pattern, when the first scan section is shifted in, the effect of the shift frequency of the next shifted second scan section should be considered. . This is because, for example, the bit value of the shifted first scan section in the scan path may be changed by the shift frequency of the second scan section.

As another example, when the scan capture result of the first scan pattern shifted in before the second scan pattern including the first scan section and the second scan section is shifted out, the first scan section and the second scan section belonging to the second scan pattern are shifted out. 2 The effect of the scan section should be considered. This is because, if these effects are not taken into account, the scan test result for a chip without a failure may result in test failure during mass production testing.

(Consider the output result for the input pattern before or after the target scan section for which you want to find the optimal shift frequency)

When trying to find or determine the optimal shift frequency of the target scan section, the scan path for the target scan section as well as the input pattern located before or after it or the scan pattern located before or after the scan pattern including the target scan section 1204 is It compares the output pattern with the predicted pattern to figure out whether an IC chip that is actually normal under test can be tested as normal.

In at least one embodiment of the present invention, it is possible to find or determine the optimal shift frequency of the target scan section by repeating this process while increasing or decreasing the shift frequency. In this case, the shift frequency at which the test result is normal is the usable shift frequency of the target scan section. The output pattern of the scan path for the target scan section is a pattern obtained by performing a capture operation after loading the target scan section into the scan path, or the target scan section or a scan pattern including the target scan section is output from the scan path without a scan capture operation It can be one pattern.

(Considering the output result for the input pattern input after the target scan section to find the optimal shift frequency)

comparing also the output pattern of the scan path for the input pattern located after the target scan section or the scan pattern located after the scan pattern including the target scan section 1204 with the predicted pattern to find or determine the optimal shift frequency; may include

For example, to find or determine the optimal shift frequency of the target scan section, the output pattern for the target scan section that is shifted out of the scan path is positioned immediately after the target scan section to influence the bit value of the shifted input pattern. can give As another example, in order to find or determine the optimal shift frequency of the target scan section, the output pattern for the scan pattern including the target scan section that is shifted out from the scan path is positioned immediately after the scan pattern comprising the target scan section to be shifted It may affect the bit value of the scanned scan pattern.

(If the back input pattern can influence the target scan section to find the optimal shift frequency)

When the output pattern of the scan path with respect to the target scan section or the scan pattern including the target scan section is shifted out, the shifted-in input pattern located behind may affect the bit value of the output pattern of the target scan section.

(Considering the shift frequency of the rear input pattern)

In order to reduce or eliminate the influence of the input pattern (or scan pattern), the input pattern (or scan pattern) that is positioned immediately after and shifted in when the output pattern of the scan path for the target scan section or the scan pattern including the target scan section is shifted out. As the shift frequency of the pattern), a shift frequency capable of normally shifting the shifted input pattern (or scan pattern) in the scan path by being located behind the target scan section may be used.

(Considering the shift frequency of the front or rear input pattern)

In order to find or determine the optimal shift frequency of the target scan section, the shift frequency of the input pattern (or part of the input pattern) positioned before or after the target scan section may be the same as or different from the shift frequency of the target scan section. At this time, in at least one embodiment of the present invention, a shift frequency at which an input pattern located before or after the target scan section can be normally shifted in the scan path is used.

This is because, as described above, an input pattern located before or after the target scan section for which the currently available maximum shift frequency is to be found may limit the usable maximum shift frequency of the target scan section. For example, the maximum usable shift frequency of the input pattern located before or after the target scan section may be lower than the maximum usable shift frequency of the target scan section.

18 to 20 are conceptual diagrams illustrating an example of a configuration of a scan pattern, a scan section, and shift frequency information necessary to find a usable shift frequency of a scan section.

Referring to FIG. 18 , a scan pattern is a scan section in which a usable shift frequency or an optimal shift frequency at which a chip can be normally tested is a scan pattern. Each scan pattern N+1, scan pattern N+2, and scan pattern N+3 of the test data 1800 is a scan section in which an usable shift frequency or an optimal shift frequency is to be found. 18 shows the configuration of scan pattern, scan section and shift frequency information necessary to find or determine an usable shift frequency or optimal shift frequency of scan pattern N+1, scan pattern N+2, and scan pattern N+3, respectively; .

In at least one embodiment of the present invention, in FIG. 18 , T1, T2, T3, and Target_T indicate information related to a scan shift frequency or period of a scan shift frequency, and for convenience of description, a timing identifier, a timing set, or a timing It can be called information.

In at least one embodiment of the present invention, the timing information may include or indicate the shift frequency or the period of the shift frequency as information related to the shift frequency or the period of the shift frequency. The timing information may be used to identify or control a scan pattern or scan section. For example, the test apparatus may increase or decrease the shift frequency or period of the shift frequency of the scan pattern or scan section identified by the timing information.

There may be restrictions on the number of frequencies that the test device can control, and accordingly, there may be restrictions on the number of timing identifiers over which the test device can control frequencies. For convenience of description below, the number of timing identifiers provided by the test apparatus means the number of frequencies that the test apparatus can control or set or the number of timing identifiers that the test apparatus can control or set frequencies with.

In FIG. 18 , T1 indicates a shift frequency for the scan pattern N or information related to the period of the shift frequency, and may be referred to as timing information of the scan pattern N. In FIG. 18 , Target_T for scan pattern N+1 indicates information related to a shift frequency or period of scan shift frequency for scan pattern N+1, which is a scan section for which an usable shift frequency or optimal shift frequency is to be found, and scan pattern N It may also be referred to as +1 timing information. That is, in FIG. 18 , T1, T2, and T3 are timing information of a scan pattern located in front of a scan section to find an optimal shift frequency, and Target_T is timing information of a scan section that is a shift frequency optimization target.

In FIG. 18 , at least two or more of Target_T, T1, T2, and T3 may have the same or different shift frequency or period of shift frequency.

In FIG. 18 , the shift frequency of T1, T2, or T3 or period information of the shift frequency is a shift frequency or period of shift frequency that allows the scan pattern or scan section corresponding to T1, T2 or T3 to be normally input to the scan path. do. In this case, the shift frequency corresponding to Target_T or the period of the shift frequency may be increased or decreased to find an optimal value. In addition, it is not limited to the example of FIG. 18 , and one or more shift frequencies, periods or timing information of shift frequencies may be variously allocated or used in one scan pattern.

In at least one embodiment of the present invention, the search data 1810, 1820, 1830 used to find a usable shift frequency or an optimal shift frequency of a certain scan section includes at least two or more scan patterns as shown in FIG. can be configured.

The search data 1810 for finding the usable shift frequency or the optimal shift frequency of the scan pattern N+1 includes at least the scan pattern N+1 and the scan pattern N positioned before it. For example, a scan section or scan pattern included in the search data 1810 , 1820 , and 1830 may be repeatedly input into a scan path to find an usable shift frequency or an optimal shift frequency of a specific scan section.

At this time, it is determined whether the test for each scan pattern is normal or failed based on the scan test output pattern of the chip using at least two or more respective scan patterns included in the search data 1810 , 1820 , and 1830 . For example, the output pattern may be compared with the prediction pattern, and the prediction pattern may be included in the search data 1810 , 1820 , and 1830 and managed. In other words, the search data 1810 , 1820 , and 1830 may include each of the scan patterns N+1 and each prediction pattern corresponding to each output pattern of the scan pattern N positioned in front of it. And based on the test success or failure information, it is possible to find an usable shift frequency or an optimal shift frequency of the scan section. For example, an usable shift frequency or an optimal shift frequency of the scan pattern N+1 corresponding to Target_T may be found.

A scan test is performed using the scan pattern N+1 and the scan pattern N located in front of it to find an usable shift frequency or an optimal shift frequency of the scan pattern N+1. In this case, success or failure of the test may be determined based on the scan test output pattern of the chip for each of the two scan patterns N+1 and N. In addition, an usable shift frequency or an optimal shift frequency for the scan pattern N+1 may be found. A shift frequency at which both the scan pattern N+1 and the scan test result using the scan pattern N positioned before it are normal is the usable shift frequency of the scan pattern N+1.

Referring to FIG. 19 , a scan section in which a usable shift frequency or an optimal shift frequency is to be found is a scan pattern. At least three or more scan patterns are used, including those located before and after the target scan section, to find the optimal shift frequency for the scan section.

For example, the search data 1910 , 1920 , and 1930 used to find the usable shift frequency or the optimal shift frequency of the scan section includes at least three or more scan patterns as shown in FIG. 19 . The scan pattern or scan section of the search data 1910 , 1920 , and 1930 used to find an usable shift frequency or an optimal shift frequency may be repeatedly input to the scan path. At this time, based on the comparison of the output pattern of the scan pattern included in the search data (1910, 1920, 1930)) and the predicted pattern, it is determined whether the test of the IC chip succeeds or fails. In addition, it is possible to find an usable shift frequency of the scan section to find an optimal shift frequency based on whether the test is successful or not.

In order to find a usable shift frequency or an optimal shift frequency of the scan pattern N+1 in the search data 1910, a chip test is performed using the scan pattern N+1 and the scan pattern N located in front of it. In this case, the shift frequency when the test result is normal is the usable shift frequency of the scan pattern N+1. In this case, the scan pattern N+2 located after the scan pattern N+1 uses a shift frequency that is normally shifted in the scan path, so that the chip test by the scan pattern N+2 can be omitted. Alternatively, the shift frequency when the chip test result based on the scan pattern N+2 is also normal may be determined as the usable shift frequency of the scan pattern N+2.

Referring to FIG. 19 , at least two or more of the timing information Target_T, T1, T2, T3, T4, T5, and T6 may be the same or different shift frequencies or periods of shift frequencies. The period of the shift frequency is a time interval of a shift operation for shifting the scan pattern with the shift frequency and is the reciprocal of the shift frequency. In at least one embodiment of the present invention, the shift frequency or period information of the shift frequency of the timing information T1, T2, T3, T4, T5 or T6 includes a scan pattern corresponding to T1, T2, T3, T4, T5 or T6 or A shift frequency or period of shift frequency is used so that the scan section can be normally input into the scan path. In this case, the shift frequency corresponding to Target_T or the period of the shift frequency may be increased or decreased to find an optimal value.

Also, it is not limited to the example of FIG. 19 , and one or more shift frequencies, periods or timing information of shift frequencies may be used in various ways in one scan pattern.

Referring to FIG. 20 , a scan section for which an usable shift frequency or an optimal shift frequency is to be found is a part of a scan pattern. That is, each of the scan sections A, A+1, and A+2 of the scan pattern N+1 is a scan section for which an optimal shift frequency is to be found.

Timing information T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10 is the scan pattern located before or after the scan section to find the usable shift frequency or the optimal shift frequency or timing information of the scan section . And Target_T is timing information of a scan section that is a shift frequency optimization target.

At least two or more of Target_T, T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 may have the same or different shift frequencies or periods of shift frequencies.

In at least one embodiment of the present invention, the shift frequency or period information of the shift frequency of T1, T2, T3, T4, T5, T6, T7, T8, T9 or T10 is T1, T2, T3, T4, T5, T6 , T7, T8, T9 or T10, or a shift frequency or period of shift frequency that allows the scan section to be normally input to the scan path is used. In this case, the shift frequency corresponding to Target_T or the period of the shift frequency may be increased or decreased to find a test normal value or an optimal value. Also, it is not limited to the example of FIG. 20 , and one or more shift frequencies, periods or timing information of shift frequencies may be used in various ways in one scan pattern.

An example of search data 2010, 2020, and 2030 for finding an optimal shift frequency for a scan section shorter than the scan pattern or scan path length is shown in FIG. 20 . The scan patterns included in the search data 2010, 2020, and 2030 may include at least two or more scan patterns as shown in FIG. 18 or at least three or more scan patterns as shown in FIG. 19 . When the search data 2010, 2020, and 2030 are composed of three scan patterns, output patterns of scan paths for at least three or more scan patterns may be compared with the prediction patterns.

As an example with reference to FIGS. 18, 19, and 20, the scan pattern or scan section included in the search data for finding the usable shift frequency or the optimal shift frequency of the scan section may be repeatedly input to the scan path. can

Also, the example of FIGS. 18 to 20 is not limited, and timing information for at least two scan patterns or scan sections included in the search data may be different or the same.

The search data used to find the optimal shift frequency of the scan section may include at least two or more scan patterns as in each case of FIGS. 18, 19, or 20 . In at least one embodiment of the present invention, the search data may include information related to the timing information of FIG. 18 , 19 , or 20 . The timing information may be used by the test device to control the timing of inputting the scan pattern or scan section into the scan path. The timing is the shift frequency or period of the shift frequency. Also, as an example, as shown in FIGS. 18 to 20 , scan patterns overlapping each other may be included in each of the search data used to find the optimal shift frequency for each neighboring scan section.

In at least one embodiment of the present invention, it may be efficient to batch-process using a computer program or software to generate data for searching used to find the optimal shift frequency of each of the numerous scan sections.

For example, as shown in FIGS. 18 to 20, a scan pattern used to find an optimal shift frequency of each scan section, the scan section, and the operation of constructing or dividing timing information or data related to the scan section and shift frequency require a computer program or software. It can be processed in batches using In addition, information such as the number of scan sections to be optimized, the bit length of the scan section, and the location of the scan section may be used in the above operation.

In addition, a prediction pattern may also be included in the search data used to find an usable shift frequency or an optimal shift frequency of a specific scan section. In addition, the search data used to find the usable shift frequency or the optimal shift frequency of a specific scan section includes primary input test data or primary output prediction data of the IC chip used together in the scan test. It may also be included.

21 to 28 are diagrams illustrating a method of generating search data according to at least one embodiment of the present invention. Among them, FIGS. 21 to 23 relate to a method of generating data for a search when the scan section is a scan pattern, and FIGS. 24 to 26 are a method of generating data for a search when the scan section is a part of a scan pattern. it's about

21 is a conceptual diagram illustrating an example of test data including a plurality of scan patterns.

Referring to FIG. 21 , a single shift frequency (eg, T1=50ns (ie, 20MHz)) is assigned to all scan patterns in the test data 2100 . Therefore, all scan patterns are shifted in and out with the same shift frequency in the scan path of the IC chip.

The test data 2100 may include a plurality of sub test data including an input scan pattern and a prediction pattern as a pair. For example, the 51st input scan pattern is paired with the prediction pattern of the 50th input scan pattern. The test data may be written in a format such as STIL (Standard Test Interface Language) or WGL (Wavefrom Generation Language).

The Doncare prediction pattern of the first sub-test data means that a test for comparing the output pattern shifted out when the first input scan pattern is shifted in the scan path with the prediction pattern is not performed. That is, the Doncare prediction pattern means that the IC chip is not tested or the test result is ignored by using the output pattern shifted out of the IC chip. The money care prediction pattern can be expressed in various ways, such as using specific characters meaning the money care prediction pattern or assigning a mark indicating the money care prediction pattern to the prediction pattern.

The output pattern shifted out when the first input scan pattern is input after the flip-flops are set or reset to a specific value may not be the money care prediction pattern.

22 is a conceptual diagram illustrating an example of a method of generating search data for finding an optimal shift frequency for each scan section when a scan section is a scan pattern.

Referring to FIG. 22 , timing information Target_T is given to a target scan section 2210 for which an optimal shift frequency is to be found in the original test data 2100 of FIG. 21 . The timing information Target_T is used to identify the target scan section 2210 or control a shift frequency of the target scan section. For example, Target_T may be increased or decreased by the test device in the initial 50ns.

When the target scan section 2210 is the input scan pattern 51, in order to find a usable shift frequency or an optimal shift frequency of the input scan pattern 51, the search data 2200 to which the Target_T is assigned is repeatedly input into the chip. For each repeated input, the period of the shift frequency of the target scan section 2210 corresponding to Target_T is changed. In this case, the period of the shift frequency of the input scan pattern other than the target scan section 2210 is the period of the shift frequency (eg, T1=50ns) at which the scan pattern can be normally input to the scan path.

For example, the search data 2200 is repeatedly input to the chip while decreasing the period of the shift frequency corresponding to Target_T until the maximum usable shift frequency of the target scan section 2210 is found. In this case, the output pattern for the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub test data 51 . Also, the output pattern for the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub test data 52 . The shift frequency when the test results of the input scan pattern 50 and the input scan pattern 51 are both normal is the usable shift frequency of the target scan section 2210 .

As the size of the search data 2200 used to find the usable shift frequency or the optimal shift frequency of the target scan section 2210 is smaller, the time used to find the optimal shift frequency can be reduced.

23 is a conceptual diagram illustrating an example of a method of generating search data for reducing a time required to find an optimal shift frequency.

Referring to FIG. 23 , search data 2300 for finding an usable shift frequency or an optimal shift frequency of an input scan pattern 51 that is a target scan section 2310 includes the target scan section 2310 and the input positioned before and after the target scan section 2310 , respectively. scan patterns 50,52. In addition, the prediction pattern included in the sub test data 50 located in front of the target scan section 2310 is a money care prediction pattern. That is, when the input scan pattern 50 is shifted in the scan path, the shifted output pattern is not compared with a specific prediction pattern.

The search data 2300 is repeatedly input into the scan path of the chip while changing the period of the shift frequency corresponding to Target_T until the maximum usable shift frequency of the target scan section 2310 is found. The test result using the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub test data 51 . Also, the test result using the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub test data 52 . The shift frequency when the test results of the input scan pattern 50 and the input scan pattern 51 are both normal is the usable shift frequency of the target scan section 2310 .

The search data 2300 is not limited to the example of FIG. 23 , and may further include two or more input scan patterns positioned before or after the target scan section.

24 is a conceptual diagram illustrating an example of test data including a plurality of scan patterns, and FIGS. 25 to 28 are a method of generating search data for finding an optimal shift frequency when a scan section is a part of a scan pattern. It is a conceptual diagram illustrating an example.

Referring to FIG. 24 , a single shift frequency (eg, T1 = 50 ns (ie, 20 MHz)) is assigned to all scan patterns in the test data 2400 . Therefore, all scan patterns are shifted in and out with the same shift frequency in the scan path of the IC chip.

The test data 2400 may include a plurality of sub test data including an input scan pattern and a prediction pattern as a pair. For example, the 51st input scan pattern is paired with the prediction pattern of the 50th input scan pattern.

The test data 2400 may be divided into a plurality of scan sections. For convenience of explanation, this embodiment shows a method of generating search data for finding the optimal shift frequency of each scan section when the input scan pattern 51 is divided into three scan sections 2410, 2420, and 2430 25 to 28 will be described.

25 to 27 , search data 2500 , 2600 , 2700 includes input scan patterns 51 including target scan sections 2510 , 2610 , and 2710 and input scan patterns 50 and 52 positioned before and after them. do. And the prediction pattern included in the sub test data 50 is the money care prediction pattern. That is, when the input scan pattern 50 is shifted in the scan path, the shifted output pattern is not compared with a specific prediction pattern. The timing information Target_T is used to identify the target scan sections 2510 , 2610 , and 2710 or to control a shift frequency of the target scan section. For example, Target_T may be increased or decreased by the test device in the initial 50n.

Referring to FIG. 25 , in the search data 2500 , timing information of Target_T is given to the first target scan section 2510 that is a part of the input scan pattern 51 , and the timing information of T1 is maintained in the remainder of the input scan pattern 51 . do. The search data 2500 is repeatedly input into the scan path of the chip while changing the period of the shift frequency corresponding to Target_T until the maximum usable shift frequency of the first target scan section 2510 is found. The test result using the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub test data 51 . Also, the test result using the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub test data 52 . The shift frequency when the test results using the input scan pattern 50 and the input scan pattern 51 are both normal is the usable shift frequency of the first target scan section.

When finding the optimal shift frequency of the second target scan section 2610 or the third target scan section 2710, the search data 2600 and 2700 of FIGS. 26 and 27, respectively, are repeatedly input to the chip in the same manner as in FIG. to scan test.

In order to find the optimal shift frequency of each scan section when one scan pattern is divided into a plurality of scan sections, data for search for each scan section (2500, 2600, 2700) is not created as shown in Figs. 25 to 27, in Fig. 28, one search data 2800 may be created.

Referring to FIG. 28 , the search data 2800 includes timing information Target_T1 , Target_T2 , and Target_T3 respectively in the first to third target scan sections 2810 , 2820 , and 2830 . In other words, timing identifiers as many as the number of target scan sections to be simultaneously searched for usable shift frequencies or optimal shift frequencies are created and allocated to each target scan section 2810 , 2820 , and 2830 . For example, when the usable shift frequency or the optimal shift frequency of the first target scan section 2810 is found, the shift frequency corresponding to Target_T1 may be increased or decreased.

When one search data 2800 for a plurality of target scan sections is generated as shown in FIG. 28, data for search 2800 is stored in comparison with FIGS. 25 to 27 that generate search data for each target scan section. storage capacity can be saved. For example, in order to find the optimal shift frequencies of the three target scan sections 2410, 2420, and 2430 of FIG. 24, as in the embodiments of FIGS. 25 to 27, data for searching for each target scan section is required, so three We need data for retrieval. However, according to the embodiment of FIG. 28 , only one search data 2800 is used, and thus, the following effects and advantages are obtained.

(1) The storage capacity of the storage medium can be saved.

(2) When each data for search 2800 is made into individual files, it is possible to reduce compilation time for converting all data files for search into files for use in a test device.

(3) When each data 2800 for search is made into an individual file, the number of data files for search is reduced, so that file management can be made easy and convenient.

However, when there is a restriction on the number of available timing identifiers or the number of frequencies of the test device, there may be a case where one search data 2800 for a plurality of target scan sections cannot be used as shown in FIG. 28 .

For example, if the maximum number of usable timing identifiers of the test device for shift frequency search target scan sections is limited to three, and the scan pattern is divided into four target scan sections, each The optimal shift frequency can be found by creating search data (2500, 2600, 2700) for each target scan section.

The search data 2500 , 2600 , 2700 , 2800 are not limited to FIGS. 25 to 28 , and may further include two or more input scan patterns positioned before or after the input scan pattern including the target scan section.

As the size of the search data used to find the usable shift frequency or optimal shift frequency of the scan pattern or scan section is as small as possible, the time required to find the shift frequency can be reduced. For example, the less the number of scan patterns or scan sections is used, the less time it takes to find a usable shift frequency or an optimal shift frequency.

To calculate the total number of shift clock cycles required to find the optimal shift frequency for all scan patterns of the test data, SN, BL, and FN are defined as follows.

SN: the number of scan patterns constituting the test data

BL: The bit length of one scan pattern, and one shift clock cycle is used to shift one bit.

FN: The number of times the shift frequency is increased to find the optimal shift frequency per scan pattern, and is sequentially increased at regular intervals from a preset low shift frequency to a preset high shift frequency.

In at least one embodiment of the present invention, it is assumed that SN = 5,000, BL = 1,000 and FN = 20. And, for the following methods 1 and 2, the total number of shift clock cycles required to find the optimal shift frequency for all scan patterns of the test data is calculated as follows.

Method 1

As shown in FIG. 22 , the number of total shift clock cycles required to find the optimal shift frequency of each scan pattern using search data including the entire input scan pattern is as follows:

Total Duration = SN x SN x BL x FN = 500,000,000,000 shift clock cycles

Method 2

As shown in FIG. 23, the number of total shift clock cycles required to find the optimal shift frequency of each input scan pattern using search data including three input scan patterns is as follows (in this case, the first scan pattern pattern When finding the optimal shift frequency of , the search data including the first and second two input scan patterns is used, and when finding the optimal shift frequency of the last input scan pattern, the last input scan pattern and the previous input scan pattern Data for retrieval containing two input scan patterns is used):

Total time required = (3 x (SN-2) x BL x FN) + (2 x 2 x BL x FN) = 299,960,000 shift clock cycles

In the above equation, (3 x (SN-2) x BL x FN) is each and every scan except the two scan patterns of the set of scan patterns (that is, the first input to the chip and the last one). Total number of shift clock cycles used to find the optimal shift frequency of the pattern.

In the above equation, (2 x 2 x BL x FN) is the total number of shift clock cycles used to find the optimal shift frequency of the scan pattern input first and the last scan pattern input to the chip.

It can be seen that by using method 2, 99.94% of the total number of shift clock cycles used in method 1 is reduced.

Accordingly, the search data used to find the usable shift frequency or optimal shift frequency of the scan pattern or scan section includes as few scan patterns or scan sections as possible.

In at least one embodiment of the present invention, as exemplified with reference to FIG. 18 , the search data includes at least two scan sections for which a shift frequency or optimal shift frequency is to be found and a scan pattern located before or after it. It may be composed of the above scan patterns.

Also, as in each example of FIGS. 19 to 28 , the search data may consist of at least three scan patterns including a scan section to find a shift frequency or an optimal shift frequency and scan patterns located before and after it. .

In at least one embodiment of the present invention, the search data used to find the usable shift frequency or the optimal shift frequency of the scan section may be stored in a computer-readable recording medium in the form of a data code or file. can

In addition, the step of generating data for searching used to find an available shift frequency or an optimal shift frequency of the scan section may be performed in the same device or in different devices, respectively, in a test device or a device such as a computer. may be performed.

29 is a flowchart illustrating an example of a method for minimizing scan test time according to the present invention.

Referring to FIG. 29 , the scan test time minimization apparatus divides a bit pattern or one or more scan patterns into at least two scan sections ( S2900 ). Various methods exist for dividing a bit pattern or a set of scan patterns of test data into scan sections, an example of which is shown in FIGS. 5 to 10 .

In the division step, the operation of creating a file containing the search data for a scan section or section group that is divided into thousands or tens of thousands of scan patterns for testing the IC chip or a file containing these data is performed using a computer program or software. Batch processing can be efficient.

For example, the computer program or software may use information related to the division of scan sections, such as the number of scan sections for which the shift frequency is to be optimized, the bit length of the scan sections, and the location of the scan sections, to convert the test data into scan sections or groups of scan sections. By dividing, you can batch create files containing data for searching or data for searching for a divided scan section or group of scan sections.

Information pertaining to segmentation of scan sections may be obtained through user interface devices such as keyboards, mice, speech recognition devices, or information data codes or files containing information pertaining to segmentation of scan sections, or data communication networks, etc. can be used by

As an example of division of the scan pattern, the method shown in FIGS. 5 to 10 may be used. The scan test time minimization apparatus allocates a plurality of shift frequencies to each scan section (S2910). Here, the shift frequency assigned to each scan section is equal to or less than the shift frequency before the output pattern of the scan path is different from the predicted pattern. The division of the scan pattern into scan sections (S2900) and the assignment of the scan section of the shift frequency (S2910) may be performed in the same device or in different devices, respectively, or may be performed in a device such as a test device or a computer. there is.

That is, the scan test time minimization apparatus may find the shift frequency just before the output pattern and the prediction pattern change as the shift frequency increases as the maximum shift frequency allocable to the scan section. As another example, the scan test time minimization apparatus may find a shift frequency when the output pattern and the predicted pattern are different from each other and become the same as the shift frequency is reduced as the maximum shift frequency allocable to the corresponding scan section. For example, while increasing or decreasing the shift frequency of the scan section, it is possible to find a test normal shift frequency while approaching the boundary between scan test normal and fail, and find a test normal shift frequency as the maximum shift frequency allocable to the scan section.

30 is a flowchart illustrating another example of a method of determining an optimal shift frequency for each scan section in order to minimize a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 30 , the scan test time minimization apparatus divides one or more scan patterns into at least two or more scan sections ( S3000 ).

The scan test time minimization apparatus increases or decreases the frequency at which the scan section is shifted in the scan path, and finds a shift frequency when the output pattern is different from the same predicted pattern or the same when the predicted pattern is different (S3010). For example, as a chip used to find an optimal shift frequency, a chip that has been tested as a good product in advance may be used. For example, an optimal shift frequency is searched for according to the present embodiment by using a non-defective chip in which a scan test result using a nominal shift frequency shows that the test is normal. It may be the same in other embodiments below.

In addition, the scan test time minimization apparatus determines the shift frequency that is normal for the test before the time when the output pattern and the predicted pattern are the same but different from each other as the shift frequency of the corresponding scan section (S3020). The previous shift frequency also includes a shift frequency smaller than the time point at which it is different.

For example, if the output pattern and the prediction pattern are the same at the first shift frequency, but the output pattern and the prediction pattern of the scan path are different at the second shift frequency, the first shift frequency is increased by a certain amount, the scan test time minimizing device is 2 It is possible to determine or provide information capable of determining a shift frequency that is smaller than the shift frequency and that is normal for testing as the shift frequency of the scan section.

In order to find the optimal shift frequency, the increase/decrease size may be preset in the test device, or the increase/decrease size may be changed or set by the user.

Although this embodiment describes a method of finding the optimal shift frequency for each scan section through increase or decrease of the shift frequency to be shifted in for convenience of explanation, it is possible to find the optimal shift frequency while increasing or decreasing the shifting frequency according to the embodiment there is. The same applies to the following examples.

Each of the steps described with reference to FIG. 30 is not all performed in the scan test time minimization apparatus according to an embodiment, but at least a part thereof may be performed in other apparatuses such as a computer.

31 is a flowchart illustrating a more detailed process of a method for minimizing a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 31 , the scan test time minimization apparatus divides one or more scan patterns into a plurality of scan sections ( S3100 ).

The scan test time minimization apparatus selects one scan section in which the shift frequency is not determined according to the present embodiment among the scan sections (S3110). For example, if a predetermined order is determined between scan patterns for a scan test, the scan test time minimization apparatus may sequentially select the scan test section from the first scan section. Alternatively, the user may select a scan section for which the shift frequency is to be optimized, and the scan test time minimization apparatus may perform shift frequency optimization on the selected scan section. In addition, there may be various methods of selecting a scan section for which the shift frequency is to be optimized.

The scan test time minimization apparatus increases the shift frequency (S3120). For example, the initial shift frequency in the scan test time minimization apparatus may be variously set to a nominal shift frequency or the like.

The scan test time minimization apparatus determines whether it is possible to normally shift the scan section into the scan path at the increased or decreased shift frequency starting from the initial shift frequency at which the scan test result appears normally (S3130). An example of a specific method of determining whether the selected shift frequency determination target scan section can be normally shifted in to the current shift frequency will be described with reference to FIG. 32 .

If a normal shift-in of the scan section is possible (S3140), the scan test time minimization apparatus increases the shift frequency again (S3120) and repeats the process of determining whether a normal shift-in is possible (S3130).

When the normal shift-in of the scan section occurs due to the increase of the shift frequency (S3140), the scan test time minimization device determines or can determine the maximum shift frequency or less with the normal shift-in as the shift frequency of the scan section. Information may be stored in a computer-readable recording medium (S3150). The above process is repeated until shift frequencies for all scan sections are determined or information for determining shift frequencies is stored in a computer-readable recording medium (S3160). Here, as an example of the information stored in the recording medium, it may be information about shift for each shift frequency or test normality or failure with respect to the IC chip under test.

The scan test time minimization apparatus may group scan sections into section groups as needed (S3170). For example, if the test device performing the actual scan test has constraints such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required to change the shift frequency, minimize the scan test time The device may group scan sections so that the number of scan sections satisfies the above constraint, and in this case, it may be considered so that the total scan test time can be minimized. In this case, the lowest shift frequency or less among the optimal shift frequencies of at least two scan sections included in one scan section group may be determined as the shift frequency of the corresponding section group. The process of grouping the sections ( S3170 ) may be omitted in some embodiments.

For example, if the maximum number of shift frequency changes supported by the test device is 5, the scan test time minimization device divides the scan sections into 5 or less section groups if the number of current scan sections exceeds 5, and each section group Among the optimal shift frequencies of my section, the lowest optimal shift frequency or less may be determined as the shift frequency of the corresponding section group. As a method of grouping into section groups, there may be various methods in which the total scan test time can be minimized, such as a method of grouping scan sections having the same or similar optimal shift frequency.

The embodiments discussed so far have mainly been a process of finding an optimal shift frequency by considering only an increase in the shift frequency. As another example, the optimal shift frequency of the corresponding scan section may be found while the shift frequency is decreased.

For example, the scan test time minimization apparatus may determine whether it is possible to normally shift the scan section into the scan path at the reduced shift frequency starting from an initial shift frequency that is a test failure. When a normal shift-in of the scan section occurs due to a decrease in the shift frequency, the scan test time minimization device determines the shift frequency below the maximum shift frequency with normal shift-in as the shift frequency of the scan section, or transmits information that can be determined to the computer. can be stored on a readable recording medium.

As another example, since the chip is also affected by the supply voltage or ambient temperature, the optimal shift frequency can be found by reflecting these environmental conditions. That is, the scan test time minimization apparatus may perform a process of finding an optimal shift frequency while changing conditions such as a supply voltage or an external temperature.

For example, the scan test time minimization apparatus may increase or decrease the voltage supplied to the chip in consideration of the specifications of the chip or quality-related policies such as quality assurance (QA) and quality control (QC) (S3120). In addition, the scan test time minimization apparatus finds an optimal shift frequency for each scan section according to an embodiment of the present invention from each increased or decreased supply voltage. If there are a plurality of optimal shift frequencies found for each supply voltage of the selected scan section, the scan test time minimization apparatus may determine the lowest optimal shift frequency or less as the shift frequency of the selected scan section ( S3150 ). In addition, the process of finding the optimal shift frequency for each temperature increase or decrease or other various conditions is repeated, and the lowest optimal shift frequency or less among them may be determined as the shift frequency of the corresponding scan section.

In this case, identifying characteristics such as an operating frequency range of the IC chip while changing the supply voltage or ambient temperature of the IC chip is generally referred to as electrical testing or shmooing. Making a diagram of characteristic information by performing electrical characteristic testing or shmooing is called shmoo plotting. The plot may be called a shmoo plot.

Each step of FIG. 31 may be performed not only by the scan test time minimization device but also by other devices such as a computer.

32 is a flowchart illustrating an example of a detailed process for determining a normal shift-in in a method for minimizing a scan test time according to at least one embodiment of the present invention. That is, FIG. 32 may correspond to step S3130 of FIG. 31 , but is not limited to the specific step of FIG. 31 , and may be applied to various embodiments including a process of determining or determining whether a shift-in is normally performed in a scan path.

12 and 32 together, the scan test time minimization apparatus shifts the input pattern K-1 1202 located in front of the target scan section K 1204 to be determined the currently selected shift frequency to the scan path 1210. do (S3200). For example, the input pattern K-1 1202 is located in front of the scan pattern M including the target scan section K 1204, and there may be examples of (1) or (2) as follows.

(1) When the input pattern K-1 (1202) is the scan pattern used for the actual scan test

The scan test time minimization apparatus shifts the scan pattern M-1 to the scan path and performs a scan capture process. In this case, there is an advantage in that the actual scan test operation can be reflected. Here, the scan pattern M-1 is a pattern located in front of the scan pattern M including the target scan section K.

(2) When the scan pattern M-1 is an output pattern predicted as a scan test result using the scan pattern M-1 used for the actual scan test

The scan test time minimization device eliminates the need to perform a separate scan capture process after shifting the scan pattern M-1 to the scan path. Accordingly, in this case, the time required for the clock for scan capture can be reduced, and thus the time required for finding the optimal shift frequency can be reduced.

The scan test time minimization apparatus performs a scan capture operation after shifting the input pattern K-1 1202 to the scan path (S3200). In another embodiment, the scan capture operation may not be performed. Then, the scan test time minimization apparatus shifts the target scan section K 1204 into the scan path with the increased or decreased shift frequency (S3210). If the target scan section K 1204 is a part of the scan pattern M as shown in FIG. 14 , the scan pattern M including the target scan section K 1204 is shifted into the scan path.

At this time, while the target scan section K 1204 or the scan pattern M including the target scan section K 1204 is shifted into the scan path, the bit patterns stored on the scan path are simultaneously shifted out (S3210). Here, the bit pattern to be shifted out is not limited to the above example, and may vary depending on the type of scan circuit capable of simultaneously performing shift-in and shift-out operations on a scan path.

For example, when the target scan section K 1204 is shorter than the length of the scan path as a part of the scan pattern M as shown in FIG. 14 , the scan pattern M including the target scan section K 1204 is shifted into the scan path. . At this time, the shift frequency of the remaining part of the scan pattern M except for the determined target scan section K 1204 is not limited in finding the optimal shift frequency of the target scan section K 1204 . To this end, in the scan pattern M, the shift frequency of the remaining parts except for the part of the target scan section K (1204) is not increased or decreased together with the shift frequency of the target scan section K (1204), or a frequency different from that of the target scan section K (1204) is selected. can be used Alternatively, the shift frequency of the remaining portions except for the target scan section K 1204 in the scan pattern M may use a shift frequency capable of normally inputting the remaining portions except for the target scan section K 1204 into the scan path.

In at least one embodiment of the present invention, the shift frequency of a portion other than the target scan section K 1204 is less than or equal to the nominal shift frequency, or when the optimal shift frequency has already been determined through the method according to an embodiment of the present invention, corresponding to A preset shift frequency such as less than or equal to the optimal shift frequency may be used. The preset shift frequency may be variously changed according to embodiments, such as a value obtained by adjusting the nominal shift frequency, a value set in the device by a program, or a value set by a user, and is not necessarily limited to the above example.

The scan test time minimization apparatus compares whether the output pattern K-1 of the input pattern K-1 of the test target chip and the prediction pattern K-1 are the same (S3220). If the output pattern K-1 and the predicted pattern K-1 are not the same (S3220), the scan test time minimization device determines or determines that the target scan section K 1204 cannot be normally shifted into the scan path with the current shift frequency. do (S3270). For example, the scan test time minimization apparatus may store test failure information in a computer-readable recording medium.

If the output pattern K-1 of the input pattern K-1 and the prediction pattern K-1 are the same (S3220), the scan test time minimization apparatus performs a scan capture (S3230) operation on the target scan section K 1204, and then A shift-out (S3240) operation is performed. In another embodiment, the shift-out (S3240) operation may be performed without performing the scan capture (S3230) operation. In addition, the bit pattern shifted out ( S3240 ) may vary according to the type of scan circuit in which shift-in and shift-out operations can be simultaneously performed on the scan path.

When the output pattern for the target scan section K 1204 is shifted out (S3240), the bit pattern of the target scan section K 1204 shifted out (S3240) is intended for the input pattern K+1 (1206) shifted in at the same time A shift frequency that does not change inadvertently is used. That is, a shift frequency at which the shift-out (S3240) operation can be normally performed is used. In addition, the input pattern K+1 (1206) that is shifted in simultaneously when the shift-out (S3240) operation of the target scan section K 1204 is performed uses a shift frequency that can be normally shifted in the scan path.

The scan test time minimization apparatus compares whether the output pattern K of the target scan section K 1204 of the chip under test is the same as the predicted pattern K ( S3250 ). If the output pattern K of the target scan section K 1204 and the predicted pattern K are not the same (S3250), the scan test time minimization device normally shifts the target scan section K 1204 to the scan path with the currently used shift frequency. It is determined or determined that it cannot be done (S3270). For example, the scan test time minimization apparatus may store test failure information in a computer-readable recording medium.

If the output pattern K of the target scan pattern K 1204 and the predicted pattern K are the same (S3250), the scan test time minimization device can normally shift the target scan section K 1204 into the scan path with the currently used shift frequency. It is determined or determined that there is (S3260). For example, the scan test time minimization apparatus may store test normal information in a computer-readable recording medium.

In at least one embodiment of the present invention, the output pattern of the chip for the scan pattern preceding it, as well as the scan pattern comprising the target scan section K 1204, is also compared to the predicted pattern of the target scan section K 1204. You can find an available shift frequency or an optimal shift frequency.

In at least one embodiment of the present invention, the test apparatus determines or determines whether the scan test results for the target scan section K 1204 and the input pattern K-1 1202 positioned before it are both normal. And if all tests are OK, the shift frequency used for the target scan section K 1204 is a possible shift frequency that normally shifts the target scan section K 1204 into the scan path.

33 is a flowchart illustrating another example of a method for minimizing a scan test time according to at least one embodiment of the present invention.

Depending on the type and state of the chip manufacturing process, there may be process variations between IC chips on different wafers or between IC chips on the same wafer, which greatly affects the operating frequency and power consumption of the IC chip. can go crazy In particular, it has a greater impact on micro-processing and low-power processes.

Referring to FIG. 33 , the scan test time minimization apparatus performs a process of determining an optimal frequency for each salpin scan section for a plurality of chips (S3300). Here, the plurality of chips may be IC chips on the same wafer or IC chips on different wafers, and may be chips that have been tested as good products in advance.

The scan test time minimization device may determine the lowest shift frequency or less among a plurality of optimal shift frequencies identified through a plurality of IC chips for a scan section as the optimal shift frequency of the scan section, or may determine the shift frequency. information can be stored in a computer-readable recording medium (S3310), and this can be performed for each scan section. Here, as an example of the information stored in the recording medium, it may be information about the pass or fail of a shift or test for each shift frequency.

For example, it is assumed that the shift frequency of the target scan section K of the first chip is A, and the shift frequency of the target scan section K of the second chip is B. If the shift frequency A is smaller than the shift frequency B, the test apparatus may select A or less as the shift frequency of the target scan section K, or may store selectable information in a computer-readable recording medium.

Each step of FIG. 33 may be performed by not only the scan test time minimization device but also other devices such as a computer using the scan pattern set and shift frequency information identified for each scan section for a plurality of chips.

34 is a block diagram illustrating a configuration of an apparatus for minimizing scan test time according to at least one embodiment of the present invention.

The scan test time minimization apparatus of FIG. 34 may perform the method of the present invention described above for optimizing the shift frequency of each scan section, and in at least one embodiment of the present invention, a part of the method of FIGS. 12 to 33 or The whole can be applied.

Referring to FIG. 34 , the scan test time minimization apparatus includes a condition setting unit 3400 , a pattern dividing unit 3405 , a pattern input unit 3410 , a pattern comparing unit 3420 , and a frequency determining unit 3430 . The condition setting unit 3400 includes a frequency increase/decrease unit 3402 , a supply voltage increase/decrease unit 3404 , a temperature increase/decrease unit 3406 , and the like.

First, the condition setting unit 3400 sets various conditions for finding the optimal shift frequency for each scan section. Specifically, the frequency increase/decrease unit 3402 increases or decreases the shift frequency, the supply voltage increase/decrease unit 3404 increases or decreases the voltage supplied to the chip, and the temperature increase/decrease unit 3406 increases or decreases the ambient temperature of the test environment. The condition setting unit 3400 may increase or decrease the shift frequency while setting conditions such as supply voltage and ambient temperature. For example, the condition setting unit 3400 may be provided in the host computer 200 or 300 , the tester body 210 or 310 , the test heads 220 or 320 , or the prober 350 .

The pattern dividing unit 3405 may divide one or more scan patterns into a plurality of scan sections. For example, the pattern dividing unit 3405 may be provided in the host computers 200 and 300 , the tester bodies 210 and 310 , the test heads 220 and 320 , or the prober 350 . The pattern divider 3405 may divide the test data into at least one scan section using the method illustrated in FIGS. 5 to 10 .

The pattern input unit 3410 shifts the scan section into the scan path of the test target chip under the condition set by the condition setting unit 3400 . More specifically, the pattern input unit 3410 may sequentially shift a scan pattern or a scan section positioned before and after a scan section to find an optimal scan shift frequency into a scan path together with a scan section to be determined with a shift frequency. . For example, the pattern input unit 3410 may be provided in the host computer 200 or 300 , the tester body 210 or 310 , the test heads 220 or 320 , or the prober 350 .

The pattern comparator 3420 compares whether the output pattern shifted out of the scan section shifted in to the test target chip by the pattern input unit 3410 is the same as the predicted pattern. For example, the pattern comparator 3420 may be provided in the host computer 200 or 300 , the tester body 210 or 310 , the test heads 220 or 320 , or the prober 350 . According to the increase or decrease of the shift frequency by the condition setting unit 3400 , there may be a time point or frequency in which the output pattern and the prediction pattern are the same and then become different or become the same after being different.

The frequency determining unit 3430 reads the shift frequency information for finding the same shift frequency or the shift frequency before the output pattern is different from the predicted pattern using the comparison result information or the comparison result by the pattern comparison unit 3420 with a computer. It can be stored in a recordable medium. For example, shift frequency information normally usable for the scan section may be stored in a computer-readable recording medium. Also, an optimal shift frequency of the scan section may be determined using the information.

In at least one embodiment of the present invention, the frequency determiner 3430 determines the shift frequency when both the scan section positioned before the current shift frequency determination target scan section and the output pattern for the determination target scan section are the same as the prediction pattern It can be stored in a computer-readable recording medium as usable shift frequency information of the scan section. In addition, in FIG. 34 , each of two or more units may be integrated into one module or further subdivided. For example, the frequency determiner 2030 may be provided in the host computers 200 and 300 , the tester bodies 210 and 310 , the test heads 220 and 320 , or the prober 350 .

The apparatus for minimizing the salpin scan test time may be implemented in various forms using hardware or software. In addition, all or part of the scan test time minimization apparatus may be implemented in the salpin test apparatus in FIGS. 2 and 3 , or may be implemented using a separate apparatus such as a computer.

35 is a conceptual diagram illustrating an example of a method of finding or determining optimal shift frequencies of a plurality of scan sections in parallel.

Referring to FIG. 35 , the scan test time minimization apparatus takes to find or determine the optimal shift frequency for each of a plurality of IC chips by finding or determining the optimal shift frequency of different scan sections together in parallel time can be reduced.

For example, for each of the plurality of IC chips 3510 , 3512 , 3514 , and 3516 located on the test interface board 3500 of the test device, optimal shift frequencies of different scan sections may be found or determined together. In at least one embodiment of the present invention, optimal shift frequencies of different scan sections in each of a plurality of test devices or a plurality of test interface boards may be found or determined in parallel.

If it takes h time to find or determine the optimal shift frequency one by one for the entire scan section sequentially, it takes about h/n time to find or determine the shift frequency in parallel for n scan sections. This can be reduced. Therefore, it may be possible to optimize by dividing thousands to tens of thousands of scan patterns for testing an IC chip into shorter scan sections within the same time period.

36 is a conceptual diagram illustrating an example of a scan pattern rearrangement method for minimizing a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 36 , the scan patterns on the scan pattern set for the scan test have a predetermined order. However, the order of these scan patterns is not fixed, but may be rearranged in order to reduce the overall scan test time by allocating a high shift frequency to each scan section. For example, as shown in FIG. 36 , the order of the second scan pattern and the third scan pattern on the original scan pattern set may be changed. Accordingly, the order of the prediction output scan patterns is also changed.

When the order of shifted scan patterns in the scan path is rearranged, the switched portion of the circuit and the number of switching operations on the IC chip may be changed by the scan shift, and thus power consumption may also be changed, so the scan pattern (or scan The shift frequency that can be allocated to the section) may be increased. Therefore, by using this property, the optimal shift frequency for each scan section can be found or determined by using the embodiment of the present invention previously examined after relocating the scan pattern, thereby further reducing the overall scan test time.

As a relocation method of scan patterns, scan patterns on the original scan pattern set are arbitrarily rearranged one or more times, and the optimal shift frequency is identified for each rearranged scan pattern set according to the above-described embodiment, thereby reducing the scan test time. What is required can be determined by the arrangement of the scan pattern. As another embodiment, there are various methods, such as disposing scan patterns having the smallest bit pattern difference between scan patterns adjacent to each other.

As another example of scan pattern rearrangement, it is possible to have the highest shift frequency by using the method of finding the optimal shift frequency salpinned above while sequentially locating scan patterns whose order is not determined after the K (an integer greater than or equal to 1)-th scan pattern. A possible scan pattern may be determined as the next pattern of the K-th scan pattern.

Part or all of the operation of rearranging the order of the scan patterns may be performed by hardware, firmware, or software such as a processor provided in the test apparatus, or may be performed in another apparatus such as a computer.

Also, when it may take a lot of time to find the optimal scan pattern arrangement, there may be restrictions such as the maximum number of scan pattern rearrangement attempts or the required time to find the optimal scan pattern arrangement.

In addition, in at least one embodiment of the present invention, the stress test or burn-in test time of the IC chip may be reduced or the test quality may be improved by using the optimal frequency of at least two or more respective test data. In at least one embodiment of the present invention, it is possible to reduce the stress test or burn-in test time of the IC chip or increase the test quality by using the optimal shift frequency for at least two or more respective scan patterns or scan sections. there is. An optimal shift frequency for each scan pattern or scan section may be found by the method of minimizing scan test time according to at least one embodiment of the present invention.

Here, the stress test or burn-in test generally refers to testing the quality of an IC chip by operating the IC chip for a long time to stress the IC chip, or by applying high voltage and high temperature to the IC chip to accelerate aging. -life failure) to discover the IC chip. Burn-in tests for tens of hours or more in high-temperature environments, typically over 100. Hereinafter, the stress test or the burn-in test is collectively referred to as a burn-in test. Also, a test device capable of performing such a burn-in test is called a burn-in test device.

The aging of the IC chip is greatly affected by heat generation, and the heat generation is greatly affected by the power consumption of the IC chip.

For example, Equation 2 below shows the main factors affecting dynamic power dissipation, which is power consumption when the circuit of the IC chip operates.

a: activity factor

C: average switched capacitance (at each cycle)

f: circuit frequency

V _DD : supply voltage

In the scan mode of the IC chip, the activated circuit portion of the IC chip may vary according to the bit pattern of the scan pattern. In general, switching activities occur in more parts of a circuit in a scan mode of an IC chip than in a functional mode. Therefore, in the scan mode, as shown in Equation 2, the average switched capacitance value C increases, so that power consumption P may increase.

Also, as the shift frequency increases, as shown in Equation 2, power consumption P of the IC chip may increase in proportion to the operating frequency f of the IC chip circuit.

The increased switching operation of the IC chip further increases power consumption of the IC chip, so that the heat generation temperature of the IC chip is also increased. Therefore, the aging of the IC chip can be further accelerated.

In at least one embodiment of the present invention, the burn-in test apparatus may use the maximum shift frequency allocable to each test data or each scan section previously salvaged so as to further accelerate aging during the burn-in test to reduce the burn-in test time.

For example, a burn-in test device may use a scan pattern or scan section during burn-in testing of an IC chip to accelerate burn-in testing. In this case, a scan test may also be performed.

In addition, if the nominal shift frequency is used during the scan shift operation, high stress may be applied to some of the circuit parts activated by the scan pattern and relatively low stress may be applied to other parts of the circuit. However, as an example, by dividing the scan patterns of the test data into scan sections, and performing a burn-in test using the maximum shift frequency that can be assigned to each divided scan section, aging of only a specific part of the circuit is accelerated or aging is relatively slow progress can be reduced.

For example, FIG. 41 shows the same scan shift operation in the case where the shift frequency is not optimized for the scan patterns of the test data ( 4100 ) and when the shift frequency is optimized by dividing the scan patterns into scan sections ( 4110 ). It shows the difference in heat generation of the IC chip. That is, it can be seen that the case of using the scan section with the optimized shift frequency ( 4110 ) generates more evenly high heat generation than the case of using the test data whose shift frequency is not optimized ( 4100 ).

That is, it is possible to improve not only the speed of the burn-in test but also the quality by applying the maximum amount of stress in a more balanced way to the different parts of the IC chip activated by the bit pattern of the scan pattern. The maximum usable frequency of each scan section of the test data to test the chip can be used to reduce burn-in test time or improve quality.

37 and 38 are block diagrams illustrating the configuration of a burn-in test apparatus according to at least one embodiment of the present invention.

37 and 38 , the burn-in test apparatus includes host computers 3700 and 3800 , tester bodies 3710 and 3810 , test heads 3720 and 3820 , interface boards 3730 and 3830 , and a temperature controller 3760 , 3870 ), chambers 3750 and 3860 , and a prober 3850 .

A device under test (DUT) positioned on the interface board for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it may further include a prober.

The tester body 3710 and 3810 may control the scan test and the burn-in test as a whole. For example, the tester body controls overall processes such as setup for DUT testing, generation of electrical signals for DUT testing, observation and measurement of DUT test result signals, and temperature control of a chamber through a temperature controller. The tester body may be implemented as a computer including a central processing unit (CPU), memory, a hard disk, a user interface, and the like. According to an embodiment, a device power supply for supplying power to the DUT may be further included. In addition, the tester body controls a signal processing processor (DSP, Digital Signal Processor) (not shown) that processes various digital signals and a test head, and a controller that applies signals to the DUTs (3740, 3840) and a signal generator, etc. It may include hardware, software or firmware and the like. The tester body is also called mainframe or server.

The host computers 3700 and 3800 may be computers such as personal computers and workstations, and are devices that allow a user to execute a test program, control a test process, and analyze test results. In general, the host computer may include a central processing unit, a storage device such as a memory or hard disk, a user interface, and the like, and may be connected to the tester body through wired or wireless communication. The host computer may include dedicated hardware, software, firmware, etc. for controlling the test. Although the present embodiment shows the host computer and the tester body separately, the host computer and the tester body may be implemented as a single device.

As an example of the memory of the tester body or the host computer, DRAM, SRAM, flash memory, etc. may be used, and a program and data for performing a DUT test may be stored in the memory.

Software or firmware of the tester body or host computer is a device driver program for burn-in or scan test, an operating system (OS) program, and a program for performing DUT tests. The program, for example, is stored in the memory in the form of an instruction code for performing setup for DUT test, generation of a signal for DUT test, observation analysis of the DUT test result signal, etc., and is executed by the central processing unit can be Therefore, the scan test pattern can be applied to the DUT by such a program. In addition, reporting and analysis data for DUT tests and test results can be obtained by automatically performing through the program. As a language used for the program, various languages such as C, C++, and Java may be used. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The tester main body or the central processing unit of the host computer is a processor, and executes the code of the software or program stored in the memory. For example, when a user command is received through a user interface such as a keyboard or mouse, the central processing unit analyzes the user's command, executes it through software or a program, and displays the result through a user interface such as a speaker, printer, monitor, etc. provided to users through

The user interface of the tester body or host computer allows the exchange of information and the transfer of commands between the user and the device. For example, there are an interface device for user input such as a keyboard, a touch screen, a mouse, and a voice recognition device, and an output interface device such as a speaker, a printer, and a monitor.

The test heads 3720 and 3820 include channels for transmitting electrical signals between the tester body and the DUT. An interface board is provided above the test head. In general, an interface board used for testing a packaged IC chip is called a load board, and an interface board used for testing an IC chip on a wafer is called a probe card.

Chambers 3750 and 3860 are spaces for aging the DUT. The chamber controls the temperature of the DUT located in the chamber according to the control of the temperature controller. In addition, the temperature control unit may be included in the tester body or the host computer. The tester body or host computer can also control the burn-in test time or supply voltage to the DUT.

The burn-in test apparatus of FIGS. 37 and 38 is only one example to help the understanding of the present invention, and each configuration can be integrated and implemented as an integrated body, or one configuration can be implemented by separating it into a plurality of configurations. Various design changes are possible according to

In addition, the embodiment shown in FIGS. 37 and 38 may be implemented to simultaneously perform the burn-in test and the scan test, or to perform only one of them.

In at least one embodiment of the present invention, the burn-in test apparatus may perform the burn-in test using an optimal shift frequency for each scan section as described above. In at least one embodiment of the present invention, at this time, a test for determining whether the chip is normal may also be performed.

In at least one embodiment of the present invention, the burn-in test apparatus may perform the burn-in test together with the scan test using an optimal shift frequency for each scan pattern or scan section as described above. In the IC chip, since more switching operations occur in the IC chip circuit part in the scan mode than in the functional mode, it is possible to further accelerate the aging process by performing the scan test, thereby saving burn-in test time. In addition, if the burn-in test is performed using the maximum shift frequency that can be assigned to each divided scan section, the burn-in test time can be further reduced, and the aging of only a specific part of the circuit due to a specific scan pattern can be reduced. . That is, there is an effect that the quality of burn-in test can be improved by applying stress as much as possible in a balanced overall manner to the IC chip, and the effect can be increased as the length of the scan section using the optimized shift frequency is reduced.

In addition, the present invention is not limited to the case of simultaneously performing the scan test and the burn-in test, and only includes a process of shifting the scan pattern during the burn-in test and may not perform the scan test itself.

39 is a conceptual diagram illustrating an example of the effect of temperature on an IC chip when a burn-in test is performed using a single scan shift frequency according to at least one embodiment of the present invention.

Referring to FIG. 39 , all of the plurality of scan patterns are shifted in the scan path of the IC chip 3900 using the same scan shift frequency (eg, 25 MHz). A main part in which the IC chip is activated by each scan pattern may be different. For example, the main part 3910 of the IC chip activated by the scan pattern 1 3930 and the main part 3920 of the IC chip activated by the scan pattern 2 3932 may be different from each other.

In addition, the heat generated in the portion activated on the IC chip by each scan pattern may be different depending on the scan shift frequency or the number of times of circuit switching according to the scan pattern. For example, the temperature of the main part 3910 of the IC chip activated by the scan pattern 1 may be a°C, and the temperature of the main part 3920 of the IC chip activated by the scan pattern 2 may be b°C.

The shift frequency can be increased to accelerate the aging of burn-in tests by generating more stress or heat to the IC chip. However, if the shift frequency is excessively increased, an overkill problem of determining a normal IC chip as a defective product may occur. Conversely, when the shift frequency is lowered, there is a problem in that the aging of the burn-in test cannot be efficiently accelerated due to insufficient stress or heat generated in the IC chip.

40 is a conceptual diagram illustrating an example of the effect of temperature on an IC chip when a burn-in test is performed using an optimal frequency for each scan pattern according to at least one embodiment of the present invention. 39 and 40 are examples of using the same IC chip and the same scan pattern.

Referring to FIG. 40 , aging of the IC chip can be accelerated by shifting the scan path using the optimal shift frequency for each scan pattern.

Since the burn-in test is generally performed for several tens of hours or more in a high temperature environment of over 100°C, the time and power consumption during the burn-in test increases the test cost. In other words, since IC chip test service companies generally charge a cost in proportion to the test time, the time required for the chip test has a great impact on the chip cost. In addition, the high temperature over 100°C formed in the chamber used for burn-in testing is generally made using electricity, and the cost for this is also significant, and can have a significant impact on the cost of the test service company and the cost of the chip.

Therefore, reducing the burn-in test time and power consumed by the burn-in test is very important in reducing test cost. Reducing burn-in test time can also be critical to a product's time-to-market.

For example, when the maximum possible scan shift frequency of the scan pattern 1 3930 of FIG. 39 is 25 MHz and the shift frequency of the scan pattern 2 3932 can be higher, the scan pattern 2 4032 of FIG. By optimizing and raising the shift frequency, the aging of the IC chip can be further accelerated by the temperature (c°C) higher than the temperature (b°C) in FIG. 39 .

39 and 40 describe a case in which a shift frequency is allocated to a scan pattern to shift a scan path for convenience of explanation. You can shift the scan path by frequency.

Also, for example, the junction temperature of the chip under test needs to be maintained within a certain range so that the burn-in test time or burn-in test quality can be predicted. For example, the junction temperature of the device under test or the IC chip may be determined by the relation shown in Equation 3.

Here, T _j is the junction temperature of the device under test or IC chip, Ta _is the ambient temperature, P is the power consumption of the device or IC chip under test, and θ _ja is the heat of the device or IC chip under test. resistance respectively.

Referring to Equation 3, the controllability of T _j is dependent on the controllability of T _a and P . For example, Ta may be controlled to an appropriate temperature using _a chamber or a thermal chuck that controls the temperature of the external environment of the device under test or the IC chip. Therefore, there is a need for a method for controlling the power consumption P during burn-in testing of a chip. For example, fluctuations in power consumption during burn-in testing of a chip can significantly affect the junction temperature T _j of the chip and adversely affect the reliability screening process of the chip. there is.

The time required for the burn-in test may be predicted based on the median value of the junction temperature T _j in Equation 3 . For example, the junction temperature may be determined by the value of the power consumption P _burn-in of FIG. 42 . P _burn - _in may be a median value or an average value of power consumption by test data, or a power consumption value predicted during a good quality burn-in test.

42 is a graph illustrating an example of power consumption occurring during a burn-in test before power consumption of test data is adjusted, and FIG. 43 is an example of power consumption occurring during a burn-in test after power consumption of test data is adjusted. This is the graph shown.

Referring to FIG. 42 , when power consumption is higher than P _burn - _in or P _{margin - high} to which the margin is reflected, an over burn-in state may occur. This can adversely affect the yield of the chip.

If the power consumption is lower than P _burn - _in or P _{margin - low} reflecting the margin, an under burn-in condition may occur. This can create a situation where a potentially defective chip passes through the test process.

Therefore, power consumption by the test data needs to be close to P _burn - _in as shown in FIG. 43 in order to accurately predict the burn-in time and burn-in quality. That is, it is necessary to minimize the variation in the heat generation of the IC chip by making sure that the variation in power consumption due to the test data is not large.

An embodiment of a method of reducing or predicting burn-in time by optimizing power consumption during a burn-in test and improving burn-in quality is as follows.

Step 1

The test data is divided into at least two sub data. For example, as shown in FIG. 43 , the test data may be divided into three sub data based on the test time axis.

Step 2

A shift frequency used to input each sub data into a chip is found or determined so that a difference in power consumption of at least two or more sub data divided in step 1 is minimized. Alternatively, a frequency used to input each sub data into the chip is found or determined so that the power consumption by each sub data is close to or equal to the predicted power consumption (or predicted current consumption) for the burn-in test. For example, as shown in FIG. 43 , by adjusting the frequency of each sub data, power consumption by the test data may be close to P _burn - _in .

Step 3

For each sub data, a burn-in test is performed using the frequency found or determined in step 2. For example, as shown in FIG. 43 , the burn-in test may be performed so that the power consumption of each sub data section is close to P _burn - _in .

The sub data of steps 1 to 3 is a scan section or functional test data (data used for testing on the function of a chip).

Each of steps 1 to 3 may be performed in the same device or in different devices, for example, in a device such as a test device or a computer, depending on the embodiment.

As another embodiment, another method of reducing or predicting burn-in time by optimizing power consumption during a burn-in test and improving burn-in quality is as follows.

Step 1

The test data is divided into at least two sub data.

Step 2

For each sub data, find or determine the maximum shift frequency at which the test result of a normal chip appears normal. For example, the maximum shift frequency may be a frequency optimized to minimize a test time or a frequency in which a margin is reflected in the maximum shift frequency.

Step 3

In step 2, power consumption or current consumption is measured or estimated using the maximum shift frequency found or determined for each sub data.

Step 4

In step 3, we find sub data in which the measured or estimated power consumption or current consumption is greater than the power consumption criterion for the optimal burn-in test. For example, the criterion of power consumption for the optimal burn-in test may be P _burn - _in or P _margin-high in FIG. 42 or FIG. 43 .

Step 5

By lowering the frequency of the sub data found in step 4, the power consumption of the sub data is adjusted to be equal to or close to the power consumption or current consumption for the optimal burn-in test. For example, the criterion of power consumption for the optimal burn-in test may be P _{burn -in} , P _{margin -high} or P _{margin -low} in FIG. 42 or 43 . Also, there are times when the power consumption or current consumption of each sub data measured or estimated in step 3 is smaller than the power consumption or current consumption for the optimal burn-in test. However, caution is required because a test failure may occur if the frequency of the corresponding sub data is increased to be equal to or close to the power consumption or current consumption for the optimal burn-in test.

Step 6

A burn-in test is performed using the shift frequency of each sub data adjusted in step 5 .

In at least one embodiment of the invention, the sub data of steps 1 to 6 are scan sections or functional test data.

Each of steps 1 to 6 may be performed in the same device or in different devices, for example, in a device such as a test device or a computer, depending on the embodiment.

As another embodiment, a method of finding or determining a frequency corresponding to a desired power consumption is as follows. A certain frequency is used to measure or estimate the power consumption value consumed by the sub data. And using the relation between power consumption and frequency as in Equation 2, α x C x V _dd ² Calculate the constant value for And a frequency value to be found may be calculated by substituting a constant value and a desired power consumption value into Equation (2).

In at least one embodiment of the present invention, a desired frequency may be found or determined by measuring or estimating power consumption consumed by sub data while increasing or decreasing the frequency.

In at least one embodiment of the invention, the power consumption consumed by the sub data may be measured or estimated using a device or software that measures or estimates power or current consumption.

44 is a flowchart illustrating an example of a method for finding an optimal shift frequency for each scan section in order to minimize a burn-in test time according to at least one embodiment of the present invention.

Referring to FIG. 44 , the burn-in test time minimization apparatus divides one or more scan patterns into at least two or more scan sections ( S4400 ). As an example of division of the scan pattern, the method shown in FIGS. 5 to 10 may be used. The burn-in test time minimization apparatus allocates a plurality of shift frequencies to each scan section (S4410). Here, the value of the shift frequency allocated to each scan section is a value smaller than the shift frequency at which the output pattern of the scan path is different from the prediction pattern. Then, the burn-in test time minimization apparatus performs the burn-in test while shifting the scan section by using the shift frequency allocated to each scan section ( S4420 ).

The division of the scan pattern into scan sections (S4400), the assignment of the shift frequency to the scan section (S4410), and the execution of the burn-in test (S4420) may be performed in the same device or in different devices, respectively, according to an embodiment.

The burn-in test time minimization apparatus can find the shift frequency just before the output pattern and the predicted pattern change according to the increase or decrease of the shift frequency, or find it as the maximum shift frequency allocable to the scan section. According to an embodiment, each scan section may be allocated a shift frequency smaller than the maximum shift frequency found through the increase or decrease of the shift frequency.

For the burn-in test of the present invention, various embodiments discussed above may be used as a method of finding an optimal shift frequency for each scan section. For example, the burn-in test time minimization apparatus may find an optimal shift frequency for each scan section by performing the method shown in FIGS. 12 to 33 . In addition, the method of changing the arrangement order of the scan patterns shown in FIG. 36 may also be applied to reduce burn-in test time and improve burn-in test quality.

45 is a block diagram illustrating an example of an apparatus for minimizing burn-in test time according to at least one embodiment of the present invention.

Referring to FIG. 45 , the burn-in test time minimization apparatus includes a chamber control unit 4500 , a shifting unit 4510 , and a shift frequency determining unit 4520 .

The chamber controller 4500 controls voltage, temperature, burn-in test time, etc. supplied to the IC chip to be tested.

The shift frequency determiner 4520 identifies an optimal shift frequency shifted in the scan path of the IC chip for each scan section during the burn-in test. For example, the shift frequency determiner 4520 may determine an optimal shift frequency for each scan section based on at least one of the various embodiments described above. In addition, the optimal shift frequency may be identified or determined by performing not only in the burn-in test time minimization device but also in a separate device, and the determined or determined shift frequency may be used by the shift frequency determining unit 4520 .

While the burn-in test is performed by the chamber controller 4500, the shifting unit 4510 shifts the scan section in the scan path using the optimal shift frequency identified by the shift frequency determining unit 4520 to reduce the burn-in test time. Minimize

In at least one embodiment of the present invention, only the burn-in test may be performed using a frequency optimized for each scan section, or a chip normality test may be performed together with the burn-in test. The burn-in test time minimization device can perform the previously salpin scan test together with the burn-in test.

The burn-in test time minimization apparatus may be implemented as a part of the salpin burn-in test apparatus in FIGS. 37 and 38 . In at least one embodiment of the present invention, only the burn-in test may be performed using a frequency optimized for each scan section, or a chip normality test may be performed together with the burn-in test. For example, only the burn-in test or both the burn-in test and the scan test can be performed using a scan pattern set to which an optimized shift frequency is allocated for each scan section.

The apparatus for minimizing the burn-in test time may rearrange the order of shifted scan patterns in the scan path by using the scan pattern rearrangement method illustrated in FIG. 36 . In this case, the switched portion of the circuit and the number of switching operations on the IC chip may be different from those before the relocation due to the shift of the scan pattern at the relocated pattern position on the scan pattern set, and accordingly, the operating characteristics of the circuit such as power consumption may be changed. there is. Accordingly, the shift frequency that can be assigned to the scan pattern (or scan section) may be increased. Therefore, by using this property to find or determine the optimal shift frequency for each scan section by using the embodiment of the present invention previously examined after relocating the scan pattern, the overall burn-in test time may be further reduced or the test quality may be increased. In addition, relocation of the scan pattern may be performed not only in the burn-in test time minimization device but also in a separate device such as a computer, and may be used by the burn-in test time minimization device.

46 is a table showing experimental results using a micro control unit (MCU) processor IC chip and a test pattern of the IC chip. A scan section to be determined for a shift frequency corresponds to one scan pattern one-to-one. 46 is a power-limit-based method for finding the maximum possible shift frequency while power consumption by a scan pattern does not exceed the allowable power consumption of the IC chip and the shift frequency increase/decrease-based method of the present invention. (shift-frequency-scaling-based method) is used to show the maximum shift frequency found for each scan pattern.

Referring to FIG. 46 , the optimization using the shift-frequency-scaling-based method was performed using the method of FIG. 12 . Also, referring to FIG. 46, the difference between the maximum shift frequency results by the power-limit-based method and the shift-frequency-scaling-based method is the actual IC chip and the IC chip. This is because, in addition to power consumption of the IC chip, there are circuit structures and features, various physical conditions and environments that can affect the shift frequency in the test environment.

The power consumption limit of FIG. 46 is about 285 mW as the average power consumption when the IC chip is operated in the functional mode at 80 MHz, which is the functional frequency limit of the IC chip.

In general, the functional frequency limit and the frequency limit or scan shift frequency limit at which the IC chip can be damaged can be different. For example, the frequency limit may be different from circuit operating characteristics, power consumption, signal crosstalk effect, critical timing path, etc. by scan test or functional mode of operation. am. In addition, it may be subject to various restrictions, such as a difference in voltage or power supplied to different locations on the circuit.

The first column of FIG. 46 is the scan pattern number, and the second column is the power consumption due to the leakage current of the IC chip. The third column is the dynamic power dissipation consumed by the scan shift using a nominal shift frequency of 25 MHz. The fourth column is the sum of the second and third columns, and is the total power consumption for each scan pattern using a nominal shift frequency of 25 MHz. The fifth column is the maximum possible shift frequency of each scan pattern without exceeding the power consumption limit of 285mW.

The sixth column is the MCU IC chip test result when tested with the shift frequency of the fifth column for each scan pattern, indicating test success or failure.

The seventh column is the maximum shift frequency found using the shift frequency increase/decrease method according to the method of the present invention, and all of the test results are normal.

The eighth column shows the increase/decrease ratio ( %) is shown.

Referring to FIG. 46 , the shift-frequency increase/decrease-based method is an average of about 30% or more, except for the case of the sixth scan pattern in which the scan test is not normally performed by the power-limit-based method. It can be seen that the shift frequency of the -scaling-based method) is high. For example, depending on the shifted bit pattern, a false critical pass may occur or there may be various reasons such as a bit on the scan pattern that is a don't-care bit that does not affect the test result. can

As in the case of the sixth scan pattern in FIG. 46, even if a shift frequency is used so that the power consumption by the scan pattern does not exceed the allowable power consumption of the IC chip, there may be cases in which the IC chip cannot be tested normally. Able to know. The reason for this is that the shift frequency limit is not only due to power consumption, but also signal delay time of the critical timing path due to the circuit structure of the IC chip, signal crosstalk, This is because it may be affected by various factors such as voltage or power difference, signal or power noise, chip manufacturing process variation, and circuit physical characteristics. This is because the test environment and conditions such as the ambient temperature of the test target chip and the connection state of the chip and the chip test equipment may also be affected.

In addition, even if the bit value of the scan section or scan pattern is unintentionally changed and loaded into the scan path during shift in the process of determining the optimal shift frequency through shift frequency increase or decrease, the result after the scan capture operation according to the structure of the IC chip circuit The pattern may appear as a normal bit pattern on the scan path.

Therefore, before loading the scan section into the scan path through shift frequency increase or decrease and scan capture, compare the output result of the main output port of the IC chip with the predicted result and check whether the main output result is pass, so that the optimal shift is more accurate. frequency can be found.

47 is a graph illustrating an example of a test fail hole that may occur during an IC chip test.

In order to test an IC chip, there is a process of setting up a test device, test data, or a test program. In this case, an abnormal test failure may occur within a range of a normal shift frequency in which a normal IC chip should be determined to be fault-free. This abnormal test failure 4700 is called a test fail hole, a test frequency fail hole, or a fail hole of the period of the test frequency.

Referring to FIG. 47 , an abnormal test failure 4700 occurs at 30 MHz when testing an IC chip. The test fail hole may make the mass-production test of the IC chip unstable and may adversely affect the yield, so it is desirable to remove it.

48 is a graph illustrating an example of a method for solving a test fail hole problem according to at least one embodiment of the present invention.

Referring to FIG. 48 , as an embodiment of a method for solving a test fail hole problem, a test is performed on specific sub data in which a test fail hole is generated or has an effect on the occurrence of a fail hole There is a way to prevent that from happening.

For example, there is a method in which test output data of an IC chip for sub data in which a fail hole has occurred is not compared with predicted data. This method may be called test data masking or predicted result masking of test data. In the following embodiments, sub data means scan pattern, scan section, or functional test data. A case in which the test data masking method is applied to the scan pattern may be referred to as scan pattern masking or predicted result masking of a scan test. As another example, there is a method of removing or not using sub data affecting the generation of a test fail hole.

In the case of FIG. 48 , the second sub data in which the fail hole is generated at 30 MHz may be found and masked or removed. However, a method of masking or removing the sub data may lower the fault coverage of the IC under test. Also, due to a method of masking or removing sub data, a faulty IC chip may be determined as a fault-free test. And this may cause a field escape problem in which a faulty IC chip goes out to the field.

Accordingly, as another embodiment of a method for solving the test fail hole problem, a fail hole is generated by finding sub data and a frequency corresponding to the fail hole that occur or affect the occurrence of the fail hole. Alternatively, a frequency at which a fail hole does not occur is used in the specific sub data that affects the fail hole generation.

49 is a flowchart of a method for resolving a fail hole problem in accordance with at least one embodiment of the present invention.

49 , the test device selects sub data constituting the test data (S4900). Here, the sub data may be a scan pattern or a scan section. The test apparatus performs a test of the IC chip while increasing or decreasing the frequency of the sub data (S4910), and finds a frequency or a fail hole usable for the selected sub data based on the PASS or FAIL test result of the IC chip (S4920). Then, the IC chip is tested using a frequency at which a fail hole does not occur for the selected sub data (S4930).

For example, when finding a fail hole for a scan pattern or scan section, various methods described above for finding an usable shift frequency of a scan pattern or scan section using shift frequency increment/decrement may be used.

50 is a diagram illustrating another example of a method for solving a fail hole problem according to at least one embodiment of the present invention.

Referring to FIG. 50 , a frequency of 25 MHz or less may be used for second sub data in which a test fail hole 5000 is generated. Here, the sub data may be a scan pattern, a scan section, or functional test data.

It is assumed that the first sub data, the second sub data, and the third sub data are a first scan pattern, a second scan pattern, and a third scan pattern, respectively. The first scan pattern, the second scan pattern, and the third scan pattern are sequentially shifted in the scan path of the IC chip under test. The method of finding a test fail hole 5000 for a second scan pattern or a scan section included in the second scan pattern is the previously described method of finding an usable shift frequency of a scan pattern or scan section using shift frequency increments and decrements. Various methods can be used.

For example, while increasing or decreasing the shift frequency of the second scan pattern, the first scan pattern or the third scan pattern positioned before or after the second scan pattern is shifted in using a frequency that can be normally input to the scan path. In addition, a fail hole and a usable shift frequency range for the second scan pattern may be found using the scan test result. Each shift frequency of the first scan pattern or the third scan pattern used to find a fail hole or an usable frequency range for the second scan pattern may be the same as or different from each other.

In the scan test process to find a fail hole or usable frequency range for the second scan pattern, not only the output pattern of the second scan pattern but also the output pattern of the first scan pattern located in front of the second scan pattern is predicted pattern can be compared. In this case, when the test results of the first scan pattern and the second scan pattern are both normal, the current shift frequency is the usable shift frequency of the second scan pattern. As another example, the output pattern of the third scan pattern, which is a scan pattern located behind the second scan pattern, and the prediction pattern may be compared. And when the test results of the second scan pattern and the third scan pattern are both normal, the current shift frequency is a usable shift frequency of the second scan pattern.

A scan pattern in which a test fail hole is generated or a fail hole is generated may be a first scan pattern or a third scan pattern inputted before or after the second scan pattern. This is because the shift frequency of the second scan pattern may affect the bit value on the scan path when the output pattern of the first scan pattern is shifted out. This is because, when the test result by the second scan pattern is shifted out, the bit value on the scan path may be affected by the shift frequency that shifts the third scan pattern into the scan path. Therefore, if there is a test fail hole in the test result by a specific scan section or scan pattern, it is determined whether the scan section or scan pattern located before or after the scan section or scan pattern affects the occurrence of the fail hole.

For example, a frequency that can be normally shifted in the scan path is used for the second scan pattern, and the test result is checked while increasing the shift frequency of the third scan pattern. At this time, if the test result by the second scan pattern fails and the test result by the third scan pattern is normal, the shift frequency of the third scan pattern uses a frequency at which the test failure of the second scan pattern does not occur. do. In this way, the influence of the third scan pattern on the fail hole appearing in the test result of the second scan pattern can be removed.

In at least one embodiment of the present invention, the scan test is performed while increasing or decreasing the shift frequency. And when a fail hole is generated at a specific shift frequency, a scan test using the shift frequency corresponding to the fail hole fails to find a specific scan pattern. In addition, the chip test is performed using a shift frequency lower than the shift frequency at which the fail hole is generated for a specific scan pattern and a scan pattern adjacent to or before the specific scan pattern. That is, a shift frequency lower than the shift frequency at which the fail hole occurs may be used for neighboring scan patterns that may affect the fail hole.

In at least one embodiment of the present invention, a scan section or scan pattern in which a fail hole is generated and a corresponding shift frequency are found using shift frequency increment/decrement. In addition, a shift frequency that does not generate a fail hole within a margin range of the shift frequency in consideration of the manufacturing process and the test process is used for the scan section or scan pattern. For example, a shift frequency in which a fail hole is not generated within a margin range while being higher than a shift frequency in which a fail hole is generated may be used. As another example, even in a scan section or scan pattern adjacent to a scan section or scan pattern in which a fail hole is generated, a shift frequency in which a fail hole is not generated may be used within a margin range while being higher than a shift frequency in which a fail hole is generated.

As described above, if a frequency or a frequency period in which a fail hole does not occur for specific sub data is used for mass-production testing of the chip, the failure detection rate of the IC chip due to the method of masking or removing the sub data The problem of (fault coverage) being lowered can be eliminated. Also, the field escape problem in which a faulty IC chip leaves the field can be eliminated. It can be used to test the chip by finding a specific frequency or range of frequency periods in which a fail hole does not occur.

51 is a diagram illustrating a method of finding a shift frequency for reducing test time and improving yield according to at least one embodiment of the present invention.

Referring to FIG. 51 , it is assumed that at least two scan sections are shifted using different shift frequencies in the scan path of the chip and the chip is tested. At this time, the shift frequency with the increased margin is used for the first scan section having a small test normal margin based on the specific shift frequency 5100 for which the test results of two or more scan sections are all normal. Alternatively, a shift frequency with a reduced margin is used for the second scan section having a large test normal margin of the shift frequency.

The shift frequency margin of the scan section can be found or determined using the test pass or fail information in the scan section. For example, it is possible to find or determine a margin representing an interval between a frequency or a period of a frequency that is a boundary between test success and failure of a scan section and a specific shift frequency 5100 . The scan section using the shift frequency reflected by the margin and the test results by the scan section located in front of it should all be normal.

If the margin of the scan section with a small shift frequency margin is increased, the test is less affected by variations in the manufacturing process of the chip or the test environment. Therefore, there may be an effect of improving the yield.

In addition, if the margin is reduced for a scan section having a large shift frequency or a shift frequency period margin, the test time can be reduced.

Therefore, the opposite effects of improving yield and reducing test time can be obtained together by considering the frequency margin for each scan section.

Referring to FIG. 51 , both the first scan section and the second scan section are test passes at a nominal shift frequency 5100 of 20 MHz. When the margin of the shift frequency of the first scan section on the basis of 20 MHz is less than a preset reference value, the test device increases the margin of the shift frequency of the first scan section to help improve the yield in mass-production testing of the chip. . That is, the shift frequency used in the first scan section is changed to a value smaller than 20 MHz to satisfy the reference value. In addition, if the margin of the shift frequency or period of the shift frequency of the second scan section on the basis of 20 MHz is greater than the reference value, the margin of the frequency or period of the second scan section is reduced to reduce the overall test time during mass-production testing of the chip. can That is, the shift frequency used in the second scan section is changed to a value greater than 20 MHz to satisfy the reference value.

As described above, in performing a chip test by finding an optimal shift frequency for each of at least two or more scan sections, there is a case where the shift timing of boundary bits of adjacent scan sections becomes a problem.

If the period of the shift frequency between the last bit of the scan section S1 and the first bit of the scan section S2 that is sequentially shifted into the scan path thereafter is called CP_boundary (Clock Period of Boundary Bits), the optimal maximum shift frequency of the scan section S2 When the period of is found, the first CP_boundary of S1 and S2 and the second CP_boundary of S1 and S2 for which the period of the optimal shift frequency is determined may be different from each other. For example, when the second CP_boundary2 is smaller than the first CP_boundary, the scan test using the scan sections S1 and S2 is likely to determine that there is a failure for a normal chip.

In this case, in order to solve the shift timing problem of boundary bits of adjacent scan sections, the following method may be used.

(1) When the optimum maximum shift frequency of the scan section S1 is determined, when the optimum maximum shift frequency of the scan section S2 that is shifted in following the scan section S1 is found, the scan section S1 is the optimum shift frequency determined for S1 use

(2) The clock edge on which the scan bit shift operation is performed is positioned at the boundary or close to the boundary of the CDP (Clock Definition Period). The CDP is a time interval in which the shape of the clock is defined, and the rising or falling timing of the clock signal is defined within the interval. CDP can be established in the instrument or test data.

(3) The period or shift time interval of the shift frequency between the last bit of the scan section S1 and the first bit of the scan section S2 that is sequentially shifted in the scan path thereafter is adjusted. For example, when a scan test is performed using a scan pattern including S1 and S2, it can be adjusted to a period of a shift frequency that can determine that a normal chip is normal. The period of the shift frequency or the shift time interval may be defined in the test data or set in the test device. For example, when creating new test data to which the period of the optimal shift frequency is assigned for each of the scan sections S1 and S2, the timing information for the last bit of the scan section S1 or the first bit of S2 is newly created, and the timing information includes When a scan test is performed using a scan pattern including S1 and S2, a shift frequency period for determining that a normal chip is normal may be allocated. For example, the period of the nominal shift frequency, etc. may be assigned.

(4) If it is determined that there is a failure in the scan test for a normal chip due to a shift timing problem of the boundary bits of adjacent scan sections, increase the period of the shift frequency of the scan section or scan pattern including the boundary bits make it

In some cases, there are restrictions on the number of frequency or timing identifiers that an IC chip test device can set or control. Controlling the frequency includes controlling to change a frequency value or change a transition time characteristic of a corresponding electrical signal.

For example, if the number of frequency or timing identifiers that can be set or controlled by the IC chip test device is 32, it means that the number of frequency or timing identifiers that can be set or controlled independently of each other by the IC chip test device is 32 do. For example, if the number of frequency or timing identifiers that can be set or controlled by the IC chip test device is 32, the 32 frequency controllers of the IC chip test device can set or control the frequencies independently of each other. Alternatively, the method of setting or controlling the timing identifier and the configuration of the frequency controller for the same may vary depending on the IC chip test apparatus.

52 to 59 show shift frequencies available for each scan section when the number of frequencies or timing identifiers that can be set or controlled by the IC chip test apparatus is smaller than the number of scan sections dividing the input scan pattern (for example, A method and apparatus for generating search data for finding a maximum shift frequency) are provided.

52 is a diagram illustrating an example of test data according to an embodiment of the present invention.

Referring to FIG. 52 , the input scan pattern 5210 of the sub test data 51 in the test data 5200 may be divided into four scan sections 5212 , 5214,5216 , and 5218 . In one embodiment, if the number of frequencies that the IC chip test apparatus can set or control is 5 or more, the search data used to find the shift frequency for each scan section included in the input scan pattern 51 of FIG. 52 is shown in FIG. Together, they can be created as one search data. However, if the number of frequencies that can be set or controlled by the IC chip test device is three or less, the data for searching to find the optimal shift frequency of the four scan sections 5212,5214,5216,5218 is one as shown in FIG. It cannot be created as data for retrieval of Therefore, as in FIGS. 25 to 27 , data for searching should be generated for each target scan section 5121, 5214,5216, and 5218 of the input scan pattern 51 of FIG. 52. In this case, four pieces of data for searching are required.

If the number of data for search increases, the time for compiling and loading the data for search into memory becomes longer, which increases the time of the entire process of finding a usable shift frequency. Therefore, use as few data for search as possible. Thus, it is desirable to find the optimal shift frequency for each scan section.

Although the maximum number of frequencies that the IC chip test apparatus can set or control is limited, the number of scan sections dividing the input scan pattern may be variously set by the user. However, in the following, for convenience of explanation, the number of frequencies that the IC chip test device can set or control is three, and the number of target scan sections for which a shift frequency or an optimal shift frequency that can be used in the input scan pattern is found is four. A case is assumed and described.

53 and 54 are diagrams illustrating an example of search data according to an embodiment of the present invention. 53 and 54 show an example of search data for finding a shift frequency or a maximum shift frequency available for four target scan sections 5212, 5214,5216, 5218 included in the input scan pattern 51 of FIG. has been

53 and 54 , the input scan pattern 51 of the search data 5300 and 5400 is divided into two segments 5310 and 5320 . Since the number of frequency or timing identifiers that can be set or controlled by the IC chip test device is smaller than the number of available shift frequency search target scan sections 5212,5214,5216,5218, the input scan pattern has a plurality of segments 5310 ,5320). Each segment 5310,5320 also includes a plurality of scan sections 5212,5214,5216,5218 divided from each other. A segment including at least one scan section dividing the input scan pattern may be referred to as a scan segment.

The number of segments 5310 and 5320 dividing the input scan pattern may be determined by the number of frequency or timing identifiers that the IC chip test apparatus can set or control and the number of scan sections dividing the input scan pattern. For example, the number of segments is an integer greater than or equal to a value obtained by dividing the number of scan sections dividing the input scan pattern by the number of frequency or timing identifiers that can be set or controlled by the IC chip test apparatus for the scan sections. can be decided with That is, for example, if the number of scan sections of the input scan pattern is 30 and the number of frequency or timing identifiers that the IC chip test apparatus can set or control for the scan sections is 10, the number of segments is 3 It can be a dog or more. This embodiment will be described on the assumption that the number of segments is two.

The number of frequency or timing identifiers that can be set or controlled by the IC chip test apparatus for the scan sections dividing the input scan pattern may be a number excluding a predetermined number according to IC chip test conditions. For example, the number may be the number excluding the number of timing identifiers used for other purposes, such as a scan section other than a scan section to be searched for a usable shift frequency.

53 to 55 will be described on the assumption that the number of segments is two.

Search data 5300 and 5400 for a plurality of target scan sections 5212 , 5214,5216 , and 5218 of the input scan pattern may be generated as many as the number of segments 5310 and 5320 . In this embodiment, since the input scan pattern 51 is divided into two segments 5310 and 5320, a search for available shift frequencies for each target scan section 5212, 5214,5216, 5218 of the input scan pattern 51 is performed. The use data 5300 and 5400 may be generated as the first search data 5300 of FIG. 53 and the second search data 5400 of FIG. 54 .

Two of the four target scan sections 5212,5214,5216,5218 of the input scan pattern 51 of FIG. 52 are the input scan pattern 51 of the first search data 5300 of FIG. 53 When included as target scan sections 5212 and 5214 in divided and included as

When the generated search data includes a plurality of search object scan sections, timing identifiers assigned to each search object scan section are different from each other. Also, in the data for retrieval, timing identifiers other than the timing identifier assigned to the scan section to be retrieved are different from the timing identifier assigned to the scan section to be retrieved in the data for retrieval.

In the first search data 5300 , the same timing identifier T1 is assigned to all scan sections 5216 and 5218 included in the second segment 5320 , and each scan section included in the first segment 5310 ( Different timing identifiers (Target_T1, Target_T2) are allocated to 5212 and 5214. In an embodiment, the timing identifier T1 assigned to the scan section of the second segment 5320 is a fixed shift in order to search for available frequencies of each target scan section 5212 and 5214 using the search data 5300 . Timing identifiers (Target_T1, Target_T2) assigned to each target scan section of the first segment 5310 shift each time a scan test using the search data 5300 is performed to find an usable shift frequency. The frequency (or period of the shift frequency) may be changed.

Accordingly, the IC chip test apparatus fixes the shift frequencies of the timing identifiers (Target_T2, T1) of the second scan section 5214 and the second segment 5320, and the timing identifier (Target_T1) assigned to the first scan section 5212 The scan test is repeatedly performed while changing the shift frequency of to search for an usable shift frequency or an optimal shift frequency for the first scan section 5212 . Also, in the IC chip test apparatus, the timing identifier (Target_T2) assigned to the second scan section 5214 in a state in which shift frequencies of the timing identifiers (Target_T1, T1) of the first scan section 5212 and the second segment 5320 are fixed. The scan test is repeatedly performed while changing the shift frequency of to search for an optimal shift frequency for the second scan section 5214 . That is, the IC chip test apparatus sequentially designates the first scan section 5212 and the second scan section 5214 included in the input scan pattern 51 as target scan sections by using the first search data 5300. Each optimal shift frequency may be searched for.

Also, in one embodiment, the maximum frequency available using the first search data 5300 is the maximum frequency of the first scan section 5212 found first, or a frequency obtained by a predetermined increase or decrease with respect to the maximum frequency in the first scan section ( In a state where the frequency of the timing identifier (Target_T1) of 5212 is fixed, the maximum usable shift frequency of the second scan section 5214 that is the next scan section to be searched may be found. In this way, when the maximum shift frequency of each scan section found in the step of searching for available shift frequencies of each target scan section is applied to all of the scan sections, it is correlated with the maximum shift frequency for each scan section found in the search step. It has the advantage of increasing correlation.

The optimal shift frequencies of the third and fourth scan sections 5216 and 5218 of the input scan pattern 51 may be found using the search data 5400 of FIG. 54 . In the second retrieval data 5400 , all scan sections 5212 and 5214 included in the first segment 5310 are assigned the same timing identifier T1 , and each scan section 5216 of the second segment 5320 , 5218 , different timing identifiers (TargetT1, TargetT2) are allocated. The IC chip test apparatus designates the third and fourth scan sections 5216 and 5218 as target scan sections, respectively, in the same manner as in the search process of the optimal shift frequency using the first search data 5300, and the timing identifiers (TargetT1, TargetT2) ), the optimal shift frequencies for the third and fourth scan sections 5216 and 5218 may be searched while changing the shift frequency.

In the plurality of search data 5300 and 5400 , positions of segments 5310 and 5320 to which the same timing identifier is allocated may be different from each other. For example, suppose that the input scan pattern is divided into 5 segments, each segment includes 10 scan sections, and the number of timing identifiers is 10. In this case, five pieces of data for retrieval are generated, the same timing identifier (T1) is allocated to all of the second to fifth segments of the first data for retrieval, and the same timing identifier (T1) is assigned to all of the first and third to fifth segments of the second data for retrieval. The positions of segments to which the same timing identifier is assigned in respective data for search, such as to which the timing identifier T1 is assigned, may be different from each other. The IC chip test apparatus sets or changes the frequencies of different timing identifiers (TargetT1, TargetT2...) assigned to each scan section included in the first segment in the case of the first data for retrieval, and sets or changes the frequency of the data for the second retrieval. Set or change the frequencies of different timing identifiers (TargetT1, TargetT2...) assigned to each scan section included in the second segment to find the available shift frequency or optimal shift frequency of the scan section of each segment. can

55 and 56 are diagrams illustrating another example of search data according to an embodiment of the present invention. 55 and 56 show an example of search data for finding an optimal shift frequency of four scan sections included in the input scan pattern 51 .

55 and 56 , an input scan pattern of search data 5500 and 5600 is divided into two segments 5310 and 5320 . 53 and 54 are data for search 5300 and 5400 to which the same timing identifier is assigned in units of segments, whereas the examples of FIGS. 55 and 56 are identical to at least one scan section existing in a plurality of segments. Search data 5500 and 5600 to which timing identifiers are assigned.

The first data for retrieval 5500 is data for retrieval for finding the optimal shift frequency of the first scan section 5212 and the third scan section 5216 , and the second data for retrieval 5600 is the second scan section ( 5214) and data for searching for the optimal shift frequency of the fourth scan section 5218.

In the first search data 5500, the second scan section 5214 of the first segment 5310 and the fourth scan section 5218 of the second segment 5320 are all assigned the same timing identifier T1, Different timing identifiers TargetT1 and TargetT2 are allocated to the first scan section 5212 of the first segment 5310 and the third scan section 5216 of the second segment 5320 , respectively. Conversely, in the second search data 5600 , the second scan section 5214 of the first segment 5310 and the fourth scan section 5218 of the second segment 5320 have different timing identifiers (TargetT1, TargetT2). ), and the same timing identifier T1 is assigned to both the first scan section 5212 of the first segment 5310 and the third scan section 5216 of the second segment 5320 .

When the search data 5300,5400,5500,5600 that may include a plurality of target scan sections is generated as shown in FIGS. 53 to 56 , FIGS. 25 to 27 for generating search data for each target scan section By comparison, the storage capacity of the data storage medium for retrieval can be saved. For example, in order to find the optimal shift frequency of the four target scan sections 5212, 5214,5216, 5218 of FIG. We need 4 data for retrieval. However, as in the embodiments of FIGS. 53 and 54 or 55 and 56 , since the optimal shift frequencies of four target scan sections can be found only with two pieces of data for search, there are the following effects and advantages.

(1) The storage capacity of the storage medium can be saved.

(2) When each search data is made into individual files, it is possible to reduce the compilation time for converting all search data files into files for use in the IC chip test device.

(3) If each data for search is made into an individual file, the number of data files for search is reduced, making file management easier and more convenient.

(4) When each data file for search is made into an individual file, the number of data files for search is reduced, so that the number of times to load the search data file into the IC chip test device can reduce the overall load time. Thus, it is possible to reduce the time of the entire process of finding the optimal shift frequency of all target scan sections.

In addition, when segments are used as shown in FIGS. 53 to 56, the input scan pattern is divided into many target scan sections regardless of the number of frequency or timing identifiers (or timing sets, timing information) that the IC chip test device can set or control. And, there is an effect and advantage of being able to include a plurality of target scan sections in one search data.

57 is a flowchart illustrating an example of a method for generating search data according to an embodiment of the present invention.

Referring to FIG. 57 , the search data generating device generates the input scan pattern when the number of frequencies or the number of timing identifiers that the IC chip test device can set or control is smaller than the number of scan sections dividing the input scan pattern. It is divided into at least two or more segments including at least one scan section (S5700). For example, referring to FIG. 52 , if the number of target scan sections of the input scan pattern 51 is 4, and the number of frequencies or timing identifiers that the IC chip test apparatus can set or control is 3, The data generating apparatus divides the input scan pattern into two segments as shown in FIG. 53 .

The search data generating apparatus generates a plurality of search data corresponding to the number of segments (S5710). For example, when the input scan pattern 51 of FIG. 52 is divided into four scan sections, the search data generating apparatus generates the two search data of FIGS. 53 and 54 , or in FIGS. 55 and 56 . You can create two types of data for retrieval.

Each of the plurality of search data includes at least two or more scan sections to which the same timing identifier is assigned among a plurality of scan sections included in a target input scan pattern including an available or maximum shift frequency search target scan section. As an embodiment, the search data generating apparatus may allocate the same timing identifier in units of segments. For example, as shown in FIG. 53 , the same timing identifier T1 may be allocated to all scan sections included in the second segment 5320 . In another embodiment, the search data generating apparatus may use the same timing identifier for at least one scan section existing in at least two or more segments. For example, the same timing identifier T1 may be allocated to some scan sections of the first and second segments as shown in FIGS. 55 and 56 .

Also, the plurality of data for search may have different positions of scan sections to which the shift frequency or timing identifiers (TargetT1, TargetT2) of which the period of the shift frequency is changed in order to find a usable shift frequency are allocated. For example, referring to FIGS. 53 and 54 , in the first search data 5300 , timing identifiers (TargetT1, TargetT2) capable of changing the shift frequency are included in the first and second scan sections of the first segment 5310 . (5212 and 5214), while the second data for retrieval 5400 is assigned to the third and fourth scan sections 5216 and 5218 of the second segment 5320, respectively. As another example, referring to FIGS. 55 and 56 , in the first search data 5500, timing identifiers (TargetT1, TargetT2) capable of changing the shift frequency are allocated to the first and third scan sections 5212 and 5216. On the other hand, the second search data 5600 is allocated to the second and fourth scan sections 5214,5218, respectively.

That is, the search data generating device allocates timing identifiers (TargetT1, TargetT2) capable of changing the shift frequency to each available frequency search target scan section existing in the input scan pattern of each search data, and assigns them to all other scan sections. The same timing identifier T1 may be allocated, but positions of the frequency search target scan sections usable for a plurality of search data may be different from each other. Also, the timing identifier of the scan section located immediately before or after the target scan section is different from the timing identifier of the target scan section.

Alternatively, the search data generating apparatus allocates different timing identifiers (Target_T1, Target_T2) to each frequency search target scan section existing in the input scan pattern of each search data, and allocates different timing identifiers (Target_T1, Target_T2) to the remaining scan sections to the target scan section. Allocate timing identifiers different from the timing identifiers (Target_T1, Target_T2), so that the number of timing identifiers assigned to all scan sections of the input scan pattern is less than or equal to the number of frequency or timing identifiers that can be set or controlled by the IC chip test apparatus can do. Also, the timing identifier of the scan section located immediately before or after the target scan section is different from the timing identifier of the target scan section.

In the search data, when the input scan pattern first input to the IC chip under test is input to the IC chip, the Don't-care prediction pattern is the prediction pattern for the pattern output from the IC chip. can be included in

22, 23, 25 to 28, and 53 to 56 are examples of data for search, and a timing identifier different from the timing identifier used in the original test data is used for the timing identifier used for the search data. may be For example, a timing identifier different from the existing timing identifier T1 used in the original test data of FIG. 51 may be used for the timing identifier T1 of FIGS. 52 and 53 .

22, 23, 25 to 28, and 53 to 56 are an example of search data, and a target input scan pattern including a shift frequency search target scan section usable in the search data (for example, , one or more input scan patterns may be included before or after the input scan pattern 51 of FIG. 53 . In this case, it is preferable that the number of total input scan patterns included in the search data be smaller than the number of total input scan patterns included in the original scan pattern set. In this case, the following effects and advantages are provided.

(1) It can reduce the time to search for available frequencies of all target scan sections.

(2) The storage capacity of the data storage medium for retrieval can be saved.

(3) It is possible to reduce the compile time for converting the search data file into a file for use in the IC chip test device.

(4) It is possible to reduce the time for loading the data file for search into the IC chip test device, thereby reducing the time of the entire process of finding the optimal shift frequency of all target scan sections.

22, 23, 25 to 28, and 53 to 56 are one embodiment of data for search, and the target input scan pattern including the shift frequency search target scan section usable in the search data is the target scan section It may contain one or more scan sections other than

22, 23, 25 to 28, and 53 to 56 are an example of search data, and in addition to a target input scan pattern including a shift frequency search target scan section usable in the search data, the search One or more different input scan patterns included in the data may include a plurality of scan sections assigned different timing identifiers. In addition, a timing identifier assigned to a scan section other than the target scan section in the search data is different from the timing identifier of the target scan section. The number of timing identifiers set or controlled by the IC chip test apparatus in the search data is less than or equal to the number of frequency or timing identifiers that the IC chip test apparatus can set or control.

58 is a diagram illustrating an example of a data file for search according to an embodiment of the present invention.

Referring to FIG. 58 , a plurality of search data 5812 , 5822 , and 5832 exist together in one file 5800 . Each of the search data 5812 , 5822 , and 5832 is data used to find an usable shift frequency or an optimal shift frequency of a specific target scan section. For example, the search data 5300 and 5400 of FIGS. 53 and 54 may be generated as one file. The number of search data stored in one file may be variously modified according to an embodiment. In addition, as in the embodiment of FIG. 58 , various types of search data for finding a usable shift frequency of a scan section are available for search data stored in one file.

The plurality of data for search 5812 , 5822 , and 5832 may be stored in a file together with identifiers 5810 , 5820 , and 5830 for identifying or distinguishing data for search. That is, the identifiers 5810 , 5820 , and 5830 are used to perform a scan test using specific search data. The IC chip test apparatus may determine which data for search is data for search for finding the optimal shift frequency of which target scan section, based on the identifiers 5810, 5820, and 5830. The IC chip test apparatus finds usable shift frequencies of at least one target scan section included in the search data while repeatedly performing a scan test using the search data identified based on the identifiers 5810, 5820, and 5830. can

The IC chip test apparatus may read the data file for search and store information or data on the identifiers 5810 , 5820 , and 5830 and the search data 5812 , 5822 , and 5832 in a memory. For example, information or data on the first identifier 5810 - the first search data 5812 - the second identifier 5820 - the second search data 5822 may be sequentially stored in the memory. .

According to an embodiment, the identifiers 5810, 5820, and 5830 may be used to identify a start position and an end position of search data for the IC chip test apparatus to perform a scan test. For example, when it is desired to find the optimal shift frequency of the scan section using the second data for retrieval 5822 , the IC chip test apparatus uses a second identifier 5820 indicating a start position of the data for second retrieval 5822 . After finding out from the memory, a process of sequentially reading test data from the memory from the location of the second identifier 5820 to perform a scan test may be performed until the third identifier is met. That is, the second identifier and the third identifier may be used as test start position and stop position information of the second search data or a test device command for starting and stopping the scan test.

In another embodiment, information indicating an existence period of data for search may be present together with each identifier 5810 , 5820 , and 5830 . For example, markers indicating the start and end positions of each data for retrieval (eg, start position "{" end position "}") may exist before and after the data for retrieval 5812 , 5822 , and 5832 . . In this case, when it is desired to find the optimal shift frequency of the scan section using the second search data 5822 , the IC chip test apparatus performs an area in the memory where the second search data exists based on the second identifier 5820 . After acknowledging , the scan test process of the IC chip can be performed by reading the test data existing between the predefined start position and the end position.

Creating multiple search data into one file has the following effects and advantages.

(1) The number of times of loading a search data file for searching an available frequency or an optimal frequency into the memory of the IC chip test device is reduced, so that the entire search data load time can be reduced.

(2) Duplicate contents such as header data duplicated in multiple search data files are reduced, so that the byte size of the search data file can be reduced. Therefore, it is possible to save the storage space of the storage medium for storing the data file for search.

(3) It is possible to reduce the time for compiling a file in the form used in the IC chip test device. For example, the compilation time of data files for retrieval can be reduced because it can reduce the redundant operation time that the compiler processes for multiple individual files. In addition, the compilation time can be further reduced for the reason of (2) above.

59 is a diagram illustrating an example of an apparatus for generating data for a search according to an embodiment of the present invention.

Referring to FIG. 59 , the search data generating device 5900 includes a segment generating unit 5910 , a data generating unit 5920 , and a data storage unit 5930 . The search data generating device 5900 may be implemented as a part of the host computer of FIG. 2 or 3 , or may be implemented as a separate computing device.

When the number of frequencies or the number of timing identifiers that can be set or controlled by the IC chip test apparatus is smaller than the number of scan sections dividing the input scan pattern, the segment generator 5910 generates the input scan pattern in at least one scan section. It is divided into at least two or more segments containing

The data generator 5920 generates a plurality of search data corresponding to the number of segments. Examples of generation of data for retrieval are shown in FIGS. 53 to 56 . For example, each of the search data includes at least two or more scan sections to which the same timing identifier is assigned among a plurality of scan sections included in the input scan pattern, and a scan test using the search data is performed to find an usable shift frequency. The scan sections to which the shift frequency or the timing identifier to which the period of the shift frequency is changed during repetition are allocated may be generated to be different from each other.

Also, as an embodiment, timing identifiers assigned to each of the available shift frequency search target scan sections included in the input scan pattern in each of the search data are assigned to be different from each other, and a timing identifier assigned to a scan section other than the target scan section is different from the timing identifier assigned to the target scan section, provided that the total number of different timing identifiers assigned to each scan section of the input scan pattern is less than or equal to the number of frequency or timing identifiers that the IC chip test device can set or control. Data for search may be generated as much as possible. And, in the data for retrieval, the timing identifier of the scan section to be searched is different from the timing identifier of the scan section immediately before or after the scan section to be searched.

The data storage unit 5930 may store a plurality of data for retrieval as individual files or may store them as one file by classifying them by identifiers. An example of storing a plurality of data for retrieval as one file is shown in FIG. 58 .

As the process of manufacturing an IC chip becomes more refined, the influence of a manufacturing process variation or an unstable test environment on yield increases. As a result, the yield may become unstable or low, which may lead to a lot of time and great economic loss. Therefore, it is necessary to find, analyze, and solve the cause of unstable or low yield as quickly as possible.

The scan shift frequency characterization data obtained on the basis of the available shift frequency information for each scan section may be used to find and analyze the cause of destabilizing or lowering the yield. An example of this is shown in FIGS. 60 to 62 .

60 is a diagram illustrating an example of a method for finding a failure or defect location candidate of an IC chip based on shift frequency information for each scan section according to an embodiment of the present invention.

Referring to FIG. 60 , the chip analysis apparatus may analyze a failure or defect location candidate of an IC chip using IC design data 6000 , original scan pattern data 6010 , and scan shift frequency characteristic data 6020 . The chip analysis apparatus may be implemented as a part of the host computer of FIG. 2 or 3 or may be implemented as a separate computing device.

First, let's look at the data used in this embodiment.

The IC design data 6000 includes circuit structure data of the IC chip, and may be gate-level netlist design data or physical layout design data.

The original scan pattern data 6010 is at least one scan pattern used for testing the IC chip.

Information on available frequencies for each scan section in which the scan pattern is divided may be information obtained by the salpin method in FIGS. 1 to 59 . Alternatively, the frequency available for each scan section may be information obtained through various conventional methods not disclosed in the present invention. In other words, in the present embodiment, the method of determining the available frequencies for each scan section is not limited to a specific method. In another embodiment, information on usable shift frequencies for each scan section may be predefined.

The scan shift frequency characteristic data 6020 may be information on usable frequencies of the scan section or analysis and statistical data based on the information. For example, statistical data such as the minimum or maximum shift frequency, the average of the minimum or maximum shift frequencies, the variance of the minimum or maximum shift frequencies, or the standard deviation of the minimum or maximum shift frequencies obtained for each scan section for a plurality of IC chips can In another embodiment, the scan shift frequency characteristic data 6020 may be information on a shift frequency hail hall generated between two shift frequency sections in which the scan test result is a pass. Also, the shift frequency characteristic data 6020 may be data using a shift frequency period (ie, shift clock period) value.

The scan shift frequency characteristic data to be used to identify a circuit part candidate capable of generating an IC fault or defect may vary according to embodiments. The chip analysis apparatus may select a scan section having a value corresponding to a predefined condition based on the scan shift frequency characteristic data 6020 as the scan section of interest in this embodiment to find the location of the circuit part that affects the yield, etc. . For example, the chip analysis apparatus may select the scan section having the largest value among the standard deviations of the maximum shift frequencies determined for each scan section of the plurality of IC chips as the scan section of interest. The circuit part activated by the selected scan section of interest in the design of the IC may be identified as a candidate for a circuit location that may cause an unstable or low yield, such as an IC fault caused by a process variation or the like.

The chip analysis apparatus may find a position of a circuit activated on the IC design by the scan section of interest selected based on the shift frequency characteristic data of the scan section through simulation or the like ( 6030 ). For example, the activated position in the IC chip may be a position of a circuit portion in which a bit value is changed when a scan section is input. Various conventional simulation methods for finding a circuit position activated in the IC chip when a scan pattern (or scan section) is input to the IC chip based on the IC design data may be applied to the present embodiment. The selected scan section (ie, the scan section of interest) may be an input scan pattern or part of an input scan pattern.

The chip analysis apparatus may output the position of the circuit part of the IC chip activated by the scan section of interest in the form of data or in the form of visualization as shown in FIG. 61 ( 6040 ).

By using the method of the present embodiment, there is an effect that the range of a circuit location to be checked for failure or defect cause analysis of a manufactured IC chip can be reduced. Therefore, it not only helps to locate the cause of the failure, but also has the advantage of reducing the time required to identify and solve the cause of the failure. In addition, when many fault location candidates are found in the IC design through various other methods, there is an advantage in that additional information can be obtained to more accurately find the actual fault location when the present embodiment is used together.

61 is a diagram illustrating an example of a method of visualizing and displaying a circuit part of an IC chip activated by a scan section according to an embodiment of the present invention.

Referring to FIG. 61 , when the scan section 6110 of interest is selected in the input scan pattern 6100, the chip analysis device determines the circuit position 6130 of the IC chip 6120 activated by the selected scan section 6110 of interest. figure out For example, the chip analysis apparatus may determine a position of a circuit part in which a bit value is changed when the scan section 6110 of interest is input to the IC chip 6120 based on the IC design data as an activated circuit position. The chip analysis apparatus may visualize and display the position 6130 of the circuit part activated based on the IC design data.

62 is a diagram illustrating a configuration of an example of a chip analysis apparatus according to an embodiment of the present invention.

Referring to FIG. 62 , the chip analysis apparatus 6200 includes a data analysis unit 6210 , a circuit location determining unit 6220 , and an output unit 6230 .

The data analysis unit 6210 analyzes information on available shift frequencies for each scan section to determine scan shift frequency characteristic data.

The circuit location determining unit 6220 selects a scan section of interest that satisfies a predefined condition based on the scan shift frequency characteristic data in order to identify a circuit part that may affect a failure or defect of the chip, and select the selected scan of interest The position of the circuit part of the IC chip activated by the section is determined based on the IC design data.

The output unit 6230 outputs the identified position of the circuit part in the form of data or visualizes and outputs it as shown in FIG. 61 .

The function for performing the present invention and scan shift frequency information obtained by performing the present invention or scan section information in which information is reflected can be implemented as computer readable codes or data on a computer readable recording medium. An example of the code is an executable computer program or software. The code or data may be executed or used on a device such as a scan test device, burn-in test device, or computer. The computer-readable recording medium includes all types of recording devices in which data readable by a computer system is stored. Examples of the computer-readable recording medium include various types of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, and optical data storage device.

In addition, the computer-readable recording medium may be distributed in network-connected computer systems to store and execute computer-readable codes or data in a distributed manner. In at least one embodiment of the present invention, the computer program code or data is stored on a server computer, and the client computer may access the server computer to use the code or data, or download it to the client computer for storage or use. For example, the program code may be executed on a server computer or a client computer.

So far, the present invention has been looked at with respect to preferred embodiments thereof. Those of ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments are to be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

Claims (14)

A method for generating searchable data used to find usable shift frequencies of a scan section used for IC chip testing, the method comprising:
If the number of frequency or timing identifiers that can be set or controlled by the IC chip test device is smaller than the number of scan sections dividing the input scan pattern, the input scan pattern is divided into at least two segments including at least one scan section. distinguishing; and
Including; generating a plurality of data for search corresponding to the number of segments;
The input scan pattern included in each of the plurality of data for retrieval consists of at least two scan sections to which timing identifiers equal to or less than the number of frequencies or timing identifiers that can be set or controlled by the IC chip test apparatus are assigned,
Timing identifiers assigned to each of the available frequency search target scan sections included in the input scan pattern in each of the plurality of search data are different from each other,
In each of the plurality of search data, a timing identifier assigned to a scan section other than the available frequency search target scan section included in the input scan pattern is different from a timing identifier assigned to the target scan section,
A shift frequency or a period of a shift frequency of the scan section included in the data for search can be set or changed using a timing identifier assigned to the scan section. The method of claim 1, wherein the generating of the search data comprises:
Allocating the same timing identifier to the scan sections included in at least one segment among the plurality of segments, and generating a plurality of search data in which at least one location of the segment to which all the same timing identifier is assigned is different from each other; includes; A method for generating data for search, characterized in that The method of claim 1, wherein the generating of the search data comprises:
Allocating the same timing identifier to some scan sections of at least two or more segments among a plurality of segments, and generating a plurality of data for retrieval in which at least one location of the scan sections to which the same timing identifier is assigned is different from each other; A method of generating data for search, characterized in that. The method of claim 1,
The plurality of data for search are divided by identifiers and are generated as one file. The method of claim 1,
In the search data, a Don't-care prediction pattern is defined as a prediction pattern for a pattern output from the IC chip when the first input scan pattern input to the test target IC chip is input to the IC chip. A method of generating data for search, characterized in that it is included together. The method of claim 1,
The search data includes a target input scan pattern including an available shift frequency search target scan section;
an input scan pattern input to the IC chip immediately before the target input scan pattern;
including an input scan pattern input to the IC chip immediately after the target input scan pattern,
A method for generating data for a search, comprising fewer input scan patterns than the total number of input scan patterns in the original scan pattern set. In the computer-readable recording medium on which a plurality of search data are recorded,
The number of retrieval data used to find an usable shift frequency of each of a plurality of scan sections dividing one input scan pattern depends on the number of frequency or timing identifiers that can be set or controlled by the IC chip test equipment and the number of input scan patterns. equal to the number of segments of the input scan pattern determined based on a difference in the number of scan sections dividing
Each of the plurality of search data,
first data including an input scan pattern composed of a plurality of scan sections configured to be sequentially input to a scan input port of the IC chip; and
and second data including information on a plurality of timing identifiers allocated to the plurality of scan sections;
The number of different timing identifiers allocated to the scan section included in the input scan pattern in each of the plurality of search data is less than or equal to the number of frequency or timing identifiers that the IC chip test apparatus can set or control,
A timing identifier assigned to a target scan section for which a shift frequency usable in the search data is to be found and a timing identifier of a scan section located before or after the target scan section are different from each other;
A computer-readable recording medium recording data for search, characterized in that the shift frequency or period of the shift frequency of the scan section included in the data for search can be set or changed using a timing identifier assigned to the scan section. 8. The method of claim 7,
The plurality of search data is characterized in that the same timing identifier is assigned to all scan sections included in at least one segment among the plurality of segments, and at least one or more positions of the segments to which all the same timing identifier are assigned are different from each other. A computer-readable recording medium on which data for retrieval is recorded. 8. The method of claim 7,
In the search data, a Don't-care prediction pattern is defined as a prediction pattern for a pattern output from the IC chip when the first input scan pattern input to the test target IC chip is input to the IC chip. A computer-readable recording medium on which data for retrieval is recorded, characterized in that it is included together. 8. The method of claim 7,
The plurality of data for search are divided by identifiers and stored as a single file. A computer-readable recording medium recording data for search. 8. The method of claim 7,
The search data includes a target input scan pattern including an available shift frequency search target scan section;
an input scan pattern input to the IC chip immediately before the target input scan pattern;
including an input scan pattern input to the IC chip immediately after the target input scan pattern,
A computer-readable recording medium for recording search data, characterized in that it includes input scan patterns that are less than the total number of input scan patterns in the original scan pattern set. If the number of frequency or timing identifiers that can be set or controlled by the IC chip test device is smaller than the number of scan sections dividing the input scan pattern, the input scan pattern is divided into at least two segments including at least one scan section. segment generating unit to distinguish; and
Including; a data generator for generating a plurality of data for search corresponding to the number of segments;
The input scan pattern included in each of the plurality of data for retrieval consists of at least two scan sections to which timing identifiers equal to or less than the number of frequencies or timing identifiers that can be set or controlled by the IC chip test apparatus are assigned,
Timing identifiers assigned to each of the available frequency search target scan sections included in the input scan pattern in each of the plurality of search data are different from each other,
In each of the plurality of search data, a timing identifier assigned to a scan section other than the available frequency search target scan section included in the input scan pattern is different from a timing identifier assigned to the target scan section,
A shift frequency or a period of a shift frequency of the scan section included in the data for retrieval can be set or changed using a timing identifier assigned to the scan section. 13. The method of claim 12,
and a data storage unit for classifying the plurality of search data by identifiers and storing the data in a single file. A computer-readable recording medium recording a computer program for performing the method according to any one of claims 1 to 6.

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