KR101923142B1 - Apparatus, method, and system for testing integrated circuit chip - Google Patents

Abstract

A scan test is performed in which a scan pattern is input to a scan path through a scan input port of an IC chip including a circuit to be tested and an output value outputted through a scan output port is compared with a predetermined predicted value to check whether or not an IC chip is defective An IC chip testing apparatus for performing a shift test shifts a target scan section to be searched for usable shift frequencies among at least two or more scan sections included in a set of scan patterns by a scan path so that a shift frequency And a shift frequency search unit for searching for the shift frequency. The shift frequency search unit may increase or decrease the shift frequency of the target scan section in the shift frequency search for the target scan section differently from at least one of the other scan sections that shift in the scan path, And searches for a shift frequency whose scan test result is normal or failed.

Description

[0001] The present invention relates to an IC chip testing apparatus, an IC chip testing method, and an IC chip testing system,

The present invention relates to an IC (Integrated Circuit) chip test apparatus, an IC chip test method, and an IC chip test system.

The most common method for testing an IC chip is to apply test data to the input of the IC chip and compare the output value of the IC chip with an expected value or an expected result (for example, , See Patent Document 1). However, in the case of an IC chip including a sequential logic having a storage element such as a flip-flop, a desired value is applied to the flip-flop in the IC chip from the outside or a value of the flip- It is not easy to detect at.

The scan design method is one of the design-for-testability (DFT) methods used to increase the controllability and observability of circuits. Using the scan design method, the ATPG (Automatic Test Pattern Generator) is used to automatically generate a test pattern based on the structural information of a circuit. The size of the test pattern is small and has a high fault coverage Test data can be obtained.

In other words, the scan design allows sequential logic to be combinational logic during scan test so that the circuit can be easily controlled and observed outside the chip, and the size of test data can be minimized through ATPG have. The test data obtained through the scan design and the ATPG software are composed of at least one scan pattern. The scan patterns may have an order in performing the scan test.

The general scan test procedure is as follows.

(1) Apply the main input test data to the main input port of the IC chip.

(2) Set the IC chip to the scan mode by applying a scan enable signal to the scan enable port.

(3) Load the scan pattern into the flip-flop on the scan path by shifting the scan pattern to the scan input port. In the present specification, there is a case where a shift-in from the scan input port or a shift-out from the scan output port is simply referred to as "shift ". The time interval (period) for shifting the scan pattern and the shift frequency are inversely related. The scan pattern loaded in the scan path is applied to the combinational circuit. After the scan pattern is applied to the combination circuit, the result output through the main output port is compared with the predicted main output value, and if the comparison result is different, the IC chip is judged as defective.

(4) Turn on the scan enable signal to switch the IC chip from scan mode to functional mode. In the functional mode, when a clock signal is applied, the flip-flop captures the output value of the combinational circuit. This operation is called scan capture, and the mode at this time is also referred to as a scan capture mode.

(5) Scan Activation The scan enable signal is applied to the port to switch the IC chip back from the functional mode to the scan mode.

(6) Then, the value captured in the flip-flop on the scan path is shifted out and unloaded through the scan output port.

(7) The unloaded output pattern is compared with a predicted pattern that is known beforehand to determine whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern that is output through the scan output port after the main input test data and the scan pattern are applied and the scan capture operation is performed when the IC chip is normal, and is a known value or a predicted result pattern before the test. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the IC chip is good because the test result is pass, otherwise the IC chip is defective. A test pass means a case in which the IC chip is judged to be fault-free, and a test failure means a case in which it is judged that there is an abnormality in the IC chip.

The types of scan tests are divided into stuck-at-fault test and delay fault test. In this case, a stuck-at fault refers to a state in which any signal line on the IC chip is inadvertently stuck to a logic 0 (logic 0) or logic 1 (logic 1) value, and a delay fault means a signal line or path path) of the IC chip due to the delay time when the signal value is transmitted through the IC chip.

Delayed fault tests include transition delay tests and path delay tests, also called at-speed tests. The transition delay test is to test whether a specific node or signal line on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem. The path delay test is to test whether a particular signal path on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem.

On-Capture and Launch-On-Shift methods are representative methods for delay fault test, and these methods also scan scan patterns for delay fault test And an unload operation for shifting out the delay fault test result captured in the flip-flop on the scan path.

In the case of such a scan test, the number of clock pulses for shifting by the number of flip-flops in the scan path is required. Therefore, there is a problem that it takes much time to shift-in and shift-out operation. However, in order to reduce the test time, the frequency of the clock signal for shifting the scan pattern to the scan path, that is, the shift frequency, can not simply be increased.

For example, when the scan shift frequency is simply increased, there is a problem of over kill in which a good product is determined as a defective product due to a power consumption or a critical path delay time problem.

In addition to the micro-fabrication process and the low-power manufacturing process as well as the low-power design, the IC chip is further reduced in power consumption, and the influence of the power supply noise on the IC chip operating frequency is further increased. In particular, since the IC chip generates more switching operation than the scan mode in the functional mode, additional delay of the signal line due to the power supply noise due to the switching operation can cause delay test overkill, There is a limit to it.

In addition, the problem of signal integrity due to signal crosstalk on the IC chip has become more important as it goes to DSM microprocessing. Interference among the signal lines can be further exacerbated by the switching operation which occurs frequently in the scan mode. Therefore, additional delay in the signal line due to inter-signal line interference in the delay test may cause delay test overkill.

In the case of finding the shift frequency based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, due to an excessive circuit switching operation and process variation This may cause scan test failure problems due to IR-drop or ground-bounce.

For example, in a delay test using a scan pattern, an additional delay may occur in a particular signal line due to the influence of IR-drop, i.e., voltage drop, which may cause a delay test overrun. Conversely, even if the power consumption of the scan pattern exceeds the specification of the IC chip, the IR-drop or ground-bounce problem may not occur due to the manufacturing process and design characteristics of the IC chip. Therefore, there is a limit to finding an optimal shift frequency for the IC chip by simply using the power consumption value. Also, when searching for the maximum shift frequency only by the power consumption value of the scan pattern, a critical path timing problem may occur on the scan path due to the increased shift frequency even if the power consumption value does not exceed the specification of the IC chip have.

In addition, if the shift frequency is increased, a critical path timing problem may occur on the scan path, but a logical problem due to the scan pattern may not occur. In other words, depending on the state of the bit value on the critical path of the scan path, a false critical path case may occur in a certain scan shift cycle.

For example, if two consecutive logical-0 bit values are shifted and stored in two flip-flops forming a critical path on the scan path, then a shift operation with a high shift frequency is stored in the flip-flop at the beginning of the critical path There may be a critical path delay time problem where the signal for the logical-0 bit value can not reach the next flip-flop in the normal time. However, a false critical path may occur in which a logical problem of bit values stored in two flip-flops forming a critical path does not occur due to a shift operation.

In addition, a low-power IC chip using a voltage island or voltage domain technique provides a high voltage in a design area requiring high-speed performance and a relatively low voltage in a non- As a result, the allowable power consumption differs for each voltage region.

Patent Document 1: Korean Patent Laid-Open Publication No. 10-2012-0102876

An object of the present invention is to provide an IC chip testing apparatus, an IC chip testing method, and an IC chip testing system capable of reducing test time and improving test quality and yield by optimizing the frequency of test data.

According to at least one embodiment of the present invention, a scan pattern is input to a scan path through a scan input port of an IC chip including a circuit to be tested, and an output value output through a scan output port is compared with a predetermined predicted value An IC chip testing apparatus for performing a scan test to check for the presence or absence of a defect in an IC chip, the IC chip testing apparatus comprising: a shift register for shifting a target scan section, which is intended to search for usable shift frequencies among at least two or more scan sections included in a set of scan patterns, And a shift frequency search unit for searching for a shift frequency in which the scan test result is normal or failed. The shift frequency search unit searches for a shift frequency of the target scan section in the scan frequency, Increase in at least one scan section Or shifts to another shift frequency to search for a shift frequency whose scan test result is normal or failed.

In at least one embodiment of the present invention, the shift frequency searcher is configured to determine whether the scan test result is changed from normal to failed, or a failure is detected while the shift frequency of the target scan section is increased or decreased, To search for the shift frequency of the region that changes from normal to normal.

In at least one embodiment of the present invention, the shift frequency searcher is configured to determine, at a search of the available shift frequency for the target scan section, a first scan test result obtained using the first shift frequency for the target scan section, The first shift frequency is determined as a usable shift frequency for the target scan section when the second scan test results obtained by using the first shift frequency and the second shift frequency for the previous one scan section are all normal .

In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

According to at least one embodiment of the present invention, a scan pattern is input to a scan path through a scan input port of an IC chip including a circuit to be tested, and an output value output through a scan output port is compared with a predetermined predicted value 1. An IC chip testing apparatus for performing a scan test for checking whether or not an IC chip is defective, comprising: a first test step of performing a test by shifting a first scan pattern including a first scan section to a scan path; And a second test step of performing a test by shifting a second scan pattern including a second scan section after the first scan section to a scan path to search for a usable shift frequency for the second scan section , The shift frequency search unit shifts the first scan section to the scan path at the first shift frequency in the first test step Shifts the second scan section to a scan path at a second shift frequency that is different from the first shift frequency in a second test step and at a shift frequency search that is available for the second scan section, And determines the second shift frequency as a usable shift frequency for the second scan section when the scan test result and the second scan test result of the second test step are both normal.

In at least one embodiment of the invention, the first scan section is a first scan pattern or a portion of a first scan pattern, and the second scan section is a second scan pattern or a portion of a second scan pattern.

In at least one embodiment of the present invention, the shift frequency searcher is configured to search for a shift frequency that is available for the second scan section, and at least one scan section among other scan sections that shift the second shift frequency to the scan path The shift frequency for the second scan section is retrieved by increasing or decreasing differently or setting it to another frequency.

In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

According to at least one embodiment of the present invention, a scan pattern is input to a scan path through a scan input port of an IC chip including a circuit to be tested, and an output value output through a scan output port is compared with a predetermined predicted value A method of testing an IC chip for use in an IC chip test apparatus for performing a scan test for checking the presence or absence of a defect in an IC chip, And a shift frequency search step of searching for a shift frequency whose scan test result is normal or failed by shifting a section of the target scan section to a scan path, Of the other scan sections shifting the scan path To one of the scan section and is increased or decreased, or otherwise set to a different shift frequency to provide, IC chip test comprises the step of scanning the test results searches for the normal or fail the shift frequency.

In at least one embodiment of the present invention, the shift frequency search process is performed in such a way that, upon search of the available shift frequency for the target scan section, the scan test results are changed from normal to failed while increasing or decreasing the shift frequency of the target scan section And searching for a shift frequency of a region that changes from failure to normal.

In at least one embodiment of the present invention, the shift frequency search process includes a first scan test result obtained using the first shift frequency for the target scan section and a second scan test result obtained using the first scan frequency for the target scan section, The first shift frequency is determined as a usable shift frequency for the target scan section when the second scan test result obtained by using the first shift frequency and the second shift frequency for any one of the scan sections before the section is normal .

In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

According to at least one embodiment of the present invention, a scan pattern is input to a scan path through a scan input port of an IC chip including a circuit to be tested, and an output value output through a scan output port is compared with a predetermined predicted value A method of testing an IC chip for use in an IC chip testing apparatus for performing a scan test for checking the presence or absence of a defect in an IC chip, the method comprising: a first step of performing a test by shifting a first scan pattern including a first scan section A second test step of performing a test by shifting a second scan pattern including a test step and a second scan section after the first scan section to a scan path is performed to search for a usable shift frequency for the second scan section And a shift frequency search process, wherein the shift frequency search process is performed in a first test step, Shifting the second scan section to a scan path at a second shift frequency different from the first shift frequency in a second test step and shifting the second scan section to a scan path at a shift frequency search available for the second scan section, And determining the second shift frequency as a usable shift frequency for the second scan section when the first scan test result of the first test step and the second scan test result of the second test step are both normal , And an IC chip test method.

In at least one embodiment of the invention, the first scan section is a first scan pattern or a portion of a first scan pattern, and the second scan section is a second scan pattern or a portion of a second scan pattern.

In at least one embodiment of the present invention, the shift frequency search process comprises at least one scan section of the other scan sections shifting the second shift frequency to the scan path during search of the available shift frequency for the second scan section, Includes searching for a shift frequency for the second scan section by increasing or decrementing the scan frequency differently or setting it to another frequency.

In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

According to at least one embodiment of the present invention, there is provided a method of testing a semiconductor device, comprising: a tester body for controlling a scan test of an IC circuit; a host computer embedded in or separately from the tester body; A test head for inputting a data signal, and an IC chip test apparatus according to any one of claims 1, 2, 5, and 6.

In at least one embodiment of the present invention, the host computer includes an IC chip test apparatus.

According to at least one embodiment of the present invention, there is provided a computer-readable recording medium having recorded thereon a program for performing an IC chip testing method according to at least one embodiment of the present invention.

According to at least one embodiment of the present invention, a method of testing an IC chip according to at least one embodiment of the present invention, comprising the steps of: A recording medium which can be read is provided.

According to at least one embodiment of the present invention there is provided a method of testing an IC chip according to at least one embodiment of the present invention, The test data is recorded on a computer-readable recording medium.

According to at least one embodiment of the present invention, there is provided a method for controlling a shift register, comprising the steps of: storing, in a recording medium, first data including bit pattern information of a target scan section for which a shift frequency usable for a scan test is sought; Storing second data including bit pattern information of the first scan section on a recording medium and storing third data including a target scan section and timing information of the first scan section on a recording medium And the timing information of the target scan section and the timing information of the first scan section are different from each other.

In at least one embodiment of the present invention, the timing information is information indicating the shift frequency of the bit pattern or the period of the shift frequency, or information for identifying a bit pattern for controlling the shift frequency or the cycle of the shift frequency.

According to at least one embodiment of the present invention, there is provided a method for searching a bitstream of a first scan section, which includes first data including bit pattern information of a target scan section for which a shift frequency usable for a scan test is searched, And a third data including a target scan section and timing information of the first scan section are recorded and the timing information of the target scan section and the timing information of the first scan section are different from each other, A recording medium which can be read is provided.

In at least one embodiment of the present invention, the timing information is information indicating the shift frequency of the bit pattern or the period of the shift frequency, or information for identifying a bit pattern for controlling the shift frequency or the cycle of the shift frequency.

According to the present invention, when shifting frequency is increased in consideration of power consumption or critical path delay time only in scan pattern, scan section or section group at the time of IC chip test, good product is judged as defective due to overshift frequency It is possible to provide an optimal shift frequency that can reduce the scan test time while solving the over kill problem.

In addition, it is possible to provide an optimum shift frequency in consideration of influence of power supply noise and influence of interference between signal lines at the time of IC chip test.

In addition, IR-drop or ground-bounce, which can be caused by excessive circuit switching operation by scan test during IC chip test, manufacturing process variation, microfabrication process, low power manufacturing process or low power design The optimum shift frequency can be provided by reflecting the influence.

In addition, it is possible to provide an optimum shift frequency in consideration of the influence of the critical path timing on the scan path that may occur when the shift frequency is increased during the IC chip test.

When the critical path of the scan path becomes a false critical path state according to the bit value on the scan path during the IC chip test, the critical timing constraint is ignored, and the scan shift By maximizing the frequency, the test time can be minimized.

In addition, higher-shift frequencies can be enabled by don't-care bits on the scan pattern set during IC chip testing. The money-care bits are bits that do not affect the outcome of the scan test.

Also, in the case of a low power IC chip using a voltage island or a voltage domain or region technique at the time of IC chip test, the optimum shift frequency Can be provided.

In addition, since the circuit design information of the IC chip is not required in finding the optimal shift frequency of the scan pattern or the scan section at the time of IC chip test, it is possible to obtain optimal Of the shift frequency.

In the IC chip test, a predetermined constant shift frequency such as a nominal shift frequency is initially allocated to all scan sections, and an optimal shift frequency for a scan pattern or a scan section in which power consumption or current consumption of each scan section is more than a certain level The processing time can be reduced as compared with the method of finding the optimal shift frequency for each of the entire scan patterns or scan sections.

In addition, it is possible to suppress the increase of the test time to solve the fail hole problem in which abnormal test fail occurs within the range of the shift frequency which should be the test path in the IC chip test. It is possible to suppress the fault coverage of the chip or the occurrence of the field escape problem in order to solve the fail hole problem.

In addition, stress or burn-in testing, which accelerates chip aging, can reduce test time and improve test quality. In addition, the time required for stress or burn-in testing can be accurately predicted and the quality of the stress or burn-in test can be accurately predicted.

In addition, the IC chip test can search for information for improving the yield or improve the yield.

1 is a conceptual diagram showing an example of an IC chip to which a scan design method is applied.
Figures 2 and 3 are block diagrams illustrating configurations of a chip test system in accordance with at least one embodiment of the present invention.
4 is a conceptual diagram illustrating an example of a scan pattern according to at least one embodiment of the present invention.
5 to 9 are conceptual diagrams showing a method of dividing test data according to at least one embodiment of the present invention.
10 is a graph illustrating the relationship between the number of scan sections and the scan test time reduction rate in accordance with at least one embodiment of the present invention.
11 is a conceptual diagram illustrating an example of assigning a shift frequency to each scan section in order to minimize the time of a chip test according to at least one embodiment of the present invention.
12 is a conceptual diagram illustrating an example of a method for finding a shift frequency in order to minimize the time of a chip test according to at least one embodiment of the present invention.
13 to 15 are conceptual diagrams illustrating an example of a pattern input to a scan path for determining a shift frequency according to at least one embodiment of the present invention.
16 is a graph illustrating an example of a method for finding a usable shift frequency of a scan pattern according to at least one embodiment of the present invention.
17 is a graph illustrating a case where a test result of another scan pattern fails when increasing or decreasing a shift frequency of a scan pattern to search for an optimal shift frequency according to at least one embodiment of the present invention.
FIGS. 18 to 20 are conceptual diagrams showing an example of a configuration of a scan pattern, a scan section, and shift frequency information necessary for finding an optimal shift frequency according to at least one embodiment of the present invention.
21 to 28 are conceptual diagrams showing various examples of a method for generating search data according to at least one embodiment of the present invention.
29 is a flow chart illustrating an example of a method for minimizing the time of a chip test according to at least one embodiment of the present invention.
30 is a flowchart illustrating another example of a method for determining an optimal shift frequency for each scan section in order to minimize the time of a chip test according to at least one embodiment of the present invention.
31 is a flow chart illustrating an example of a more specific process of a method for minimizing the time of a chip test according to at least one embodiment of the present invention.
FIG. 32 is a flowchart illustrating an example of a concrete process of determining whether a test is normal in a method of minimizing a time of a chip test according to at least one embodiment of the present invention.
33 is a flow chart illustrating another example of a method for minimizing the time of a chip test according to at least one embodiment of the present invention.
34 is a block diagram illustrating the configuration of an apparatus for minimizing chip test time according to at least one embodiment of the present invention.
35 is a conceptual diagram illustrating an example of a method for finding or determining an optimal shift frequency of a plurality of scan sections in parallel in accordance with at least one embodiment of the present invention.
36 is a conceptual diagram showing an example of a method of rearranging scan patterns in order to minimize the time of a chip test according to at least one embodiment of the present invention.
37 and 38 are block diagrams showing the configuration of a burn-in test system according to at least one embodiment of the present invention.
FIG. 39 is a conceptual diagram showing an example of the temperature effect on the IC chip when the burn-in test is performed using a single scan shift frequency according to at least one embodiment of the present invention.
FIG. 40 is a conceptual diagram showing an example of a temperature effect on an IC chip when a burn-in test is performed using an optimal shift frequency for each scan pattern according to at least one embodiment of the present invention.
FIG. 41 is a thermal image showing the heat generation state of the IC chip during the scan shift operation when the shift frequency for each scan section is not optimized and when the shift frequency is optimized.
FIG. 42 is a graph showing an example of power consumption that occurs during the burn-in test before the power consumption of the test data is adjusted.
FIG. 43 is a graph showing an example of power consumption that occurs during the burn-in test after the power consumption of the test data is adjusted.
44 is a flowchart illustrating an example of a method for finding an optimal shift frequency for each scan section in order to minimize the time of the burn-in test according to at least one embodiment of the present invention.
45 is a block diagram illustrating an example of a burn-in test time minimization apparatus in accordance with at least one embodiment of the present invention.
FIG. 46 is a table showing a comparison between the shift frequency at the time of approaching the threshold power consumption of the IC chip for each scan pattern and the experimental result for the optimized shift frequency through the shift frequency increasing / decreasing method.
47 is a graph showing an example of a test fail hole that can be generated in the IC chip test.
48 is a graph showing an example of a method for solving the test fail hole problem according to the present invention.
Figure 49 is a flow diagram of a method for solving the fail hole problem in accordance with at least one embodiment of the present invention.
50 is a graph illustrating another example of a method for solving the fail-hole problem according to at least one embodiment of the present invention.
51 is a graph illustrating a method for finding a shift frequency for test time reduction and yield improvement in accordance with at least one embodiment of the present invention.

Hereinafter, a method and apparatus for minimizing scan test time according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing an example of an IC chip to which a scan design method is applied.

In the example of Fig. 1, the IC chip 100 includes a combination circuit 110 and a sequential logic. The sequential logic is composed of a plurality of flip-flops 120, 130 and 140. Each of the flip-flops 120, 130, and 140 may be implemented in various ways including a multiplexer (MUX) type scan flip-flop.

The IC chip 100 includes a primary input port (PI) 150, a primary output port 152, a scan enable (SE) port 160, a scan input port 162 A clock input port 164, a scan output port 166, and the like. The scan enable port 160 and the clock input port 164 are connected to the flip-flops 120, 130 and 140. Each of the flip-flops 120, 130, and 140 is connected to the combinational circuit 110 to output the value stored in each flip-flop to the combinational circuit, and can receive the value output from the combinational circuit.

The main input port 150 and the main output port 152 are ports for inputting and outputting data during normal operation of the IC chip, respectively.

The scan enable port 160 is a port for inputting a scan enable signal or a scan inactivate signal. The scan enable signal or the scan inactivation signal is applied to a normal mode (or a functional mode ) Or a scan mode in which the IC chip is tested.

The scan input port 162 is a port for inputting a scan pattern for testing the IC chip 100 and the scan output port 166 is a port for outputting a test result based on a scan pattern. The bit pattern output through the scan output port is referred to as an output scan pattern, an output pattern, or a scan test result pattern.

The clock input port 164 shifts the scan pattern input through the scan input port 162 to the flip-flops 120, 130 and 140 or captures the output of the combinational circuit 110 and outputs the scan pattern to the flip-flops 120, 130 and 140 It is a port for inputting a clock signal for triggering so that it can be stored. For example, the flip-flops 120, 130, and 140 are triggered by a rising edge or a falling edge of a clock signal input through the clock input port 164.

A path (dotted line path) connected from the scan input port 162 to the scan output port 166 through the plurality of flip flops 120, 130 and 140 is referred to as a scan chain or a scan path. Although FIG. 1 illustrates a single scan path, a plurality of scan paths may be used.

In the functional mode, the combinational circuit 110 receives data via the main input port 150 and performs the operation of outputting the result through the main output port 152. In addition, in the functional mode, the flip-flops 120, 130 and 140 receive the output value of the combinational circuit 110 according to the clock signal, and during the scan test, this operation is called scan capture.

In the scan mode, each bit of the scan pattern is sequentially shifted to the flip-flops 120, 130 and 140 existing in the scan path according to the clock signal, and sequentially shifted through the scan output port 166 Out (Shift-Out). A state in which the scan patterns are shifted to the flip-flops 120, 130 and 140 is referred to as a load and a state in which the values stored in the flip-flops 120, 130 and 140 are shifted out through the scan output port 166 is referred to as unload do.

For example, if the number of the flip-flops 120, 130, 140 on the scan path in the IC chip is three, the length of each scan pattern is made up of the same 3-bit length as the number of flip- And are sequentially shifted to the flip-flops 120, 130, and 140 on the scan path according to the signals.

That is, when the value is stored in the flip-flop at the rising edge of the clock signal, the first bit of the scan pattern is stored and input to the first flip-flop 140 at the rising edge of the first clock signal, The output value of the first flip-flop 140 is stored in the second flip-flop 130 and the second bit value of the scan pattern is stored in the first flip-flop 140. At the rising edge of the third clock signal, the output value of the second flip-flop 130 is stored in the third flip-flop 120 and the output value of the first flip-flop 140 is stored in the second flip- And the third bit value of the scan pattern is stored in the first flip-flop 140. Thus, one scan pattern is loaded into the flip-flops 120, 130, and 140 on the scan path with three clock signals. Similarly, the values of the flip-flops 120, 130, and 140 on the scan path are unloaded through the scan output port 166 with three clock signals.

The scan test process will be described in more detail as follows.

(1) Main input test data is applied to the main input port 150 of the IC chip 100.

(2) The scan activation signal is applied to the scan activation port 160 to set the IC chip 100 to the scan mode.

(3) The scan pattern is shifted to the scan input port 162 to load the scan pattern into the flip flops 120, 130, and 140 on the scan path. The scan pattern loaded in the scan path is applied to the combinational circuit 110. After the scan pattern is applied to the combination circuit, the result output through the main output port 152 is compared with the predicted main output value, and if the comparison result is different, it is determined that the IC chip is defective.

(4) A scan inactivation signal is applied to the scan enable port 160 to switch the IC chip 100 from the scan mode to the functional mode. In the functional mode, when a clock signal is applied, the flip-flops 120, 130 and 140 capture the output value of the combinational circuit 110, and this operation is referred to as a scan capture, which is also referred to as a scan capture mode.

(5) The scan enable signal is applied to the scan enable port 160 to switch the IC chip back from the functional mode to the scan mode.

(6) Then, the values captured in the flip-flops 120, 130 and 140 on the scan path are shifted out and unloaded through the scan output port 166.

(7) The unloaded output pattern is compared with a predicted pattern that is known beforehand to determine whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern output through the scan output port 166 after applying the main input test data and the scan pattern when the IC chip is normal and performing the scan capture operation, to be. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the IC chip is good because the test result is pass, otherwise the IC chip is defective. A test pass means a case in which the IC chip is judged to be fault-free, and a test failure means a case in which it is judged that there is an abnormality in the IC chip.

2 and 3 are block diagrams respectively showing configurations of an embodiment of an IC chip test system called ATE (Automatic Test Equipment) to which the present invention is applied.

2 and 3, the chip test system includes a host computer 200, 300, a tester body 210, 310, a test head 220, 320, and an interface board 230, 330. A device under test (DUT) (240, 340) located on an interface board for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on the wafer, it may further include a prober 350. Hereinafter, an IC circuit, an IC chip on a wafer, or a packaged IC chip is collectively referred to as an IC chip or a chip for convenience of explanation.

The tester bodies 210 and 310 control the scan test as a whole. For example, the tester body controls overall processes such as setup for DUT testing, generation of electrical signals for DUT testing, observation and measurement of DUT test result signals, and the like. The tester bodies 210 and 310 may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and may include a device power supply device Power Supply).

The tester main bodies 210 and 310 include a controller for controlling a signal processing processor (DSP) (not shown) for processing various digital signals and the test heads 220 and 320, a controller for applying a signal to the DUTs 240 and 340, Dedicated hardware, such as a generator, software or firmware, and the like. The tester bodies 210 and 310 may also be referred to as a mainframe or a server.

The host computer 200, 300 can be a computer such as a personal computer, a workstation, or the like, and is a device that enables a user to execute a test program, control a test process, and analyze test results. In general, the host computers 200 and 300 may include a central processing unit, a storage device such as a memory or a hard disk, a user interface, and the like, and may be connected to the tester bodies 210 and 310 through wired or wireless communication. The host computer 200, 300 may include dedicated hardware, software, or firmware for controlling the test. Although the host computer and the tester main body are shown separately in this embodiment, the host computers 200 and 300 and the tester main bodies 210 and 310 may be implemented as a single device.

An example of the memory of the tester main body 210 or 310 or the host computer 200 or 300 may be a DRAM, an SRAM, a flash memory, or the like, and the memory may store programs and data for performing the DUT test.

Software or firmware of the tester main body 210 or 310 or the host computer 200 or 300 is a device driver program, an operating system (OS) program for a scan test, a program for performing a DUT test, a setup for a DUT test, a DUT test And the like, and may be stored in a memory in the form of an instruction code for performing observation analysis of the DUT test result signal, and may be performed by the central processing unit. Therefore, the scan pattern can be applied to the DUT by such a program. It is also possible to obtain the DUT test and the reporting and analysis data of the test result automatically through the program. The language used in the program can be a variety of languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The central processing unit of the tester main body 210 or 310 or the host computer 200 or 300 is a processor and executes the code of the software or program stored in the memory. For example, when receiving a user command through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes the command through a software or a program, and outputs the result to a user interface such as a speaker, To the user.

The user interface of the tester main body 210, 310 or the host computer 200, 300 allows information to be communicated between the user and the device and to communicate commands. For example, there are an interface device for user input such as a keyboard, a touch screen, a mouse and the like, and an output interface device such as a speaker, a printer, and a monitor.

The test heads 220 and 320 include channels for electrical signal transmission between the tester main bodies 210 and 310 and the DUTs 240 and 340. Interface boards 230 and 330 are provided on the test heads 220 and 320, respectively. The interface board used to test the packaged IC chip is generally referred to as a load board. The interface board used for IC chip testing on a wafer is generally referred to as a probe card.

In at least one embodiment of the present invention, the host computer 200, 300 includes an IC chip test apparatus 250, 360.

In at least one embodiment of the present invention, the IC chip testing apparatus (250, 360) shifts the target scan section, which is intended to search for usable shift frequencies among at least two or more scan sections included in the set of scan patterns, And shift frequency search units 251 and 361 for searching shift frequencies whose test results are normal or failed.

The shift frequency search sections 251 and 361 may increase or decrease the shift frequency of the target scan section in the shift frequency search for the target scan section differently from at least one of the other scan sections that shift in the scan path, Set the frequency to search for the shift frequency where the scan test result is normal or failed.

The shift frequency search units 251 and 361 search the available scan frequency for the target scan section to determine whether the shift frequency of the target scan section is increased or decreased while the scan test result is changed from normal to failed Search for the shift frequency.

The shift frequency search units 251 and 361 are configured to perform a shift frequency search for a target scan section by using a first scan test result obtained using a first shift frequency for a target scan section and a scan The first shift frequency is determined as a usable shift frequency for the target scan section when the second scan test result obtained by using the second shift frequency different from the first shift frequency for the section is normal.

In at least one embodiment of the present invention, the IC chip testing apparatus 250, 360 includes a first test step of performing a test by shifting a first scan pattern including a first scan section to a scan path, And a second test step of performing a test by shifting a second scan pattern including a second scan section of the first scan section to a scan path to search for a usable shift frequency for the second scan section Respectively.

The shift frequency search sections 251 and 361 shift the first scan section to the scan path at the first shift frequency in the first test step and shift the second scan section to the second shift frequency at the second shift frequency And when the first scan test result of the first test step and the second scan test result of the second test step are both normal at the search of the available shift frequency for the second scan section, The shift frequency is determined to be a shift frequency usable for the second scan section.

In at least one embodiment of the invention, the first scan section is a first scan pattern or a portion of a first scan pattern, and the second scan section is a second scan pattern or a portion of a second scan pattern.

The shift frequency search sections 251 and 361 may increase or decrease the second shift frequency differently from at least one of the other scan sections shifting the scan frequency in the scan path at the search of the available shift frequency for the second scan section The shift frequency for the second scan section is searched for by setting to another frequency.

2 and 3, the IC chip testing apparatuses 250 and 360 are included in the host computers 200 and 300. However, the IC chip testing apparatuses 250 and 360 may be included in a separate computer having a processor, And may be connected to the bodies 210 and 310 to perform functions.

The test system of FIG. 2 and FIG. 3 is merely an example for facilitating the understanding of the present invention, and each of the configurations may be integrated into one unit, or one unit may be divided into a plurality of units. Various design variations are possible.

The scan pattern means a bit pattern input to the scan path for performing a scan test, or a bit pattern output from the scan path.

The bit length of the scan pattern is the length of the bit pattern necessary for one scan test operation. For example, the bit length of the scan pattern may be equal to the bit length of the bit pattern shifted in the scan path until the scan capture operation is performed. As another example, the bit length of the scan pattern may be equal to the number of bit storage elements, such as flip flops, on the scan path. The bit length of the scan pattern is not limited to the above description, and may be variously set according to the scan test circuit.

The embodiments of the present invention can be applied not only to the IC chip of FIG. 1 but also to various kinds of chips that shift the bit pattern to the scan path and shift out the output pattern from the scan path.

For example, embodiments of the present invention may be applied to various types of chips, including circuits that can perform operations to shift scan patterns to a scan path, scan capture operations, and shift out captured bit patterns Can be applied.

4 is a conceptual diagram illustrating an example of a scan pattern that may be applied to a chip test according to at least one embodiment of the present invention.

Referring to FIG. 4, shift in and shift out operations are simultaneously performed in order to reduce the time required for performing the shift in operation and the shift out operation in the scan mode, respectively. That is, the load and unload operations are performed simultaneously.

For example, when the input pattern K 430 is shifted in the scan path via the scan input port, the test result by the input pattern K-1 400 is simultaneously shifted out through the scan output port and unloaded . At this time, the unloaded output pattern is compared with the predicted pattern K-1 (440) for the input pattern K-1 (400). Generally, the predicted pattern K-1 440 and the input pattern K 430 for the input pattern K-1 400 can be managed in pairs in the test data or the file.

In at least one embodiment of the present invention, the input pattern K 430 shifted through the scan input port and the input pattern K-1 400 (FIG. 4) are shifted in order to scan test by overlapping the shift- (440) are managed as a pair. As such, the scan patterns can have an order with respect to each other. Depending on the embodiment, the scan patterns may be rearranged in various ways in an unordered manner.

In at least one embodiment of the present invention, the output pattern that is shifted out simultaneously when shifting the first scan pattern to the scan path may be a don't-care pattern or a scan path state by reset of the chip under test Lt; / RTI >

Another way to minimize scan test time is to reduce the total number of scan patterns for the scan test and to increase the scan shift speed.

Here, increasing the scan shift speed means increasing the shift frequency of the scan pattern shift or shift-out, or decreasing the cycle of the shift frequency. Lowering the scan shift speed means lowering the shift frequency or increasing the cycle of the shift frequency. Also, optimizing the scan shift speed means optimizing the shift frequency or optimizing the shift frequency period.

Each of the increase and decrease of the shift frequency is substantially the same as the decrease or increase in the cycle of the shift frequency. Therefore, for convenience of explanation, a method of minimizing the scan test time will be described mainly from the viewpoint of increasing or decreasing the shift frequency. Therefore, even if there is no explicit description below, the frequency increase or decrease can be interpreted as a decrease or increase in the cycle of the frequency, and a decrease or increase in the frequency cycle can be interpreted as an increase or decrease in the frequency. The period of the frequency may also be referred to simply as the period and may be referred to as the clock period of the input clock.

5 to 9 are conceptual diagrams illustrating various examples of a method for dividing test data into at least one scan section in order to minimize the time of a chip test according to at least one embodiment of the present invention.

5, the bit pattern of the test data 500 shifted in the scan path is divided into a plurality of scan sections 510, 512, 514, 516 and 518 for testing the IC chip, and an optimal shift frequency for each scan section 510, 512, 514, 516 and 518 is found It can be applied during scan test to save time for scan test.

In at least one embodiment of the present invention, the bit pattern 500 of test data may be composed of a plurality of scan patterns as shown in FIG.

Referring to FIG. 6, a plurality of scan patterns may be used for testing an IC chip. The scan section may be constituted by at least one scan pattern or a part of the scan pattern, and an optimal shift frequency may be found for each scan section to apply the scan frequency during the scan test, thereby further saving the scan test time.

In the first embodiment, the scan section 600 includes one scan pattern and may correspond to a scan pattern one-to-one. That is, the scan pattern may be a scan section.

In a second embodiment, the scan section 610 may include two scan patterns. The number of scan patterns included in the scan section may be variously changed according to the embodiment.

In the third embodiment, the scan section 620 may be composed of a part of the first scan pattern and a part of the second scan pattern.

In the fourth embodiment, the scan section 630 may be configured as a part of one scan pattern.

In a fifth embodiment, one scan pattern may be divided into two scan sections 640, 650. The number of scan sections included in one scan pattern can be variously changed according to the embodiment.

The test data can be divided by any one of the above-mentioned various embodiments (600, 610, 620, 630, 640, and 650) as well as two or more of these embodiments. For example, the test data composed of N scan patterns shown in FIG. 6 includes a first scan section 600 including one scan pattern, a second scan section 610 including two scan patterns, And third and fourth scan sections 640 and 650, which include a portion of the first and second scan sections 640 and 650, respectively.

Referring to FIG. 7, an interval having the same and continuous bit values in the bit pattern of the test data 700 may be divided into scan sections 702, 704, 706, 708, and 710. If the same bit value is successively shifted to the scan path, the bit value switching activity of the scan path is reduced and the power consumption is reduced, so that a high shift frequency can be assigned to the scan section having successive bit values.

For example, the test data 700 may be divided into at least one or more scan sections 702, 704, 706, 708, and 710, based on the boundary where the bit values in the bit pattern of the test data 700 change from 0 to 1 or from 1 to 0 . Or M (M is an integer) bits within a section 710 of a continuous bit pattern of 0 or 1 bit values may be grouped into the scan sections 720 and 722. [

As another example, if the length of the section having the same and continuous bit values in the bit pattern of the test data is shorter than a predetermined length, the section is divided into the scan sections and the at least two sections 702 and 704 are grouped into one scan section (703).

Referring to FIG. 8, the scan section 810 may be divided into a plurality of sub scan sections 812 and 814 again. For example, the scan section 810 having a relatively low optimal shift frequency among the optimal shift frequencies found for the scan sections 810 and 820 is divided again into a plurality of sub scan sections 812 and 814, divided sub scan sections 812 and 814, The optimal shift frequency can be found again.

Referring to FIG. 9, the number of scan sections to divide the test data into the test data (900, 910) in consideration of the estimated time (hereinafter referred to as "expected time") required for finding the optimal shift frequency to be applied to each scan section Can be determined. As the number of scan sections increases, the estimated time required to find the optimal shift frequency of the entire scan section increases. The estimated elapsed time can be calculated by a predetermined formula indicating the relationship between the number of scan sections and the estimated elapsed time.

In the example of FIG. 9, if there is a constraint condition of A time that can be used to find the optimal shift frequency, the number N of scan sections to divide the test data 900 is determined so that the expected elapsed time may be less than A time. If there is a constraint of B time (A> B) that can be used to find the optimal shift frequency, the number M (N> M) of scan sections to divide the test data 910, Is determined.

When the number of test data 900 to be divided is determined to be N, the test data 900 is divided into N determined scan sections. For example, a method of dividing test data 900 into N scan sections having equal bit lengths, a section having the same and continuous bit values as shown in FIG. 7 is divided into scan sections, where the number of sections is N And a method of dividing the image only until it is opened.

The following information may be used to calculate the estimated time required:

- Start frequency for finding the optimum shift frequency

- End frequency to find the optimal shift frequency

- Frequency increase / decrease unit for finding the optimum shift frequency

- Frequency increase / decrease method to search for optimum shift frequency (increase / decrease frequency continuously or increase / decrease by binary search method)

- Number of scan patterns included in test data (SPN)

- Bit length of scan pattern (SBL)

- The method of dividing test data into scan sections or criteria (such as dividing by a certain bit length, dividing by a certain number, or dividing by the boundary where bit values change)

- Number of scan sections (SSN)

- How to find the optimal shift frequency The performance of the implemented device (eg, processor performance (CPU speed, etc.), memory and hard disk capacity and speed, etc.)

- Finding the optimum shift frequency Other margin time considering the data input / output time of the implemented device

In at least one embodiment of the present invention, an example of a formula for calculating the expected time period is given by the following mathematical expression: < RTI ID = 0.0 > It is like the expression.

Here, SSN is the number of scan sections, SPN is the number of scan patterns, SBL is the bit length of the scan pattern, SFP is the period of the shift frequency, and FN is the number of shift frequencies for finding the optimal shift frequency per scan section.

In Equation (1), if the expected time is given, the number of scan sections can be determined by satisfying the expected time.

10 is a graph illustrating the relationship between the number of scan sections and the scan test time reduction rate in accordance with at least one embodiment of the present invention.

Referring to FIG. 10, the number of scan section divisions of test data can be determined using the number of scan sections or the transition information of the scan test time reduction rate according to the method of dividing scan sections. As the number of scan sections with optimized shift frequencies increases, the time reduction rate of scan tests using test data can be increased.

In FIG. 10, the vertical axis represents the reduction rate of the scan test time required when using the optimal shift frequency for each scan section, compared to the scan test time required when using a single shift frequency for all the test data. The abscissa represents the number of scan sections in which the shift frequency is optimized.

As the number of scan sections dividing the test data increases, the average bit length of the scan sections becomes shorter. As the bit length of the scan section is shortened, the optimum shift frequency becomes higher and the scan test time can be shortened.

The various division methods of the scan scan section are various embodiments for facilitating understanding of the present invention, but the present invention is not limited to the respective methods of FIGS. In addition to the methods shown in Figs. 5 to 10, various methods of dividing test data can be applied.

11 is a conceptual diagram illustrating an example in which a shift frequency is allocated to each scan section in order to minimize a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 11, a plurality of shift frequencies are allocated to each scan section. In the case of the conventional scan test, a single shift frequency is used which can normally shift all the scan patterns of the test data to the scan path of the IC chip. Such a single shift frequency is also referred to as a nominal shift frequency.

In general, the nominal shift frequency may be a shift frequency used when making a scan pattern with the ATPG software, or a shift frequency slightly adjusted based on the shift frequency, and all the scan patterns for testing the IC chip may be normally shifted to the scan path of the IC chip (E. G., About 5 MHz) as a single frequency.

Therefore, when the nominal shift frequency is used as it is in the thousands to tens of thousands of scan patterns constituting the test data, the scan test time is considerably long. In particular, the IC chip cost and the time-to- market can have a significant impact. For example, assuming that it takes two seconds to test one IC chip, testing sequentially 10 million chips will take about 5,556 hours, or about 231 days. Even if expensive chips are used to test several chips at the same time, it takes a lot of time to test them. Typically, IC chip test service companies charge a fee in proportion to the number of test equipment used and test time, so the chip test time can have a significant impact on chip cost.

However, when the nominal shift frequency is increased, the power consumption occurring when shifting or shifting the scan pattern is out of the power consumption range allowed by the IC chip, so that the normal scan test can not be performed. In addition, due to the overshift frequency, there may occur an over kill problem in which a good product is determined to be a defective product due to a critical path delay time problem, an increase in power supply noise influence, and an increase in influence of interference between signal lines. This can have an important effect on the yield and cost of mass production of IC chips.

Therefore, the present embodiment does not apply a single shift frequency such as a nominal shift frequency to the entire scan pattern, but allocates an optimal shift frequency that can be normally shifted to the scan path for each scan section. The process of finding the optimal shift frequency for each scan section will be described in more detail with reference to FIG. The optimal shift frequency means a shift frequency that is less than or equal to the maximum shift frequency available for the scan section.

In the example of FIG. 11, the scan section 1 is assigned shift frequency A and the scan section 2 is assigned shift frequency B. And scan section 3 is assigned the same shift frequency A as scan section 1. [ As such, each scan section may be assigned the same shift frequency or may be assigned a different shift frequency.

For example, when one scan pattern is divided into a plurality of scan sections, a plurality of shift frequencies may be assigned to one scan pattern. Referring to FIG. 6, two scan sections 640 and 650 belonging to one scan pattern can be assigned different shift frequencies. That is, two shift frequencies are assigned to one scan pattern.

Each scan section assigned shift frequency may be integrated into a section group according to an embodiment. For example, the second scan section and the third scan section may be grouped into a section group, and a smaller shift frequency of the shift frequencies A and B of each scan section or less may be assigned to the corresponding section group.

The main input test data may be applied to the main input port during the scan test and the test result observation at the main output after the scan pattern input to the scan path may or may not be applied to the chip test process of the following embodiments.

12 is a conceptual diagram illustrating an example of a method for finding a shift frequency for minimizing a scan test time according to at least one embodiment of the present invention.

First, the relationship between the input pattern, the scan section, the scan pattern, and the output pattern will be described.

The input patterns 1202, 1204, and 1206 are bit patterns that are input to the scan path 1210. In FIG. 12, the scan section K, which is the current shift frequency determination target, corresponds to the input pattern K 1204 in one-to-one correspondence. The bit pattern located before or after the input pattern K 1204 including the scan section K (hereinafter referred to as the target scan section K) for which an optimum shift frequency is sought or to be determined is determined by the auxiliary scan section or the auxiliary bit Pattern.

(An input pattern when the scan section and the scan pattern correspond one-to-one)

The input pattern K-1 1202, the input pattern K 1204, and the input pattern K + 1 1206 correspond to the scan pattern M-1, One-to-one correspondence with the scan pattern M and the scan pattern M + 1.

(Output pattern K when the scan section and the scan pattern correspond one-to-one)

The output pattern of the scan path 1210 for the target scan section K 1204 corresponds to the output pattern K of the scan path 1210 for the scan pattern M when the target scan section K 1204 corresponds one- (1224). The output pattern K 1224 may be a scan capture result pattern for the target scan section K 1204 or a pattern in which the scan pattern M is output as is from the scan path.

(Output pattern K-1 when the scan section and the scan pattern correspond one-to-one)

The output pattern of the scan path for the input pattern K-1 1202 corresponds to the output pattern K-1 of the scan path for the scan pattern M-1 when the target scan section K 1204 corresponds one- 1222). The output pattern K-1 1222 may be a scan capture result for the scan pattern M-1 or a pattern in which the scan pattern M-1 is directly output from the scan path.

(Output pattern K + 1 when the scan section corresponds to the scan pattern one-to-one)

The output pattern of the scan path for the input pattern K + 1 1206 is the output pattern K + 1 of the scan path for the scan pattern M + 1 when the target scan section K 1204 is one-to-one correspondence with the scan pattern M . The output pattern K + 1 may be a scan capture result pattern for the scan pattern M + 1 or a pattern in which the scan pattern M + 1 is directly output from the scan path.

(Input patterns K-1 and K + 1 when the scan section is part of the scan pattern)

For example, referring to Fig. 14, when the target scan section K (1204) is a part of the scan pattern M, the input pattern K-1 1202 includes the scan pattern M- 1204). ≪ / RTI > The input pattern K + 1 1206 may include a scan pattern M + 1 and a portion other than the scan section K 1204 in the scan pattern M. [

(Output pattern K when the scan section is part of the scan pattern)

14, the output pattern K (1224) of the scan path for the target scan section K (1204) is used as the scan pattern for the target scan section 1204 when the target scan section K (1204) A result pattern, or a scan capture result pattern for a scan pattern M including a scan section K. [ Alternatively, the output pattern K 1224 may be a pattern in which the scan section K 1204 is directly output from the scan path or a pattern in which the scan pattern M including the scan section K 1204 is directly output from the scan path.

(Output patterns K-1 and K + 1 when the scan section is part of the scan pattern)

When the target scan section K 1204 is a part of the scan pattern M as shown in FIG. 14, the output pattern K-1 1222 of the scan path for the input pattern K-1 1202 corresponds to the scan pattern M- Output pattern, or an output pattern for a part of the scan pattern M-1 and the scan pattern M. The output pattern K + 1 of the scan path for the input pattern K + 1 1206 may be an output pattern for the scan pattern M + 1, or an output pattern for the scan pattern M + 1 and a portion of the scan pattern M. As another example, the output pattern of the scan path for a part of the scan pattern M included in the input pattern K-1 1202 or the input pattern K + 1 1206 may be a scan pattern M including the target scan section K 1204 May be reflected in the output pattern of the scan path to the scan path. As another example, the output pattern for the input pattern K-1 1202 or the input pattern K + 1 1206 may be such that the input pattern K-1 1202 or the input pattern K + 1 1206 is directly output from the scan path Pattern.

(If the scan section spans a plurality of scan patterns)

For example, referring to FIG. 15, the target scan section K 1204 may span a plurality of scan patterns. In this case, the input pattern K-1 1202 may include a portion excluding the portion of the target scan section K 1204 in the scan pattern M-1, and the input pattern K + 1 1206 may include the scan pattern M + 1 The portion of the target scan section K 1204 may be omitted. In this case, it is possible to separately grasp the optimal shift frequency for each portion of the target scan section K (1204) that spans each scan pattern, and determine the optimal shift frequency that can be assigned to the target scan section K (1204) .

The present invention is not limited to this example. The scan pattern may be divided into various types of scan sections as described with reference to FIGS. 5 to 10. The scan pattern may be divided into various types of scan sections according to the division pattern of the scan section, the input pattern K, May also vary. That is, the input pattern K-1 1202 or the input pattern K + 1 1206 may include at least one scan section.

FIG. 12 illustrates an example of a method for minimizing a scan test time when the shift in and shift-out operations illustrated in FIG. 4 are performed in an overlapping manner. FIG. 12 illustrates one example according to the present invention, and the present invention is not limited to the case where shift in and shift out described in FIG. 4 are simultaneously performed.

In the IC chip scan test, the test result pattern 1220 for the input pattern 1200 is compared with the predicted pattern 1230 to determine whether the test is normal. That is, the input pattern 1200 is loaded into the scan path 1210 and then the result pattern 1220 obtained by performing the capture operation is unloaded, or the input pattern is loaded and unloaded without performing the capture operation, and the predicted pattern 1230 and the unloaded The result pattern 1220 is compared to determine whether the test is normal.

In at least one embodiment of the present invention, for shift frequency optimization for a scan pattern or scan section, the output pattern shifted out simultaneously (or sequentially) when the target scan pattern or the target scan section is shifted to the scan path is also normal . For example, even if the target scan pattern or the target scan section is normally shifted to the scan path at the increased shift frequency, an error may occur in the test result pattern for the previous input pattern shifted out at the increased shift frequency.

In the example of FIG. 12, the input pattern K-1 1202 and the input pattern K + 1 1206 are used to check whether the scan section K 1204, which is the current shift frequency determination object, Can be used together. That is, the input pattern K-1 1202 that can initialize the scan path to a constant bit pattern can be used every time the target scan section K 1204 is repeatedly input to the scan path 1210. Also, the input pattern K + 1 1206 shifted to the scan path by a constant bit pattern can be used whenever the output pattern of the scan path for the k-th scan section 1204 is repeatedly shifted out.

The input pattern K-1 1202 is the scan pattern M-1 used for the actual scan test located before the target scan section K 1204 when the target scan section K 1204 corresponds one-to-one to the scan pattern M , A scan pattern M-1 is loaded into the scan path, and then a scan pattern is obtained.

As another example, when the target scan section K (1204) is a part of the scan pattern M as shown in FIG. 14, the input pattern K-1 1202 includes a scan pattern M-1 or the scan pattern M-1 into the scan path and then scan-captures the scan pattern. Also, the input pattern K-1 1202 may include a portion excluding the target scan section K (1204) in the scan pattern M. [ Here, the portion of the scan pattern M excluding the target scan section K may be a part of a bit pattern used in an actual scan test.

As another example, the input pattern K-1 1202 may be configured with a bit '0' or '1' to reduce the switching operation of the scan path, or an arbitrary set of '0' Pattern.

As another example, the input pattern K-1 1202 may be composed of at least one scan section as shown in FIG.

The k + 1 th input pattern 1206 is the scan pattern M + 1 used for the actual scan test located behind the scan section K 1204, or the scan pattern M + 1 used for the actual scan test located behind the scan section K 1204 when the target scan section K 1204 corresponds one- May be a predictive pattern for the resultant pattern obtained by scanning the pattern after loading the pattern M + 1 into the scan path.

As another example, if target scan section K (1204) is part of scan pattern M as shown in FIG. 14, input pattern K + 1 1206 is used for an actual scan test located after target scan section K (1204) Scan pattern M + 1, and so on. Also, the input pattern K + 1 1206 may include a portion of the scan pattern M excluding the target scan section K (1204). Here, the portion excluding the target scan section K (1204) may be a part of a bit pattern used in an actual scan test.

As another example, input pattern K + 1 1206 may be configured with a bit '0' or '1' in order to reduce the switching operation on the scan path or an arbitrary set of '0' Pattern.

As another example, the input pattern K + 1 1206 may be composed of at least one scan section as shown in FIG.

In order to reduce the switching operation of the scan path, the input patterns located respectively before and after the last scan section of the first scan section in the scan test are composed of bits '0' or '1' Quot; 1 " and " 1 ". The input pattern before the first scan section may also be a value on the scan path when the chip under test is in the reset state.

In at least one embodiment of the present invention, the input pattern K-1 1202 or the input pattern K + 1 1206 may each be comprised of one or more scan sections, and the shift frequency of these sections may be a current shift frequency determination object It is possible not to restrict the search for the maximum shift frequency of the scan section K (1204).

For example, assume that the input pattern K-1 1202 is normally shiftable to the scan path up to 30 MHz and the target scan section K 1204 is normally shiftable to the scan path up to 50 MHz. When the input pattern K-1 1202 and the target scan section K 1204 are sequentially shifted to the scan path with the same shift frequency while increasing the shift frequency, the maximum shift frequency K (1) 1204 found for the target scan section K (1204) Is limited to 30 MHz. That is, when the shift frequency exceeds 30 MHz, the output pattern for the input pattern K-1 1202 may be different from the predicted pattern. Also, even if the input pattern K + 1 1206 is normally shiftable to the scan path up to 30 MHz, the maximum shift frequency that can be found for the target scan section K 1204 may be limited to 30 MHz.

Therefore, in at least one embodiment of the present invention, the shift frequency of input pattern K-1 1202 or input pattern K + 1 1206 is set to a predetermined shift frequency (30 MHz in this example) Can not be exceeded.

For example, the shift frequency of the input pattern K-1 1202 or the input pattern K + 1 1206 is fixed to a predetermined shift frequency (in the above example, 30 MHz or less) By increasing or decreasing only the frequency, the maximum shift frequency usable in the target scan section K (1204) can be found.

As another example, it is also possible to increase or decrease the shift frequency together with the shift frequency (30 MHz or less in the above example) set for the input pattern K-1 1202, the target scan section K 1204, and the input pattern K + 1 1206 And shifts only the shift frequency of the target scan section K 1204 when the shift frequency is out of the predetermined shift frequency.

In other words, the shift frequency of the target scan section K (1204) and the shift frequency of the remaining input patterns 1202 and 1206 can be controlled differently. Of course, if the maximum allowable shift frequency of the input pattern K-1 1202 or the input pattern K + 1 1206 is larger than the maximum shift frequency of the target scan section K 1204, the target scan section K 1204 and the remaining input patterns 1202 and 1206 can be increased or decreased equally. Here, the predetermined shift frequency can be variously changed according to the embodiment, such as a nominal shift frequency or a shift frequency adjusted by a nominal shift frequency, or a preset value by a program or a user preset value It is not necessarily limited to the above example.

In at least one embodiment of the present invention, when the optimal shift frequency has already been determined through the method according to an embodiment of the present invention for input pattern K-1 1202 or input pattern K + 1 1206, The input pattern K-1 1202 or the input pattern K + 1 1206 may be shifted to the scan path by applying a frequency or less.

For example, when the method according to the present invention is applied to scan patterns sequentially, at least one scan section constituting the input pattern K-1 before the shift frequency determination process of the target scan section K (1204) The optimum shift frequency can be predetermined. Therefore, the apparatus for minimizing the scan test time uses the optimal shift frequency for each scan section of the input pattern K-1 1202 and uses the shift frequency for the input pattern K + 1 1206, which is the shift frequency adjusted for the nominal shift frequency or the nominal shift frequency Can be applied.

Then, input patterns 1202, 1204, and 1206 are sequentially input to the scan path 1210 while increasing or decreasing the shift frequency of the target scan pattern K to determine whether the actual output pattern 1220 is the same as the predicted pattern 1230 . At this time, if necessary, a scan capture operation may be performed on at least one of the input patterns 1202, 1204, and 1206.

For example, the scan test time minimizing apparatus uses a nominal shift frequency as an initial shift frequency, and increases the shift frequency in units of a predetermined shift frequency in the scan test time minimizing apparatus. That is, after the input pattern K-1 1202 is shifted to a predetermined shift frequency such as a nominal frequency in the scan path and the target scan section K 1204 is shifted to the scan frequency at the shift frequency of "initial shift frequency + At the same time, shifts out the test result (i.e., the output pattern K-1) 1222 by the input pattern K-1 1202 and compares it with the previously-known predicted pattern K-1 1232 .

At this time, the predetermined shift frequency for at least one scan section included in the input pattern K-1 1202 or the input pattern K-1 1202 may be different from the initial shift frequency of the target scan section K 1204. Then, at the same time as shifting of the input pattern K + 1 (1206), the output pattern K (1224) obtained by shifting out the test result for the target scan section K (1204) is equal to the predicted pattern K . At this time, when the target scan section K 1204 is a part of the scan pattern as shown in FIG. 14, the input pattern K-1 1202, the target scan section K 1204, the input pattern K + 1 1206, The output pattern is as described above.

In at least one embodiment of the present invention, the pre-set shift frequency referred to above may be such that there is no restriction on finding the optimal shift frequency of the target scan section K (1204). In at least one embodiment of the present invention, the shift frequency of the input pattern K-1 1202 or the input pattern K + 1 1206 may not be increased or decreased with the shift frequency of the target scan section K 1204, K 1204 and a shift frequency capable of normally inputting the scan section of the input pattern K-1 1202 or the input pattern K +1 1206 to the scan path.

In at least one embodiment of the invention, the predetermined shift frequency may vary according to the embodiment, such as a nominal shift frequency adjusted value in addition to the nominal shift frequency, or a value set by the program in the device, or a value set by the user And is not necessarily limited to the above example.

If the output pattern K-1 1222 and the predicted pattern K-1 1232 are the same, and the output pattern K 1224 and the predicted pattern K 1234 are the same, the current shift frequency is stored in the target scan section K 1204 Is the available shift frequency. The scan test time minimizing apparatus increases the shift frequency for the target scan section K 1204 by a predetermined amount and inputs the output pattern K-1 1202 to the scan path from the input pattern K-1 1202 again. 1220) and the prediction pattern 1230 are compared with each other.

The shift frequency for the target scan section K 1204 is continuously increased to the point at which the output pattern 1220 and the predicted pattern 1230 are different from each other, 1204, respectively.

Although the present embodiment mainly describes a method of finding the optimal shift frequency by increasing the shift frequency, in another embodiment, the shift frequency may be set such that the output pattern 1220 of the target scan section K 1204 and the predicted pattern 1230 are different It is possible to find a point at which the output pattern 1220 and the predicted pattern 1230 become the same by repeatedly decreasing from the high frequency. The optimal shift frequency of the target scan section K (1204) may be determined to be equal to or less than the shift frequency of the point at which the output pattern 1220 and the predicted pattern 1230 become the same.

As an example of the range of increase / decrease of the shift frequency when the output pattern for the scan section or the scan pattern is repeatedly compared with the predicted pattern while increasing / decreasing the shift frequency, the range of increase / decrease within the range set in the scan test time minimizing apparatus, If the pattern 1220 and the prediction pattern 1230 are the same but are different or different, but the same point is found, the increase and decrease of the shift frequency can be stopped. In this case, it is possible to reduce the time required to find the maximum shift frequency usable for each scan section.

According to the embodiment, the initial shift frequency for finding the optimal shift frequency for the target scan section K (1204) may be set to various values other than the nominal frequency, and may not be increased at the lower shift frequency, It is also possible to find the shift frequency at the point where the output pattern and the predicted pattern become equal, starting at these different high shift frequencies and lowering the shift frequency. Also, instead of sequentially increasing or decreasing the shift frequency of the target scan section K (1204), the optimum shift frequency may be found at a faster time by changing the shift frequency in various ways through various algorithms.

In at least one embodiment of the present invention, a binary search algorithm may be used. For example, if the shift frequency is test normal at 10 MHz and the test fails at 20 MHz, try the next shift frequency between them, 15 MHz. And if the test is normal, try between 15MHz and 20MHz, and if it fails, try between 10MHz and 15MHz. Test normal means that the chip to be tested is determined to be good, and test failure means that the chip to be tested is determined to be a defective product.

Binary search has the effect of reducing the time required to find the frequency that is the boundary between the test normal and the failure or the usable frequency range that is normal to test, as compared with the case of performing a linear search. For example, if you use a linear search to find the maximum frequency tested with N frequency increments, you can use the binary search to find the maximum test frequency at about log ₂ (N) times. Using binary search, the search time savings of the test normal maximum frequency is more effective than the linear search method as the number of whole scan sections and the unit value of the frequency which is increased or decreased by the test equipment becomes smaller.

In another embodiment, the optimal frequency or cycle can be determined or determined by considering the variation margin of the supply voltage supplied to the chip under test. For example, the following steps can be used to quickly find the optimal frequency or period within the range of voltages supplied to the chip under test.

Step 1

Minimizing the scan test time The device finds the maximum shift frequency or shift frequency range in which the test result of the test data is normal for each voltage while changing the voltage supplied to the chip to be tested to a certain unit. That is, instead of finding the shift frequency for each scan section into which the test data is divided, the maximum shift frequency or shift frequency range available for the entire test data is searched.

Step 2

From the result of Step 1, the scan test time minimizing device selects a specific voltage to be supplied to the chip to be tested. Here, the specific voltage to be supplied to the chip under test is a voltage representing the lowest maximum shift frequency among the maximum shift frequencies for each voltage found in step 1, or a voltage adjacent thereto. In addition, the voltage supplied to the chip to be tested can be selected in consideration of a test setup, a manufacturing process, or a test process.

Step 3

Minimize scan test time The device supplies the specific voltage selected in step 2 to the chip under test. And, the scan test time minimization device increases or decreases the shift frequency for each scan section while supplying a specific voltage, and grasps the test normal or failure of each scan section according to the shift frequency.

Step 4

The scan test time minimizing device finds or determines the optimum shift frequency for each scan section using the shift frequency information mapped to the result of test normal or failure for each scan section found in step 3.

Step 5

Minimizing the scan test time The device uses the optimal shift frequency for each scan section found or determined in step 4 to determine if the test result is normal while changing the supply voltage to the chip under test.

In at least one embodiment of the present invention, the voltage change range in step 5 may be the same as the voltage change range in step 1. [ Or the voltage change range in step 5 may be a range in which the range of change in step 1 is adjusted in consideration of a test setup, a manufacturing process, or a test process. While changing the voltage within the change range of the voltage, check whether the scan test result using the optimal shift frequency of each scan section found or determined in step 4 is normal. The shift frequency is normally optimized if each scan section is all tested within the voltage change range. In addition, there may be various criteria that the shift frequency per scan section is normally optimized considering test setup, manufacturing process, or test process. For example, a test failure may be allowed for certain voltages.

If you need to find the optimal frequency in consideration of the variation of the supply voltage supplied to the chip under test, you can use the same method as the previous one to find the voltage and frequency of each scan section by changing the voltage and frequency respectively. When used, there is an effect that a cycle of the optimal shift frequency or the shift frequency can be quickly found or determined.

For example, assume that SN (number of scan sections) = 1,000, VN (number of voltage changes) = 10, and FN (frequency change number) = 10.

Case 1

Number of searches required to find test normal or failure with varying voltage and frequency for all scan sections = SN x VN x FN = 100,000

Case 2

(Step 1) VN x FN + (step 3) SN x FN + (step 5) VN = (VN + SN) x FN + VN = 10, 110

In case 2, the number of times is reduced to about 10% than in case 1.

The scan section K 1204 for finding the optimal shift frequency may be configured as a part of the scan pattern M as shown in FIG. That is, the length of the target scan section K 1204 may be shorter than the length of the scan path. In this case, in the scan pattern M including the target scan section K (1204), the shift frequency of the portion excluding the target scan section 1204 does not restrict the search for the optimum shift frequency of the target scan section K (1204).

For example, the shift frequency of the portion excluding the target scan section K (1204) in the scan pattern M may not be increased or decreased along with the shift frequency of the target scan section K (1204) Can be used. In at least one embodiment of the present invention, the shift frequency of the portion excluding the target scan section K (1204) in the scan pattern M is a shift frequency capable of normally inputting the portion excluding the target scan section K (1204) Can be used.

In another embodiment, the shift frequency applied to the portion excluding the target scan section K (1204) in the scan pattern M may be equal to or less than the nominal shift frequency, or the portion excluding the target scan section K (1204) The optimum shift frequency may be used as a predetermined shift frequency below the optimum shift frequency. For the target scan section K (1204), an optimal frequency is searched for by increasing or decreasing the shift frequency as described above. The predetermined shift frequency may be a value obtained by adjusting the nominal shift frequency, a value set in the device by the program, or a value set by the user, and the present invention is not limited to the above example.

FIG. 12 shows a method of finding the optimum shift frequency of the target scan section K 1204 using the input pattern K-1 1202 together, but the present invention is not limited thereto. According to the embodiment, only the output pattern of the scan path for the scan pattern including the target scan section K 1204 or the target scan section K 1204 may be compared with the predicted pattern to find or determine the optimal shift frequency.

(Consideration of comparison of output pattern with front input pattern)

In at least one embodiment of the present invention, when an optimal shift frequency of the target scan section K (1204) is to be found or determined, the input pattern K-1 1202 immediately before the target scan section K (1204) The output pattern for the scan pattern located immediately before the scan pattern including the output pattern or the target scan section K (1204) can also be compared with the predicted pattern.

For example, when the output pattern of the scan path for the target scan section K 1204 is the same as the predicted pattern, and the output pattern for the input pattern K-1 1202 is also the same as the predicted pattern, The shift frequency used when shifting the scan path 1204 to the scan path can be grasped as the usable shift frequency of the target scan section K (1204).

As another example, when the target scan section K (1204) is part of the scan pattern as shown in FIG. 14, the output pattern K (1224) of the scan path for the scan pattern M including the target scan section K (1204) And the output pattern K-1 1222 of the scan path for the scan pattern M-1 located before the scan pattern M is the same as the predicted pattern K-1 1232, The shift frequency used when shifting the shift register 1204 to the scan path can be grasped as an available shift frequency of the target scan section K (1204).

The reason why the output pattern 1222 and the predicted pattern 1232 are compared with the target scan section K 1204 and the input pattern 1202 located in front of the target scan section K 1204 is that the input pattern (Or a portion of the input pattern) may be affected by the shift frequency of the target scan section K 1204. Here, the shift-out output pattern for the input pattern is a pattern obtained by performing a scan capture operation after the input pattern (or a part of the input pattern) located in front of the target scan section K 1204 is input to the scan path, Or may be a pattern output from the scan path without the scan path.

FIG. 16 is a graph illustrating an example of a method for finding a usable shift frequency of a scan pattern according to at least one embodiment of the present invention, and FIG. 17 is a graph illustrating a method for finding an optimal shift frequency according to at least one embodiment of the present invention And a test result of another scan pattern is failed when the shift frequency of the scan pattern is increased or decreased.

Referring to FIG. 16, the first scan pattern, the second scan pattern, and the third scan pattern are sequentially input to the scan path in order to find the optimal shift frequency of the second scan pattern. In at least one embodiment of the present invention, a shift frequency (for example, 5 MHz) capable of normally inputting the first scan pattern in the scan path is used for shifting the first scan pattern. In other words, the shift frequency at which the scan test result by the first scan pattern becomes normal is used for shifting the first scan pattern.

When the shift frequency of the second scan pattern is increased from 5 MHz to 25 MHz sequentially, the test results of the first scan pattern and the second scan pattern are all normal. In this case, all shift frequencies below 25 MHz are available shift frequencies for the second scan pattern.

Referring to FIG. 17, when the shift frequency of the second scan pattern is increased to 30 MHz, the test result of the second scan pattern is normal, but the test result of the first scan pattern is failure. This is because the test result of the first scan pattern shifted out is influenced by the shift frequency of the second scan pattern. Therefore, in at least one embodiment of the present invention, the test result of the first scan pattern, which is the input pattern before the second scan pattern as well as the second scan pattern for which the optimum shift frequency is to be searched, Lt; / RTI >

The scan section to find the optimal shift frequency may be part of the scan pattern. At this time, the shift frequency when the test results of the first scan pattern are all normal as well as the second scan pattern including the target scan section for which the optimum shift frequency is to be searched is usable frequency of the target scan section. In the bit pattern excluding the target scan section, a shift frequency capable of normally inputting the bit pattern into the scan path is used.

A shift frequency that is normally shifted to the scan path in the third scan pattern and simultaneously shifts out a test result for the second scan pattern is used.

When the first scan section and the second scan section neighboring to each other are sequentially input to the scan path of the chip in order to find the optimum shift frequency of the scan section or to reduce the chip production test time, Scan test can be performed by setting the shift frequencies of the two scan sections to be different from each other. For example, the different shift frequencies used in the two scan sections may be less than or equal to the shift frequency value at which the scan test using the two scan sections becomes normal.

The scan test can be performed by setting the shift frequency of the second scan section to be larger or smaller than the shift frequency of the first scan section for the neighboring first scan section and the second scan section. At this time, each shift frequency of two neighboring scan sections when the test result for the fault-free chip is normal is used to reduce the chip production test time. That is, the influence of neighboring scan sections on each other during the scan test must be considered.

For example, when the first scan section and the second scan section are neighboring scan patterns, when the scan capture result by the first scan section is shifted out, the influence of the shift frequency of the second scan section input subsequently is considered . For example, when the scan capture result pattern is shifted out, the bit value of the result pattern may be changed according to the shift frequency.

As another example, when neighboring first scan sections and second scan sections are included in one scan pattern, the influence of the shift frequency of the second scan section, which is subsequently shifted when the first scan section is shifted, should be considered . For example, the bit value of the first scan section shifted in the scan path may be changed by the shift frequency of the second scan section.

As another example, when the scan capture result of the first scan pattern shifted in front of the second scan pattern including the first scan section and the second scan section is shifted out, the first scan section belonging to the second scan pattern, The influence of two scan sections should be considered. If this effect is not taken into account, the scan test results for chips without failures during the mass production test may fail the test.

(Consider the output for the input pattern before or after the target scan section for which you want to find the optimal shift frequency)

When an optimal shift frequency of the target scan section is to be sought or determined, the scan path for the scan pattern located before or after the scan pattern including the target scan section as well as the input pattern or target scan section 1204 positioned before or after the target scan section The output pattern is compared with the predicted pattern to determine whether a normal test object IC chip can be tested as normal.

In at least one embodiment of the invention, this process can be repeated to increase or decrease the shift frequency to find or determine the optimal shift frequency of the target scan section. The shift frequency at which the test result is normal is the available shift frequency of the target scan section. The output pattern of the scan path for the target scan section is a pattern obtained by performing a capture operation after loading the target scan section into the scan path or outputting a scan pattern including the target scan section or the target scan section from the scan path without a scan capture operation It can be one pattern.

(Taking into account the output of the input pattern that is input after the target scan section to find the optimal shift frequency)

In order to find or determine the optimal shift frequency, an output pattern of a scan path for a scan pattern located after the scan pattern including the input pattern or target scan section 1204 located after the target scan section is also compared with the predicted pattern . ≪ / RTI >

For example, in order to find or determine the optimal shift frequency of the target scan section, the output pattern for the target scan section shifted out of the scan path is located immediately after the target scan section and affects the bit value of the shifted input pattern . As another example, in order to find or determine the optimal shift frequency of the target scan section, the output pattern for the scan pattern including the target scan section shifted out of the scan path is located immediately after the scan pattern including the target scan section, Can affect the bit value of the scan pattern.

(If the back input pattern can affect the target scan section to find the optimal shift frequency)

When the output pattern of the scan path for the scan pattern including the target scan section or the target scan section is shifted out, the input pattern shifted later may affect the bit value of the output pattern of the target scan section.

(Considering shift frequency of rear input pattern)

In order to reduce or eliminate the influence of the input pattern (or scan pattern), an input pattern (or scan) that is positioned immediately behind and shifted when the output pattern of the scan path for the scan pattern including the target scan section or the target scan section is shifted out, Pattern) can be shifted to a shift frequency that can be shifted to the scan path by normally shifting the input pattern (or scan pattern) that is located after the target scan section.

(Consider shift frequency of front or rear input pattern)

In order to find or determine the optimum shift frequency of the target scan section, the shift frequency of the input pattern (or part of the input pattern) located before or after the target scan section may be the same or different from the target scan section. Here, in at least one embodiment of the present invention, a shift frequency is used at which the input pattern located before or after the target scan section can be normally shifted to the scan path.

This is because the input pattern located before or after the target scan section for which the currently available maximum shift frequency is to be sought can be constrained to the maximum available shift frequency of the target scan section as described above. For example, the maximum available shift frequency of the input pattern located before or after the target scan section may be lower than the maximum available shift frequency of the target scan section.

FIGS. 18 to 20 are conceptual diagrams showing an example of a configuration of a scan pattern, a scan section, and shift frequency information necessary for finding a usable shift frequency of a scan section.

Referring to FIG. 18, there is a scan pattern in which a scan section is searched for a usable shift frequency or optimum shift frequency at which a chip can be normally tested. Each scan pattern N + 1, scan pattern N + 2, and scan pattern N + 3 of the test data 1800 is a scan section for searching for a usable shift frequency or an optimum shift frequency. FIG. 18 shows a configuration of scan patterns, scan sections, and shift frequency information necessary for finding or determining usable shift frequencies or optimal shift frequencies of the scan patterns N + 1, N + 2, and N + 3 .

In at least one embodiment of the present invention, in FIG. 18, T1, T2, T3 and Target_T represent information related to the scan shift frequency or the period of the scan shift frequency and for convenience of description, a timing identifier, Information.

In at least one embodiment of the present invention, the timing information may include or indicate a shift frequency or a cycle of the shift frequency as information related to the shift frequency or period of the shift frequency. The timing information may be used to identify or control the scan pattern or scan section. For example, the test apparatus may increase or decrease the frequency of the shift frequency or shift frequency of the scan pattern or scan section identified by the timing information.

In FIG. 18, T1 indicates information related to a shift frequency or a cycle of a shift frequency with respect to the scan pattern N, and may be referred to as timing information of the scan pattern N. In FIG. 18, Target_T for the scan pattern N + 1 represents information related to the shift frequency or the cycle of the scan shift frequency for the scan pattern N + 1, which is a scan section for searching for a usable shift frequency or an optimal shift frequency. May be referred to as timing information of +1. That is, in FIG. 18, T1, T2 and T3 are timing information of a scan pattern located in front of a scan section to which an optimum shift frequency is to be searched, and Target_T is timing information of a scan section to be a shift frequency optimization target.

In Fig. 18, at least two of the Target_T, T1, T2, and T3 may be the same shift frequency or different shift frequency.

In FIG. 18, the shift frequency or shift frequency period information of T1, T2, or T3 is used as a shift frequency or a shift frequency period so that a scan pattern or scan section corresponding to T1, T2, or T3 can be normally input to the scan path. do. At this time, the cycle of the shift frequency or the shift frequency corresponding to Target_T may be increased or decreased to find the optimum value. Also, the present invention is not limited to the example of FIG. 18, and one or more shift frequencies, shift frequency periods, or timing information may be variously allocated or used in one scan pattern.

In at least one embodiment of the present invention, the search data (1810, 1820, 1830) used to find the available shift frequency or optimal shift frequency of a scan section includes at least two scan patterns Lt; / RTI >

The search data 1810 for searching for usable shift frequencies or optimum shift frequencies of the scan pattern N + 1 includes at least the scan pattern N + 1 and the scan pattern N located before the scan pattern N + 1. For example, the scan section or scan pattern included in the search data 1810, 1820, 1830 may be repeatedly input into the scan path to find an available shift frequency or optimal shift frequency of a particular scan section.

At this time, based on the scan test output pattern of the chip using at least two scan patterns included in the search data 1810, 1820, and 1830, it is determined whether the test is normal or failed for each scan pattern. For example, the output pattern may be compared with the predicted pattern, and the predicted pattern may be included in the search data 1810, 1820, 1830 and managed. In other words, the search data 1810, 1820, and 1830 may include each predictive pattern corresponding to each output pattern for each scan pattern N + 1 and the scan pattern N positioned before the scan pattern N + 1. And find available shift frequencies or optimal shift frequencies of the scan section based on test success or failure information. For example, the usable shift frequency or optimum shift frequency of the scan pattern N + 1 corresponding to Target_T can be found.

A scan test is performed using a scan pattern N + 1 and a scan pattern N positioned in front of the scan pattern N + 1 to find a usable shift frequency or optimal shift frequency of the scan pattern N + 1. At this time, the test success or failure can be determined based on the scan test output pattern of the chip for the two scan patterns N + 1 and N, respectively. And find available shift frequencies or optimal shift frequencies for scan pattern N + 1. The shift frequency having a normal scan test result using the scan pattern N + 1 and the scan pattern N positioned before the scan pattern N + 1 is the usable shift frequency of the scan pattern N + 1.

Referring to FIG. 19, a scan section for searching for an available shift frequency or an optimal shift frequency is a scan pattern. At least three scan patterns are used, including the scan patterns located before and after the target scan section to find the optimal shift frequency for the scan section.

For example, the search data (1910, 1920, 1930) used to search for an available shift frequency or an optimal shift frequency of the scan section includes at least three scan patterns as shown in FIG. A scan pattern or a scan section of search data 1910, 1920, 1930 used to search for an available shift frequency or an optimal shift frequency may be repeatedly input to the scan path. At this time, based on the comparison of the output pattern of the scan pattern included in the search data (1910, 1920, 1930) and the predicted pattern, whether the test of the IC chip is successful or not is determined. Based on the success of the test, the available shift frequency of the scan section to find the optimal shift frequency can be found.

A chip test is performed on the scan pattern N + 1 and the scan pattern N positioned before the scan pattern N + 1 to find an available shift frequency or an optimal shift frequency of the scan pattern N + 1 in the search data 1910. At this time, the shift frequency when the test result is normal is the usable shift frequency of the scan pattern N + 1. At this time, since the scan pattern N + 2 located after the scan pattern N + 1 uses a shift frequency that is normally shifted in the scan path, the chip test by the scan pattern N + 2 can be omitted. Alternatively, the chip test result by the scan pattern N + 2 may also determine the shift frequency at the normal time as the usable shift frequency of the scan pattern N + 2.

Referring to FIG. 19, at least two of the timing information Target_T, T1, T2, T3, T4, T5, and T6 may be the same or different shift frequency or shift frequency period. The shift frequency period is a reciprocal of the shift frequency in a time interval of a shift operation for shifting a scan pattern to a shift frequency. In at least one embodiment of the present invention, the shift information of the shift frequency or shift frequency of the timing information T1, T2, T3, T4, T5 or T6 is a scan pattern corresponding to T1, T2, T3, T4, T5 or T6 A cycle of the shift frequency or the shift frequency is used so that the scan section can be normally input to the scan path. At this time, the cycle of the shift frequency or the shift frequency corresponding to Target_T may be increased or decreased to find the optimum value.

Also, the present invention is not limited to the example of FIG. 19, and one or more shift frequencies, shift frequency periods, or timing information may be used in one scan pattern.

Referring to FIG. 20, a scan section for searching for an available shift frequency or an optimal shift frequency is a part of a scan pattern. That is, each of the scan sections A, A + 1, and A + 2 of the scan pattern N + 1 is a scan section for searching for an optimum shift frequency.

The timing information T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10 are the timing information of the scan pattern or scan section located before or after the scan section for which the available shift frequency or optimum shift frequency is sought . And Target_T is the timing information of the scan section to be subjected to the shift frequency optimization.

At least two or more shift frequency or shift frequency periods may be used for at least two of Target_T, T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10.

In at least one embodiment of the present invention, the shift frequency or shift frequency period information of T1, T2, T3, T4, T5, T6, T7, T8, , A cycle of the shift frequency or the shift frequency that allows the scan pattern or scan section corresponding to T7, T8, T9, or T10 to be normally input to the scan path is used. At this time, the cycle of the shift frequency or shift frequency corresponding to Target_T may be increased or decreased to find a test normal value or an optimum value. Also, the present invention is not limited to the example of FIG. 20, and one or more shift frequencies, shift frequency periods, or timing information may be used in one scan pattern.

20 shows an example of search data 2010, 2020, and 2030 for searching for an optimal shift frequency for a certain scan section shorter than the scan pattern or the scan path length. The scan patterns included in the search data 2010, 2020, and 2030 may include at least two scan patterns as shown in FIG. 18, or at least three scan patterns as shown in FIG. When the search data 2010, 2010, 2010, and 2010 are composed of three scan patterns, the output pattern of the scan path for at least three or more scan patterns can be compared with the predicted pattern.

18, 19, and 20, the scan pattern or the scan section included in the search data for finding the usable shift frequency or the optimal shift frequency of the scan section is repeatedly input to the scan path .

Also, the present invention is not limited to the examples of Figs. 18 to 20, and the timing information for at least two scan patterns or scan sections included in the search data may be different from each other or the same.

The search data used for finding the optimal shift frequency of the scan section may include at least two scan patterns as in each of FIGS. 18, 19, and 20. In at least one embodiment of the present invention, the data for retrieval may include information related to the timing information of FIG. 18, FIG. 19, or FIG. The timing information may be used by the test apparatus to control the timing of inputting the scan pattern or scan section into the scan path. The timing is the shift frequency or the cycle of the shift frequency. For example, as shown in FIGS. 18 to 20, each search data used to search for an optimal shift frequency for each neighboring scan section may include scan patterns superimposed on each other.

In at least one embodiment of the present invention, the step of creating the search data used to find the optimal shift frequency of a large number of each scan section may be efficient to batch process using a computer program or software.

For example, as shown in Figs. 18 to 20, the task of composing or dividing the timing information or data related to the scan pattern, the scan section, and the shift frequency used to find the optimal shift frequency of each scan section is performed by a computer program or software Can be processed collectively. In addition, information such as the number of scan sections to be optimized in the above operation, the bit length of the scan section, and the position of the scan section may be used.

In addition, predictive patterns may also be included in the search data used to find an available shift frequency or an optimal shift frequency of a particular scan section. Also, the search data used to find an available shift frequency or an optimal shift frequency of a specific scan section may include the primary input test data of the IC chip or the primary output prediction data May also be included.

21-28 are diagrams illustrating a method for generating search data in accordance with at least one embodiment of the present invention. FIGS. 21 to 23 relate to a method of generating search data when the scan section is a scan pattern, and FIGS. 24 to 26 show a method of generating search data when the scan section is part of a scan pattern .

21 is a conceptual diagram showing an example of test data including a plurality of scan patterns.

Referring to FIG. 21, a single shift frequency (for example, T1 = 50 ns (i.e., 20 MHz)) is given to all the scan patterns in the test data 2100. Thus, all scan patterns are shifted in and shifted out at the same shift frequency in the scan path of the IC chip.

The test data 2100 may be composed of a plurality of sub-test data including a pair of an input scan pattern and a predictive pattern. For example, the 51st input scan pattern is paired with the prediction pattern of the 50th input scan pattern. The test data can be written in a format such as STIL (Standard Test Interface Language) or WGL (Waveform Generation Language).

The money care prediction pattern of the first sub test data means that the output pattern shifted out when the first input scan pattern is shifted to the scan path is not compared with the specific prediction pattern. The output pattern shifted out when the first input scan pattern is input after the flip-flops are set or reset to a certain value may not be a money care prediction pattern.

22 is a conceptual diagram showing an example of a method for generating search data for searching for an optimal shift frequency for each scan section when the scan section is a scan pattern.

Referring to FIG. 22, timing information Target_T is given to a target scan section 2210 in which the optimum shift frequency is to be found in the original test data 2100 of FIG. The timing information Target_T is used to identify the target scan section 2210 or to control the shift frequency of the target scan section. For example, Target_T may be increased or decreased by the test device in the initial 50 ns.

When the target scan section 2210 is the input scan pattern 51, the search data 2200 to which the Target_T is assigned is repeatedly input to the chip to find the available shift frequency or optimal shift frequency of the input scan pattern 51. The cycle of the shift frequency of the target scan section 2210 corresponding to Target_T is changed each time it is repeatedly input. The period of the shift frequency of the input scan pattern except for the target scan section 2210 is a shift frequency period (for example, T1 = 50 ns) at which the scan pattern can be normally input to the scan path.

For example, the search data 2200 is repeatedly input to the chip while reducing the period of the shift frequency corresponding to Target_T until the maximum available shift frequency of the target scan section 2210 is found. At this time, the output pattern for the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub-test data 51. Also, the output pattern for the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub-test data 52. The shift frequency when the test results of the input scan pattern 50 and the input scan pattern 51 are all normal is the usable shift frequency of the target scan section 2210.

The smaller the size of the search data 2200 used to search for the available shift frequency or optimum shift frequency of the target scan section 2210, the shorter the time used for finding the optimal shift frequency.

FIG. 23 is a conceptual diagram showing an example of a method of generating search data for reducing the time required to find an optimal shift frequency.

23, search data 2300 for searching for a usable shift frequency or optimum shift frequency of the input scan pattern 51, which is a target scan section 2310, includes a target scan section 2310 and inputs Scan patterns 50,52. And the prediction pattern included in the sub test data 50 located in front of the target scan section 2310 is a money care prediction pattern. That is, the output pattern shifted out when the input scan pattern 50 is shifted to the scan path is not compared with the specific predicted pattern.

The search data 2300 is repeatedly inputted to the scan path of the chip while changing the cycle of the shift frequency corresponding to Target_T until the maximum available shift frequency of the target scan section 2310 is found. The test result using the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub test data 51. [ Also, the test result using the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub test data 52. The shift frequency when the test results of the input scan pattern 50 and the input scan pattern 51 are all normal is the usable shift frequency of the target scan section 2310.

The search data 2300 is not limited to the example of FIG. 23, and may further include two or more input scan patterns located before or after the target scan section.

FIG. 24 is a conceptual diagram showing an example of test data including a plurality of scan patterns. FIGS. 25 to 28 illustrate a method of generating search data for searching for an optimal shift frequency when a scan section is a part of a scan pattern And Fig.

Referring to FIG. 24, a single shift frequency (for example, T1 = 50 ns (i.e., 20 MHz)) is given to all the scan patterns in the test data 2400. Thus, all scan patterns are shifted in and shifted out at the same shift frequency in the scan path of the IC chip.

The test data 2400 may be composed of a plurality of sub-test data including a pair of the input scan pattern and the predictive pattern. For example, the 51st input scan pattern is paired with the prediction pattern of the 50th input scan pattern.

The test data 2400 may be divided into a plurality of scan sections. For convenience of description, the present embodiment is directed to a method for generating search data for finding an optimal shift frequency of each scan section when the input scan pattern 51 is divided into three scan sections 2410, 2420, and 2430 25 to Fig.

25 to 27, the search data 2500, 2600, 2700 includes the input scan pattern 51 including the target scan sections 2510, 2610, 2710 and the input scan patterns 50, do. The predicted pattern included in the sub-test data 50 is a money care prediction pattern. That is, the output pattern shifted out when the input scan pattern 50 is shifted to the scan path is not compared with the specific predicted pattern. Timing information Target_T is used to identify the target scan sections 2510, 2610, 2710 or to control the shift frequency of the target scan section. For example, Target_T may be incremented or decremented by the test device in the initial 50n.

25, the search data 2500 provides the timing information of Target_T to the first subject scan section 2510, which is a part of the input scan pattern 51, and retains the timing information of T1 to the remainder of the input scan pattern 51 do. The search data 2500 is repeatedly input to the scan path of the chip while changing the cycle of the shift frequency corresponding to Target_T until the maximum available shift frequency of the first target scan section 2510 is found. The test result using the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the sub test data 51. [ Also, the test result using the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the sub test data 52. The shift frequency when the test results using both the input scan pattern 50 and the input scan pattern 51 are normal is the usable shift frequency of the first target scan section.

When the optimum shift frequency of the second target scan section 2610 or the third target scan section 2710 is found, the search data 2600 and 2700 shown in FIGS. 26 and 27 are repeatedly input to the chip Scan test.

When one scan pattern is divided into a plurality of scan sections, search data (2500, 2600, 2700) for each scan section is not created as shown in FIG. 25 to FIG. 27 to find the optimal shift frequency of each scan section It is possible to create one search data 2800 as shown in FIG.

Referring to FIG. 28, the search data 2800 includes respective timing information Target_T1, Target_T2, and Target_T3 in the first to third target scan sections 2810, 2820, and 2830, respectively. In other words, a timing identifier is created by the number of target scan sections for which an available shift frequency or optimum shift frequency is simultaneously sought, and allocated to each target scan section 2810, 2820, 2830. For example, when searching for the available shift frequency or optimum shift frequency of the first subject scan section 2810, the shift frequency corresponding to Target_T1 may be increased or decreased.

As shown in FIG. 28, when one search data 2800 for a plurality of target scan sections is generated, storage capacity of the storage medium can be saved as compared with generating search data for each target scan section. However, there may be a limit on the number of available timing identifiers or the number of shift frequencies of the test apparatus.

For example, if the number of timing identifiers available in the test apparatus is limited to three, and the scan pattern is divided into four target scan sections, the search data 2500, 2600, 2700) to find the optimal shift frequency.

The search data 2500, 2600, 2700, and 2800 are not limited to FIG. 25 to FIG. 28, but may further include two or more input scan patterns located before or after the input scan pattern including the target scan section.

The smaller the possible search frequency or the size of the search data used to search for the optimal shift frequency in the scan pattern or scan section, the more time it takes to find the shift frequency. For example, the less the number of scan patterns or scan sections is used, the less time is required to find available shift frequencies or optimal shift frequencies.

SN, BL, and FN are defined as follows to calculate the total number of shift clock cycles required to find the optimal shift frequency for all the scan patterns of the test data.

SN: number of scan patterns constituting test data

BL: Bit length of one scan pattern, one shift clock cycle to shift one bit is used.

FN is the number of times of shift frequency increase for finding the optimum shift frequency per scan pattern, and is sequentially increased from a predetermined low shift frequency to a preset high shift frequency at regular intervals.

In at least one embodiment of the invention, it is assumed that SN = 5,000, BL = 1,000 and FN = 20. For the following methods 1 and 2, the total number of shift clock cycles required to find the optimal shift frequency for all the scan patterns of the test data is calculated as follows.

Method 1

As shown in FIG. 22, the total number of shift clock cycles required when searching for the optimum shift frequency of each scan pattern using the search data including the entire input scan pattern is as follows:

Total time required = SN x SN x BL x FN = 500,000,000,000 shift clock cycles

Method 2

As shown in FIG. 23, the total number of shift clock cycles required for finding the optimal shift frequency of each input scan pattern using search data including three input scan patterns is as follows Search data including the first and second input scan patterns are used to find the optimal shift frequency of the last input scan pattern. When finding the optimum shift frequency of the last input scan pattern, the last input scan pattern and the input scan pattern Search data is used, including two input scan patterns):

Total time required = (3 x SN-2 x BL x FN) + (2 x 2 x BL x FN) = 299,960,000 shift clock cycles

In the above equation (3 x (SN-2) x BL x FN), every scan except the two scan patterns of the set of scan patterns (i.e., the first scan pattern input to the chip and the last scan pattern input) The total number of shift clock cycles used to find the optimal shift frequency of the pattern.

In the above equation (2 x 2 x BL x FN) is the total number of shift clock cycles used to find the optimal shift frequency of the scan pattern pattern first entered into the chip and the last input scan pattern

Using Method 2, it can be seen that 99.94% of the total number of shift clock cycles used in Method 1 has been reduced.

Thus, the search data used to search for the available shift frequency or optimum shift frequency of the scan pattern or scan section includes as few scan patterns or scan sections as possible.

In at least one embodiment of the present invention, as is the case with reference to FIG. 18, the search data includes at least two scan sections, including a scan section seeking a shift frequency or an optimal shift frequency, The scan pattern can be configured as described above.

Also, as in the examples of FIGS. 19 to 28, the search data may be composed of at least three scan patterns including a scan section for searching for a shift frequency or an optimal shift frequency, and scan patterns positioned before and after the scan section .

In at least one embodiment of the invention, the search data used to find the available shift frequency or optimal shift frequency of the scan section is stored in a computer readable recording medium in the form of a data code, a file, .

Also, the step of creating search data used to search for an available shift frequency or an optimal shift frequency of the scan section may be performed in the same device or in a different device, respectively, according to the embodiment, .

29 is a flowchart illustrating an example of a scan test time minimization method according to the present invention.

Referring to FIG. 29, the apparatus for minimizing scan test time divides a bit pattern or at least one scan pattern into at least two scan sections (S2900). There are various methods of dividing a bit pattern or a set of scan patterns of test data into scan sections, and one example is shown in Figs. 5 to 10.

In the dividing step, the task of creating data for retrieval of a scan section or a section group or a file containing these data by dividing several thousand or tens of thousands of scan patterns for testing an IC chip is performed using a computer program or software It may be efficient to process them collectively.

As an example, a computer program or software may use the information associated with the scan section division, such as the number of scan sections for which the shift frequency is to be optimized, the bit length of the scan section, the location of the scan section, And a file including search data or search data for a divided scan section or a scan section group can be collectively created.

The information associated with the scan section segmentation may be obtained via an information data code or file, including a user interface device such as a keyboard, a mouse, a speech recognition device, or information relating to scan section segmentation, or via a data communication network, Lt; / RTI >

As an example of the division of the scan pattern, the method shown in Figs. 5 to 10 can be used. The scan test time minimizing apparatus allocates a plurality of shift frequencies to each scan section (S2910). Here, the shift frequency assigned to each scan section is equal to or less than the shift frequency before the output pattern of the scan path is different from the predicted pattern. The division of the scan pattern into the scan section (S2900) and the scan frequency allocation of the shift frequency (S2910) may be performed in the same device or different devices, respectively, according to the embodiment, have.

That is, the scan test time minimizing apparatus can find the shift frequency immediately before the output pattern and the predicted pattern change as the shift frequency increases, as the maximum shift frequency assignable to the scan section. As another example, the scan test time minimizing apparatus can find the shift frequency when the output pattern and the predicted pattern are different from each other and equal to each other as the maximum shift frequency assignable to the scan section as the shift frequency decreases. For example, it is possible to find a test normal shift frequency close to the boundary between scan test normal and failure while increasing or decreasing the shift frequency of the scan section, and to find the test normal shift frequency as the maximum shift frequency assignable to the scan section.

30 is a flowchart illustrating another example of a method for determining an optimal shift frequency for each scan section in order to minimize a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 30, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (S3000).

The scan test time minimizing apparatus searches for a shift frequency when the output pattern is the same as the predicted pattern but is different or different from the frequency of shifting the scan section to the scan path (S3010). For example, a chip used to search for an optimal shift frequency may use a chip that has been previously tested with a good product. For example, an optimal shift frequency is searched for according to the present embodiment using a chip whose test result is a normal test result using a nominal shift frequency. But may be the same in other embodiments described below.

In step S3020, the apparatus for minimizing the scan test time determines a test normal shift frequency before the point of time when the output pattern and the predicted pattern are the same but is different from each other, as the shift frequency of the corresponding scan section. The previous shift frequency also includes a shift frequency smaller than the point at which the difference is made.

For example, if the output pattern and the predicted pattern are the same at the first shift frequency but the output pattern and the predicted pattern of the scan path are different at the second shift frequency where the first shift frequency is increased by a certain magnitude, 2 < / RTI > shift frequency and determine the shift frequency of the test section to be the shift frequency of the scan section.

The size to increase or decrease to find the optimum shift frequency may be preset in the test apparatus, or the increase / decrease size may be changed or set by the user.

Although the present embodiment describes a method for finding an optimal shift frequency for each scan section by increasing or decreasing a shift frequency shifted in for convenience of explanation, it is possible to find an optimum shift frequency by increasing or decreasing a shift- have. The same goes for the following embodiments.

Each step described in FIG. 30 is not performed in the apparatus for minimizing the scan test time according to the embodiment, but at least a part thereof may be performed in another apparatus such as a computer.

31 is a flowchart illustrating a method of minimizing a scan test time according to at least one embodiment of the present invention.

Referring to FIG. 31, the apparatus for minimizing scan test time divides one or more scan patterns into a plurality of scan sections (S3100).

The scan test time minimizing apparatus selects one scan section in which the shift frequency is not determined according to the present embodiment among the scan sections (S3110). For example, if a certain order is set between the scan patterns for the scan test, the apparatus for minimizing the scan test time can sequentially select from the first scan section. Alternatively, the user may select a scan section for which to optimize the shift frequency, and the scan test time minimization device may perform shift frequency optimization for the selected scan section. There may also be other ways to select the scan section to optimize the shift frequency.

The scan test time minimizing device increases the shift frequency (S3120). For example, in an apparatus for minimizing a scan test time, an initial shift frequency may be variously set to a nominal shift frequency or the like.

The scan test time minimization apparatus determines whether the scan section can be normally shifted to the scan path at an increased or decreased shift frequency starting from an initial shift frequency at which the scan test result is normal (S3130). An example of a specific method for determining whether the selected shift frequency determination target scan section is normally shiftable to the current shift frequency will be described with reference to FIG.

If the normal shift of the scan section is possible (S3140), the scan test time minimization device increments the shift frequency again (S3120) and repeats the process of determining whether a normal shift is possible (S3130).

If the normal shift of the scan section can not be achieved according to the increase of the shift frequency (S3140), the apparatus for minimizing the scan test time can determine or determine the shift frequency of the corresponding scan section to be less than or equal to the shift- The information can be stored in a computer-readable recording medium (S3150). Then, the above process is repeated until the shift frequency for all scan sections is determined or the information for determining the shift frequency is stored in a computer-readable recording medium (S3160). Here, as an example of the information stored in the recording medium, it may be information about shift or test normal or failure for each shift frequency with respect to the IC chip under test.

Minimizing scan test time The device may group scan sections into section groups as needed (S3170). For example, when the test apparatus performing the actual scan test has constraints such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required for changing the shift frequency, The device can group the scan sections into groups so that the number of scan sections meets the above constraints, at which time the entire scan test time can be considered to be minimized. At this time, the shift frequency of the corresponding section group may be determined to be the lowest shift frequency or less among the optimal shift frequencies of at least two scan sections included in one scan section group. The process of grouping into a section group (S3170) may be omitted according to the embodiment.

For example, if the maximum number of shift frequency changes that can be supported by the test apparatus is 5, the scan test time minimizing apparatus divides the scan sections into five or less section groups when the number of current scan sections exceeds 5, The shift frequency of the corresponding section group can be determined to be equal to or less than the lowest optimal shift frequency of the optimal shift frequency of the section. There may be a variety of ways in which the overall scan test time can be minimized, such as a method of grouping scan sections with the same or similar optimal shift frequency.

The embodiments thus far have been mainly the process of finding the optimal shift frequency only considering the increase of the shift frequency. As another example, it is possible to find the optimal shift frequency of a corresponding scan section while reducing the shift frequency.

For example, the scan test time minimizer can determine whether a scan section can be normally shifted into the scan path at a reduced shift frequency, starting from an initial shift frequency that is a test failure. The scan test time minimizing device may determine information that can determine or determine the shift frequency of the scan section below the maximum shift frequency that has become the normal shift in the computer, And the like.

As another example, the chip is also affected by the supply voltage and the ambient temperature, so that the optimum shift frequency can be found by reflecting these environmental conditions. That is, the apparatus for minimizing the scan test time can perform the process of finding the optimum shift frequency while changing the conditions such as the supply voltage and the external temperature.

For example, the apparatus for minimizing the scan test time may increase or decrease the voltage supplied to the chip in consideration of the specifications of the chip, quality-related policies such as QA (Quality Assurance), QC (Quality Control), and the like (S3120). And the scan test time minimization device finds the optimum shift frequency for each scan section according to the embodiment of the present invention at each incremental supply voltage. If there are a plurality of optimal shift frequencies found for the supply voltage of the selected scan section, the scan test time minimizing apparatus can determine the shift frequency of the selected scan section to be the lowest shift frequency of the selected one (S3150). The process of finding the optimum shift frequency for each of the other temperature conditions and other various conditions is repeated, and the shift frequency of the scan section below the lowest optimal shift frequency can be determined.

Here, it is generally referred to as electrical testing or shmooing to determine characteristics such as the operating frequency range of the IC chip while changing the supply voltage or ambient temperature of the IC chip. It is said that shmoo plotting is done by electrical characteristic testing or shimming to make a plot of characteristic information. The diagram can be called a shmoo plot.

Each step of FIG. 31 may be performed by another apparatus such as a computer as well as a scan test time minimizing apparatus.

FIG. 32 is a flowchart illustrating a specific procedure for determining a normal shift-in in the scan test time minimization method according to at least one embodiment of the present invention. That is, FIG. 32 corresponds to step S3130 of FIG. 31, but is not limited to the specific step of FIG. 31, and can be applied to various embodiments including a process of determining or determining whether a shift in is normal in the scan path.

12 and 32, the apparatus for minimizing the scan test time shifts the input pattern K-1 1202 located in front of the target scan section K 1204 to be shifted to the scan path 1210, (S3200). For example, the input pattern K-1 1202 is located in front of the scan pattern M that includes the target scan section K 1204, and may have the following example (1) or (2).

(1) When the input pattern K-1 1202 is a scan pattern used in an actual scan test

The scan test time minimizing device shifts the scan pattern M-1 to the scan path and performs scan capture. In this case, there is an advantage that the actual scan test operation can be reflected. Here, the scan pattern M-1 is a pattern located in front of the scan pattern M including the target scan section K.

(2) When the scan pattern M-1 is an output pattern predicted as a scan test result using the scan pattern M-1 used in the actual scan test

The scan test time minimizing device does not need to perform a separate scan capture process after shifting the scan pattern M-1 to the scan path. Therefore, in this case, it is possible to reduce the time required for the clock for the scan capture, thereby reducing the time required for finding the optimal shift frequency.

The scan test time minimizing device performs a scan capture operation after shifting the input pattern K-1 1202 to the scan path (S3200). In another embodiment, the scan capture operation may not be performed. Next, the scan test time minimizing device shifts the target scan section K (1204) to the scan path at the increased shift frequency (S3210). If the target scan section K (1204) is part of the scan pattern M as shown in Fig. 14, the scan pattern M including the target scan section K (1204) is shifted to the scan path.

At this time, the scan pattern M including the target scan section K (1204) or the target scan section K (1204) is shifted to the scan path, and the bit pattern stored on the scan path is simultaneously shifted out (S3210). Here, the bit pattern shifted out is not limited to the above example, and may vary according to the type of the scan circuit in which shift in and shift out operations with respect to the scan path can be performed simultaneously.

For example, if the target scan section K (1204) is shorter than the length of the scan path as a part of the scan pattern M as shown in Fig. 14, the scan pattern M including the target scan section K (1204) is shifted to the scan path . At this time, the shift frequency of the remaining portion of the scan pattern M excluding the determination target scan section K (1204) does not restrict the search for the optimal shift frequency of the target scan section K (1204). For this purpose, the shift frequency of the remaining portion of the scan pattern M excluding the portion of the target scan section K (1204) is set so as not to be increased or decreased along with the shift frequency of the target scan section K (1204) Can be used. Alternatively, the shift frequency of the remaining portion of the scan pattern M excluding the portion of the target scan section K 1204 may be a shift frequency capable of normally inputting the remaining portion excluding the target scan section K 1204 in the scan path.

In at least one embodiment of the present invention, the shift frequency of the portion excluding the target scan section K (1204) is less than or equal to the nominal shift frequency, or, if the optimal shift frequency has already been determined through the method according to an embodiment of the present invention, Optimum Shift Frequency You can use a predefined shift frequency as follows. The predetermined shift frequency may be a value obtained by adjusting the nominal shift frequency, a value set in the device by the program, or a value set by the user, and the present invention is not limited to the above example.

The scan test time minimizing apparatus compares the output pattern K-1 of the input pattern K-1 of the chip under test with the predicted pattern K-1 (S3220). If the output pattern K-1 is not the same as the predicted pattern K-1 (S3220), the scan test time minimizing device determines or determines that the target scan section K (1204) can not be shifted normally into the scan path at the current shift frequency (S3270). For example, the scan test time minimization device may store information of a test failure on a computer readable recording medium.

If the output pattern K-1 of the input pattern K-1 is the same as the predicted pattern K-1 (S3220), the scan test time minimizing apparatus performs the scan capture (S3230) operation on the target scan section K 1204 Shift-out operation S3240. In another embodiment, the shift-out operation S3240 may be performed without performing the scan capture operation S3230. In addition, the bit pattern shifted out (S3240) may vary according to the type of scan circuit in which shift in and shift out operations for the scan path can be performed at the same time.

The bit pattern of the target scan section K 1204 shifted out (S3240) to the input pattern K + 1 (1206) shifted at the same time when the output pattern for the target scan section K 1204 shifts out (S3240) A shift frequency is used so as not to be changed. That is, a shift frequency at which shift-out operation S3240 can be performed normally is used. Also, when the shift-out operation S3240 of the target scan section K 1204 is performed, a shift frequency that can be shifted normally in the scan path is used for the input pattern K + 1 1206 shifted at the same time.

The scan test time minimizing apparatus compares the output pattern K of the target scan section K (1204) of the chip to be tested with the predicted pattern K (S3250). If the output pattern K of the target scan section K (1204) is not the same as the predicted pattern K (S3250), the scan test time minimizing apparatus normally shifts the target scan section K (1204) (S3270). For example, the scan test time minimization device may store information of a test failure on a computer readable recording medium.

If the output pattern K of the target scan pattern K 1204 is the same as the predicted pattern K (S3250), the scan test time minimizing device can normally shift the target scan section K 1204 to the scan path at the currently used shift frequency (S3260). For example, the scan test time minimization device may store the test normal information on a computer readable recording medium.

In at least one embodiment of the present invention, not only the scan pattern including the target scan section K (1204) but also the output pattern of the chip with respect to the scan pattern positioned in front of the target scan section K (1204) You can find the available shift frequency or the optimal shift frequency.

In at least one embodiment of the present invention, the test apparatus determines or determines whether the scan test results for the target scan section K (1204) and the input pattern K-1 (1202) preceding it are both normal. And if both are test normal, the shift frequency used in the target scan section K (1204) is the shift frequency at which the target scan section K (1204) can be normally shifted to the scan path.

33 is a flowchart illustrating another example of a scan test time minimization method according to at least one embodiment of the present invention.

There may be a process variation between IC chips on different wafers or between IC chips on the same wafer depending on the type and state of the chip manufacturing process. This may affect the operation frequency and power consumption of the IC chip I can go crazy. Especially in micro and low power processes.

Referring to FIG. 33, in step S3300, the apparatus for minimizing scan test time determines a frequency optimum for each scan section for a plurality of chips. Here, the plurality of chips may be IC chips on the same wafer or IC chips on different wafers, and may be chips previously tested with good products.

The scan test time minimizing apparatus may determine an optimal shift frequency of the scan section to be the lowest shift frequency among a plurality of optimal shift frequencies obtained through a plurality of IC chips for a certain scan section, The information can be stored in a computer-readable recording medium (S3310), and can be performed for each scan section. Here, an example of the information stored in the recording medium may be information on a shift or test pass or failure for each shift frequency.

For example, assume that the shift frequency of the target scan section K of the first chip is A and the shift frequency of the target scan section K of the second chip is B. If shift frequency A is less than shift frequency B, the test apparatus may select A or less at the shift frequency of target scan section K, or may store selectable information on a computer readable recording medium.

Each step of FIG. 33 may be performed in another apparatus such as a computer as well as a scan test time minimizing apparatus using a set of scan patterns and shift frequency information obtained for each scan section for a plurality of chips.

34 is a block diagram illustrating a configuration of an apparatus for minimizing scan test time according to at least one embodiment of the present invention.

The scan test time minimizing device of FIG. 34 may perform the method of the present invention described above for shift frequency optimization of each scan section, and in at least one embodiment of the present invention, The whole can be applied.

34, the scan test time minimizing apparatus includes a condition setting unit 3400, a pattern dividing unit 3405, a pattern inputting unit 3410, a pattern comparing unit 3420, and a frequency determining unit 3430. The condition setting unit 3400 includes a frequency adjuster 3402, a supply voltage adjuster 3404, a temperature adjuster 3406, and the like.

First, the condition setting unit 3400 sets various conditions for finding the optimal shift frequency for each scan section. Specifically, the frequency adjuster 3402 increases or decreases the shift frequency, the supply voltage adjuster 3404 increases or decreases the voltage supplied to the chip, and the temperature adjuster 3406 increases or decreases the ambient temperature of the test environment. The condition setting unit 3400 sets conditions such as the supply voltage and the ambient temperature, and can increase or decrease the shift frequency. For example, the condition setting unit 3400 may be provided in the host computers 200 and 300, the tester main bodies 210 and 310, the test heads 220 and 320, the prober 350, and the like.

The pattern division unit 3405 may divide one or more scan patterns into a plurality of scan sections. For example, the pattern dividing unit 3405 may be provided in the host computers 200 and 300, the tester bodies 210 and 310, the test heads 220 and 320, the prober 350, and the like. The pattern division unit 3405 may divide the test data into at least one scan section using the method shown in FIGS.

The pattern input unit 3410 shifts the scan section to the scan path of the test target chip under the condition set by the condition setting unit 3400. [ More specifically, the pattern input unit 3410 may sequentially shift the scan patterns or scan sections, which are located before and after the scan section for which the optimum scan shift frequency is to be searched, along with the scan frequency determination target scan section sequentially in the scan path . For example, the pattern input unit 3410 may be provided in the host computers 200 and 300, the tester main bodies 210 and 310, the test heads 220 and 320, the prober 350, and the like.

The pattern comparison unit 3420 compares the output pattern shifted out of the test result by the scan section shifted to the chip under test by the pattern input unit 3410 to determine whether the output pattern is the same as the predicted pattern. For example, the pattern comparator 3420 may be included in the host computers 200 and 300, the tester main bodies 210 and 310, the test heads 220 and 320, the prober 350, and the like. There may be a point in time or a frequency at which the output pattern and the predicted pattern are the same but different or different from each other as the shift frequency is increased or decreased by the condition setting unit 3400. [

Using the comparison result information or the comparison result by the pattern comparing unit 3420, the frequency determining unit 3430 reads the shift frequency before the output pattern is different from the predicted pattern or the shift frequency information for finding the same shift frequency, Lt; RTI ID = 0.0 > media. ≪ / RTI > For example, normally available shift frequency information for the scan section can be stored in a computer-readable recording medium. The information may also be used to determine the optimal shift frequency of the scan section.

In at least one embodiment of the present invention, the frequency determining unit 3430 determines a shift frequency when at least a scan section located before a current shift frequency determination target scan section and an output pattern for a determination target scan section are the same as a predicted pattern, And can be stored on a computer readable recording medium as available shift frequency information of the scan section. Also, in FIG. 34, two or more parts may be integrated into one module or further subdivided into one module. For example, the frequency determination unit 2030 may be provided in the host computers 200 and 300, the tester main bodies 210 and 310, the test heads 220 and 320, the prober 350, and the like.

Minimizing the test time of the scanning test The device may be implemented in various forms using hardware or software. Also, all or part of the scan test time minimizing device may be implemented in a test device as shown in FIGS. 2 and 3, or may be implemented using another separate device such as a computer.

FIG. 35 is a conceptual diagram showing an example of a method of finding or determining an optimal shift frequency of a plurality of scan sections in parallel. FIG.

Referring to FIG. 35, the apparatus for minimizing the scan test time searches for or determines an optimal shift frequency by searching or determining in parallel the optimal shift frequencies of different scan sections for each of a plurality of IC chips Time can be reduced.

For example, an optimal shift frequency of different scan sections may be searched or determined for each of a plurality of IC chips 3510, 3512, 3514, and 3516 located in the test interface board 3500 of the test apparatus. In at least one embodiment of the present invention, an optimal shift frequency of different scan sections may be sought in parallel or determined in a plurality of respective test devices or a plurality of test interface boards.

If it takes time h to find or determine the optimal shift frequency one by one for the entire scan section, if the shift frequency is sought or determined in parallel with n scan sections, Can be saved. Accordingly, it is possible to divide and optimize several thousand to several tens of thousands of scan patterns for testing IC chips within the same time period into shorter scan sections.

36 is a conceptual diagram illustrating an example of a method of rearranging scan patterns for minimizing scan test time according to at least one embodiment of the present invention.

Referring to FIG. 36, scan patterns on a set of scan patterns for a scan test have a predetermined order. However, the order of the scan patterns is not fixed but can be rearranged to reduce the entire scan test time by allocating a high shift frequency for each scan section. For example, as shown in FIG. 36, the order of the second scan pattern and the third scan pattern on the original set of scan patterns can be changed. Accordingly, the order of the predicted output scan patterns is also changed.

In the case where the order of the scan patterns shifted in the scan path is rearranged, the scan portion of the circuit and the number of switching operations on the IC chip can be changed by the scan shift, Section) can be increased. Therefore, by using the above-described property, the optimal scan frequency for each scan section can be found or determined by using the embodiment of the present invention, which is described above after rearranging the scan pattern, thereby further reducing the overall scan test time.

In the method of rearranging scan patterns, the scan patterns on the original set of scan patterns are arbitrarily rearranged one or more times, and the optimum shift frequency is grasped according to the preceding embodiment for each set of rearranged scan patterns, It is possible to determine what is required by the arrangement of the scan patterns. In another embodiment, there are various methods such as arranging the scan patterns having the smallest bit pattern difference between the scan patterns adjacent to each other.

As another example of the scan pattern rearrangement, a method of locating scan patterns that are not sequentially followed by K (one or more integer) scan patterns and successively finding an optimal shift frequency to search for is used to obtain the highest shift frequency The scan pattern can be determined as the next pattern of the Kth scan pattern.

Some or all of the operations of rearranging the order of the scan patterns may be performed by firmware and / or software, such as a processor included in the test apparatus, or may be performed in another separate apparatus such as a computer.

Also, when it takes a long time to find the optimal scan pattern arrangement, constraints such as the number of scan pattern relocation times or the time required to try to find the optimal scan pattern arrangement can be set.

Also, in at least one embodiment of the present invention, the optimal frequency of at least two respective test data may be used to reduce the stress test or burn-in test time of the IC chip or to increase the test quality. In at least one embodiment of the present invention, the optimal shift frequency for each of at least two respective scan patterns or scan sections may be used to reduce the stress test or burn-in test time of the IC chip or to increase the test quality have. The optimal shift frequency for each scan pattern or scan section can be found by minimizing the scan test time according to at least one embodiment of the present invention.

Here, a stress test or a burn-in test generally tests the quality of an IC chip by accelerating aging by applying stress to the IC chip or applying a high voltage and a high temperature to the IC chip by operating the IC chip for a long time, -life failure) to find an IC chip. Generally, burn-in tests are conducted for several hours or more in a high-temperature environment of 100 or more. Hereinafter, a stress test or a burn-in test is collectively referred to as a burn-in test. A test apparatus capable of performing such a burn-in test is also called a burn-in test apparatus.

The deterioration of the IC chip is greatly affected by the heat generation, and the heat generation is greatly influenced by the power consumption of the IC chip.

For example, Equation 2 below shows the major factors affecting dynamic power dissipation, which is the power consumption of an IC chip circuit.

a: activity factor

C: average switched capacitance (at each cycle)

f: circuit frequency

V _DD : supply voltage

The circuit portion of the IC chip which is activated according to the bit pattern of the scan pattern in the scan mode of the IC chip may be changed. In general, in the scan mode of the IC chip, switching activities occur in a larger portion of the circuit than in the functional mode. Therefore, in the scan mode, as shown in Equation (2), the average switching capacitance value C increases and the power consumption P can be increased.

Also, if the shift frequency is increased, the power consumption P of the IC chip may increase in proportion to the operating frequency f of the IC chip circuit as shown in Equation (2).

The increased switching operation of the IC chip further increases the power consumption of the IC chip, thereby raising the heat generation temperature of the IC chip. Therefore, the deterioration of the IC chip can be further accelerated.

In at least one embodiment of the present invention, the burn-in test device may use the maximum shift frequency that can be assigned to each test data or each scan section previously examined to further accelerate aging during burn-in testing to reduce burn-in test time.

For example, the burn-in test apparatus can accelerate a burn-in test using a scan pattern or scan section during a burn-in test of an IC chip. At this time, a scan test can also be performed.

In addition, when the nominal shift frequency is used in the scan shift operation, high stress may be applied to some of the circuit regions activated by the scan pattern and relatively low stress may be applied to the other portions. However, as an example, the scan patterns of the test data are divided into scan sections, and the burn-in test is performed using the maximum shift frequency assignable to each divided scan section, so that only a specific area on the circuit is aged faster or relatively slow The progress can be reduced.

For example, FIG. 41 shows a case where the shift frequency is not optimized (4100) with respect to the scan patterns of the test data, and the case where the scan frequency is optimized (4110) by dividing the scan patterns into scan sections It shows difference of heat of IC chip. That is, it can be seen that, when the test section 4110 in which the shift frequency is not optimized (4100) is used (4110) in which the shift frequency is optimized, a more balanced and high heat generation occurs.

That is, it is possible to improve the quality of the burn-in test as well as the burn-in test by applying stress more balanced to different parts of the IC chip activated by the bit pattern of the scan pattern. The burn-in test time can be shortened or the quality can be increased by using the maximum usable frequency of each scan section of the test data for testing the chip.

37 and 38 are block diagrams showing the configuration of a burn-in test apparatus according to at least one embodiment of the present invention.

37 and 38, the burn-in test apparatus includes host computers 3700 and 3800, tester bodies 3710 and 3810, test heads 3720 and 3820, interface boards 3730 and 3830, temperature controllers 3760, 3870, chambers 3750, 3860 and a prober 3850.

A device under test (DUT) located on the interface board for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it may further include a prober.

The tester bodies 3710 and 3810 can control the scan test and the burn-in test as a whole. For example, the tester body controls overall processes such as setup for DUT testing, generation of electrical signals for DUT testing, observation and measurement of DUT test result signals, and temperature control of chamber through temperature controller. The tester body may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like. And may further include a device power supply that supplies power to the DUT according to an embodiment. In addition, the tester main body includes a signal processing processor (DSP) (not shown) for processing various digital signals, a controller for controlling the test head, a controller for applying signals to the DUTs 3740 and 3840, and a signal generator Hardware, software, firmware, and the like. The tester body is also called a mainframe or server.

The host computer 3700, 3800 can be a computer such as a personal computer, a workstation, or the like, and is a device that enables a user to execute a test program, control a test process, and analyze test results. In general, the host computer may include a central processing unit, a storage unit such as a memory or a hard disk, a user interface, and the like, and may be connected to the tester body by wire or wireless communication. The host computer may include dedicated hardware, software, firmware, etc. to control the test. Although the host computer and the tester main body are shown separately from each other in this embodiment, the host computer and the tester main body can be realized as a single device.

As an example of the memory of the tester main body or the host computer, a DRAM, an SRAM, a flash memory, or the like can be used, and programs and data for performing the DUT test can be stored in the memory.

Software or firmware of the tester main body or host computer is a device driver program, an operating system (OS) program, and a DUT test program for burn-in test or scan test. The program is stored in memory in the form of instruction code for performing, for example, setup for DUT test, generation of a signal for DUT test, observation analysis of DUT test result signal, etc., and is performed by the central processing unit . Thus, the scan test pattern can be applied to the DUT by such a program. It is also possible to obtain the DUT test and the reporting and analysis data of the test result automatically through the program. The language used in the program can be a variety of languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The tester body or the central processing unit of the host computer is a processor, which executes the code of the software or program stored in the memory. For example, when receiving a user command through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes the command through a software or a program, and outputs the result to a user interface such as a speaker, To the user.

The user interface of the tester body or the host computer allows information to be exchanged between the user and the device and to transmit commands. For example, there are an interface device for user input such as a keyboard, a touch screen, a mouse, a voice recognition device and the like, and an output interface device such as a speaker, a printer, and a monitor.

The test heads 3720 and 3820 include channels and the like for electrical signal transmission between the tester body and the DUT. An interface board is provided above the test head. Generally, an interface board used for testing a packaged IC chip is called a load board, and an interface board used for testing an IC chip on a wafer is called a probe card.

Chambers 3750 and 3860 are spaces that can agitate the DUT. The chamber controls the temperature of the DUT located in the chamber under the control of the temperature control unit. The temperature control unit may be included in the tester body or the host computer. The tester body or host computer can also control the burn-in test time or supply voltage for the DUT.

37 and 38 are merely examples for facilitating the understanding of the present invention, and each of the configurations may be integrated into one unit, or one unit may be divided into a plurality of units, Various design changes are possible.

37 and 38 may be implemented to perform the burn-in test and the scan test at the same time, or to perform only one of them.

In at least one embodiment of the present invention, the burn-in test apparatus can perform the burn-in test using the optimal shift frequency for each scan section as described above. In at least one embodiment of the present invention, a test for determining whether the chip is normal may also be performed.

In at least one embodiment of the present invention, the burn-in test device may perform a burn-in test with a scan test using an optimal shift frequency for each scan pattern or scan section as described above. Since the switching operation occurs in the IC chip circuit portion of the IC chip in the scan mode rather than in the functional mode, the scan test can be further accelerated to save the burn-in test time. Further, if the burn-in test is performed using the maximum shift frequency assignable to each divided scan section, not only the burn-in test time can be further reduced, but also the phenomenon that the aging is accelerated only in a specific area on the circuit by a specific scan pattern can be reduced . That is, it is possible to improve the quality of the burn-in test by applying the stress to the IC chip in a balanced manner as a whole, and the effect can be further increased as the length of the scan section using the optimized shift frequency is made smaller.

In addition, the present invention is not limited to the case where the scan test is performed simultaneously with the burn-in test, and includes only the process of shifting the scan pattern during the burn-in test, and may not perform the scan test itself.

FIG. 39 is a conceptual diagram illustrating an example of the temperature effect on the IC chip when the burn-in test is performed using a single scan shift frequency according to at least one embodiment of the present invention. FIG.

Referring to FIG. 39, a plurality of scan patterns are all shifted to the scan path of the IC chip 3900 using the same scan shift frequency (for example, 25 MHz). The main part in which the IC chip is activated by each scan pattern may be different. For example, the main portion 3910 of the IC chip activated by the scan pattern 1 3930 and the main portion 3920 of the IC chip activated by the scan pattern 2 3932 may be different from each other.

In addition, depending on each scan pattern, the part to be activated on the IC chip may have different heat generated depending on the scan shift frequency, the number of switching cycles of the circuit depending on the scan pattern, and the like. For example, the temperature of the main part 3910 of the IC chip activated by the scan pattern 1 is a 占 폚, and the temperature of the main part 3920 of the IC chip activated by the scan pattern 2 may be b 占 폚.

The shift frequency can be increased to accelerate aging of the burn-in test by generating more stress or heat in the IC chip. However, if the shift frequency is excessively increased, there may arise a problem of over kill in which a normal IC chip is determined to be a defective product. Conversely, when the shift frequency is lowered, there is a problem that stress and heat generated in the IC chip are insufficient and the aging of the burn-in test can not be efficiently accelerated.

FIG. 40 is a conceptual diagram illustrating an example of the temperature effect on the IC chip when the burn-in test is performed using the optimal frequency for each scan pattern according to at least one embodiment of the present invention. 39 and 40 show an example using the same scan pattern as the IC chip.

Referring to FIG. 40, the aging of the IC chip can be accelerated by shifting the scan path using the optimal shift frequency for each scan pattern.

The burn-in test generally takes more than several tens of hours in a high-temperature environment of more than 100 ° C, so time and power consumption during burn-in test increase the test cost. That is, in general, IC chip test service companies charge a fee in proportion to the test time, so the time required for chip test has a great influence on the chip cost. In addition, the high temperature above 100 ° C formed in the chamber used for the burn-in test is generally made using electricity, and the cost for this is also significant and can have a significant impact on the cost of the test service company and on the chip cost.

Therefore, reducing the power consumed by the burn-in test time and the burn-in test is very important for reducing the test cost. Reducing the burn-in test time can also be very important for the product's time-to-market.

For example, when the maximum possible scan shift frequency of the scan pattern 1 3930 in FIG. 39 is 25 MHz and the shift frequency of the scan pattern 2 3932 can be higher, The shift frequency can be optimized and increased to further accelerate the deterioration of the IC chip by the temperature (c DEG C) higher than the temperature (b DEG C) of FIG.

FIGS. 39 and 40 illustrate a case where a shift frequency is assigned to a scan pattern by a shift pattern for convenience of explanation. However, as shown in FIGS. 5 to 10, when a scan pattern is divided into at least two scan sections, You can shift to the scan path by frequency.

Also, for example, the junction temperature of the chip to be tested needs to be maintained within a certain range so that the burn-in test time or the burn-in test quality can be predicted. For example, the junction temperature of the IC chip or the device under test can be determined by the relationship shown in Equation 3.

Where T _j is the junction temperature of the device under test or IC chip, T _a is the ambient temperature, P is the power consumption of the device under test or IC chip, and θ _ja is the temperature of the IC Respectively.

Referring to Equation (3), the controllability of T _j depends on the control chart of T _a and P. For example, T _a can be controlled to an appropriate temperature by using a device such as a chamber or a thermal chuck for controlling the temperature of the device under test or the external environment of the IC chip. Therefore, there is a need for a method for controlling power consumption P during a chip burn-in test. For example, the fluctuation of power consumption during the chip burn-in test can significantly affect the junction temperature T _j of the chip and can adversely affect the reliability screening process of the chip have.

The time required for the burn-in test can be predicted based on the median value of the junction temperature T _j in Equation (3). For example, the junction temperature may be determined by the value of the power consumption P _burn-in of FIG. P _{burn -in} may be a median value or average power consumption by the test data, or may be a power consumption value predicted in a good quality burn-in test.

FIG. 42 is a graph showing an example of power consumption occurring during the burn-in test before the power consumption of the test data is adjusted, and FIG. 43 is an example of power consumption occurring during the burn-in test after the power consumption of the test data is adjusted. Fig.

Referring to FIG. 42, an overburn-in state may occur when the power consumption is higher than _{Pburn- in} or _{margin - high} P _{margin - high} . This can adversely affect the yield of the chip.

If the power consumption is lower than P _{burn- in} or margin P _{margin - low} , an under burn-in condition may occur. This can create a situation where a chip with potential defects passes the test process.

Therefore, the power consumption by the test data needs to be close to P _{burn -in} as shown in FIG. 43 so that the prediction of burn-in time and burn-in quality is accurate. That is, it is necessary to minimize variation of the power consumption by the test data so that the variation of the heat generation of the IC chip is minimized.

An embodiment of a method for reducing the burn-in time and improving the burn-in quality by optimizing the power consumption in the burn-in test is as follows.

Step 1

The test data is divided into at least two sub data. For example, as shown in FIG. 43, the test data may be divided into three sub data based on the test time axis.

Step 2

The shift frequency used to input each sub data to the chip is searched or determined such that the difference in power consumption of at least two or more sub data divided in step 1 is minimized. Or the frequency used to input each sub data to the chip so that the power consumption by each sub data is close to or equal to the predicted power consumption (or predicted current consumption) for the burn-in test. For example, as shown in FIG. 43, the frequency of each sub data can be adjusted so that the power consumption by the test data is close to P _{burn -in} .

Step 3

The burn-in test is performed using the frequencies found or determined in step 2 for each sub-data. For example, as shown in FIG. 43, it is possible to perform a burn-in test such that the power consumption of each sub data period is close to P _{burn -in} .

The sub data in Steps 1 to 3 is a scan section or functional test data (data used for testing regarding the function of the chip).

Steps 1 to 3 may be performed in the same device or different devices, respectively, depending on the embodiment, and may be performed in an apparatus such as a test device or a computer, for example.

In another embodiment, another method for reducing the burn-in time and making the burn-in time predictable and improving the burn-in quality by optimizing the power consumption during the burn-in test is as follows.

Step 1

The test data is divided into at least two sub data.

Step 2

For each subdata, the maximum shift frequency at which the test result of the normal chip appears normal is determined or determined. For example, the maximum shift frequency may be an optimized frequency to minimize the test time, or a frequency that reflects the margin at the maximum shift frequency.

Step 3

In step 2, the power consumption or current consumption is measured or estimated using the maximum shift frequency determined for each subdata or determined.

Step 4

Finds subdata where the measured or estimated power consumption or current consumption in step 3 is greater than the power consumption criterion for the optimal burn-in test. For example, the criteria for power consumption for an optimal burn-in test may be P _{burn -in} or P _{margin-high in} FIG. 42 or FIG.

Step 5

The frequency of the sub data found in step 4 is lowered to adjust the power consumption of the sub data to be equal to or close to the power consumption or current consumption for the optimum burn-in test. For example, the criteria for power consumption for an optimal burn-in test may be P _{burn -in} , P _{margin- high} or P _{margin -low in} FIG. 42 or FIG. Also, there is a case in which power consumption or current consumption of each sub data measured or estimated in step 3 is smaller than power consumption or current consumption for optimum burn-in test. However, care must be taken when the frequency of the corresponding sub data is increased to be equal to or close to the power consumption or current consumption for the optimum burn-in test.

Step 6

The burn-in test is performed using the shift frequency of each sub data adjusted in step 5.

In at least one embodiment of the invention, the subdata from step 1 to step 6 is a scan section or functional test data.

Steps 1 to 6 may be performed in the same device or different devices, respectively, depending on the embodiment, and may be performed in an apparatus such as a test device or a computer, for example.

In another embodiment, a method for finding or determining a frequency corresponding to a desired power consumption is as follows. A certain frequency is used to measure or estimate the power consumption consumed by the sub-data. Then, using the relation between power consumption and frequency as shown in Equation 2, α x C x V _dd ² Lt; / RTI > The frequency value to be sought can be calculated by substituting the constant value and the desired power consumption value into Equation (2).

In at least one embodiment of the invention, a desired frequency can be found or determined by measuring or estimating the power consumption consumed by the sub-data while increasing or decreasing the frequency.

In at least one embodiment of the invention, the power consumption consumed by the subdata may be measured or estimated using a device or software that measures or estimates power or current consumption.

44 is a flowchart illustrating an example of a method for finding an optimal shift frequency for each scan section in order to minimize the time of the burn-in test according to at least one embodiment of the present invention.

Referring to FIG. 44, the burn-in test time minimizing apparatus divides one or more scan patterns into at least two scan sections (S4400). As an example of the division of the scan pattern, the method shown in Figs. 5 to 10 can be used. The burn-in test time minimizing apparatus allocates a plurality of shift frequencies to each scan section (S4410). Here, the value of the shift frequency assigned to each scan section is smaller than the shift frequency at which the output pattern of the scan path is different from the predicted pattern. The burn-in test time minimizing device performs a burn-in test while shifting the corresponding scan section using the shift frequency allocated to each scan section (S4420).

The division of the scan pattern into the scan section S4400, the allocation of the scan frequency of the scan frequency S4410, and the execution of the burn-in test S4420 may be performed in the same device or in different devices, respectively.

The burn-in test time minimizing apparatus can find the shift frequency immediately before the output pattern and the predicted pattern are different from each other, or grasp the maximum shift frequency assignable to the scan section according to the increase or decrease of the shift frequency. According to an embodiment, each scan section may be assigned a shift frequency that is smaller than the maximum shift frequency found by increasing or decreasing the shift frequency.

For the burn-in test of the present invention, various embodiments may be used as a method of finding an optimal shift frequency for each scan section. For example, the burn-in test time minimizing apparatus can perform the method shown in FIGS. 12 to 33 to find an optimal shift frequency for each scan section. The method of changing the arrangement order of the scan patterns shown in FIG. 36 can also be applied for reducing the burn-in test time and improving the quality of the burn-in test.

45 is a block diagram illustrating an example of a burn-in test time minimization apparatus in accordance with at least one embodiment of the present invention.

Referring to FIG. 45, the burn-in test time minimizing apparatus includes a chamber control unit 4500, a shifting unit 4510, and a shift frequency determining unit 4520.

The chamber controller 4500 controls the voltage supplied to the IC chip to be inspected, the temperature, the burn-in test time, and the like.

The shift frequency determining unit 4520 grasps the optimum shift frequency shifted in the scan path of the IC chip in the scan section during the burn-in test. For example, the shift frequency determining unit 4520 can determine an optimum shift frequency for each scan section based on at least one of the various embodiments described above. Also, the optimum shift frequency can be grasped or determined by a separate device as well as the burn-in test time minimizing device, and the shift frequency determined or determined may be used by the shift frequency determining unit 4520.

The shifting unit 4510 shifts the scan section to the scan path by using the optimum shift frequency detected by the shift frequency determining unit 4520 while the burn-in test is performed by the chamber control unit 4500, Minimize it.

In at least one embodiment of the invention, it is possible to perform only a burn-in test using an optimized frequency for each scan section, or to perform a chip health test together with a burn-in test. The burn-in test time minimization device can perform the burn-in test together with the scan test previously.

The burn-in test time minimizing apparatus may be implemented as a part of the burn-in burn-in test apparatus in FIG. 37 and FIG. In at least one embodiment of the invention, it is possible to perform only a burn-in test using an optimized frequency for each scan section, or to perform a chip health test together with a burn-in test. For example, it is possible to perform only a burn-in test or a burn-in test and a scan test together using a set of scan patterns assigned with an optimized shift frequency for each scan section.

The burn-in test time minimizing apparatus can rearrange the order of the scan patterns shifted in the scan path by using the relocation method of the scan pattern shown in FIG. In this case, by switching the scan pattern of the pattern position rearranged on the set of scan patterns, the number of switching operations and the number of switching operations of the circuit on the IC chip can be changed from before rearrangement, have. Therefore, the shift frequency that can be assigned to the scan pattern (or the scan section) may be increased. Therefore, by using the above-described property, the optimal shift frequency for each scan section can be found or determined by using the embodiment of the present invention, which is discussed above, after the scan pattern relocation, and the overall burn-in test time can be further reduced or the test quality can be improved. In addition, the rearrangement of the scan pattern may be performed by a device for minimizing the burn-in test time, and also by a separate device such as a computer.

46 is a table showing experimental results using a test pattern of an MCU (Micro Control Unit) processor IC chip and an IC chip, in which a shift frequency determination scan section corresponds to one scan pattern one-to-one. FIG. 46 shows a power-limit-based method for finding the maximum possible shift frequency without power consumption exceeding the allowable power consumption of the IC chip by the scan pattern and the above shift frequency increase based method of the present invention (shift-frequency-scaling-based method) to show the maximum shift frequency found for each scan pattern.

Referring to FIG. 46, the optimization using the shift-frequency-scaling-based method is performed as shown in FIG. 46, the difference between the maximum shift frequency result by the power-limit-based method and the shift-frequency-scaling-based method is smaller than the difference between the actual IC chip and the IC chip In addition to the power consumption of the IC chip, the test environment also has a circuit structure and characteristics that can affect the shift frequency, and various physical conditions and environments.

The power consumption limit in FIG. 46 is about 285 mW as an average power consumption when the IC chip is operated in the functional mode at 80 MHz which is the functional frequency limit of the IC chip.

In general, the functional frequency limit and the frequency limit or scan shift frequency limit at which the IC chip may be damaged may be different. For example, the frequency limit may vary due to circuit operation characteristics, power consumption, signal crosstalk effects, and critical timing path due to scan test or functional mode of operation to be. And may be subject to various constraints such as differences in voltage or power supplied to different locations on the circuit.

The first column in FIG. 46 is the scan pattern number, and the second column is the power consumption due to the leakage current of the IC chip. The third column is the dynamic power consumption consumed by the scan shift using the nominal shift frequency of 25 MHz. The fourth column is the sum of the second and third columns and is the total power consumption per scan pattern when the nominal shift frequency of 25 MHz is used. The fifth column is the maximum possible shift frequency of each scan pattern without exceeding the power consumption limit of 285 mW.

The sixth column shows the test normal or failure as a result of the MCU IC chip test when tested with the shift frequency of the fifth column for each scan pattern.

The seventh column is the maximum shift frequency found using the shift frequency increasing / decreasing method according to the above-described method of the present invention, and all test results are normal.

The eighth column shows the increase / decrease ratio for the seventh column, which is the result of the shift-frequency-scaling-based method relative to the fifth column, which is the result of the power-limit-based method %).

Referring to FIG. 46, except for the sixth scan pattern in which the scan test is not performed normally in the power-limit-based method, the shift frequency-based method (Shift-frequency -scaling-based method) has a high shift frequency. For example, there may be a variety of reasons, such as a false critical path depending on the bit pattern being shifted or a bit on a scan pattern corresponding to a don't-care bit that does not affect the test result .

The IC chip can not be normally tested even if a shift frequency is used so that the power consumption consumed by the scan pattern does not exceed the allowable power consumption of the IC chip as in the case of the sixth scan pattern in FIG. Able to know. The reason for this is that the shift frequency limit is not limited to the power consumption but also to the signal delay time, the signal crosstalk of the critical timing path due to the circuit structure of the IC chip, Voltage or power differences, signal or power noise, chip manufacturing process variations, and physical characteristics of the circuit. This is because the test environment and conditions can also be influenced by the ambient temperature of the chip under test and the connection status of the chip and chip test equipment.

Even when the bit values of the scan section or the scan pattern are unintentionally shifted and loaded into the scan path during the process of grasping the optimum shift frequency through the increase / decrease of the shift frequency, the result after the scan capture operation The pattern may appear as a normal bit pattern on the scan path.

Therefore, before the scan section is loaded on the scan path through the shift frequency increase and scan capture, the output result of the main output port of the IC chip is compared with the predicted result, and it is confirmed whether the main output result is pass, You can find the frequency.

47 is a graph showing an example of a test fail hole that can be generated in the IC chip test.

In order to test an IC chip, there is a process of setting up a test apparatus, test data or a test program. At this time, an abnormal test failure may occur within the range of the normal shift frequency at which the normal IC chip should be judged to be fault-free. This abnormal test failure 4700 is referred to as a fail hole, a test frequency fail hole, or a fail hole in the period of the test frequency.

Referring to FIG. 47, when an IC chip is tested, an abnormal test failure (4700) occurs at 30 MHz. It is desirable to remove the test fail hole because it can make the IC chip mass production test unstable and adversely affect the yield.

Figure 48 is a graph illustrating an example of a method for solving a test fail hole problem in accordance with at least one embodiment of the present invention.

Referring to FIG. 48, as an embodiment of a method for solving the test fail hole problem, a test is performed on specific sub data that causes a test fail hole or affects occurrence of a fail hole There is a way to avoid that.

For example, there is a method in which the test output data of the IC chip for the sub data in which the fail hole is generated is not compared with the predicted data. Such a method may be referred to as expected data masking or expected result masking of test data. In the following embodiments, the sub data means a scan pattern, a scan section, or functional test data. The case where the test data masking method is applied to the scan pattern may be referred to as scan pattern masking or expected result masking of the scan test. As another example, there is a method of eliminating or not using sub data that affects the occurrence of a test fail hole.

In the case of FIG. 48, the second sub data at which the fail hole is generated at 30 MHz can be found and masked or removed. However, masking or removing subdata may reduce the fault coverage of the IC under test. In addition, the method of masking or removing the sub data may be fault-free test determination that the faulty IC chip is fault-free. This can result in a field escape problem in which a faulty IC chip goes out of the field.

Therefore, as another embodiment of the method for solving the test fail hole problem, it is possible to search the frequency corresponding to the sub data and the fail hole which are generated or affect the occurrence of the fail hole, Or a frequency at which no fail hole is generated in a specific sub data that affects the occurrence of a fail hole is used.

Figure 49 is a flow diagram of a method for solving the fail hole problem in accordance with at least one embodiment of the present invention.

Referring to FIG. 49, the test apparatus selects sub data constituting test data (S4900). Here, the sub data may be a scan pattern or a scan section. The test apparatus performs the test of the IC chip while increasing or decreasing the frequency of the sub data (S4910), and finds a usable frequency or a fail hole for the selected sub data based on the PASS or FAIL test result of the IC chip (S4920). Then, the IC chip is tested using a frequency at which fail holes are not generated for the selected sub data (S4930).

For example, various methods as described above can be used to find a scan pattern or an available shift frequency of a scan section using a shift frequency increase or decrease when looking for a fail hole for a scan section.

50 is a diagram illustrating another example of a method for solving the fail-hole problem according to at least one embodiment of the present invention.

Referring to FIG. 50, frequencies below 25 MHz may be used for the second sub data in which a test fail hole 5000 is generated. Here, the sub data may be a scan pattern, a scan section, or functional test data.

Let the first sub data, the second sub data, and the third sub data be the first scan pattern, the second scan pattern, and the third scan pattern, respectively. The first scan pattern, the second scan pattern, and the third scan pattern are sequentially shifted to the scan path of the IC chip to be tested. A method of finding a test fail hole 5000 for a scan section included in the second scan pattern or the second scan pattern is performed by using a shift frequency increase / Various methods can be used.

For example, a shift frequency of the second scan pattern is increased or decreased, and a first scan pattern positioned before or after the second scan pattern or a third scan pattern is shifted by using a frequency capable of normally inputting to the scan path. A fail hole and a usable shift frequency range for the second scan pattern can be found using the scan test result. The shift frequencies of the first scan pattern or the third scan pattern used to find a fail hole or a usable frequency range for the second scan pattern may be the same or different from each other.

The output pattern of the first scan pattern located in front of the second scan pattern as well as the output pattern of the second scan pattern may be predicted in the scan test process for finding a fail hole or usable frequency range for the second scan pattern, Patterns can be compared. At this time, when the test results of the first scan pattern and the second scan pattern are all normal, the current shift frequency is the usable shift frequency of the second scan pattern. As another example, the output pattern of the third scan pattern, which is a scan pattern located after the second scan pattern, can be compared with the predicted pattern. When the test results of the second scan pattern and the third scan pattern are all normal, the current shift frequency is the usable shift frequency of the second scan pattern.

A scan pattern that generates a test fail hole or affects generation of a fail hole may be a first scan pattern or a third scan pattern input before or after the second scan pattern. The shift frequency of the second scan pattern may affect the bit value on the scan path when the output pattern of the first scan pattern is shifted out. Also, when the test result of the second scan pattern shifts out, the bit value on the scan path can be influenced by the shift frequency shifting the third scan pattern into the scan path. Therefore, if there is a test fail hole in a test result by a specific scan section or a scan pattern, it is determined whether a scan section or a scan pattern positioned before or after the scan pattern affects generation of a fail hole.

For example, in the second scan pattern, a frequency capable of normally shifting the scan path is used, and the test result is confirmed while increasing the shift frequency of the third scan pattern. At this time, if the test result by the second scan pattern is failure and the test result by the third scan pattern is normal, the shift frequency of the third scan pattern is a frequency at which the test failure of the second scan pattern does not occur do. By doing so, the influence of the third scan pattern on the fail hole that appears in the test result of the second scan pattern can be eliminated.

In at least one embodiment of the invention, a scan test is performed with increasing or decreasing the shift frequency. And, when a fail hole occurs at a certain shift frequency, a specific scan pattern in which a scan test using a shift frequency corresponding to the fail hole fails is searched. A chip test is performed using a shift frequency lower than a shift frequency at which a fail hole is generated, in a specific scan pattern and a scan pattern adjacent to a specific scan pattern. That is, a shift frequency lower than the shift frequency at which a fail hole is generated can be used for neighboring scan patterns that may affect the fail hole.

In at least one embodiment of the present invention, the shift frequency increase or decrease is used to find the scan section or scan pattern and corresponding shift frequency at which the fail hole is generated. A shift frequency at which a fail hole is not generated within a margin range of a shift frequency considering a manufacturing process and a test process is used for a scan section or a scan pattern. For example, a shift frequency that is higher than the shift frequency at which the fail hole is generated and does not generate a fail hole within the margin range may be used. As another example, a shift frequency at which a fail hole is generated may be used in a scan section where a fail hole is generated or in a scan section or a scan pattern adjacent to the scan pattern, in which a fail hole is higher than a shift frequency at which a fail hole is generated but within a margin range.

As described above, if the frequency or frequency period in which fail-holes are not generated for specific sub data is used at the time of mass production test of the chip, the failure detection rate of the IC chip due to the method of masking or removing the sub data the problem of low fault coverage can be eliminated. In addition, the field escape problem in which a faulty IC chip enters the field can be eliminated. It can be used to test a chip by looking for a range of frequencies of a specific frequency or frequency that fail-holes do not occur.

Figure 51 is a diagram illustrating a method for finding a shift frequency for test time reduction and yield improvement in accordance with at least one embodiment of the present invention.

Referring to FIG. 51, it is assumed that at least two or more scan sections are shifted by using shift frequencies different from each other in the scan path of the chip, and the chip is tested. At this time, a shift frequency with a margin increased is used for the first scan section in which the test normal margin is small based on the specific shift frequency 5100 in which test results are all normal in two or more scan sections. Or a shift frequency with a reduced margin is used in the second scan section in which the test normal margin of the shift frequency is large.

The shift frequency margin of the scan section can be determined or determined using the test normal or failure information in the scan section. For example, a margin may be found or determined that represents the interval between the frequency of the frequency or frequency of the test normal and the failure of the scan section and the specific shift frequency 5100. Both the scan section using the shift frequency reflecting the margin and the scan section located in front of it should be normal.

Increasing the margin for scan sections with small shift frequency margins will be less influenced by variations in chip manufacturing process and test environment. Therefore, the improvement of the yield may be effective.

In addition, the test time can be reduced by reducing the margin for a scan section having a large margin of the shift frequency or shift frequency period.

Thus, the opposite effects of yield improvement and test time reduction can be achieved by considering the frequency margin per scan section.

Referring to FIG. 51, the first scan section and the second scan section are all test passes at a nominal shift frequency 5100 of 20 MHz. If the margin of the shift frequency of the first scan section on the basis of 20 MHz is smaller than the predetermined reference value, the test apparatus can increase the margin of the shift frequency of the first scan section to help improve the yield in the mass production test of the chip . That is, the use shift frequency of the first scan section is changed to a value smaller than 20 MHz so as to satisfy the reference value. Also, if the margin of the shift frequency of the second scan section or the cycle of the shift frequency is larger than the reference value on the basis of 20 MHz, the margin of the cycle of the frequency or frequency of the second scan section is reduced to reduce the entire test time . The use shift frequency of the second scan section is changed to a value larger than 20 MHz so as to satisfy the reference value.

In this manner, in performing the chip test by searching for the optimal shift frequency for at least two or more scan sections, the shift timing of the boundary bits of neighboring scan sections may become a problem.

Assuming that the period of the shift frequency between the last bit of the scan section S1 and the first bit of the scan section S2 shifted in the scan path sequentially thereafter is CP_boundary (Clock Period of Boundary Bits), the optimum maximum shift frequency The first CP_boundary of S1 and S2 and the second CP_boundary of S1 and S2 where the cycle of the optimal shift frequency is determined may be different from each other. For example, if the second CP_boundary2 is smaller than the first CP_boundary, the scan test using the scan sections S1 and S2 may determine that there is a failure for a normal chip.

In this case, the following method can be used to solve the shift timing problem of the boundary bits of neighboring scan sections.

(1) When the optimum maximum shift frequency of the scan section S1 is determined, when the optimum maximum shift frequency of the scan section S2 to be shifted following the scan section S1 is found, the scan section S1 determines the optimum shift frequency Lt; / RTI >

(2) a clock edge at which a shift operation of a scan bit is performed is located at a position close to the boundary or boundary of the CDP (Clock Definition Period). CDP is a time interval in which the shape of the clock is defined, and the rising or falling timing of the clock signal within the interval is defined. CDP can be set in the equipment or test data.

(3) adjusts the period or shift time interval of the shift frequency between the last bit of the scan section S1 and the first bit of the scan section S2, which is shifted sequentially to the scan path after the last bit. For example, when a scan test is performed using a scan pattern including S1 and S2, a normal chip can be adjusted to a cycle of a shift frequency at which it can be determined to be normal. The period or shift time interval of the shift frequency can be defined in the test data or set in the test device. For example, when creating new test data to which a cycle of the optimum shift frequency is assigned for each of the scan sections S1 and S2, timing information for the last bit of the scan section S1 or the first bit of S2 is newly created, When a scan test is performed using a scan pattern including S1 and S2, a period of a shift frequency that can determine a normal chip as normal can be assigned. For example, a period of a nominal shift frequency, or the like.

(4) When it is determined that there is a failure in a scan test for a normal chip due to a shift timing problem of boundary bits of neighboring scan sections, the cycle of the shift frequency of the scan section or the scan pattern including the boundary bit is increased .

The function for performing the present invention and the scan section information obtained by performing the present invention or the scan section information in which the information is reflected can be implemented as a computer readable code or data in a computer readable recording medium. An example of the code is an executable computer program or software. The code or data may be executed or used in a device such as a scan test device, a burn-in test device, or a computer. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include various types of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, optical data storage, and the like.

The computer-readable recording medium may also be distributed and distributed in a networked computer system so that computer readable code or data may be stored and executed in a distributed manner. In at least one embodiment of the invention, the computer program code or data may be stored on a server computer and accessed from a client computer to a server computer for use in code or data or downloaded to a client computer for use or storage. For example, you can run program code on a server computer or client computer.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (23)

A scan pattern is input to the scan input port of an IC chip including a scan input port, a scan path, and a scan output port, and an output result output from the scan output port is compared with a predetermined prediction result to determine whether the IC chip has a defect Scan test data input to the scan input port is searched for a usable shift frequency for a scan section constituted by a part or all of at least one scan pattern input to the scan input port A computer-readable recording medium having recorded thereon a computer program,
First data including at least one scan section configured to be sequentially input to the scan input port; And
And second data including timing information of at least one or more scan sections included in the first data, and storing the generated scan test data in the recording medium,
In the second data, the timing information of a target scan section to which an available shift frequency is to be sought is different from the timing information of a scan section located before or after the target scan section,
The timing information is information for controlling a shift frequency or a shift clock cycle of a scan section input to the scan input port,
Wherein the usable shift frequency of the target scan section is obtained by inputting the scan section located before or after the target scan section and the target scan section as different timing information to the scan input port, Wherein the scan test data is searched based on the scan test data. The method according to claim 1,
Wherein the first data comprises a plurality of target scan sections,
Wherein the timing information of the plurality of target scan sections are different from each other in the second data. The method according to claim 1,
Wherein the timing information in the second data includes at least one of a shift frequency for shifting a scan section to the scan input port or shift frequency information corresponding to a cycle of a shift clock and scan section identification information for identifying the scan section Wherein the scan test data is recorded on the recording medium. The method according to claim 1,
Wherein the first data includes a second scan pattern constituting the target scan section and a first scan pattern located immediately before the second scan pattern,
Wherein the first scan pattern and the second scan pattern are sequentially input to the scan input port. The computer-readable recording medium according to claim 1, wherein the first scan pattern and the second scan pattern are sequentially input to the scan input port. 5. The method of claim 4,
A first prediction pattern for an output pattern input from the scan output port by inputting the first scan pattern into the scan input port; And
And a second prediction pattern for an output pattern input from the scan output port by inputting the second scan pattern to the scan input port. A recording medium capable of. 2. The method according to claim 1,
And a don't-care pattern in a predicted pattern of an output pattern input from the scan output port by inputting a first scan pattern input to the scan input port into the scan input port. A computer-readable recording medium recording a computer program for performing scan test data creation. 5. The method of claim 4,
Wherein the first data includes a third scan pattern positioned immediately after the second scan pattern,
Wherein the second scan pattern and the third scan pattern are sequentially input to the scan input port. ≪ Desc / Clms Page number 20 > 8. The method of claim 7,
Wherein the first data includes a third prediction pattern for an output pattern input from the output port by inputting the third scan pattern to the scan input port. A computer readable recording medium. The method according to claim 1,
Wherein the number of scan patterns used to search for the available shift frequency of the target scan section is less than or equal to the total number of scan patterns for testing the IC chip. A computer readable recording medium. A scan pattern is input to the scan input port of an IC chip including a scan input port, a scan path, and a scan output port, and an output result output from the scan output port is compared with a predetermined prediction result to determine whether the IC chip has a defect In a scan test for generating scan test data for searching a usable shift frequency for a scan section constituted by a part or all of at least one scan pattern input to the scan input port, ,
Storing in the recording medium first data including at least one scan section configured to be sequentially input to the scan input port;
And storing second data including timing information of each scan section included in the first data on a recording medium,
In the second data, the timing information of a target scan section to which an available shift frequency is to be sought is different from the timing information of a scan section located before or after the target scan section,
The timing information is information for controlling a shift frequency or a shift clock cycle of a scan section input to the scan input port,
Wherein the usable shift frequency of the target scan section is obtained by inputting the scan section located before or after the target scan section and the target scan section as different timing information to the scan input port, Wherein the scan test data is searched based on the scan test data. 11. The method of claim 10,
Wherein the first data comprises a plurality of target scan sections,
Wherein in the second data, timing information of a plurality of target scan sections is different from each other. 11. The method of claim 10,
Wherein the timing information includes at least one of a shift frequency for shifting a scan section to the scan input port or shift frequency information corresponding to a cycle of a shift clock and scan section identification information for identifying the scan section. How to create scan test data. 11. The method of claim 10,
Wherein the first data includes a second scan pattern constituting the target scan section and a first scan pattern located immediately before the second scan pattern,
Wherein the first scan pattern and the second scan pattern are sequentially input to the scan input port. 14. The method according to claim 13,
A first prediction pattern for an output pattern input from the scan output port by inputting the first scan pattern into the scan input port; And
And a second predicted pattern for an output pattern input from the scan output port by inputting the second scan pattern into the scan input port. 11. The method of claim 10,
The first data may include a don't-care pattern as a predictive pattern of an output pattern output from the scan output port by inputting a first scan pattern input to the scan input port to the scan input port Wherein the scan test data is generated based on the scan test data. 14. The method of claim 13,
Wherein the first data further includes a third scan pattern positioned immediately after the second scan pattern,
Wherein the second scan pattern and the third scan pattern are sequentially input to the scan input port. 17. The method of claim 16,
Wherein the first data includes a third prediction pattern for an output pattern input from the output port by inputting the third scan pattern into the scan input port. 11. The method of claim 10,
Wherein the number of scan patterns used for finding the available shift frequency of the target scan section is set to be less than or equal to the total number of scan patterns for testing the IC chip. 11. The method of claim 10,
Based on the bit length of the scan section from at least one scan pattern, the number of sections that divide the scan pattern into scan sections, the boundary bit at which the bit value changes in the scan pattern, or the estimated time required to search for the optimal shift frequency, Wherein the scan test data is divided into a plurality of scan test data. A computer-readable recording medium having recorded thereon a program for executing the method for generating a scan test data according to any one of claims 10 to 19. A scan pattern is input to the scan input port of an IC chip including a scan input port, a scan path, and a scan output port, and an output result output from the scan output port is compared with a predetermined prediction result to determine whether the IC chip has a defect The scan test apparatus comprising:
A part or all of at least one scan pattern inputted to the scan input port constitutes at least one scan section,
The scan test data stored in the recording medium to search for an available shift frequency for the at least one scan section,
First data including at least one scan section configured to be sequentially input to the scan input port; And
And second data including timing information of each scan section included in the first data,
In the second data, the timing information of a target scan section to which an available shift frequency is to be sought is different from the timing information of a scan section located before or after the target scan section,
The timing information is information for controlling a shift frequency or a shift clock cycle of a scan section input to the scan input port,
Wherein the usable shift frequency of the target scan section is obtained by inputting the scan section located before or after the target scan section and the target scan section as different timing information to the scan input port, The scan test apparatus comprising: A scan pattern is input to the scan input port of an IC chip including a scan input port, a scan path, and a scan output port, and an output bit value output from the scan output port is compared with a predetermined prediction result, The method of claim 1,
A part or all of at least one scan pattern inputted to the scan input port constitutes at least one scan section,
The scan test data stored in the recording medium to search for an available shift frequency for the at least one scan section,
First data including at least one scan section configured to be sequentially input to the scan input port; And
And second data including timing information of each scan section included in the first data,
In the second data, the timing information of a target scan section to which an available shift frequency is to be sought is different from the timing information of a scan section located before or after the target scan section,
The timing information is information for controlling a shift frequency or a shift clock cycle of a scan section input to the scan input port,
Wherein the usable shift frequency of the target scan section is obtained by inputting the scan section located before or after the target scan section and the target scan section as different timing information to the scan input port, The scan test method comprising: A computer-readable recording medium on which a program for executing the method according to claim 22 is recorded.

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