WO2016068385A1 - Method and device for minimizing scan test time - Google Patents

Abstract

Disclosed are a method and a device for minimizing scan test time. A device for minimizing scan test time divides a plurality of scan patterns into two or more scan sections, acquires, with respect to each scan section, a first shift frequency in which an output pattern of a scan chain differs from a prediction pattern by means of increase and decrease of shift frequencies, and then determines a second shift frequency, which is smaller than the first shift frequency, as a shift frequency of each scan section.

Description

Method and apparatus for minimizing scan test time

The present invention relates to an integrated circuit (IC) chip scan test, and more particularly, to a method and apparatus for optimizing a shift frequency to minimize the time of a scan test.

The most common way to test an IC chip is to apply test data to the IC chip's input and compare the observed value at the IC chip's output with a known predicted value. However, if you want to test an IC chip that contains a sequential logic with storage elements such as flip-flop, externally apply the desired value to the flip-flop in the IC chip or the value of the flip-flop. It is very difficult to observe from outside. There is a scan design method to solve this problem.

The scan design method is one of the design for testability (DFT) methods considering the test used to increase the controllability and observability of the circuit. Using the scan design method, a small but high fault coverage test is performed using the Automatic Test Pattern Generator (ATPG) software, which automatically generates test patterns based on the structural information of the circuit. Data can be obtained.

In other words, the scan design turns sequential logic into combinational logic during the scan test, making it easier to control and observe the circuit outside the chip, and minimize the size of the test data through ATPG. have. Test data obtained through scan design and ATPG software consists of at least one scan pattern. In general, scan patterns are ordered in the performance of scan tests. The test pattern set consists of one or more scan patterns.

1 is a diagram illustrating an example of an IC chip to which a conventional scan design method is applied.

Referring to FIG. 1, the IC chip 100 is a sequential logic composed of at least one combination circuit 110 and a plurality of flip- flops 120, 130, and 140. In the case of FIG. 1, the flip- flops 120, 130, and 140 may be a scan flip-flop of a multiplexer (MUX) method, or various other methods.

The IC chip 100 may include a primary input (PI) port 150, a primary output (PO) port 152, a scan enable (SE) port 160, and a scan input port 162. ), A clock input port 164, a scan output port 166, and the like. The scan activation port 160 and the clock input port 164 are connected to the flip- flops 120, 130, and 140, respectively. Each flip- flop 120, 130, 140 may be connected to the combination circuit 110 to output a value stored in each flip-flop to the combination circuit, and receive a value output from the combination circuit.

The main input port 150 and the main output port 152 are ports for inputting and outputting data during normal operation of the IC chip.

The scan activation port 160 is a port for inputting a scan enable signal or a scan disable signal, and according to the scan enable signal or the scan disable signal, the IC chip enters a normal or functional mode in which a normal operation is performed. The scan mode is tested to test the IC chip.

The scan input port 162 is a port for inputting a scan pattern for testing the IC chip 100, and the scan output port 166 is a port for outputting a test result by the scan pattern. The test results output through the scan output port are called output scan patterns or output patterns.

The clock input port 164 shifts and loads a scan pattern input through the scan input port 162 to the flip- flops 120, 130, and 140, or captures the output of the combination circuit 110 on the flip- flops 120, 130, and 140. It is a port to input clock signal for triggering. For example, the flip- flops 120, 130, and 140 are triggered by the rising edge or the falling edge of the clock signal input through the clock input port 164 to store or capture an input value.

A path (dashed path) connected to the scan output port 166 through the plurality of flip- flops 120, 130, and 140 from the scan input port 162 is called a scan chain or a scan path. 1 illustrates a single scan chain, a plurality of scan chains may be used.

In the functional mode, the combination circuit 110 performs a normal operation of receiving data through the main input port 150 and outputting a result through the main output port 152. In addition, in the function mode, the flip- flops 120, 130, and 140 receive an output value of the combination circuit 110 according to the clock signal, and this operation is called scan capture during the scan test.

In scan mode, each bit of the scan pattern is sequentially shifted-in to flip- flops 120, 130, and 140 present on the scan path in accordance with the clock signal, and sequentially through the scan output port 166. It is shifted out. Here, a state in which the scan pattern is shifted-in to the flip- flops 120, 130, and 140 is called a load, and an unloaded state in which the value stored in the flip- flop 120, 130, and 140 is shifted out through the scan output port 166 is unloaded. ).

For example, if the number of flip- flops 120, 130, 140 on the scan chain in the IC chip is three, the length of each scan pattern consists of three bits of length equal to the number of flip-flops on the scan chain, and the three-bit scan pattern is The shift signals are sequentially shifted into the flip- flops 120, 130 and 140 on the scan chain according to the clock signal. That is, when a value is stored in the flip-flop on the rising edge of the clock signal, the first bit of the scan pattern is input and stored in the first flip-flop 140 on one rising edge of the clock signal, and then stored in the next clock signal. The output value of the first flip-flop 140 is stored in the second flip-flop 130, and the second flip-flop 140 stores the second bit value of the scan pattern. In the next clock signal, the output value of the second flip-flop 130 is stored in the third flip-flop 120, and the output value of the first flip-flop 140 is stored in the second flip-flop 130, and the first The third flip-flop 140 stores the third bit value of the scan pattern. Therefore, one scan pattern is loaded into the flip- flops 120, 130 and 140 on the scan chain with three clock signals. Similarly, with the three clock signals, the values of the flip- flops 120, 130 and 140 on the scan chain are unloaded through the scan output port 166.

In more detail, the general scan test process is as follows.

(1) Main input test data is applied to the main input port 150 of the IC chip 100.

(2) The scan activation signal is applied to the scan activation port 160 to make the chip 100 in the scan mode.

(3) Shift-in the scan pattern to the scan input port 162 to load the scan pattern to the flip- flops 120, 130 and 140 on the scan chain. The scan pattern loaded in the scan chain is applied to the combination circuit 110. After the scan pattern is applied to the combination circuit, the result output through the main output port 152 is compared with the predicted main output value. If the comparison result is different, the IC chip is defective.

(4) The scan deactivation signal is applied to the scan activation port 160 to switch the chip 100 from the scan mode to the function mode. In the functional mode, when a clock signal is applied, the flip- flops 120, 130, and 140 capture the output values of the combination circuit 110, and this operation is called scan capture.

(5) The scan activation signal is applied to the scan activation port 160 to switch the chip back from the functional mode to the scan mode.

(6) Then, the values captured in the flip- flops 120, 130, and 140 on the scan chain are shifted out through the scan output port 166 and unloaded.

(7) The unloaded output pattern is compared with a known prediction pattern to determine whether the IC chip is operating normally. Here, the prediction pattern is a scan pattern that is output through the scan output port 166 after applying the main input test data and the scan pattern and performing the scan capture operation when the IC chip is normal, and is a value known before the test. In other words, if the comparison result in step (3) and the comparison result in step (7) are the same, the IC chip is good and the IC chip is defective.

There are two types of scan tests: stuck-at-fault tests and delay fault tests. Here, the fixing failure refers to a problem in which a signal line on the IC chip is inadvertently stuck to a logic 0 or logic 1 value, and the delay failure refers to any signal line or path on the IC chip. When passing the signal value through the path, it means a failure that does not meet the specifications of the IC chip due to the delay time.

Types of delay failure tests also include transition delay tests and path delay tests. The transition delay test is to test whether a specific node or signal line on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay problem. The path delay test is to test whether a particular path on the IC chip has a 0-to-1 or 1-to-0 signal value transition delay time problem.

Representative methods for delay failure testing include launch-on-capture and launch-on-shift methods, which also scan the scan pattern for delay failure testing. It consists of a load operation that shifts in on the chain and an unload operation that shifts out the delayed test results that are captured by flip-flops on the scan chain.

In the conventional scan test, since the number of clock pulses for shifting the number of flip-flops on the scan chain is required, there is a problem in that it takes a lot of time due to the shift-in and shift-out operations. However, you can't simply increase the clock signal's frequency, or shift frequency, to reduce test time.

For example, simply increasing the scan shift frequency may cause an overkill problem in which a good product is judged to be defective due to a power consumption or a critical path delay time.

In addition to deep sub-micron (DSM) microprocessing and low-power processes, as well as lower power designs, IC chips are becoming more power-lower, and the impact of power supply noise on IC chip operating frequencies is higher. In particular, since the IC chip generates more switching operation in scan mode than in function mode, the additional delay of the signal line caused by power supply noise due to switching operation can cause delay test overkill, which simply increases the shift frequency. There is a limit.

In addition, the issue of signal integrity due to signal crosstalk on IC chips has become more important as the DSM fine process proceeds. More switching behavior occurs in scan mode, resulting in more interference between signal lines. Therefore, an additional delay occurring in the signal line due to the interference between the signal lines during the delay test may cause the delay test overkill.

In addition, when the shift frequency is found based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the IC chip specification, due to the influence of excessive circuit switching operation and process variation on the IC chip due to the scan test characteristics, the IR Scan test error problems can occur due to -drop or ground-bounce. For example, in a delay test using a scan pattern, the effects of IR-drop, or voltage drop, can cause additional delays on certain signal lines, which can cause delay test overkill. In contrast, even if the power consumption of the scan pattern exceeds the specifications of the IC chip, IR-drop or ground-bounce problems may not occur due to the process and design characteristics of the chip. Therefore, there is a limit to finding the optimal shift frequency for the IC chip with only the power consumption value. In addition, in the case of finding the maximum shift frequency using only the power consumption value of the scan pattern, the critical shift timing problem may occur on the scan chain due to the increased shift frequency even if the power consumption value does not exceed the IC chip specification. have.

In addition, increasing the shift frequency may cause a critical path timing problem on the scan chain, but may not cause a logical problem due to the scan pattern. In other words, depending on the state of the bit value on the critical path of the scan chain, the case of a false critical path may occur in a particular scan shift cycle.

In addition, low-power IC chips that use multiple voltage island or voltage domain or region techniques provide high voltages for design areas that require high speed performance, and relatively low voltages for areas that do not. As a result, the permissible power consumption is different for each voltage region.

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for minimizing scan test time by optimizing a shift frequency used by a scan section to shift-in or shift-out a scan pattern into a scan chain. have.

One example of the scan test time minimization method according to the present invention for achieving the above technical problem, for each of the at least two or more scan sections, the output pattern of the scan chain is different from the prediction pattern through the increase or decrease of the shift frequency Identifying a first shift frequency; And determining a second shift frequency smaller than the first shift frequency as the shift frequency of each scan section.

In order to achieve the above technical problem, another example of the scan test time minimization method according to the present invention includes determining a different shift frequency for each of the at least two scan sections; for each scan section The determined shift frequency is characterized in that the output pattern of the scan chain is smaller than the shift frequency which is different from the prediction pattern.

In order to achieve the above technical problem, an example of an apparatus for minimizing scan test time according to the present invention includes: a frequency increase and decrease unit configured to increase or decrease a scan shift frequency; A pattern input unit configured to input a scan pattern including at least one scan section into a scan chain; A pattern comparison unit to determine whether an output pattern of the scan chain is identical to a prediction pattern; And a frequency grading unit that grasps a shift frequency smaller than a shift frequency at a point in time at which the output pattern and the prediction pattern are different as possible shift frequencies of the scan section, wherein each of the shift frequencies identified for at least two scan sections is included. Some or all of them are different from each other.

Another example of a method for minimizing scan test time according to the present invention for achieving the above technical problem is power consumption or consumption when shifting a scan section in a scan chain at a predetermined initial shift frequency among at least two scan sections. And determining, for at least one scan section whose current is above or above a predetermined threshold, an output frequency of the scan chain is equal to a prediction pattern.

Another example of the scan test time minimization method according to the present invention to achieve the above technical problem, the power consumption or current consumption when shifting the first scan section and the second scan section in the scan chain is a predetermined threshold Determining a first shift frequency and a second shift frequency that are above or above a value; And determining a third shift frequency and a fourth shift frequency when the power consumption or current consumption when shifting the third scan section and the fourth scan section to the scan chain is less than or equal to the threshold value. The first shift frequency and the second shift frequency are different from each other, and the third shift frequency and the fourth shift frequency are the same.

According to another aspect of the present invention, there is provided a scan test time minimizing apparatus according to the present invention, including: a power detector configured to detect power consumption or current consumption when shifting a scan section to a scan chain at a first shift frequency; A first frequency grasp for identifying or determining the first shift frequency or less as a possible shift frequency of the scan section for at least one or more scan sections whose power consumption or current consumption by the first shift frequency is below or below a predetermined threshold; part; And identifying or determining at least one second shift frequency for at least one scan section in which power consumption or current draw is above or above the threshold, the output pattern of the scan chain being equal to a prediction pattern. 2 frequency grasping unit; includes.

According to the present invention, an optimum shift frequency for each scan pattern, scan section or section group is provided. In addition, when increasing the shift frequency by considering only power consumption or critical path delay time, scan test time can be minimized while solving an over kill problem in which a good product is judged to be defective due to an overshift frequency. Find the optimal shift frequency.

In addition, the optimum shift frequency can be found by considering the influence of power supply noise and interference between signal lines. In addition, the optimum shift frequency can be found by reflecting the effects of IR-drop or ground-bounce that may be caused by excessive circuit switching behavior, process variation, microprocessing, low-power processes, or low-power designs caused by scan tests. Can be.

In addition, the optimum shift frequency can be found by considering the influence of the critical path timing on the scan chain that may occur when the shift frequency is increased.

In addition, if the critical path of the scan chain becomes a false critical path according to the bit value on the scan chain, it ignores the critical timing constraint and maximizes the scan shift frequency within the range where the IC chip can operate normally. Can be minimized.

In addition, for low-power IC chips using multiple voltage island or voltage region or region techniques, the optimal shift frequency can be found by reflecting the power consumption allowed for each voltage island or voltage region.

In addition, the circuit design information of the IC chip is not needed to find the optimal shift frequency of the scan pattern or scan section. Therefore, even if the chip design information is lost or lost, only the chip and scan pattern set is required. Find the frequency.

In addition, a predetermined predetermined shift frequency, such as a nominal shift frequency, is initially assigned to all scan sections, and then a process of finding an optimal shift frequency for a scan pattern or scan section in which the power consumption or current consumption of each scan section is a certain level or more is performed. This can save time compared to finding the optimal shift frequency for each full scan pattern or scan section. It also reduces burn-in test time.

1 is a diagram illustrating an example of an IC chip to which a conventional scan design method is applied;

2 and 3 are views illustrating the configuration of an embodiment of a scan test apparatus to which the present invention is applied;

4 is a view showing an example of a scan pattern that can be applied to the method of minimizing scan test time according to the present invention to reduce scan test time;

5 illustrates an example of a scan section according to the present invention;

6 is a diagram illustrating an example of allocating a shift frequency for each scan section in order to minimize scan test time according to the present invention;

7 illustrates an example of a method for finding a shift frequency for minimizing scan test time according to the present invention;

8 is a flowchart illustrating an example of a method for minimizing scan test time according to the present invention;

9 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

10 is a flowchart illustrating a more specific process of a scan test time minimization method according to the present invention;

11 is a flowchart illustrating a specific process of identifying a normal shift-in in a scan test time minimization method according to the present invention;

12 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

13 is a view showing the configuration of an embodiment of an apparatus for minimizing scan test time according to the present invention;

14 illustrates another example of a method for allocating an optimum shift frequency for each scan section according to the present invention;

15 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention;

16 is a view showing another example of a scan test time minimization apparatus according to the present invention, and

17 is a diagram illustrating an example of a method of repositioning a scan pattern for minimizing scan test time according to the present invention.

Hereinafter, a method and apparatus for minimizing scan test time according to the present invention will be described in detail with reference to the accompanying drawings.

2 and 3 are diagrams illustrating the configuration of an embodiment of an IC chip test apparatus, that is, a scan test apparatus, generally called an automatic test equipment (ATE) to which the present invention is applied.

2 and 3, the scan test apparatus includes host computers 200 and 300, tester bodies 210 and 310, test heads 220 and 320, and interface boards 230 and 330. The device under test (DUT) 240 and 340 positioned on the interface board for the test may be an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it may further include a prober 350. Hereinafter, an IC chip or a packaged IC chip on a wafer is collectively called an IC chip.

The tester bodies 210 and 310 control the scan test as a whole. For example, the tester body controls the overall process of setting up for the DUT test, generating the electrical signal for the DUT test, and observing and measuring the DUT test result signal. The test bodies 210 and 310 may be implemented as a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and according to an embodiment, a device power supply device for supplying power to the DUTs 240 and 340. It may further include a power supply). In addition, the tester main body 210 or 310 controls a signal processing processor (DSP) (not shown) for processing various digital signals and the test heads 220 and 320, and a controller and a signal for applying a signal to the DUTs 240 and 340. It may include dedicated hardware such as a generator, software or firmware. The test bodies 210 and 310 may also be called mainframes or servers.

The host computers 200 and 300 may be computers, such as workstations, and are devices that allow a user to execute a test program, control a test process, and analyze test results. In general, the host computer 200 or 300 may include a configuration such as a central processing unit, a storage device such as a memory or a hard disk, a user interface, and the like, and may be connected to the tester bodies 210 and 310 by wire or wireless communication. The host computers 200 and 300 may include dedicated hardware, software, firmware, and the like for controlling the tests. In the present embodiment, the host computer and the test body are illustrated separately, but the host computers 200 and 300 and the test bodies 210 and 310 may be implemented as a single device.

An example of memory of the tester main body 210 or 310 or the host computer 200 or 300 may be a DRAM, an SRAM, a flash memory, or the like, and a program and data for performing a DUT test may be stored in the memory.

Software or firmware of the tester main body 210 or 310 or the host computer 200 or 300 is a device driver program for operating a scan test, an operating system (OS) program, a program for performing a DUT test, and performs setup for a DUT test and a DUT test. The signal may be stored in a memory in the form of an instruction code for generation of a signal, an observation analysis of a DUT test result signal, or the like, and may be performed by a central processing unit. Thus, the scan test pattern can be applied to the DUT by this program. In addition, reporting and analysis data for DUT tests and test results can be obtained automatically through the program. The language used in the program may be various languages such as C, C ++, and Java. The program may be stored in a storage device such as a hard disk, magnetic tape or flash memory.

The central processing unit of the tester body 210 or 310 or the host computer 200 or 300 is a processor and executes code of software or a program stored in a memory. For example, when a user command is received through a user interface such as a keyboard or a mouse, the central processing unit analyzes the user's command and executes it through software or a program, and then outputs the result to a user interface such as a speaker, a printer, or a monitor. To the user through.

The user interface of the tester body 210, 310 or the host computer 200, 300 allows the user and the device to exchange information and communicate commands. For example, an interface device for user input such as a keyboard, a touch screen, a mouse, and the like, and an output interface device such as a speaker, a printer, a monitor, and the like.

The test heads 220 and 320 include a channel for transmitting an electrical signal between the tester bodies 210 and 310 and the DUTs 240 and 340. Interface boards 230 and 330 are provided on the test heads 220 and 320. The interface board used for testing a packaged IC chip is generally called a load board, and the interface board used for testing an IC chip on a wafer is called a probe card.

2 and 3 is only one example for better understanding of the present invention, and may be implemented in one piece by integrating each component, or in one embodiment by dividing one configuration into a plurality of configurations. Various design changes are possible according to this.

4 is a diagram illustrating an example of a scan pattern that can be applied to a method for minimizing scan test time according to the present invention to reduce scan test time.

Referring to FIG. 4, the shift-in and shift-out operations are simultaneously performed to reduce the time required when the shift-in operation and the shift-out operation are performed in the scan mode. In other words, the load and unload operations are performed at the same time.

For example, when the k-th input scan pattern 430 is loaded shift-in through the scan input port into the scan chain, the test results by the k-1 th input scan pattern 400 simultaneously shift the scan output port. -Out and unload. In this case, the unloaded output pattern is compared with the predicted output scan pattern 440 for the k-1 th input scan pattern 400 managed in pairs with the k th input scan pattern 430.

Predictions for the k-th input scan pattern 430 and the k-1 th input scan pattern 400 that are shifted-in through the scan input port in order to scan scan by overlapping the shift-in and shift-out operation. The output scan pattern 440 is managed in pairs. Thus, the scan patterns can be in order with each other. Scan patterns can also be rearranged in various ways.

When the first scan pattern is shifted in to the scan chain, the output pattern that is shifted out at the same time may be a Don't-care pattern or a scan chain state value by resetting the chip under test.

Another way to minimize scan test time is to reduce the total amount of scan patterns for scan tests, and to increase the shift frequency to quickly apply scan patterns to IC chips. The present invention mainly describes a method that can minimize the scan test time by increasing the shift frequency.

5 is a diagram illustrating an example of dividing a scan pattern into scan sections in order to minimize the time of a scan test according to the present invention.

Referring to FIG. 5, a scan pattern set composed of one or more input scan patterns is divided into at least two scan sections. That is, the scan section may be composed of at least one scan pattern or part of the scan pattern, and further reduce scan test time by finding and applying an optimum shift frequency for each scan section.

According to a first embodiment, the scan section 500 may be configured as one scan pattern and correspond one-to-one with the scan pattern. That is, the scan pattern may soon be a scan section.

In a second embodiment, the scan section 510 may include two scan patterns. The number of scan patterns included in the scan section may be variously changed according to an embodiment.

In a third embodiment, the scan section 520 may be configured as part of the first scan pattern and part of the second scan pattern.

In a fourth embodiment, the scan section 530 may be configured as part of one scan pattern.

According to a fifth embodiment, one scan pattern may be divided into two scan sections 540 and 550. The number of scan sections included in one scan pattern may be variously changed according to embodiments.

One or more scan patterns may be divided by any one of the various embodiments 500, 510, 520, 530, 540, and 550 previously described, and the scan patterns may be divided by applying two or more of these embodiments. For example, a scan pattern set consisting of N scan patterns of FIG. 5 includes a first scan section 500 including one scan pattern, a second scan section 510 including two scan patterns, and one scan. It may be divided into third and fourth scan sections 540 and 550 that include part of the pattern.

In addition, various methods of dividing the scan pattern set into scan sections may be applied, and the present invention is not limited to the scan section shown in FIG. 5.

6 is a diagram illustrating an example of allocating a shift frequency for each scan section to minimize scan test time according to the present invention.

Referring to FIG. 6, a plurality of shift frequencies are assigned to each scan section. In the case of the conventional scan test, a single constant scan shift frequency is fixed according to the IC chip, which is called a nominal shift frequency.

The nominal shift frequency is either the shift frequency used when creating scan patterns with ATPG software or a fairly low shift frequency based on this. Therefore, using these frequencies as they are may require a lot of scan test time.

However, if you increase the nominal shift frequency, the power consumption of shift-in and shift-out depending on the scan pattern will be beyond the power range required by the IC chip, preventing normal scan testing. In addition, the overshift frequency may cause an over kill problem in which good quality is determined as a defective product due to a critical path delay time problem, a deep power supply noise effect, a deep interference effect between signal lines, and the like.

Therefore, the present invention does not apply a single shift frequency, such as the nominal shift frequency, to the entire scan pattern, but allocates an optimal shift frequency that can be normally shifted in the scan chain for each scan section. A process of finding an optimal shift frequency for each scan section will be described in more detail with reference to FIG. 8 or below. Here, the optimal shift frequency may be the maximum allowable shift frequency or a smaller shift frequency.

Referring back to FIG. 6, the first scan section is assigned a shift frequency A, and the second scan section is assigned a shift frequency B. And the third scan section is assigned the same shift frequency A as the first scan section. As such, each scan section may be assigned the same shift frequency or different shift frequencies.

For example, when one scan pattern is divided into a plurality of scan sections, a plurality of shift frequencies may be assigned to one scan pattern. Referring to FIG. 5, two scan sections 540 and 550 belonging to one scan pattern may be assigned different shift frequencies. That is, two shift frequencies are allocated to one scan pattern.

Each scan section assigned a shift frequency may be integrated into a section group according to an embodiment. For example, the second scan section and the third scan section may be grouped into a section group, and a smaller shift frequency or less than the shift frequencies A and B of each scan section may be assigned to the corresponding section group.

Applying test data to the main input port of the general scan test procedure described in the background technology of the present invention and observing the test result at the main output after inputting the scan pattern to the scan chain can be applied as a general scan test procedure in the following description. have.

7 illustrates an example of a method for finding a shift frequency for minimizing scan test time according to the present invention.

FIG. 7 illustrates an example of a method for minimizing scan test time when the shift-in and the shift-out described in FIG. 4 are performed by overlapping. FIG. 7 illustrates an example according to the present invention, and is not limited to the case where the shift-in and the shift-out described in FIG. 4 are performed at the same time.

Also, for convenience of description, it is assumed that the k th scan section 704 is a section to find the optimal scan shift frequency, and the k th scan section 704 corresponds one-to-one with the k th input scan pattern. Of course, the k th scan section 704 may be part of a scan pattern or may be composed of a plurality of scan patterns as described with reference to FIG. 5.

Referring to FIG. 7, the k-1 th input pattern 702 and the k + 1 th input pattern 706 in order to verify that the k th scan section 704 is normally shifted-in to the scan chain at a particular shift frequency. This is necessary.

The k-1 th input pattern 702 is the k-1 th scan pattern used for the actual scan test located in front of the k th scan section 704, or is scanned after loading the k-1 th scan pattern into the scan chain. It may be a prediction pattern obtained when capturing. The k + 1 th input pattern 706 is the k + 1 th scan pattern used for the actual scan test located behind the k th scan section 704, or a bit '0' or '1' to reduce switching operations on the scan chain. It may be an arbitrary pattern that is mainly composed or mainly composed of consecutive bits '0' or '1'.

In the scan test, the input scan pattern, which is located before the first scan section and after the last scan section, is composed of bit '0' or '1' oriented or consecutive bit '0' to reduce switching operation on the scan chain. Alternatively, the pattern may be any predetermined pattern composed mainly of '1'. In addition, the input scan pattern located in front of the first scan section may be a value on the scan chain when the chip under test is in the reset state.

The k−1 th input pattern 702 or the k + 1 th input pattern 706 may each consist of one or more scan sections, each of which is optimally below the nominal shift frequency or by means of the method according to the invention. If the shift frequency of is already determined, the k-1 th input pattern 702 or the k + 1 th input pattern 706 is shifted by applying a preset shift frequency to the corresponding section as below a corresponding optimum shift frequency. You can also The preset shift frequency may be variously changed according to an embodiment, such as a nominal shift frequency or more, or a preset value for each device or a value set by a user, and is not necessarily limited to the above example.

For example, when the method according to the present invention is sequentially applied to the scan patterns, the optimum shift of the scan section for the k-1 th scan pattern before the process of determining the shift frequency of the scan section for the k th scan pattern The frequency is predetermined. Therefore, the scan test time minimization apparatus may use the determined optimal shift frequency for the scan section of the k−1 th scan pattern and use the nominal shift frequency for the scan section for the k + 1 th scan pattern.

And while increasing or decreasing the shift frequency for the section to find the optimal shift frequency of the k-th scan pattern, sequentially input the k-1, k, k + 1st scan pattern to the scan chain 710 to the actual output pattern (720) ) Is equal to the prediction pattern 730.

For example, the scan test time minimization apparatus sets the initial shift frequency to the nominal shift frequency, and increases the shift frequency in units of variation of the shift frequency preset in the scan test time minimization apparatus. That is, after shifting-in the k-1th input scan pattern 702 with a preset shift frequency, such as a nominal frequency, in the scan chain, the k-th scan section 704 is shifted by "initial shift frequency + increment of a certain unit". Shift-in the scan chain at a frequency, and simultaneously shift out the test result (i.e., output pattern K-1) 722 by the k-1 th input scan pattern 702 to predict the predicted pattern K-1 in advance. Determine if it is the same as (732). At the same time as the shift-in of the k + 1 th input scan pattern 706, the predictive pattern K 734 which knows in advance the output pattern K 724 obtained by shifting out the test result by the k th scan pattern 704. ) Is equal to).

The preset shift frequency mentioned above may be variously changed according to an embodiment, such as being above or below the nominal shift frequency in addition to the nominal shift frequency, or a preset value or a user-set value for each device. It doesn't happen.

If the output pattern K-1 722 and the prediction pattern K-1 732 are the same, and the output pattern K 724 and the prediction pattern K 734 are the same, the scan test time minimization apparatus tries to find an optimal shift frequency. The shift frequency for the scan section K 704 is increased again by a predetermined size, and as described above, the shift frequency from the k-1 th input scan pattern 702 is input to the scan chain to predict the output pattern 720 and the output pattern 720. The comparison process of the pattern 730 is performed again.

As such, the shift frequency for the k th scan section 704 is continuously increased to the point where the output pattern 720 and the prediction pattern 730 are different, and the shift frequency before the point is less than or equal to the k th scan section. Determine the optimal shift frequency.

According to an embodiment, the initial shift frequency for finding the optimal shift frequency for the k th scan section may be set to various values in addition to the nominal frequency, and is not increased from a low value but is a high value in which the output pattern and the prediction pattern are different. You can start by shifting the shift frequency down to find the shift frequency at the point where the output and prediction patterns are the same. In addition, instead of sequentially increasing or decreasing the shift frequency of the k-th scan section, various algorithms may be used to change the shift frequency to find an optimal shift frequency at a faster time.

For example, you can use a binary search algorithm. For example, if the shift frequency succeeds at 10 MHz and fails at 20 MHz, the next shift frequency tries 15 MHz in between. If it is successful, try between 15 MHz and 20 MHz, and if it fails, try between 10 and 15 MHz.

In the example of FIG. 7, scan section K 704 to find the optimal shift frequency corresponds one to one with scan pattern K 704, but may be configured as part of the scan pattern, such as scan section 530 of FIG. 5. In this case, in the scan pattern including the scan section selected to find the optimal shift frequency, the portion except the scan section is below the nominal shift frequency or when the optimal shift frequency has already been determined by the method according to the present invention. A preset shift frequency may be used as below frequency. For the scan section selected to find the optimal shift frequency, the optimum frequency is found by shifting the frequency up or down as described above. The preset shift frequency may be variously changed according to an embodiment, such as a nominal shift frequency or more, or a preset value for each device or a value set by a user, and is not necessarily limited to the above example.

8 is a flowchart illustrating an example of a method for minimizing scan test time according to the present invention.

Referring to FIG. 8, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (S800). As an example of division of the scan pattern, the method illustrated in FIG. 5 may be used. The scan test time minimization apparatus allocates a plurality of shift frequencies to each scan section (S810). Here, the shift frequency assigned to each scan section is a value smaller than the shift frequency at which the output pattern of the scan chain is different from the prediction pattern. The division (S800) as the scan section of the scan pattern and the scan section allocation (S810) of the shift frequency may be performed in the same device or different devices according to an embodiment.

That is, the scan test time minimization apparatus recognizes the shift frequency just before the output pattern and the prediction pattern change as the shift frequency increases or decreases as the maximum shift frequency that can be allocated to the corresponding scan section. According to an embodiment, each scan section may be assigned a shift frequency smaller than the maximum shift frequency found through the increase and decrease of the shift frequency.

9 illustrates another example of a method of using an optimal shift frequency for each scan section to minimize scan test time according to the present invention.

Referring to FIG. 9, the scan test time minimization apparatus divides one or more scan patterns into at least two scan sections (S900).

The scan test time minimization apparatus detects the shift frequency at the time when the output pattern is different from the prediction pattern while increasing or decreasing the frequency shifting-in the scan section to the scan chain (S910). Chips used to find the optimal shift frequency are preferably chips that have been tested for good quality in advance. For example, as a result of a scan test using a nominal shift frequency, an optimal shift frequency is searched according to the present embodiment using a good chip. The same is true in other embodiments below.

In operation S920, the scan test time minimization apparatus determines a shift frequency before a time point at which the output pattern and the prediction pattern differ from each other in the scan section. The former shift frequency also includes a smaller shift frequency.

For example, when the output pattern and the prediction pattern are the same at the first shift frequency, but the output pattern and the prediction pattern of the scan chain are different at the second shift frequency in which the first shift frequency is increased by a certain amount, the scan test time minimization apparatus 2 Determine the shift frequency, or smaller, as the shift frequency of the scan section.

The magnitude of the increase and decrease in order to find the optimal shift frequency is preset in the scan test apparatus, and the increase and decrease size may be changed by the user.

Each step described in FIG. 9 may not be all performed in the scan test time minimizing apparatus, but may be distributed among various apparatuses.

10 is a flowchart illustrating a more detailed process of the scan test time minimization method according to the present invention.

Referring to FIG. 10, the apparatus for minimizing scan test time divides one or more scan patterns into a plurality of scan sections (S1000).

The scan test time minimization apparatus selects one scan section of which no shift frequency is determined according to the present exemplary embodiment among the scan sections (S1010). For example, if a predetermined order is defined between scan patterns for the scan test, the scan test time minimizing apparatus may sequentially select from the first scan section.

The scan test time minimization apparatus increases or decreases the shift frequency (S1020). For example, the scan test time minimization apparatus may variously set the initial shift frequency to a nominal shift frequency.

The scan test time minimization apparatus determines whether the scan section can normally be shifted-in to the scan chain at the increased shift frequency starting from the initial shift frequency (S1030). An example of a specific method of determining whether the selected scan section is normally shift-in at the current shift frequency will be described with reference to FIG. 11.

If the normal shift-in of the scan section is possible (S1040), the scan test time minimization apparatus increases or decreases the shift frequency (S1020) and repeats the process of determining whether normal shift-in is possible (S1030).

If the shift section does not normally shift-in the scan section due to the increase or decrease of the shift frequency (S1040), the scan test time minimization apparatus scans below the shift frequency before the current shift frequency where the scan section is not normally shifted-in. Determine the shift frequency of the section (S1050). And the above process is repeated until the shift frequency for all the scan section is determined (S1060).

The apparatus for minimizing scan test time may group scan sections into section groups as necessary (S1070). For example, if the scan test device that performs the actual scan test has constraints such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required for the shift frequency change, the scan test time The minimization apparatus may group the scan sections into groups so that the number of scan sections satisfies the above constraints, and the total scan test time may be considered to be minimized. In this case, the lowest shift frequency among the optimal shift frequencies of at least two scan sections included in one section group may be determined as the shift frequency of the corresponding section group. The step S1070 of grouping the sections into groups may be omitted according to an embodiment.

For example, if the maximum number of shift frequency changes supported by the scan test device is 5, the scan test time minimizer divides the scan sections into 5 or less section groups if the current number of scan sections exceeds 5, and each section The lower or lower optimal shift frequency among the optimal shift frequencies of the sections in the group may be determined as the shift frequency of the corresponding section group. As a method of grouping into section groups, there may be various methods such as grouping by section groups having similar optimal shift frequencies, and it is desirable to minimize the total scan test time.

The embodiments discussed so far have mainly been a process of finding an optimal shift frequency in consideration of only the increase and decrease of the shift frequency. However, the chip is also affected by supply voltage and ambient temperature, so it is necessary to find the optimal shift frequency to reflect these environmental conditions.

Therefore, the scan test time minimizing apparatus may perform a process of finding an optimum shift frequency while changing conditions such as supply voltage and external temperature.

For example, the scan test time minimization apparatus increases or decreases the voltage supplied to the chip in consideration of a specification range of the chip or quality related policies such as QA (Quality Assurance) and QC (Quality Control). In addition, the scan test time minimization apparatus finds an optimal shift frequency for each scan section according to an embodiment of the present invention at each increased or decreased supply voltage. If there are a plurality of optimal shift frequencies found for each supply voltage of the selected scan section, the scan test time minimization apparatus determines a shift frequency of the selected scan section below the lowest optimal shift frequency among them (S1050). In addition, the process of finding the optimal shift frequency may be repeated for temperature increase or decrease and various other conditions, and the lower than the lowest optimal shift frequency may be determined as the shift frequency of the corresponding scan section.

Here, to grasp the characteristics such as the operating frequency range of the IC chip while changing the supply voltage or ambient temperature of the IC chip, generally referred to as electrical testing or shiming, electrical characteristics testing or Making a plot of characteristic information by making a drawing is called 'smooth plotting'. The plot is called a shmoo plot.

Each step of FIG. 10 may be performed in a separate device as well as a scan test time minimization apparatus by using the scan pattern set and constraint information of the shift frequency and the scan test time minimization apparatus identified for each scan section.

11 is a flowchart illustrating a specific process of identifying a normal shift-in in the scan test time minimization method according to the present invention. That is, FIG. 11 corresponds to step S1030 of FIG. 10.

Referring to FIG. 11, the apparatus for minimizing scan test time shifts the k−1 th input pattern positioned in front of the k th scan section currently selected as shown in FIG. 7 into the scan chain (S1100). The k-1th input pattern is the k-1th input scan pattern used in front of the kth scan section to be used for the actual scan test, or the prediction that appears when the k-1th input scan pattern is loaded into the scan chain and then captured. It may be a pattern.

(1) If the k-1 th input pattern is the k-1 th scan pattern used for the actual scan test, the scan test time minimization apparatus loads the k-1 th scan pattern into the scan chain and performs a scan capture process. do. In this case, there is an advantage of reflecting the actual scan test operation.

(2) When the k-1 th input pattern is a predictive pattern that appears when the k-1 th scan pattern used for the actual scan test is scanned after loading, the scan test time minimizing apparatus scans the k-1 th input pattern After loading into the chain, there is no need to perform a separate scan capture process, which reduces the time required for clock capture.

After the scan test time minimization apparatus loads the k-1 th input pattern, the apparatus shifts the selected scan section (k th scan section) into the scan section at the increased or decreased shift frequency (S1110). If the scan section K selected to find the optimal shift frequency is part of the scan pattern, such as the scan sections 530, 540, and 550 of FIG. 5, the scan pattern portion excluding the scan section K may be equal to or less than the nominal shift frequency or the present invention. If the optimal shift frequency is already determined through the method described above, the shift-in may be performed by using a preset shift frequency, such as less than or equal to the optimum shift frequency. It then shifts out the values stored on the scan chain simultaneously. The preset shift frequency may be variously changed according to an embodiment, such as a nominal shift frequency or more, or a preset value for each device or a value set by a user, and is not necessarily limited to the above example.

For example, in the case where the k-1 th input pattern is the k-1 th scan pattern itself used for the actual scan test, the output pattern shifted out is a scan capture with the k-1 th scan pattern loaded. One result. In the case where the k-1 th input pattern is a predictive pattern for scan capture by the k-1 th scan pattern used for the actual scan test, the output pattern is a result output from the scan chain without scan capture.

The scan test time minimization apparatus compares the output pattern with the prediction pattern (S1120). If the output pattern and the prediction pattern are not the same (S1120), the scan test time minimization apparatus determines that the k-th scan section cannot be properly shifted-in to the scan section at the current shift frequency (S1170).

If the output pattern and the predictive pattern are the same, the scan test time minimization device shifts out the k th scan section located on the current scan chain as it is, or shifts out the result after the scan capture with the k th scan section loaded. (S1140). When performing scan capture, there is an advantage that can reflect the actual scan test operation process. The shift-out of the k th scan section as it is without the scan capture has an advantage of reducing the time required for the scan capture.

The scan test time minimization apparatus compares the shifted-out output pattern and the prediction pattern (S1150). For example, if the k-th scan section is shifted out as it is, the scan test apparatus compares the k-th section with the output pattern. In the case of outputting the scan capture result for the kth scan section, the scan test time minimization apparatus compares the output pattern with the predicted scan capture pattern that is known in advance for the kth scan section.

The scan test time minimizing apparatus determines that the scan section can be normally shifted-in into the scan chain at the current shift frequency when the output pattern and the prediction pattern for the k-th scan section are the same (S1160).

12 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention.

Depending on the type and state of a process, process variations between IC chips on different wafers or between IC chips on the same wafer may occur, which may greatly affect the operating frequency and power consumption of the IC chip. have. In particular, micro processes and low power processes have more influence. 12 is an example for finding an optimal scan shift frequency and reflecting the same.

Referring to FIG. 12, the scan test time minimizing apparatus performs a process of determining an optimal frequency for each salping scan section for a plurality of chips (S1200). Here, the plurality of chips may be chips on the same wafer or chips on different wafers, and chips that have been inspected with good quality in advance are preferable.

The apparatus for minimizing scan test time may determine the optimal shift frequency of the corresponding scan section to be equal to or less than the lowest shift frequency among the plurality of optimal shift frequencies found through the plurality of chips for one scan section (S1210). This can be done for the scan section.

For example, assume that the shift frequency of the k-th scan section of the first chip is A and the shift frequency of the k-th scan section of the second chip is B. If the shift frequency A is less than the shift frequency B, the scan test apparatus selects A or less as the shift frequency of the k th scan section.

Each step of FIG. 12 may be performed in a separate apparatus as well as a scan test time minimization apparatus using shift frequency information identified for each scan section for a scan pattern set and a plurality of chips.

In addition to the methods described above, the scan test time minimization apparatus may perform a burn-in test by using an optimal shift frequency found for each scan section. The burn-in test here finds an initial defective IC chip by applying high voltage and high temperature to the IC chip to accelerate aging. Typically tens of hours of burn-in tests are conducted in high temperature environments above 100 ° C.

Scan Test Time Minimization The apparatus may perform a scan test using a scan pattern during a burn-in test. More switching operations occur in scan mode than in functional mode, and as the scan shift frequency increases, the power consumption of the IC chip increases proportionally. In addition, since the heat generation of the IC chip increases in proportion to the power consumption, the aging of the IC chip is further accelerated. Thus, the scan test time minimization device can use the maximum shift frequency that can be assigned to each scan section that was previously previewed to accelerate aging during burn-in testing, thereby reducing burn-in test time. In addition, a test apparatus capable of performing such a burn-in test is called a burn-in test apparatus.

13 is a diagram showing the configuration of an embodiment of a scan test apparatus according to the present invention.

Referring to FIG. 13, the apparatus for minimizing scan test time includes a condition setting unit 1300, a pattern dividing unit 1305, a pattern input unit 1310, a pattern comparing unit 1320, and a frequency grasping unit 1330. The condition setting unit 1300 again includes a frequency increasing unit 1302, a supply voltage increasing unit 1304, a temperature increasing unit 1306, and the like.

First, the condition setting unit 1300 sets various conditions for finding an optimal shift frequency for each scan section. In detail, the frequency increase / decrease unit 1302 increases or decreases the shift frequency, the supply voltage increase / decrease unit 1304 increases or decreases the voltage supplied to the chip, and the temperature increase / decrease unit 1306 increases or decreases the ambient temperature of the test environment. The condition setting unit 1300 sets conditions such as a supply voltage and an ambient temperature, and increases and decreases the shift frequency.

The pattern divider 1305 divides one or more scan patterns into a plurality of scan sections.

The pattern input unit 1310 shifts-in the scan section into the scan chain under the condition set by the condition setting unit 1300. More specifically, the pattern input unit 1310 sequentially shifts-in scan patterns positioned in front of and behind the scan section for which the optimum scan shift frequency is to be searched into the scan chain together with the scan section.

The pattern comparison unit 1320 determines whether an output pattern shifted out at the same time as the shift-in by the pattern input unit 1310 is the same as the prediction pattern. As the shift frequency is increased or decreased by the condition setting unit 1300, there is a point where the output pattern and the prediction pattern are different.

The frequency identifying unit 1330 uses the result of the pattern comparing unit to determine a frequency lower than the shift frequency when the output pattern and the prediction pattern differ from each other as a possible shift frequency of the scan section. It can be stored in a recording medium that can be read by. The shift frequency thus determined can be used to determine the optimal shift frequency of the scan section.

14 illustrates another example of a method for allocating an optimum shift frequency for each scan section according to the present invention.

Referring to FIG. 14, when the scan section is shifted in the scan chain (ie, loaded or unloaded), the power consumed by the IC chip varies according to the magnitude of the shift frequency. For example, a higher shift frequency increases the average power consumed by the chip. In addition, even with the same shift frequency, the power consumed by the chip varies because the number of switching on the IC chip is different depending on the bit value of each scan section.

Therefore, the apparatus for minimizing scan test time sets an initial shift frequency, and when shifting the scan sections to the initial shift frequency, the average power consumption of the first scan section above or above the preset threshold and the second scan section below or below the threshold is set. Separate into groups. Here, the initial shift frequency is preferably a shift frequency larger than the nominal shift frequency, and may be a value preset or automatically set by the user based on the shift frequency determined through experience or previous experiment data. For example, a single frequency at which the average power dissipated by the scan sections approaches the allowable average power dissipation may be used as the initial shift frequency. In addition, the threshold value may be a maximum average power allowable by the IC chip or a value larger or smaller than this, and various values may be applied according to an exemplary embodiment.

The scan test time minimization apparatus allocates the initial shift frequency as it is for scan sections that are below or below a threshold. For example, in FIG. 14, scan sections 1 and 3, in which the average power consumption is less than the threshold, are all assigned the same initial shift frequency. That is, for scan sections having an average power consumption below or below a threshold value, the process of finding an optimal shift frequency as shown in FIG. 7 is omitted, thereby saving time for finding a shift frequency for each scan section.

On the other hand, in FIG. 14, the scan sections 2, 4, and 5 of which the average power consumption exceeds or exceeds the threshold are allocated the shift frequencies through the process of finding the optimal shift frequencies shown in FIG. 7. In this case, the shift frequencies allocated to the scan sections may be the same or different. If the initial shift frequency is high, all scan sections may exceed the threshold, and in this case, the scan test time minimizing apparatus performs a process of finding an optimal shift frequency for all scan sections.

As another example, a scan section that uses a peak power consumption rather than an average power consumption as a value on the vertical axis of FIG. 14 and performs a method for finding an optimal shift frequency of FIG. 7 based on the magnitude of the peak power consumption. You can distinguish between scan sections that do not.

15 is a flowchart illustrating another example of a method for minimizing scan test time according to the present invention.

Referring to FIG. 15, the scan test time minimizing apparatus divides the scan pattern into at least one scan section (S1500). The scan test time minimization apparatus calculates power consumption for each scan section when the scan section is shifted to a preset initial shift frequency (S1510). In FIG. 15, power consumption may be average power consumption or peak power consumption.

If the power consumption of the scan section is less than the preset threshold (S1520), the scan test time minimization apparatus equally allocates the initial shift frequency or less to the shift frequency of the corresponding scan section (S1560).

On the other hand, if the power consumption of the scan section is greater than the threshold (S1520), the scan test time minimizing apparatus performs a process of finding an optimal shift frequency for the scan section (S1530 to S1550).

As such, if the power consumption of each scan section is greater than or equal to the threshold value, the process of finding an optimal shift frequency may be additionally performed. If the power consumption is lower than the threshold value, an initial shift frequency or less may be determined as the shift frequency of the corresponding scan section without an additional search process. .

Looking at the method for finding the optimal shift frequency in more detail, the scan test time minimization device increases or decreases the shift frequency (S1530). The initial value of the shift frequency increased or decreased may be a nominal shift frequency, a value preset by a user, or an automatically set value.

The apparatus for minimizing the scan test time determines whether the scan section is shiftable in the scan chain based on the increased or decreased shift frequency (S1540). The determination of the identity of the output pattern and the prediction pattern may be performed by the method described with reference to FIG. 7. For example, referring to FIG. 7, in the case where the optimum shift frequency for the current k th scan section is to be found, the scan test time minimization apparatus may output the output pattern for the k-1 th scan pattern and the k th scan section. The output pattern is compared with each prediction pattern to determine whether a normal shift is possible.

If the output pattern and the prediction pattern are the same (S1540), the process proceeds to step S1530 of increasing or decreasing the shift frequency and repeats the above steps (S1530, S1540). If the output pattern and the prediction pattern are different (S1540), the scan test time minimization apparatus determines the shift frequency of the scan section below the shift frequency before increasing or decreasing (S1550). The scan test time minimization device may determine the maximum allowable shift frequency as the optimum shift frequency of the corresponding scan section immediately before the increase or decrease, or the lower shift frequency as the optimal shift frequency.

Some steps of FIGS. 14 and 15 may be performed in a separate device as well as a scan test time minimization apparatus by using constraint information of the power consumption, the shift frequency, and the scan test time minimization apparatus identified for the scan section.

16 illustrates another example of an apparatus for minimizing scan test time according to the present invention.

Referring to FIG. 16, an apparatus for minimizing scan test time includes a pattern divider 1600, a power detector 1610, a first frequency determiner 1620, and a second frequency determiner 1630. In addition, the second frequency grasping unit 1630 includes a frequency increasing / decreasing unit 1632, a pattern comparing unit 1634, and a grasping unit 1634.

The pattern divider 1600 divides one or more scan patterns into at least two scan sections.

The power detector 1610 detects power consumption when shifting (loading and unloading) the preset initial shift frequency. For example, the power detector 1610 detects average power consumption or peak power consumption during the shift to load or unload the scan section to the scan chain at the initial shift frequency.

The first frequency determiner 1620 determines or determines a scan shift frequency for the sections below the initial shift frequency for scan sections whose power consumption is less than or equal to a preset threshold. The power consumption may be average or peak power consumption.

The second frequency grading unit 1630 performs a process of finding an optimal shift frequency for scan sections whose power consumption is greater than or greater than a threshold. Here, the power consumption may be average or peak power consumption.

In detail, the frequency increasing / decreasing unit 1632 selects a scan section of which scan power whose power consumption is above or above a threshold is not yet determined or determined, and selects an optimal shift frequency for the selected scan section. Increase or decrease the shift frequency to find. The initial value of the shift frequency increased or decreased may be a nominal shift frequency.

The pattern comparison unit 1634 determines whether the scan section normally shifts in to the scan chain at the shift frequency increased or decreased by the frequency increase / decrease unit 1632. In order to determine whether it is a normal shift-in, the method of FIG. 7 may be applied to compare an output pattern and a prediction pattern. That is, the pattern comparison unit 1634 compares whether the output pattern and the prediction pattern are the same when shifting the scan section selected by the increased or decreased shift frequency, and judges that normal shifting is possible when the patterns are identical. do. The pattern comparison unit 1634 determines a maximum shift frequency that can be normally shifted by comparing the output pattern and the prediction pattern.

The grasp 1636 may determine or determine a maximum shift frequency that can be normally shifted based on the determination result of the pattern comparator 1634. That is, when the grasp 1636 grasps the shift frequency at the point where the output pattern and the prediction pattern are different by the pattern comparator 1634, the grasp 1636 selects a shift frequency before being different, that is, a shift frequency before being increased or decreased. Determine or determine the maximum shift frequency of the section.

The salping scan test time minimizing device may be implemented in various forms, such as hardware or software, and all or part of the scan test time minimizing device may be implemented in the salping scan test device in FIGS. 2 and 3 or another separate device such as a computer. It may be implemented as.

Each embodiment described with reference to FIGS. 14 to 16 discloses a method and apparatus for finding an optimal shift frequency based on power consumption. However, the embodiment is not necessarily limited to the use of power consumption, and includes all cases of using other measurement values having a constant proportionality with power consumption.

For example, since the power consumption is proportional to the current consumption, an optimal shift frequency can be found based on the current consumption.

Referring back to the embodiment of FIG. 16 in terms of power consumption, the power detector 1610 detects power consumption (average current consumption or peak current consumption), and detects the first frequency detector 1620 and the second frequency detector ( In operation 1630, the shift frequency for each scan section may be determined and determined using the current consumption and the current consumption threshold instead of the power consumption. Other embodiments may use the current consumption and current consumption thresholds instead of power consumption.

17 is a diagram illustrating an example of a method of repositioning a scan pattern for minimizing scan test time according to the present invention.

Referring to FIG. 17, the scan patterns on the scan pattern set for the scan test have a certain order. However, the order of these scan patterns is not fixed but can be rearranged to reduce the overall scan test time by assigning higher shift frequencies for each scan section. For example, as shown in FIG. 17, the order of the second scan pattern and the third scan pattern on the original scan pattern set may be changed. This also changes the order of the predictive output scan pattern.

When rearranging the order of the scan patterns shifted in the scan chain, the portion shifted on the IC chip and the number of switching operations may be changed by the scan shifting, and thus the power consumption is changed so that the scan patterns (or scan sections) are allocated. The shift frequency can be increased. Therefore, after rearranging the scan pattern using this property, the overall scan test time can be reduced by finding or determining the optimal shift frequency for each scan section using the embodiment of the present invention.

As a repositioning method of scan patterns, at least one scan pattern on an original scan pattern set is randomly rearranged, and an optimal shift frequency is identified for each relocated scan pattern set according to a prior embodiment, so that scan test time is minimal. There are a variety of methods such as determining what is required as the arrangement of the scan patterns, or arranging the scan patterns having the smallest bit pattern difference between the scan patterns next to each other.

As another example of repositioning the scan pattern, the highest shift frequency can be obtained by sequentially substituting the unordered scan patterns after the K (integer one or more) th scan pattern to find the optimal shift frequency. The scan pattern can be determined as the next pattern of the Kth scan pattern.

Some or all of the operations for rearranging the order of the scan patterns may be performed by hardware and firmware or software such as a processor included in the IC chip test apparatus, or may be performed by a separate device such as a computer.

In addition, when it may take a long time to find the optimal scan pattern arrangement, there may be constraints such as the maximum number of scan pattern relocation or the time required to find the optimal scan pattern arrangement.

In addition, a burn-in test may be performed using an optimal shift frequency found by the scan test minimization method according to the present invention. The burn-in test here finds an initial defective IC chip by applying high voltage and high temperature to the IC chip to accelerate aging. Typically tens of hours of burn-in tests are conducted in high temperature environments above 100 ° C.

For example, the scan test time minimization apparatus performs a scan test using a scan pattern during the burn-in test. More switching operations occur in the scan mode than in the functional mode. As the scan shift frequency increases, the power consumption of the IC chip increases in proportion, and the heat generation of the IC chip also increases, thereby further accelerating the aging of the IC chip. Therefore, the scan test time minimization device can use the maximum shift frequency that can be assigned to each scan section that was previously previewed to accelerate the aging during burn-in testing to reduce burn-in test time. In addition, a test apparatus capable of performing such a burn-in test is called a burn-in test apparatus.

The present invention and the scan shift frequency information obtained by performing the present invention or the scan section information reflecting the information can also be embodied as computer readable codes or data on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include various types of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, optical data storage device, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

Claims (50)

1. For each of the at least two scan sections, identifying a first shift frequency at which the output pattern of the scan chain differs from the prediction pattern by increasing or decreasing the shift frequency; And

   Determining a second shift frequency smaller than the first shift frequency as the shift frequency of each scan section.
2. The method of claim 1, wherein the determining of the first shift frequency comprises:

   Selecting a scan section for which a shift frequency is not determined;

   Increasing or decreasing the shift frequency;

   Inputting the scan section into a scan chain using the increased shift frequency;

   Moving to the step of increasing or decreasing the shift frequency if the output pattern of the scan chain is the same as the predictive pattern; And

   And determining a shift frequency when the output pattern is different from the prediction pattern as the first shift frequency.
3. The method of claim 1, wherein the determining of the first shift frequency comprises:

   Selecting a scan section for which a shift frequency is not determined;

   When a first input pattern located in front of the selected scan section, the selected scan section, and a second input pattern located behind the selected scan section are sequentially input to the scan chain, and the output pattern of the scan chain is different from the prediction pattern. Identifying a shift frequency of the first shift frequency;
4. The method of claim 3, wherein

   The shift frequency of the scan section belonging to the first input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the first input pattern,

   The shift frequency of the scan section belonging to the second input pattern is equal to or less than the nominal shift frequency or less than the predetermined shift frequency for the scan section belonging to the second input pattern.

   And shifting the shift frequency of the selected scan section until the output pattern differs from the prediction pattern.
5. The method of claim 3, wherein

   The first input pattern is an actual first input pattern located in front of the selected scan section in an actual test or a prediction pattern of scan capture by the first input pattern,

   And wherein the second input pattern is an actual second input pattern or dummy pattern located behind the selected scan section in an actual test.
6. The method of claim 3, wherein the determining of the first shift frequency comprises:

   The shift frequency at a point in time at which the output pattern of the scan chain for the first input pattern is different from the first prediction pattern or the output pattern of the scan chain for the selected scan section is different from the second prediction pattern is identified as the first shift frequency. Scan test time minimization method comprising a.
7. The method of claim 6,

   And wherein the second prediction pattern is a prediction pattern for scan capture performed while the selected scan section is loaded in the scan chain.
8. The method of claim 1, wherein the determining of the first shift frequency comprises:

   Combining the increase or decrease of the supply frequency with the increase or decrease of the shift frequency to identify a first shift frequency at a point in time at which the output pattern and the prediction pattern are different for each scan section; Minimization method.
9. The method of claim 1,

   The determining of the shift frequency may include determining, by the shift frequency of each scan section, a shift frequency divided by a shift frequency of a predetermined magnitude that may be increased or decreased by scan test equipment. Minimization method.
10. The method of claim 1, wherein the determining step,

    Determining a second shift frequency for each scan section for a plurality of chips;

    And determining a shift frequency of a corresponding scan section, which is equal to or smaller than the smallest value among the plurality of second shift frequencies determined for each scan section, for the plurality of chips.
11. The method of claim 1,

    Grouping the at least two or more scan sections into at least one section group based on at least one or more constraints including a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time resulting from a scan shift frequency change; And

    And determining the shift frequency of the section group to be less than or equal to the smallest value among the determined shift frequencies of each scan section belonging to the section group.
12. The method of claim 1,

    And performing a burn-in test and a scan test while increasing the temperature of a test chip using the shift frequency determined for the scan section.
13. The method of claim 2, wherein the inputting to the scan chain comprises:

    And inputting the selected scan section into the scan chain at every repetition while reflecting an increase or decrease of at least one of a shift frequency, a supply voltage, and an external temperature.
14. The method of claim 1,

    And rearranging and rearranging patterns on the scan pattern set including the scan section.
15. Determining a different shift frequency for each of the at least two scan sections;

    And the shift frequency determined for each scan section is a value smaller than the shift frequency at which the output pattern of the scan chain differs from the predicted pattern.
16. The method of claim 15, wherein the determining step,

    Selecting a scan section for which a shift frequency is not determined;

    The process of sequentially inputting a first input pattern located in front of the selected scan section, the selected scan section, and a second input pattern located behind the selected scan section into a scan chain, wherein the first input pattern and the first input pattern are repeatedly performed. Inputting a second input pattern into the scan chain at a preset shift frequency and inputting the selected scan section to the scan chain at an increased or decreased shift frequency at each iteration; And

    And determining a shift frequency of the selected scan section as a shift frequency of which the output pattern of the scan chain is smaller than the shift frequency of a time point different from the prediction pattern.
17. The method of claim 16,

    And the output pattern is unloaded by shifting out a result pattern of scan capture when at least one of the first input pattern and the selected scan section is loaded.
18. The method of claim 16, wherein the inputting to the scan chain comprises:

    And inputting the selected scan section into the scan chain at every repetition while reflecting an increase or decrease of at least one of a shift frequency, a supply voltage, and an external temperature.
19. The method of claim 15,

    And performing a burn-in test and a scan test while increasing the temperature of a test chip using the shift frequency determined for the scan section.
20. The method of claim 15,

    And rearranging and rearranging patterns on the scan pattern set including the scan section.
21. The method of claim 15,

    The determining of the shift frequency may include determining, by the shift frequency of each scan section, a shift frequency divided by a shift frequency of a predetermined magnitude that may be increased or decreased by scan test equipment. Minimization method.
22. The method of claim 15, wherein the determining step,

    Determining a shift frequency of each scan section for a plurality of chips; And

    And determining a shift frequency of a corresponding scan section, which is less than the smallest value among the plurality of shift frequencies determined for each scan section, for the plurality of chips.
23. The method of claim 15,

    Grouping the at least two or more scan sections into at least one section group based on at least one or more constraints including a maximum number of scan shift frequency changes, a maximum number of scan shift frequencies, and a delay time resulting from a scan shift frequency change; And

    And determining the shift frequency of the section group to be less than or equal to the smallest value among the determined shift frequencies of each scan section belonging to the section group.
24. The method of claim 16, wherein the inputting to the scan chain comprises:

    And inputting the selected scan section into the scan chain at every repetition while reflecting an increase or decrease of at least one of a shift frequency, a supply voltage, and an external temperature.
25. A frequency increase / decrease unit for increasing or decreasing a scan shift frequency;

    A pattern input unit configured to input a scan pattern including at least one scan section into a scan chain;

    A pattern comparison unit to determine whether an output pattern of the scan chain is identical to a prediction pattern; And

    And a frequency grasp unit for identifying a shift frequency smaller than a shift frequency at a time point at which the output pattern and the prediction pattern are different as possible shift frequencies of the scan section.

    At least two scan sections, wherein some or all of the identified shift frequencies are different from each other.
26. The method of claim 25,

    And a pattern divider dividing one or more scan patterns into at least two scan sections.
27. The method of claim 25, wherein the frequency grasping unit,

    Repeating the step of inputting a scan section and a scan pattern located in front of the scan section into the scan chain, the scan pattern located in front of the scan section is input to the scan chain at a preset shift frequency, the scan section is repeated A scan test time inputted to the scan chain at an increase / decrease shift frequency every time, and a shift frequency of which the output pattern of the scan chain is smaller than the shift frequency at a point in time different from the prediction pattern is identified as a possible shift frequency of the scan section Minimize device.
28. An output pattern of the scan chain for at least one scan section in which power consumption or current consumption when shifting the scan section in the scan chain at a preset initial shift frequency of at least two scan sections is above or above a preset threshold; Determining a shift frequency equal to the prediction pattern.
29. The method of claim 28,

    Allocating the initial shift frequency or less for at least one or more scan sections where power consumption or current consumption is below or below the threshold.
30. The method of claim 28,

    Determining a first shift frequency for a first scan section in which power consumption or current consumption is above or above the threshold; And

    Determining a second shift frequency for a second scan section where power consumption or current consumption is below or below the threshold;

    And wherein the first shift frequency and the second shift frequency are different from each other.
31. The method of claim 28,

    Shift frequencies of some or all of the scan sections whose power consumption or current is below or below the threshold are equal to each other,

    At least some of the scan sections whose power consumption or current is above or above the threshold are different in shift frequency from each other.
32. The method of claim 28, wherein determining the shift frequency,

    Selecting a scan section in which a shift frequency is not determined among scan sections in which power consumption or current consumption is above or above a preset threshold;

    Increasing or decreasing the shift frequency;

    Shifting the selected scan section into a scan chain at the increased or decreased shift frequency;

    Comparing whether the output pattern and the prediction pattern of the scan chain are the same;

    Moving to the step of increasing or decreasing the shift frequency if the output pattern and the prediction pattern are the same; And

    And determining the shift frequency of the selected scan section to be equal to or less than the shift frequency before the output pattern is different from the prediction pattern.
33. The method of claim 28,

    And performing a burn-in test and a scan test while increasing the temperature of the chip to be tested using the shift frequency determined and determined for the scan section and the corresponding scan section.
34. The method of claim 28,

    And rearranging and reordering the scan patterns.
35. Determining a first shift frequency and a second shift frequency at which power consumption or current consumption when shifting the first scan section and the second scan section into the scan chain is above or above a preset threshold; And

    Determining a third shift frequency and a fourth shift frequency when power consumption or current consumption when shifting a third scan section and a fourth scan section to the scan chain is less than or less than the threshold;

    The first shift frequency and the second shift frequency are different from each other,

    And the third shift frequency and the fourth shift frequency are the same.
36. 36. The method of claim 35, wherein determining the first shift frequency and the second shift frequency comprises:

    Identifying a first scan section and a second scan section whose power consumption or current consumption when shifting the scan section to the scan chain at a preset initial shift frequency is above or above the threshold;

    For each of the first scan section and the second scan section, determining a shift frequency in which the output pattern of the scan chain is equal to a prediction pattern as the first shift frequency and the second shift frequency, respectively, by increasing or decreasing the shift frequency; Scan test time minimization method comprising a.
37. 36. The method of claim 35, wherein determining the third shift frequency and the fourth shift frequency comprises:

    Identifying a third scan section and a fourth scan section whose power consumption or current consumption when shifting the scan section to the scan chain at a preset initial shift frequency is less than or equal to or less than the threshold;

    And determining, for the third scan section and the fourth scan section, the initial shift frequency or less as the third shift frequency and the fourth shift frequency.
38. The method of claim 35, wherein

    And performing a burn-in test and a scan test while increasing the temperature of the chip to be tested using the shift frequency determined and determined for the scan section and the corresponding scan section.
39. The method of claim 35, wherein

    And rearranging and reordering the scan patterns.
40. A power detector for detecting power consumption or current consumption when the scan section is shifted in the scan chain at a first shift frequency;

    A first frequency grasp for identifying or determining the first shift frequency or less as a possible shift frequency of the scan section for at least one or more scan sections whose power consumption or current consumption by the first shift frequency is below or below a predetermined threshold; part; And

    A second for identifying or determining at least one second shift frequency for at least one scan section where power consumption or current draw is above or above the threshold, the output pattern of the scan chain being equal to a prediction pattern Scan test time minimizing apparatus comprising a; frequency grasping unit.
41. The method of claim 40,

    And a pattern divider dividing the scan pattern into at least two scan sections.
42. The method of claim 40,

    Shift frequencies of some or all of the scan sections whose power consumption or current is below or below the threshold are equal to each other,

    And at least some of the scan sections whose power consumption is above or above the threshold are different in shift frequency from each other.
43. A computer-readable recording medium having recorded thereon a program for performing the method of claim 1.
44. A computer-readable recording medium storing shift frequency information determined or determined for a scan section by performing the method of claim 1, or scanning section information reflecting the shift frequency information.
45. A computer-readable recording medium having recorded thereon a program for performing the method of claim 15.
46. A computer-readable recording medium storing shift frequency information determined or determined for a scan section by performing the method described in claim 15 or scan section information reflecting the shift frequency information.
47. A computer-readable recording medium having recorded thereon a program for performing the method of claim 28.
48. 29. A computer-readable recording medium having recorded thereon the shift frequency information or the scan section information reflecting the shift frequency information, which is determined or determined for the scan section by performing the method of claim 28.
49. A computer-readable recording medium having recorded thereon a program for performing the method of claim 35.
50. A computer-readable recording medium storing shift frequency information determined or determined for a scan section or scan section information reflecting the shift frequency information by performing the method of claim 35.

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