JP2006295176A - 薄膜トランジスタ、平板表示装置用アレイ基板、薄膜トランジスタの製造方法、及び平板表示装置用アレイ基板の製造方法 - Google Patents
薄膜トランジスタ、平板表示装置用アレイ基板、薄膜トランジスタの製造方法、及び平板表示装置用アレイ基板の製造方法 Download PDFInfo
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- 239000010703 silicon Substances 0.000 claims abstract description 139
- 239000002070 nanowire Substances 0.000 claims abstract description 132
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- 229910021332 silicide Inorganic materials 0.000 description 3
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- IAQRGUVFOMOMEM-UHFFFAOYSA-N butene Natural products CC=CC IAQRGUVFOMOMEM-UHFFFAOYSA-N 0.000 description 1
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- 230000008025 crystallization Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】本発明は、基板100上に位置して、中央部と両側部を有するシリコンナノワイヤー102と、前記中央部上に位置するゲート電極114と、前記シリコンナノワイヤー102と電気的に連結され、前記両側部各々に位置するソース電極110及び前記ソース電極110と離隔されるように位置するドレイン電極112を含む薄膜トランジスタTを提供する。
【選択図】図6C
Description
本発明の実施の形態1は、アクティブ層としてシリコンナノワイヤーを含み、ソース電極及びドレイン電極は、ゲート電極と同一工程によって同一物質で構成される。
以下、本発明の実施の形態2は、シリコンナノワイヤーを基板上にスプレー方式によって形成する特徴を含む。
Claims (35)
- 基板上に位置して、中央部と両側部を有するシリコンナノワイヤーと、
前記中央部上に位置するゲート電極と、
前記シリコンナノワイヤーと電気的に連結され、前記両側部各々の上部に位置するソース電極及び前記ソース電極と離隔されるように位置するドレイン電極と
を含む薄膜トランジスタ。 - 前記シリコンナノワイヤーは、半導体物質で構成されたコアと、前記コアを取り囲む絶縁層とを含む請求項1に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーは、前記コアと前記絶縁層間に、同軸構造を有する請求項2に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーは、棒状である請求項1に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーは、多数のシリコンナノワイヤーで構成される請求項1に記載の薄膜トランジスタ。
- 前記ゲート電極は、前記ソース電極及び前記ドレイン電極と同一物質で構成される請求項1に記載の薄膜トランジスタ。
- 前記シリコンナノワイヤーと前記ゲート電極間、前記シリコンナノワイヤーと前記ソース電極間、前記シリコンナノワイヤーと前記ドレイン電極間に位置して、前記シリコンナノワイヤーを前記基板上に固定させる固定層をさらに含む請求項1に記載の薄膜トランジスタ。
- 前記固定層は、前記ソース電極及び前記ドレイン電極の一部領域を各々露出させる第1コンタクトホールと第2コンタクトホールを有し、
前記ソース電極及び前記ドレイン電極は、前記第1コンタクトホールと前記第2コンタクトホールを通じて前記シリコンナノワイヤーに連結される
請求項7に記載の薄膜トランジスタ。 - 前記固定層は、有機絶縁物質で構成される請求項7に記載の薄膜トランジスタ。
- 前記有機絶縁物質は、ベンゾシクロブテン(BCB)とアクリル系樹脂を含む請求項9に記載の薄膜トランジスタ。
- 基板上に位置して、中央部と両側部を有するシリコンナノワイヤーと、
前記中央部上に位置するゲート電極と、
前記シリコンナノワイヤーと電気的に連結され、前記両側部各々に位置する第1ソース電極及び前記第1ソース電極と離隔されるように位置する第1ドレイン電極と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極と、
前記第2ドレイン電極に連結される画素電極と
を含む平板表示装置用アレイ基板。 - 前記第1ソース電極と前記第2ソース電極間、前記第1ドレイン電極と前記第2ドレイン電極間に位置して、前記第1ソース電極及び前記第1ドレイン電極の一部領域を露出させる第1コンタクトホールと第2コンタクトホールを有するゲート絶縁膜をさらに含む請求項11に記載の平板表示装置用アレイ基板。
- 前記第2ソース電極は、前記第1コンタクトホールを通じて前記第1ソース電極に連結され、
前記第2ドレイン電極は、前記第2コンタクトホールを通じて前記第1ドレイン電極に連結される
請求項12に記載の平板表示装置用アレイ基板。 - 前記第2ドレイン電極と前記画素電極間、前記第2ドレイン電極と前記画素電極間に位置し、前記第2ドレイン電極の一部領域を露出するドレインコンタクトホールを有する保護層をさらに含む請求項11に記載の平板表示装置用アレイ基板。
- 前記画素電極は、前記ドレインコンタクトホールを通じて前記第2ドレイン電極に連結される請求項14に記載の平板表示装置用アレイ基板。
- 基板上に位置して、中央部と両側部を有するシリコンナノワイヤーと、
前記中央部上に位置するゲート絶縁膜と、
前記ゲート絶縁膜上に位置するゲート電極と、
前記シリコンナノワイヤーと直接接触して、前記両側部各々に位置するソース電極及び前記ソース電極と離隔されるように位置するドレイン電極と
を含む薄膜トランジスタ。 - 前記シリコンナノワイヤーの中央部と前記ゲート絶縁膜間に位置する固定層をさらに含む請求項16に記載の薄膜トランジスタ。
- 基板上に位置して、中央部と両側部を有するシリコンナノワイヤーと、
前記中央部上に位置するゲート絶縁膜と、
前記ゲート絶縁膜上に位置するゲート電極と、
前記シリコンナノワイヤーと直接接触して、前記両側部各々に位置する第1ソース電極及び前記第1ソース電極と離隔されるように位置する第1ドレイン電極と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極と、
前記第2ドレイン電極に連結される画素電極と
を含む平板表示装置用アレイ基板。 - 中央部と両側部を有するシリコンナノワイヤーを基板上に配置する段階と、
前記中央部上に、ゲート電極を形成する段階と、
前記両側部各々に、前記シリコンナノワイヤーと電気的に連結されるソース電極及び前記ソース電極と離隔されるドレイン電極を形成する段階と
を含む薄膜トランジスタの製造方法。 - 前記シリコンナノワイヤーと前記ソース電極間、前記シリコンナノワイヤーと前記ドレイン電極間に位置して、前記シリコンナノワイヤーを前記基板上に固定する固定層を形成する段階をさらに含む請求項19に記載の薄膜トランジスタの製造方法。
- 前記固定層を形成する段階は、前記ソース電極及び前記ドレイン電極の一部領域を露出させる第1コンタクトホールと第2コンタクトホールを形成する段階を含み、
前記ソース電極及び前記ドレイン電極は、各々前記第1コンタクトホールと前記第2コンタクトホールを通じて前記シリコンナノワイヤーに連結される
請求項20に記載の薄膜トランジスタの製造方法。 - 前記シリコンナノワイヤーは、スプレー方式によって前記基板上に配置される請求項19に記載の薄膜トランジスタの製造方法。
- 前記シリコンナノワイヤーを基板上に配置する段階は、
ナノサイズの触媒を蒸着する段階と、
シリコンを含む反応性ガスを利用して、前記触媒を結晶化する段階と
をさらに含む請求項19に記載の薄膜トランジスタの製造方法。 - 前記ゲート電極は、前記ソース電極及び前記ドレイン電極と同一工程によって形成される請求項19に記載の薄膜トランジスタの製造方法。
- 中央部と両側部を有するシリコンナノワイヤーを基板上に配置する段階と、
前記中央部上に、ゲート電極を形成する段階と、
前記両側部各々に、前記シリコンナノワイヤーと電気的に連結される第1ソース電極及び前記第1ソース電極と離隔される第1ドレイン電極を形成する段階と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、
前記第2ドレイン電極に連結される画素電極を形成する段階と
を含む平板表示装置用アレイ基板の製造方法。 - 前記第1ソース電極と前記第2ソース電極間、前記第1ドレイン電極と前記第2ドレイン電極間に位置して、前記第1ソース電極及び前記第1ドレイン電極の一部領域を各々露出する第1コンタクトホールと第2コンタクトホールを有するゲート絶縁膜を形成する段階をさらに含む請求項25に記載の平板表示装置用アレイ基板の製造方法。
- 前記第2ソース電極は、前記第1コンタクトホールを通じて前記第1ソース電極に連結され、
前記第2ドレイン電極は、前記第2コンタクトホールを通じて前記第1ドレイン電極に連結される
請求項26に記載の平板表示装置用アレイ基板の製造方法。 - 前記第2ドレイン電極と前記画素電極間、前記第2ドレイン電極と前記画素電極間に位置して、前記第2ドレイン電極の一部を露出させるドレインコンタクトホールを含む保護層を形成する段階をさらに含む請求項26に記載の平板表示装置用アレイ基板の製造方法。
- 前記画素電極は、前記ドレインコンタクトホールを通じて前記第2ドレイン電極に連結される請求項28に記載の平板表示装置用アレイ基板の製造方法。
- 中央部と両側部を有するシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、
前記シリコンナノワイヤーを除いて、前記基板から前記溶媒を除去する段階と、
前記中央部上に、ゲート絶縁膜及びゲート電極を連続的に形成する段階と、
前記両側部各々に、前記シリコンナノワイヤーと直接接触するソース電極及び前記ソース電極と離隔されるように位置するドレイン電極を形成する段階と
を含む薄膜トランジスタの製造方法。 - 前記溶媒は、界面活性剤をさらに含む請求項30に記載の薄膜トランジスタの製造方法。
- 前記溶媒は、ヒッティングによって除去される請求項31に記載の薄膜トランジスタの製造方法。
- 前記ヒッティングは、約100℃以下の温度で行われる請求項32に記載の薄膜トランジスタの製造方法。
- 前記シリコンナノワイヤーの中央部と前記ゲート絶縁膜間に固定層を形成する段階をさらに含む請求項30に記載の薄膜トランジスタの製造方法。
- 中央部と両側部を有するシリコンナノワイヤーを含む溶媒を基板上にコーティングする段階と、
前記シリコンナノワイヤーを除いて、前記基板から前記溶媒を除去する段階と、
前記中央部上に、ゲート絶縁膜及びゲート電極を連続的に形成する段階と、
前記両側部各々に、前記シリコンナノワイヤーと直接接触する第1ソース電極及び前記第1ソース電極と離隔されるように位置する第1ドレイン電極を形成する段階と、
前記第1ソース電極に連結される第2ソース電極及び前記第1ドレイン電極に連結される第2ドレイン電極を形成する段階と、
前記第2ドレイン電極に連結される画素電極を形成する段階と
を含む平板表示装置用アレイ基板の製造方法。
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JP2011517366A (ja) * | 2008-02-25 | 2011-06-02 | スモルテック アーベー | ナノ構造処理のための導電性補助層の形成及び選択的除去 |
US8866307B2 (en) | 2008-02-25 | 2014-10-21 | Smoltek Ab | Deposition and selective removal of conducting helplayer for nanostructure processing |
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Publication number | Publication date |
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US8610128B2 (en) | 2013-12-17 |
CN1845341A (zh) | 2006-10-11 |
CN100472813C (zh) | 2009-03-25 |
US20130228750A1 (en) | 2013-09-05 |
KR20060107107A (ko) | 2006-10-13 |
US20100163850A1 (en) | 2010-07-01 |
US7704806B2 (en) | 2010-04-27 |
US20060226424A1 (en) | 2006-10-12 |
KR101145146B1 (ko) | 2012-05-14 |
JP4580890B2 (ja) | 2010-11-17 |
US8426869B2 (en) | 2013-04-23 |
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