JP2006196080A - Reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a clock which is phase synchronized to reproduced digital data without being affected by environmental changes. <P>SOLUTION: A reproducing device is provided with: a converting means which converts reproduced signals into digital signals in accordance with the clock; a pattern detection means which applies processing of PR(1, 1) to the digital signals outputted from the converting means and detects a specific pattern in n bit data that are made by n sample data being obtained by binary discriminating the above process result; an extracting means which extracts the digital signals in accordance with the output of the pattern detecting means and outputs the digital signals as phase difference signals; a clock generation means which outputs the clock in accordance with the phase difference signals; and an adjusting means which extracts the digital signals in accordance with the output of the pattern detection means and detects and adjusts the offset with respect to the center level of the digital signals based on the extracted result. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reproduction apparatus, and more particularly to generation of a clock synchronized with reproduction data.

2. Description of the Related Art In recent years, apparatuses for recording and reproducing image data and the like as digital data have become widespread on optical disks capable of recording digital data at high density. In this type of apparatus, in order to accurately detect the original digital data from the reproduction signal from the disk, it is necessary to obtain a clock synchronized with the reproduction signal. Conventionally, a PLL circuit as shown in FIG. 2 has been used as a circuit for obtaining a clock synchronized with a reproduction signal (see, for example, Patent Document 1). In FIG. 2, the reproduction signal is input to the A / D converter and the phase comparator, and the phase error between the output clock from the VCO and the reproduction signal is detected by the phase comparator. The detected phase error signal is supplied to the VCO via the loop filter, and changes the oscillation frequency of the VCO. The A / D converter samples the reproduction signal according to the clock from the VCO, converts it to a digital signal, and outputs it to the reproduction signal processing circuit.
JP-A-10-144008

  However, in the conventional configuration, the PLL is configured with an analog circuit in order to obtain a clock synchronized with the reproduction signal, and the circuit characteristics tend to fluctuate due to changes in the surrounding environment such as temperature changes and changes over time. And there is a problem that sorting is necessary.

  An object of the present invention is to solve the above-described problems and to obtain a clock that is phase-synchronized with reproduced digital data without being affected by environmental changes.

  In order to solve the above-mentioned problems and achieve the object, a reproducing apparatus according to the present invention samples reproducing signals output from a reproducing medium and reproducing signals output from the reproducing means in accordance with a clock. Conversion means for converting into a multi-bit digital signal, and a continuous n sample obtained by performing partial response (1, 1) processing on the digital signal output from the conversion means and binary-determining the result A pattern detection means for detecting a specific pattern in n-bit data comprising n (n is an integer of 2 or more) data, and a digital signal output from the conversion means in accordance with the output of the pattern detection means. Extraction means for outputting a signal indicating a phase difference between the reproduction signal and the clock; and a clock for outputting the clock according to the output of the extraction means. The digital signal output from the conversion means is extracted in response to the output of the pattern generation means and the pattern detection means, and the offset relative to the center level of the digital signal output from the conversion means is detected based on the extraction result Offset detecting means for adjusting, and adjusting means for adjusting the center level of the digital signal output from the converting means based on the output of the offset detecting means.

  According to the present invention, it is possible to detect a phase difference between reproduced data and a clock with high accuracy and generate a clock synchronized with the reproduced data with a simple configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of a playback system of a playback apparatus to which the present invention is applied. The playback device of this embodiment plays back a digital video signal recorded on an optical disc, and detects the phase difference between the playback signal and the clock according to a specific data pattern in the video signal.

  In FIG. 1, an optical pickup 101 reads a video signal recorded on a disk D and outputs it to an A / D converter 102. The A / D converter 102 samples the output signal of the optical pickup 101 in accordance with the clock generated from the VCO 112 and converts it into a digital signal of one sample and multiple bits. The reproduction data output from the A / D converter 102 is extracted from the high frequency component by the high-pass filter 103, and the FIR filter 105 has a frequency characteristic that raises a predetermined high frequency via the adder 104 for center level adjustment. Is output. Data output from the FIR filter 105 is supplied to the data detector 106 and the phase detector 110.

  The data detector 106 detects 1-sample 1-bit digital data from 1-sample multiple-bit input data using the Viterbi algorithm. The reproduced data detected by the data detector 106 is output to the error correction circuit 107. The error correction circuit 107 corrects an error in the reproduction data generated on the transmission path using the parity data added at the time of recording, and outputs it to the reproduction signal processing circuit 108. The reproduction signal processing circuit 108 performs decompression / decoding processing corresponding to the compression / encoding processing performed at the time of recording on the reproduced video data input from the error correction circuit 107, and sends the reproduction signal via the output terminal 109. Output to the outside of the playback device.

  On the other hand, the phase detector 110 detects the phase difference between the reproduction data and a clock output from the VCO 112 described later, and outputs a phase error signal according to the phase difference. The phase error signal output from the phase detector 110 controls the VCO 112 through the loop filter 111 so as to generate a clock that is phase-synchronized with the reproduction signal. The phase detector 110 to the loop filter 111 to the VCO 112 to A / D 102 constitute a PLL circuit.

  Based on the output of the phase detector 110, the center level adjustment circuit 113 generates an offset signal for center level adjustment so that the center level of the digital data output from the HPF 103 becomes an optimum position, and outputs it to the adder 104. To do.

  In this embodiment, the signal recorded on the disk D is recorded by being modulated by a run length limited (hereinafter RLL) (1, 7) modulation method, and the frequency characteristics of the recording / reproducing system are the partial response (hereinafter PR). It has the characteristics of (1, 2, 2, 1). FIG. 3 shows a state transition diagram that can be taken by the signal recorded on the disc D at this time.

  S0 (0, 0, 0), S1 (0, 0, 1), S2 (0, 1, 1), S3 (1, 1, 1), S4 (1, 1, 0), S5 (1, 0 , 0) represents a state, and a line connecting the states represents a state transition. From the state transition diagram of FIG. 3, the possible values of the reproduction signal are seven values of −3, −2, −1, 0, 1, 2, and 3.

  Therefore, the eye pattern of the reproduction signal has a waveform shown in FIG. In the waveform of FIG. 4A, the clock component cannot be extracted even if binarization is performed with the value 0.

  Therefore, PR (1, 1) processing is performed on the reproduction signal waveform of FIG. 4A to convert it to the waveform of FIG. This waveform is a waveform obtained by shifting the sampling point by 0.5T (T is a sampling period), and an eye pattern is opened at the sampling point. After conversion into such a waveform, the clock can be extracted by binarizing the value 0 as a threshold value.

  The operation of the phase detector 110 will be described with reference to FIG.

  FIG. 5A shows the waveform of the reproduction signal from the disk D, the horizontal axis indicates the elapsed time, and the vertical axis indicates the value of the data sampled by the A / D converter 102. Vertical lines with a, b, c, and d indicate sampling points of the A / D converter 102, and black circles indicate output values of the A / D converter 102. A broken line indicates a reproduction signal waveform input to the phase detector 110, and here, a case where an analog reproduction waveform corresponding to [−3, −2, 0, 2, 3, 3] is input is illustrated. Yes.

  FIG. 5B shows a waveform of a signal obtained by subjecting the reproduction signal of FIG. 5A to PR (1, 1) processing. Here, [-5, -2, 2, 5, 6]. Go through the point. By binarizing the PR (1, 1) waveform of FIG. 5B with the value 0 as a threshold value, values of [0, 0, 1, 1, 1] are obtained. 5 (a) and 5 (b), zero crossing is present in the corresponding reproduced signal waveform at the change point (point a to point b) where the binarized value of the PR (1, 1) waveform changes from 0 to 1. It can be seen that dots are included. Thus, if the change point “0 to 1” or “1 to 0” of the binarized value of the PR (1,1) waveform is detected, the zero cross point of the reproduced waveform having a slope proportional to the phase difference is detected. can do.

  In this embodiment, the phase detector 110 is configured based on such an idea.

  FIG. 6 is a diagram showing the configuration of the phase detector 110 and the center level adjustment circuit 113.

  In FIG. 6, digital data of a plurality of bits output from the FIR filter 105 is input to a register 602 through a terminal 601. The input digital data and the output data from the register 602 are added by the adder 603. The addition result output from the adder 603 is input to the comparator 604. The comparator 604 determines whether or not the addition result is greater than 0. Specifically, the addition result MSB is supplied to the register 605 and the pattern detector 606. The register 605 outputs the output of the comparator 604 to the pattern detector 606 with a delay of one sample clock period. The pattern detector 606 detects a specific pattern using the 2-bit signal of the signal a output from the comparator 604 and the signal b output from the register 605, and outputs signals s and t.

  In addition, the register 612 delays a plurality of bits of data input from the terminal 601 by one sample period, and outputs the delayed data to the inversion circuit 607, the b terminal of the switch 608, and the center level adjustment circuit 113.

  The connection of the switch 608 is switched by the output signal s from the pattern detector 606, and outputs one of the output of the inverting circuit 607 and the output of the register 612. The output of the switch 608 is supplied to the a side terminal of the switch 609.

  The connection of the switch 609 is switched by a signal t from the pattern detector 606. Specifically, when the pattern detector 606 detects a pattern corresponding to the zero cross point, t = 1 is output, and the switch 607 is connected to the a side to update the value of the register 610. The output of the register 610 is output from the output terminal 611 as a phase difference signal.

  On the other hand, when the pattern detector 606 does not detect a pattern corresponding to zero cross, t = 0 is output, and the switch 609 is connected to the b-side terminal and holds the value of the register 610.

  In the center level adjustment circuit 113, a multi-bit signal output from the register 612 is output to the terminal a of the switch 621. The switch 621 is switched by a control signal e_en from the pattern detector 606.

  The pattern detector 606 outputs c_en = 1 when detecting a pattern that crosses zero, and the switch 621 updates the value of the register 622 by connecting to the a-side terminal. If the pattern detector 606 does not detect a pattern that crosses zero, c_en = 0 is output and the value of the register 622 is held.

  The data output from the register 622 is output to the terminal b of the switch 621 and the adder 623, integrated by the adder 623, limiter 624, register 625, level adjusted by the amplifier 626, and then the center level offset signal from the terminal 627. Is output to the adder 104.

  The adder 104 adds this offset to the output of the HPF 103 and adjusts the center level to an optimum position.

  Here, the reproduction waveform of the secondary distortion will be described with reference to FIG.

  In FIG. 7, reference numeral 701 denotes the relationship between the signal waveform (input) when recording on the disk D and the waveform (output) of the reproduction signal read out by the pickup 101. An example of the read signal waveform is shown. When a signal having a waveform as in 702 (c) having a linear characteristic of 701 (a) is reproduced, if the DC component is suppressed by the HPF 103, the threshold value 0 of the comparator 604 matches the center level. Therefore, no problem occurs in the phase detection characteristics.

  However, when a signal having a waveform of 702 (d) having the second-order distortion characteristic of 701 (b) is reproduced, a DC offset remains even if the HPF 103 suppresses the DC component, and the comparator There is a possibility that an error occurs between the threshold value 0 of 604 and the center level of the reproduced waveform, and the comparison result by the comparator 604 may be erroneous. In this embodiment, this problem is solved by the center level adjustment circuit 113, and an accurate phase detection characteristic is obtained even when a secondary distortion reproduction waveform is input.

  Next, pattern detection processing by the pattern detector 606 will be described. FIG. 8 is a truth table showing 2-bit data of the signals a and b inputted to the pattern detector 606 and the operation logic of the output signal.

  The pattern detector 606 is supplied with 2-bit data a and b. Of the four types of 2-bit patterns in total, the zero-crossing pattern having a slope proportional to the phase difference is two patterns “01” and “10” of the combinations of signals a and b. FIG. 9A shows the phase detection characteristic of “01”, and FIG. 9B shows the phase detection characteristic of “10”. As shown in FIG. 9, since the phase detection characteristics are reversed between “01” and “10”, the ideal pattern shown in FIG. 9A is obtained when the “10” pattern is detected. The polarity is inverted by an inversion circuit 607 so as to have phase detection characteristics.

  The switch 608 is controlled by the control signal s output from the pattern detector 606. When the polarity is inverted, s = 1 is output and connected to the terminal a, and when not inverted, s = 0 is output. And connected to the terminal b.

  Further, the control signal t is a signal indicating whether or not it is a zero cross. When the pattern detector 606 detects a pattern of “01” and “10”, a zero cross point exists in the reproduction waveform, so that the control signal t = 1 is output, the switch 609 is connected to the terminal a, the signal from the switch 608 is output to the register 610, and the value of the register 610 is updated. Conversely, if there is no zero cross point, the control signal t = 0 is output, the switch 609 is connected to the terminal b, and the value of the register 610 is held as it is.

  Next, the operation principle of phase difference detection by the phase detector 110 will be described with reference to FIG.

  In FIG. 10, vertical lines with a, b, c, and d indicate sampling points of the A / D converter 102, and black circles indicate output values of the A / D converter 102.

  The broken line indicates the waveform of the input reproduction data. Here, the reproduction data corresponding to [−3, −2, 0, 2, 3, 3] is input.

  FIG. 10A shows a sample output when the phase of the sampling clock of the A / D converter 102 matches the phase of the reproduction data. The pattern detector 606 detects the zero cross point of the reproduction waveform as shown in FIG. 10 and samples the value of the reproduction signal at that time. In FIG. 10A, a zero cross point is set between sampling points a and b. At this time, the sampling result at sampling point a is 0, so that the output result at output terminal 611 of phase detector 110 is 0, and the phase error is 0. It shows no.

  FIG. 10B shows a case where the phase of the reproduction data is ahead of the phase of the sampling clock of the A / D converter 102. As apparent from FIG. 10B, when the zero cross point is detected and the value of the reproduction signal at that time is sampled, the value is proportional to the phase difference between the reproduction signal and the sampling clock.

  Here, since the sampling result of the sampling point a is larger than the value 0, the output result of the output terminal 611 of the phase detector 110 is a positive number proportional to the phase difference between the clock and the reproduction signal. The pattern detector 606 detects the zero cross point according to the truth table of FIG. 8, extracts the reproduction data value when the zero cross point is detected, and updates the value of the register 610 so that the reproduction data is output to the output terminal 611. And a positive number corresponding to the phase shift between the clock and the clock is output. Here, a positive sign indicates that the phase of the reproduction data is ahead of the sampling clock.

  FIG. 10C shows a sample output when the phase of the reproduction data is delayed from the phase of the sampling clock of the A / D converter 102.

  Here, since the sampling result of the sampling point a is smaller than the value 0, the output result of the output terminal 611 of the phase detector 110 is a negative number. The pattern detector 606 detects the zero cross point according to the truth table of FIG. 8 and updates the value of the register 610, and a negative number corresponding to the phase shift is output to the output terminal 611. The negative sign indicates that the phase of the reproduction signal is delayed from the sampling phase of the A / D converter 102.

  As described above, in the present embodiment, the A / D conversion is performed on the video signal reproduced from the disc, the PR (1, 1) process is performed, and the binary signal is obtained from the binary determination. Since the specific pattern corresponding to the zero cross point in the reproduction signal is detected, the reproduction data at that time is extracted and the VCO is controlled as a phase difference signal, so that the reproduction data and clock at the sampling point can be easily and accurately detected. A phase difference can be detected. Further, since the specific pattern included in the video signal is detected, it is not necessary to record the specific pattern for detecting the phase fluctuation on the disc separately from the video signal, and the recording capacity of the disc can be used effectively.

  Also, by adjusting the center level offset of the playback signal using the integrated signal obtained by extracting the playback data at the zero-cross point, even if there is a secondary distortion in the playback waveform, playback at the sampling point is highly accurate. The phase difference between the data and the clock can be detected.

  Next, a second embodiment will be described.

  FIG. 11 is a diagram showing a configuration of the phase difference detector 110 and the center level adjustment circuit 113 as the second embodiment of the present invention.

  In the first embodiment, the zero-cross point is detected by detecting a specific pattern in 2-bit data obtained by binary-determining two consecutive samples, but in this embodiment, zero-crossing is performed using four consecutive samples. Detect points. Other configurations are the same as those of the circuit shown in FIG.

  As in FIG. 6, the reproduction signal subjected to PR (1, 1) processing from the adder 603 is output to the comparator 604. The comparator 604 supplies the MSB of the input signal to the register 605 and the pattern detector 606a. The registers 605, 605a, and 605b respectively delay the input data by one sample clock period and output the delayed data to the pattern detector 606a. The pattern detector 606a detects a specific pattern corresponding to the zero cross point by using the signal d output from the comparator 604 and the 4-bit signals output from the registers 605, 605a, and 605b. Then, similarly to the pattern detector 606 in FIG. 6, the control signals s and t are output.

  Each of the registers 612 and 613 delays and outputs the reproduction data of a plurality of bits input from the terminal 601 by one sample period.

  Next, the pattern detection process by the pattern detector 606a will be described. FIG. 12 is a truth table showing 4-bit data of the signals a, b, c, and d inputted to the pattern detector 606 and the operation logic of the output signal.

  From the state transition diagram of FIG. 3, it can be seen from the values of the signals a, b, c and d in FIG. 10 which of the seven values the value of the reproduced signal waveform at the point b is. The value at point b is represented as SEL in the truth table of FIG.

  As in the present embodiment, when RLL (1, 7) is employed as the data modulation method, the pulse width of the reproduction data is 2T to 8T, where T is the sample period. Therefore, in the truth table of FIG. 12, when the reproduction data and the clock are in phase, the 1T patterns 010 and 101 do not appear. In this case, it was written # in the truth table.

  Of the 16 types of 4-bit patterns in total, the patterns corresponding to the zero cross point having a slope proportional to the phase difference are the two patterns “0011” and “1100” in which the combinations of signals a, b, c, and d are combined. . The phase detection characteristic of “0011” is shown in FIG. 10A, and the phase detection characteristic of “1100” is reversed as shown in FIG. 10B. Therefore, when the pattern of “1100” is detected, A signal whose sign is inverted by the inversion circuit 607 is selected.

  Other processes are the same as those of the circuit shown in FIG.

  As described above, in this embodiment, PR (1, 1) processing is performed on the data obtained by sampling the analog waveform of the reproduction signal, and then binarized with a value of 0, which is 4 of a, b, c, and d. By detecting the pattern corresponding to the zero cross point of the reproduction signal using bit data, extracting the value of the reproduction signal at that time and outputting it as a phase error signal, the reproduction data and clock at the sampling point can be easily and accurately And the phase difference can be detected.

  Next, a third embodiment will be described.

  FIG. 13 is a diagram showing the configuration of the phase detector 110 and the center level adjustment circuit 113 as the third embodiment of the present invention.

  In the first and second embodiments, the zero cross point is detected by detecting a specific pattern in 2-bit and 4-bit data obtained by binary discrimination of 2 samples and 4 samples in succession. Then, the zero cross point is detected using 6 consecutive samples. In FIG. 13, the same components as those in FIGS. 6 and 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Similar to FIGS. 6 and 11, the reproduction signal subjected to PR (1, 1) processing from the adder 603 is output to the comparator 604. The comparator 604 supplies the MSB of the input signal to the register 605 and the pattern detector 606b. The registers 605, 605a, 605b, 605c, and 605d delay the input data by one sample clock period and output the delayed data to the pattern detector 606b. The pattern detector 606b uses the signal f output from the comparator 604 and the 6-bit signals e, d, c, b, and a output from the registers 605, 605a, and 605b to specify the zero cross point. And the control signals s and t are output in the same manner as the pattern detector 606 in FIG.

  Each of the registers 612, 613, and 614 outputs a plurality of bits of reproduction data input from the terminal 601 with a delay of one sample period.

  Next, pattern detection processing by the pattern detector 606b will be described. FIG. 14 is a truth table showing 6-bit data of signals a, b, c, d, e, and f inputted to the pattern detector 606b and the operation logic of the output signal.

  As in the present embodiment, when RLL (1, 7) is employed as the data modulation method, the pulse width of the reproduction data is 2T to 8T, where T is the sample period. Therefore, in the truth table of FIG. 14, when the reproduction data and the clock are in phase, the 1T patterns 010 and 101 do not appear. In this case, it was written # in the truth table.

  Of the 64 types of 6-bit patterns in total, the zero-crossing pattern having a slope proportional to the phase difference has a combination of signals “a”, “b”, “c”, “d”, “e”, and “f” “000111”, “011001”, “100110”. , “111000”.

  FIG. 15 is a diagram showing phase detection characteristics in each pattern.

  15A shows the phase detection characteristics of “000111” and “100110”, and FIG. 15B shows the phase detection characteristics of “011001” and “111000”. Thus, since the phase detection characteristics of “000111” and “100110” and the phase detection characteristics of “011001” and “111000” are reversed, the pattern is inverted when the patterns “011001” and “111000” are detected. A signal whose polarity is inverted by the circuit 607 is selected from the switch 6082.

  In FIG. 10A, “000111” has a doubled slope of the phase detection characteristic compared to “100110”, and in FIG. 10B, “011001” compared to “111000”. Since the slope of the phase detection characteristic is ½, the control signal u is output according to the type of pattern detected by the pattern detector 606b, and the output from the switch 608 is set to 2 by the amplifier 615. The signal converted to double and the output from the switch 608 are selected. Specifically, when the output of the switch 608 is converted to double, u = 1 is output, and when the output of the switch 608 is output as it is, t = 0 is output. Regardless of this, the phase detection characteristic is corrected to be constant.

  Other processes are the same as those of the circuits of FIGS.

  In this way, after performing PR (1, 1) processing on the data obtained by sampling the analog waveform of the reproduction signal, a pattern corresponding to the zero cross point is detected using 6-bit data obtained by binarization, By extracting the value of the reproduction signal at that time and outputting it as a phase error signal, the phase difference between the reproduction data and the clock at the sampling point can be detected easily and with high accuracy.

  Further, when detecting a 6-bit pattern, it is possible to detect the phase difference between the reproduction data and the clock at the sampling point with higher accuracy by correcting the difference in the phase difference detection characteristic according to the type of pattern. I can do it.

  Next, a fourth embodiment will be described.

  FIG. 16 is a diagram showing the configuration of the phase detector 110 and the center level adjustment circuit 113 as the fourth embodiment of the present invention.

  Also in the present embodiment, as in the third embodiment, the zero cross point is detected using six consecutive samples. In FIG. 16, the same components as those in FIG. 13 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The pattern detector 606b shown in FIG. 13 corresponds to the zero cross point by using the signal f output from the comparator 604 and the 6-bit signals e, d, c, b, and a output from the registers 605, 605a, and 605b, respectively. The specified pattern is detected, and control signals s and t are output.

  In this embodiment, the switch 609 is not switched directly by the control signal t, but the switching of the switch 609 is controlled by the switching circuit 617.

  That is, the pattern detector 606b determines whether or not the pulse width of the reproduction data waveform corresponding to the detected pattern is 2T, and outputs a control signal w that closes the determination result to the switching circuit 617. Specifically, when the patterns “011001” and “100110” are detected, w = 1 is output because the reproduction waveform is 2T, and w = 0 is output when it is not 2T.

  The lock detection circuit 618 determines whether the PLL circuit including the phase comparator 110, the loop filter 111, and the VCO 112 is locked based on the phase error signal output from the register 610, and controls the control signal. y is output to the switching circuit 617. Specifically, when the value of the phase error signal is 0 for a predetermined period, it is determined that the phase is locked, and the control signal y = 1 is output. If the phase is not locked, the control signal y = 0 is output.

  The switching circuit 617 switches the switch 609 based on the output y of the lock detection circuit 618 and the control signals t and w from the pattern detector 606b.

  First, when the phase of the clock and the reproduction signal is not locked, y = 0 is input from the lock detection circuit 618, zero cross is determined by the pattern detector 606b, and t = 1 is output. Regardless of the value of w, the switch 609 is connected to the terminal a to update the value of the register 610.

  When y = 0 is input from the lock detection circuit, and t = 0 is input without determining zero cross in the pattern detector 606b, the switch 609 is connected to the terminal b and the value of the register 610 is held.

  Truth value indicating 6 bits of data a, b, c, d, e, f input to pattern detector 606b and operation logic of output signal when output y from lock detection circuit 618 is 0 The table is shown in FIG. In FIG. 17, a signal z is a control signal output to the switch 609. When z = 1, the switch 609 is connected to the terminal a to update the value of the register 610.

  As in this embodiment, when RLL (1, 7) is adopted as the data modulation method, when the channel bit is T, the pulse width of the reproduction data is 2T to 8T. Therefore, in the truth table of FIG. 17, when the reproduction data and the clock are in phase, the 1T patterns 010 and 101 do not appear. In this case, it was written # in the truth table.

  Of the 64 types of 6-bit patterns in total, the zero-crossing pattern having a slope proportional to the phase difference has a combination of signals “a”, “b”, “c”, “d”, “e”, and “f” “000111”, “011001”, “100110”. , “111000”.

  Also in this embodiment, as shown in FIG. 15, the phase detection characteristics of “000111” and “100110” and the phase detection characteristics of “011001” and “111000” are reversed, so that “011001”, “ When the 111000 ″ pattern is detected, a signal whose polarity is inverted by the inverting circuit 607 is selected by the switch 6082.

  Further, the control signal u is output in accordance with the type of pattern detected by the pattern detector 606b, and a signal obtained by converting the output from the switch 608 into a value doubled by the amplifier 615 and the output from the switch 608 are selected. Specifically, when the output of the switch 608 is converted to double, u = 1 is output, and when the output of the switch 608 is output as it is, t = 0 is output. Regardless of this, the phase detection characteristic is corrected to be constant.

  Next, processing of the switching circuit 617 when the phase of the reproduction signal and the clock is not locked will be described.

  When the reproduction signal and the phase of the clock are synchronized and y = 1 is input from the lock detection circuit 617, the switching circuit 617 further has a pattern detected by the pattern detector 606b corresponding to the 2T pulse. The switch 609 is switched depending on whether or not there is.

  That is, when y = 1 is input, when the control signal t = 1 indicating zero crossing and 2T pulse width is not detected and w = 0 is input, the switch 609 is connected to the terminal a to register The value of 610 is updated. When y = 1 is input, a control signal t = 1 indicating zero crossing, and a 2T pulse width is detected and w = 1 is input, the switch 609 is switched to the terminal b and the value of the register 610 is changed. Hold. If the pattern detector 606b does not determine zero crossing and t = 0 is input, the switch 609 is switched to the terminal b to hold the value of the register 610.

  As described above, when the output y from the lock detection circuit 618 is 1, 6-bit data of the signals a, b, c, d, e, and f input to the pattern detector 606b and the operation logic of the output signal FIG. 18 shows a truth table indicating the above.

  Other processes are the same as those of the circuit of FIG.

  As described above, after the PR (1, 1) processing is performed on the data obtained by sampling the reproduction signal, the pattern corresponding to the zero cross point is detected using the 6-bit data obtained by binarization, and at that time By extracting the value of the reproduction signal and outputting it as a phase error signal, the phase difference between the reproduction data and the clock at the sampling point can be detected easily and with high accuracy.

  Further, when detecting a 6-bit pattern, it is possible to detect the phase difference between the reproduction data and the clock at the sampling point with higher accuracy by correcting the difference in the phase difference detection characteristic according to the type of pattern. I can do it.

  Also, until the phase of the playback signal and the clock is locked, the phase error signal is updated when the 2T pattern is detected in addition to the 1T pulse width pattern, and the 2T pulse width pattern is detected after the phase lock. Even if the phase error signal is held without being updated, the clock phase can be quickly locked to the reproduction signal, and once locked, even if a zero cross point with a 2T pulse width with a poor S / N ratio is detected. By controlling to hold the value of the phase error signal without outputting it, the phase difference between the reproduction data and the clock at the sampling point can be detected with high accuracy.

  In each of the above-described embodiments, an apparatus for reproducing a signal recorded on a disk medium has been described. However, for example, the present invention is similarly applied to an apparatus for receiving a signal via a transmission path. Applicable.

It is a figure which shows the structure of the reproducing | regenerating apparatus with which this invention is applied. It is a figure which shows the structure of the conventional reproducing | regenerating apparatus. It is a transition diagram which shows the state of the reproduction | regeneration signal in embodiment of this invention. It is a figure which shows the waveform of a reproduction signal. It is a figure which shows the signal which carried out the reproduction signal waveform containing the zero crossing point, and its PR (1, 1) process. It is a figure which shows the structure of a phase difference detection circuit. It is a figure which shows the mode of a reproduction signal waveform. It is a truth table showing a pattern detected by the phase difference detection circuit of the first embodiment and an output signal at that time. It is a figure which shows the detection characteristic of a phase difference detection circuit. It is a figure which shows the mode of the phase difference detected by a phase difference detection circuit. It is a figure which shows the structure of the phase difference detection circuit as the 2nd Embodiment of this invention. It is a truth table which shows the pattern detected with the phase difference detection circuit of a 2nd embodiment, and the output signal at that time. It is a figure which shows the structure of the phase difference detection circuit as the 3rd Embodiment of this invention. It is a truth table which shows the pattern detected with the phase difference detection circuit of 3rd Embodiment, and the output signal at that time. It is a figure which shows the mode of a phase difference detection characteristic. It is a figure which shows the structure of the phase difference detection circuit as the 4th Embodiment of this invention. It is a truth table which shows the pattern detected with the phase difference detection circuit of 4th Embodiment, and the output signal at that time. It is a truth table which shows the pattern detected with the phase difference detection circuit of 4th Embodiment, and the output signal at that time.

Claims (12)

Reproducing means for reproducing an information signal from a recording medium;
Conversion means for sampling the reproduction signal output from the reproduction means in accordance with a clock and converting it into a digital signal of one sample and a plurality of bits;
It consists of continuous n samples (n is an integer of 2 or more) data obtained by performing partial response (1, 1) processing on the digital signal output from the conversion means and binary-determining the result. pattern detection means for detecting a specific pattern in n-bit data;
An extraction means for extracting a digital signal output from the conversion means according to the output of the pattern detection means, and outputting as a signal indicating a phase difference between the reproduction signal and the clock;
Clock generating means for outputting the clock according to the output of the extracting means;
An offset detection means for extracting a digital signal output from the conversion means according to the output of the pattern detection means, and detecting an offset with respect to a center level of the digital signal output from the conversion means based on the extraction result;
A reproducing apparatus comprising: adjusting means for adjusting a center level of the digital signal output from the converting means based on the output of the offset detecting means.   2. The reproducing apparatus according to claim 1, wherein the specific pattern is a pattern in which a zero cross point is included in a digital signal from the conversion unit corresponding to the n-bit data.   2. The reproducing apparatus according to claim 1, wherein the extraction unit inverts the sign of the extracted digital signal in accordance with the type of pattern detected by the pattern detection unit.   The specific pattern is a pattern in which a zero cross point is included in the digital signal from the conversion unit corresponding to the n-bit data, and the extraction unit is an eye pattern between samples before and after the zero cross in the digital signal. 4. The reproducing apparatus according to claim 3, wherein the extracted digital signal is inverted and output in accordance with the type of the specific pattern corresponding to the inclination.   The reproducing apparatus according to claim 1, wherein the pattern detecting unit detects a plurality of patterns as the specific pattern.   The offset detection unit has an integration circuit that integrates the digital signal extracted according to the output of the pattern detection unit, and outputs the integration result of the integration circuit to the adjustment unit as the offset information. The playback apparatus according to claim 1. Reproducing means for reproducing an information signal from a recording medium;
Conversion means for sampling the reproduction signal output from the reproduction means in accordance with a clock and converting it into a digital signal of one sample and a plurality of bits;
It consists of continuous n samples (n is an integer of 2 or more) data obtained by performing partial response (1, 1) processing on the digital signal output from the conversion means and binary-determining the result. pattern detection means for detecting a specific pattern in n-bit data;
The digital signal output from the conversion means is extracted according to the output of the pattern detection means, the value of the extracted digital signal is controlled according to the type of pattern detected by the pattern detection means, and the reproduction signal And extraction means for outputting as a signal indicating a phase difference between the clock and the clock;
A reproduction apparatus comprising: clock generation means for outputting the clock according to the output of the extraction means.   The extraction means outputs the value of the extracted digital signal as it is when the pattern detection means detects the first pattern, and the extraction means when the pattern detection means detects the second pattern 8. The reproducing apparatus according to claim 7, wherein the value of the digital signal is converted to m times and output.   The specific pattern is a pattern in which a zero cross point is included in a digital signal from the conversion unit corresponding to the n-bit data, and the first pattern and the second pattern are zero cross points in the digital signal. 9. The reproducing apparatus according to claim 7, wherein the eye patterns have different inclinations between the front and rear samples. Reproducing means for reproducing an information signal from a recording medium;
Conversion means for sampling the reproduction signal output from the reproduction means in accordance with a clock and converting it into a digital signal of one sample and a plurality of bits;
It consists of continuous n samples (n is an integer of 2 or more) data obtained by performing partial response (1, 1) processing on the digital signal output from the conversion means and binary-determining the result. pattern detection means for detecting a specific pattern in n-bit data;
Extraction means for extracting a digital signal output from the conversion means according to the output of the pattern detection means;
Phase lock detection means for detecting whether or not the reproduction signal and the clock are phase locked;
Phase difference detection means for outputting a phase error signal indicating a phase difference between the reproduction signal and the clock based on the digital signal extracted by the extraction means and the output of the phase lock detection means;
A reproduction apparatus comprising: clock generation means for outputting the clock according to a phase error signal output from the phase difference detection means.   The pattern detecting unit detects a plurality of the specific patterns including a first pattern and a second pattern, and the phase difference detecting unit is configured to detect the phase lock when the phase lock is not detected by the phase lock detecting unit. When the phase error signal is updated and output by any digital signal extracted by the extraction unit according to the first pattern and the second pattern, and the phase lock is detected by the phase lock detection unit 11. The reproducing apparatus according to claim 10, wherein the phase error signal is updated and output only by the digital signal extracted by the extracting means according to the first pattern. The information signal is modulated and recorded by a run length limited (1, 7) method, and the first pattern is a pattern in which the pulse width of the waveform of the reproduction signal is 1T (T is a sample period), 12. The reproduction apparatus according to claim 8, wherein the second pattern is a pattern in which a pulse width of the waveform of the reproduction signal is 2T.

Images