JP2006344255A - Phase error detecting circuit, phase locked loop circuit, and information reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase error detecting circuit and a phase locked loop circuit for obtaining a stable phase-locked characteristic even when a reproduction level of a minimum run length signal is extremely low, and to provide an information reproducing apparatus. <P>SOLUTION: A digital signal into which an analog input signal is sampled with a predetermined clock and A/D converted is input to the phase error detecting circuit 7. An amplitude of the digital signal at a detecting point is obtained by performing the third interpolation operation for four continuous samples of the input signal, and based on the polarity of the signal, a phase error signal of the sampling is output. In that case, the circuit is restrained to output the phase error signal only when the minimum run length of a sign string of the continuous samples is two or more. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information reproduction apparatus using a partial response maximum likelihood decoding (hereinafter abbreviated as “PRML”) method, and in particular, phase error detection for generating a stable synchronization signal in such an apparatus. The present invention relates to a circuit and a phase locked loop (hereinafter abbreviated as “PLL”) circuit using the circuit.

  2. Description of the Related Art Conventionally, for example, in an information reproducing apparatus represented by a hard disk device or an optical disk device, recording information digitized and recorded on a recording medium is input with a detection signal detected as an analog signal at a predetermined clock. Read by / D conversion. At this time, as known from the following Patent Document 1, the phase error of the read signal is detected according to the FDTS (Fixed Delay Tree Search) algorithm, and the oscillation frequency of the VCO (Voltage Controlled Oscillator) is controlled based on the phase error signal. By doing so, the clock phase is synchronized with the data.

Japanese Patent Laid-Open No. 2002-25201

  In the conventional technique described above, the phase error detector that controls the oscillation of the VCO detects a phase error between the sampling timing of the sampled signal and the correct sampling timing that is originally expected. However, sufficient consideration has not been given when the reproduction level of the minimum run length (minimum number of consecutive identical codes) signal is extremely low.

  That is, in the apparatus according to the above prior art, the phase error is calculated from the two sample values consecutive before and after the digitized readout signal by the primary interpolation method. In an optical disc apparatus that reproduces recorded information from an optical disc such as a BD (Blu-ray Disk) or an HDVD that is remarkably increased in density, the reproduction level of the minimum run length signal is extremely lowered. As a result, there is a problem in that an erroneous phase error signal is output in spite of the correct sampling phase, and the subsequent phase synchronization characteristics are deteriorated, thereby increasing the clock jitter.

  In the present invention, in view of the above-described problems in the prior art, in an information reproducing apparatus that performs processing by converting a detected analog signal into a digital signal at a predetermined sampling timing (reproduced clock), the reproduction level of the minimum run length signal is An object of the present invention is to provide a phase error detection circuit capable of obtaining a stable phase locking characteristic even in an extremely low case, a phase locked loop circuit using the same, and an information reproducing apparatus.

  The phase error detection circuit of the present invention samples an analog input signal with a predetermined clock, inputs an analog / digital converted digital signal, and inputs at least three or more consecutive samples of the input digital signal. The calculation means for calculating the amplitude value of the digital signal at the detection point by the second or higher order interpolation calculation, and the sampling of the analog input signal based on the amplitude value obtained by the calculation means and the polarity of the input digital signal. Output means for outputting a phase error signal. When the consecutive samples are a specific code string pattern, a phase error signal is output from the output means.

  Preferably, the calculation means calculates an amplitude value by cubic interpolation calculation for four consecutive samples of the digital input signal. Further, when the minimum run length of the code string of consecutive samples is 2 or more, a phase error signal is output from the output means.

  The phase-locked loop circuit according to the present invention includes an A / D converter for analog / digital conversion of an input signal with a predetermined clock, and an output signal from the A / D converter for detecting the phase error of the clock. A detection circuit; and oscillation means controlled by an output signal from the phase error detection circuit and outputting a clock.

  The information reproducing apparatus according to the present invention includes a reproducing means for reading digital information recorded on a recording medium, an A / D converting means for analog / digital conversion of an output signal of the reproducing means at a predetermined clock, and the A / D conversion. Receiving the output signal of the equalizing means for equalizing the output signal of the means, the decoding means for maximum likelihood decoding of the output signal of the equalizing means, and the output signal of the A / D conversion means or equalizing means, and detecting the phase error of the clock The phase error detection circuit includes an oscillation unit that is controlled by an output signal from the phase error detection circuit and outputs a clock.

  Furthermore, the phase error detection circuit according to the present invention calculates the amplitude value of the digital signal at the detection point by second-order or higher-order interpolation calculation for at least three or more consecutive samples of the input digital signal. A phase error output means for outputting a sampling phase error signal with respect to an analog input signal based on the amplitude value obtained by the computing means and the polarity of the input digital signal, and a digital value for inputting the amplitude value obtained by the computing means DC error output means for outputting a DC error signal included in the analog input signal based on the polarity of the signal. When the consecutive samples are a specific code string pattern, the phase error signal and the DC error signal are output from the phase error output means and the DC error output means.

  According to the present invention, stable phase synchronization characteristics can be obtained even when the reproduction level is extremely low, and excellent reproduction performance can be realized particularly for a high-density recording medium.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of an information reproducing apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an optical disk medium, 2 denotes an optical pickup circuit, 3 denotes an A / D converter, 4 denotes a PR equalization circuit, 5 denotes a maximum likelihood decoding circuit (Viterbi decoding circuit), 7 denotes a phase error detection circuit, Reference numeral 8 denotes a loop filter, 9 denotes a D / A converter, 10 denotes a voltage controlled oscillator (VCO), 11 denotes a pre-equalization circuit, 20 denotes a servo circuit, and 30 denotes a system control circuit.

  In the information reproducing apparatus, the optical pickup circuit 2 collects the laser light on the information recorded on the optical disk medium 1 and irradiates the information on the medium, and detects and reproduces the amount of reflected light or polarized light. At this time, the servo circuit 20 accurately follows the focus direction and the track direction. The reproduction signal read by the optical pickup circuit 2 is equalized by the pre-equalization circuit 11 and then digitized by the A / D converter 3. Then, the signal is equalized to a predetermined PR signal by the PR equalization circuit 4 and then decoded by the maximum likelihood decoding circuit 5. The system control circuit 30 controls these series of operations. The A / D converter 3, the PR equalization circuit 4, and the maximum likelihood decoding circuit 5 described above each synchronize data with a phase of a reproduction clock generated by a voltage controlled oscillator (VCO) 10 shown below. To process.

  The phase error detection circuit 7 receives the output signal from the A / D converter 3, detects the phase error, and outputs a signal. This phase error signal is input to the VCO 10 via the loop filter 8 and the D / A converter 9, thereby synchronizing the phase of the clock that is the output signal with the reproduction signal.

  FIG. 2 is a circuit configuration diagram showing an embodiment of the phase error detection circuit 7 in FIG. In FIG. 2, reference numerals 710, 720, and 730 are registers, 711 and 721 are binarization circuits, 712, 731, and 734 are adders, 713 is a modulo 2 adder, 714 and 716 are switch circuits, and 715 is polarity inversion. A circuit, 732 indicates a subtractor, and 733 indicates a 1/8 divider.

In the phase error detection circuit 7, the registers 710, 720, and 730 sequentially delay the input signal X _{n + 1} (τ) by one bit (one clock period) and delay signals X _n (τ), X _n−1 (τ ), X _n−2 (τ). Here, τ is the phase offset amount, and the subscript n indicates the sampling timing. The binarization circuits 711 and 721 respectively binarize the input signals X _n (τ) and X _n−1 (τ) into polarity codes “0” (indicating +) and “1” (indicating −). The signals Y _n and Y _n−1 are converted. In the actual binarization circuits 711 and 721, when the input signals X _n (τ) and X _n−1 (τ) are in 2 ′s complementary format, the most significant bit (MSB) is binary as it is. Since the digitized signals Y _n and Y _n−1 are obtained, the circuit configuration can be simplified.

Subsequently, the adder 712 adds the input signals X _n (τ) and X _n−1 (τ). On the other hand, the adder 713 of Modulo 2 adds the binarized signals Y _n and Y _n−1 modulo 2 and outputs a selection control signal Z _n . That is, the polarity change point of the input signal X _n (τ) (sign change point of the binarized signal Y _n ) is detected. Note that the actual modulo-2 adder 713 is configured by an exclusive OR (Ex-OR) circuit because the binarized signal Y _n (τ) corresponds to the codes “0” and “1”. The

On the other hand, the adder 731 adds the input signals X _{n + 1} (τ) and X _n−2 (τ), and the subtracter 732 subtracts the addition result of the adder 731 from the addition result of the adder 712. The 1/8 divider 733 divides the subtraction result of the subtractor 732 by 1/8, and the adder 734 adds the division result and the addition result of the adder 712.

The switch circuit 714 receives the selection control signal Z _n and outputs an error signal S _n (τ) expressed by the following equation (1).

The switch circuit 716 receives the binarized signal Y _n and outputs a phase error signal E _n (τ) expressed by the following equation (2).

  In FIG. 2, the process of dividing by “2” in the above equation (1) is omitted, but even when the process of dividing by “2” is omitted, the gain is only doubled. The behavior does not change. Further, since the 1/8 divider 733 can be realized by a 3-bit bit shift, a complicated divider is not necessary.

FIG. 3 is a waveform diagram comparing the detection methods of the error signal S _n (τ). In FIG. 3, (a) is a conventional interpolation method approximated by a linear function, and the sampling phase error with respect to the analog input signal is calculated based on an interpolation value obtained by linear approximation using two consecutive samples of the input signal. To detect. On the other hand, (b) is an interpolation method approximating with a cubic function according to the present embodiment, and sampling of the analog input signal is performed based on an interpolation value obtained by cubic approximation with four consecutive samples of the input signal. Detect phase error. As shown by the dashed-dotted curve in the figure, the symmetry of the waveform is broken at the position where the minimum run length transitions to the long run length (or the long run length to the minimum run length). Therefore, the error signal S _n (τ) can be detected with higher accuracy in the cubic interpolation method in (b) than in the linear interpolation method in (a). Therefore, the phase error signal E _n (τ) can be detected with high accuracy as well.

In the above example, interpolation by cubic approximation using four consecutive samples of the input signal has been described, but the present invention is not limited to this. For example, in FIG. 3B, the phase error is detected by interpolating by quadratic approximation (quadratic function) using three consecutive samples (X _{n + 1} , X _n , X _n-1 ) of the input signal. It is also possible to do. Furthermore, it is also possible to perform interpolation by approximation of higher order (for example, fourth order and fifth order function) using five or more samples.

Next, FIGS. 4 and 5 are diagrams for explaining the operation of the above-described phase error detection circuit 7 using the waveform of the analog input signal X _n (τ). In these figures, the symbol (●) indicates the actual sampling point, and the symbols (◯, Δ) indicate the detection points of the error signal S _n (τ) obtained by the phase error detection circuit 7.

FIG. 4 shows a case where the phase offset τ = 0. As can be seen from the figure, the error signal S _n (τ) in this case becomes 0 (zero) together with the phase error signal E _n (τ).

FIG. 5 shows a case where the phase offset τ> 0. The error signal S _n (τ) in this case has an amplitude corresponding to the slope of the input signal X _n (τ), and signals ± ε whose polarities are alternately inverted are output, and their average value is 0 (zero) ) On the other hand, the phase error signal E _n (τ) is output as E _n (τ) = ε regardless of the gradient of the input signal X _n (τ). In FIG. 5, the case where the phase offset τ> 0 has been described. However, the same applies to the case where the phase offset τ <0. In this case, S _n (τ) = 0 and E _n (τ) = ε <0. Become.

As described in detail above, according to the phase error detection circuit 7 of the present embodiment, the phase error signal E _n (τ) can be detected with high accuracy from the input signal X _n (τ) having the phase offset τ. Can do. As a result, in the phase locked loop circuit using the phase error detection circuit 7, even when the reproduction level of the minimum run length signal is low, the phase offset is reduced and stable phase synchronization performance is realized.

  Next, in the optical pickup circuit 2 that receives the reflected light or transmitted light from the surface of the optical disk, the input signal that is the detection signal due to the change with time of the phototransistor constituting the light receiving element or the fluctuation of the driving power supply. The DC level of fluctuates. Hereinafter, a preferred embodiment will be described when the DC level of such an input signal varies.

  FIG. 6 is a block diagram showing another embodiment of the information reproducing apparatus according to the present invention. In FIG. 6, reference numeral 6 indicates a DC feedback circuit, and the same components as those in FIG.

  In this embodiment, the phase error detection circuit 7 receives an output signal from the DC feedback circuit 6 and outputs a phase error signal and a DC error signal. The phase error signal is input to the VCO 10 via the loop filter 8 and the D / A converter 9, thereby synchronizing the clock phase with the reproduction signal. On the other hand, the DC error signal is input to the DC feedback circuit 6 and is used to remove a DC component from the output signal of the DC feedback circuit 6.

  FIG. 7 is a circuit configuration diagram showing an example of the DC feedback circuit 6 in FIG. In FIG. 7, reference numeral 601 indicates a subtracter, 602, 611, and 621 indicate registers, 603, 612, and 622 indicate adders, 613 and 623 indicate attenuators, and 614 indicates an amplitude limiter. The register 611 and the adder 612, and the register 621 and the adder 622 constitute an integrating circuit.

  The DC feedback circuit 6 is characterized in that it has two feedback loops. The first loop receives the main signal, which is the output of the DC feedback circuit 6, limits the amplitude by the amplitude limiter 614, and then feeds back as a DC level via the attenuator 613, the adder 612, and the register 611. It is a loop. The second loop is a loop that receives a DC error signal from the phase error detection circuit 7 and feeds it back as a DC level via an attenuator 623, an adder 622, and a register 621. The outputs from the first and second loops are added by the adder 603 and then input to the “−” input terminal of the subtractor 601, and thus input to the “+” input terminal of the subtractor 601. Subtract from the input signal.

  Although omitted in FIG. 7, the coefficient “ND” of the attenuator 613, the coefficient “NJ” of the attenuator 623, and the amplitude limit value of the amplitude limiter 614 in the DC feedback circuit 6 are the system control circuit 30 (see FIG. 1). Is set in response to a DC feedback control signal from

  Further, the DC feedback loop can be opened and closed by controlling the operation of the integrating circuit composed of the register 611 and the adder 612 and the integrating circuit composed of the register 621 and the adder 622. For example, when the servo operation is interrupted or the servo is disconnected, or when a track jump occurs, the DC feedback circuit 6 receives the DC feedback control signal from the system control circuit 30 and opens the DC feedback loop. As a result, it is possible to prevent the internal DC level from changing when an abnormal signal is input.

FIG. 8 is a circuit configuration diagram showing an example of the phase error detection circuit 7 in FIG. The difference from the phase error detection circuit 7 shown in the first embodiment (FIG. 2) is that the input signal is an input signal X _n (δ, τ) in which a DC offset δ and a phase offset τ are mixed, and the error signal S _The phase error signal E _n (δ, τ) and the DC error signal are output from _n (δ, τ).

FIG. 9 is a diagram illustrating the operation of the phase error detection circuit 7 described above using the waveform of the analog input signal X _n (δ, τ). Here, a case where the analog input signal is DC offset δ> 0 and phase offset τ = 0 is shown. In this figure, the symbol (●) indicates the actual sampling point, and the symbol (◯) indicates the detection point of the error signal S _n (δ, τ) obtained by the phase error detection circuit 7.

The DC error signal in this case is the value of S _n (δ, τ) at the detection point, which is δ shown in the figure. The phase error detection circuit 7 outputs an error signal proportional to the DC offset δ. On the other hand, as the phase error signal E _n (δ, τ) at this time, a signal having an amplitude corresponding to the gradient of the input signal X _n (δ, τ) and the polarity is alternately inverted, E _n (δ, τ) τ) = ± δ is output. Therefore, the average value is 0 (zero). Although the case of DC offset δ> 0 has been described in FIG. 9, the same applies to the case of DC offset δ <0, in which case S _n (δ, τ) = δ <0, and the phase error signal Is still E _n (δ, τ) = 0.

  Also in this embodiment, as in FIG. 3B, the sampling phase error (phase offset τ) with respect to the analog input signal is based on the third-order approximate interpolation method using four consecutive samples of the input signal. And fluctuations in the DC component of the analog input signal (DC offset δ). At this time, the DC error signal Sn (δ) and the phase error signal En (τ) are detected independently and accurately from the input signal Xn (δ, τ) in which the DC offset δ and the phase offset τ are mixed. be able to. As a result, in the phase-locked loop circuit using the phase error detection circuit 7, it is possible to reduce not only the phase offset but also the DC offset by forming an independent DC feedback loop therein.

In the above example, interpolation by cubic approximation using four consecutive samples of the input signal has been described, but the present invention is not limited to this. For example, in FIG. 3B, the phase error is detected by interpolating by quadratic approximation (quadratic function) using three consecutive samples (X _{n + 1} , X _n , X _n-1 ) of the input signal. It is also possible to do. Furthermore, it is also possible to perform interpolation by approximation of higher order (for example, fourth order and fifth order function) using five or more samples.

  In this embodiment, the output signal of the DC feedback circuit 6 itself, that is, the input signal of the PR equalization circuit 4 is used as the DC feedback main signal, but the output signal of the PR equalization circuit 4 may be used. Moreover, in the said Example, although the pre-equalization circuit 20 was arrange | positioned in the front | former stage of the A / D converter 3, this invention is not limited to this structure. For example, the pre-equalization circuit 20 may be arranged at the subsequent stage of the A / D converter 3. In the following, other embodiments adopting such a configuration will be described.

  FIG. 10 is a block diagram showing still another embodiment of the information reproducing apparatus according to the present invention. This embodiment differs from the second embodiment (FIG. 6) in that the pre-equalization circuit 20 is deleted and the main signal and the input signal of the phase error detection circuit 7 are acquired from the output signal of the PR equalization circuit 4. This is the configuration. The phase error detection and DC feedback operation are the same as in the second embodiment. This eliminates the need for the analog processing circuit called the pre-equalization circuit 20 and has the effect of simplifying the circuit configuration.

  FIG. 11 is a block diagram showing still another embodiment of the information reproducing apparatus according to the present invention. In FIG. 11, reference numeral 12 denotes a switch circuit, and the same components as those in FIGS. 6 and 10 are denoted by the same reference numerals. The feature of this embodiment is that the switch circuit 12 is controlled by the system control circuit 30 so that the input signal of the phase error detection circuit 7 can be switched.

  According to the present embodiment, the input signal of the phase error detection circuit 7 is input to the PR equalization circuit 4 at the time of initial retraction operation, or at the time of re-retraction operation such as when the servo is disconnected or track jump is performed. Obtained from the signal to shorten the time to synchronization establishment and recovery. Thereafter, the phase error detection circuit 7 can be switched so as to obtain the input signal from the output signal of the PR equalization circuit 4 to stabilize the phase synchronization performance. Thus, by switching the input signal of the phase error detection circuit 7, it is possible to achieve both reduction of the synchronization time and stability of the synchronization performance.

  FIG. 12 is a block diagram showing another embodiment of the phase error detection circuit 7 according to the present invention. 12, 741 and 751 are binarization circuits, 743 and 753 are Modulo 2 adders, 744 and 754 are sign inversion circuits, and 745 is a logical product circuit, and the other parts are the same as those in FIGS. The same code | symbol is attached | subjected to the thing.

The feature of this embodiment is that four consecutive sample codes (binary signals) Y _{n + 1} , Y _n , Y _n−1 , Y _n−2 are in a specific pattern, for example, “0011” or “1100”. Only in this case, the phase error signal E _n (τ) and the DC error signal S _n (δ) are output. That is, the run length restriction is applied that the phase error detection of this embodiment is applied only when the run length at the sign inversion position is 2T-2T or more. Due to this limitation, for example, it is not applied to a code string including a minimum run length 1T such as “1011” or “0010”.

  If the minimum run length is too small, the reproduction level is extremely lowered, and it becomes difficult to detect the phase error even with the detection method of this embodiment. In such a case, there is a possibility that the subsequent synchronization processing may be deteriorated by an erroneous phase error signal or DC error signal, and this embodiment can avoid it.

  Conventionally, when a code error occurs due to noise or the like, an erroneous phase error signal is output, resulting in deterioration of synchronization characteristics. However, due to the run length limitation of this embodiment, an erroneous phase error signal is output. Since the output can be prevented, the synchronization characteristic can be stabilized.

  FIG. 13 is a block diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention. In FIG. 13, 760 is a register, 763 is a Modulo 2 adder, 764 is a sign inversion circuit, 765 is a switch circuit, and the same components as those in FIGS. 2, 8 and 12 are given the same reference numerals. is doing.

The feature of the present embodiment is that a code (binarized signal) Y _{n + 1} , Y _n , Y _n−1 , Y _n−2 , Y _n−3 of a continuous five samples is a specific pattern, for example “00011”. Alternatively, only in the case of “11100”, the phase error signal E _n (τ) and the DC error signal S _n (δ) are output. That is, a run length restriction of 3T-2T or more is applied. Further, the configuration can be switched to the 2T-2T run length limitation described in the fifth embodiment (FIG. 12).

  This embodiment is effective in sharing the system with the minimum run length limited to 2T and the system limited to 3T.

  The run-length restriction of this embodiment is an example, and the run-length value to be restricted can be appropriately set according to the signal format employed.

  As described in detail above, according to the phase error detection circuit and the phase-locked loop circuit of the present invention, and the information reproducing apparatus using the same, for example, an optical disk with a high density such as BD and HDVD. When reproducing recorded information from a recording medium, stable phase synchronization characteristics can be obtained even when the reproduction level of the minimum run-length signal is extremely low, and this contributes particularly to improving the reproduction performance of a high-density recording medium.

  Further, according to the phase error detection circuit and the phase locked loop circuit according to the present invention, and the information reproducing apparatus using the same, stable phase synchronization can be achieved without being affected by the DC level fluctuation or asymmetry of the analog input signal. The characteristic is obtained, and similarly contributes to the improvement of the reproduction performance of the high-density recording medium.

  Each embodiment of the present invention described above is an example for explaining the present invention, and therefore, the scope of the present invention is not limited to the embodiment. Further, those skilled in the art can implement the present invention in various other modes without departing from the gist of the present invention.

1 is a configuration diagram showing an embodiment of an information reproducing apparatus according to the present invention (Embodiment 1). FIG. FIG. 3 is a circuit configuration diagram illustrating an example of a phase error detection circuit according to the first embodiment. It is a figure explaining the error signal detection method in Example 1. FIG. FIG. 6 is a waveform diagram illustrating an operation of the phase error detection circuit according to the first embodiment. FIG. 6 is a waveform diagram illustrating an operation of the phase error detection circuit according to the first embodiment. It is a block diagram which shows the other Example of the information reproduction apparatus by this invention (Example 2). FIG. 6 is a circuit configuration diagram illustrating an example of a DC feedback circuit according to a second embodiment. FIG. 6 is a circuit configuration diagram illustrating an example of a phase error detection circuit according to a second embodiment. FIG. 6 is a waveform diagram showing the operation of the phase error detection circuit in the second embodiment. It is a block diagram which shows the further another Example of the information reproduction apparatus by this invention (Example 3). It is a block diagram which shows the further another Example of the information reproduction apparatus by this invention (Example 4). FIG. 10 is a configuration diagram showing another embodiment of the phase error detection circuit according to the present invention (Embodiment 5). FIG. 10 is a configuration diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention (Embodiment 6).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Optical disk medium, 2 ... Optical pick-up circuit, 3 ... A / D converter, 4 ... PR equalization circuit, 5 ... Maximum likelihood decoding circuit, 6 ... DC feedback circuit, 7 ... Phase error detection circuit, 8 ... Loop filter , 9 ... D / A converter, 10 ... Voltage controlled oscillator (VCO), 11 ... Pre-equalization circuit, 12 ... Switch circuit, 20 ... Servo circuit, 30 ... System control circuit, 601 ... Subtractor, 602, 611 , 621 ... Register, 603, 612, 622 ... Adder, 613, 623 ... Attenuator, 614 ... Amplitude limiter, 710, 720, 730, 760 ... Register, 711, 721, 741, 751, 761 ... Binarization Circuit, 712, 731, 734 ... adder, 713, 743, 753, 763 ... Modulo 2 adder, 714, 716, 765 ... switch circuit, 715 ... polarity inversion circuit, 732 ... subtraction , 733 ... divider, 744,754,764 ... sign inverting circuit, 745 ... AND circuit.

Claims (10)

In a phase error detection circuit that samples an analog input signal with a predetermined clock, inputs an analog / digital converted digital signal, and detects a phase error of the clock,
Arithmetic means for calculating an amplitude value of the digital signal at the detection point by second-order or higher-order interpolation calculation for at least three or more consecutive samples of the input digital signal;
Output means for outputting a sampling phase error signal with respect to the analog input signal based on the amplitude value obtained by the arithmetic means and the polarity of the input digital signal;
A phase error detection circuit which outputs a phase error signal from the output means when the continuous sample is a specific code string pattern. The phase error detection circuit according to claim 1,
The phase error detection circuit characterized in that the calculation means calculates an amplitude value by cubic interpolation calculation for four consecutive samples of the input digital signal. In the phase error detection circuit according to claim 1 or 2,
A phase error signal is output from the output means when the minimum run length of the code sequence of the consecutive samples is 2 or more. A phase-locked loop circuit using the phase error detection circuit according to claim 1,
A / D conversion means for analog / digital conversion of an input signal with a predetermined clock;
Receiving the output signal of the A / D conversion means and detecting the phase error of the clock;
A phase-locked loop circuit comprising: oscillation means controlled by an output signal from the phase error detection circuit and outputting the clock. An information reproducing apparatus using the phase error detection circuit according to any one of claims 1 to 3,
Reproducing means for reading digital information recorded on the recording medium;
A / D conversion means for analog / digital conversion of the output signal of the reproduction means with a predetermined clock;
Equalization means for equalizing the output signal of the A / D conversion means;
Decoding means for maximum likelihood decoding the output signal of the equalization means;
Receiving the output signal of the A / D conversion means or the equalization means, and detecting the phase error of the clock;
An information reproducing apparatus comprising: oscillation means controlled by an output signal from the phase error detection circuit and outputting the clock. In a phase error detection circuit that samples an analog input signal with a predetermined clock, inputs an analog / digital converted digital signal, and detects a phase error of the clock,
Arithmetic means for calculating an amplitude value of the digital signal at a detection point by second-order or higher-order interpolation calculation for at least three or more consecutive samples of the input digital signal;
Phase error output means for outputting a sampling phase error signal for the analog input signal based on the amplitude value obtained by the calculation means and the polarity of the input digital signal;
DC error output means for outputting a DC error signal included in the analog input signal based on the amplitude value obtained by the calculation means and the polarity of the input digital signal,
A phase error detection circuit for outputting a phase error signal and a DC error signal from the phase error output means and the DC error output means when the consecutive samples are a specific code string pattern. In the phase error detection circuit according to claim 6,
The phase error detection circuit characterized in that the calculation means calculates an amplitude value by cubic interpolation calculation for four consecutive samples of the input digital signal. In the phase error detection circuit according to claim 6 or 7,
A phase error detection circuit that outputs a phase error signal and a DC error signal from the phase error output means and the DC error output means when the minimum run length of the code sequence of the consecutive samples is 2 or more. A phase-locked loop circuit using the phase error detection circuit according to any one of claims 6 to 8,
A / D conversion means for analog / digital conversion of an analog input signal with a predetermined clock;
DC level control means for controlling the DC level of the output signal of the A / D conversion means;
Receiving the output signal of the DC level control means and detecting the phase error of the clock and the DC error included in the analog input signal;
Controlled by a phase error signal from the phase error detection circuit, and includes an oscillation means for outputting the clock,
The phase locked loop circuit, wherein the DC level control means is controlled by a DC error signal from the phase error detection circuit. An information reproducing apparatus using the phase error detection circuit according to any one of claims 6 to 8,
Reproducing means for reading digital information recorded on the recording medium;
A / D conversion means for analog / digital conversion of the output signal of the reproduction means with a predetermined clock;
DC level control means for controlling the DC level of the output signal of the A / D conversion means;
Equalizing means for equalizing the output signal of the DC level control means;
Decoding means for maximum likelihood decoding the output signal of the equalization means;
Receiving the output signal of the DC level control means or the equalization means, and detecting the phase error of the clock and the DC error included in the analog input signal;
Controlled by a phase error signal from the phase error detection circuit, and includes an oscillation means for outputting the clock,
The information reproducing apparatus according to claim 1, wherein the DC level control means is controlled by a DC error signal from the phase error detection circuit.

Images