JP4603469B2 - Phase error detection circuit, phase locked loop circuit, and information reproducing apparatus - Google Patents

Description

  The present invention relates to an information reproducing apparatus using a partial response maximum likelihood decoding (PRML) system, and more particularly to a phase error detection circuit for generating a stable synchronizing signal in such an apparatus and a phase locked loop (PLL) circuit using the same. About.

  2. Description of the Related Art Conventionally, in an information reproducing apparatus typified by a hard disk device or an optical disk device, when reproducing digitally recorded information on a recording medium, a signal read as an analog signal is sampled with a predetermined clock, and A / D An information signal is obtained by conversion. At that time, as known from, for example, Patent Document 1, the phase error of the sampled signal is detected according to an FDTS (Fixed Delay Tree Search) algorithm, and the oscillation frequency of the voltage controlled oscillator (VCO) is controlled based on the phase error signal. Thus, the clock phase is corrected so as to be synchronized with the read data. Here, the phase error detector detects a phase error between the timing at which the read signal is sampled and the correct sampling timing that is originally expected.

Japanese Patent Laid-Open No. 2002-25201 (page 5, FIG. 2)

  In the above prior art, the phase error detector that controls the oscillation of the VCO uses an algorithm that calculates the phase error from the absolute value of the read signal level sampled at the reference clock position in order to detect the phase error of the sampling timing. is doing. That is, the phase error is calculated by comparing the sampled signal level (the signal level is zero if there is no phase error) with the amplitude level (maximum value of the envelope) of the read signal. Thus, in the method based on the amplitude level of the read signal, the detection sensitivity of the phase error depends on the amplitude level of the read signal. Conventionally, however, it is assumed that the amplitude level of the read signal is constant, and no consideration is given to fluctuations in the amplitude level. Therefore, when the amplitude level fluctuates, there is a problem that the calculated value of the phase error fluctuates and the phase synchronization control deteriorates.

  For example, in an optical disc apparatus, when reading information from an optical disc, the surface of the optical disc is irradiated with light emitted from a light source such as an LED, and the reflected light is detected by a pickup composed of a light receiving element such as a phototransistor. . At this time, the amplitude level (maximum value) of the signal detected by the pickup may fluctuate due to changes in the optical system over time or fluctuations in the power supply level for driving the optical system. As a result, the accuracy of phase error detection deteriorates, and the control characteristics of the oscillation frequency of the VCO and the phase synchronization characteristics in the PLL circuit deteriorate.

  In view of the above-described problems in the prior art, the present invention is a phase error detection circuit capable of accurately detecting a phase error even when the amplitude level of a read signal fluctuates and thereby realizing a stable phase synchronization characteristic. An object of the present invention is to provide a phase locked loop circuit and an information reproducing apparatus.

The phase error detection circuit of the present invention samples an input signal with a predetermined clock and detects a phase error of the clock from the sampled signal level. The phase error detection circuit of the present invention includes two sampling positions n, (n− For the signal levels X _n and X _{n−1 in 1} ) , an arithmetic unit for calculating a ratio C _n (= (A _n / 2) / B _n ) between the sum _An and the difference B _n is provided. The calculation result C _n of the calculator at the sampling position where the polarities of _n and X _n−1 change is output as a phase error signal.

Further the phase error detection circuit, the signal level X _n, the value of the computed A _n of the arithmetic unit in the sampling position at which the polarity of the X _n-1 is changed, and outputs it as DC error signal of the input signal.

The phase error detection circuit according to the present invention is a phase error detection circuit that samples an input signal with a predetermined clock and detects a phase error of the clock from the sampled signal level, and has two signal levels X _n and X _{n−. For} each combination of ₁ , there is provided a memory for storing in advance a calculation value of a ratio C _n (= (A _n / 2) / B _n ) of the sum _An and the difference B _n , and two consecutive samplings of the input signal When the polarities of the signal levels X _n and X _n−1 change at the positions n and (n−1), the calculated value of C _n for the combination of the signal levels X _n and X _n−1 stored in the memory is used as the phase error signal. Output as.

  The phase-locked loop circuit of the present invention includes an A / D converter that performs analog / digital conversion on an input signal using a predetermined clock, and the phase error detection that receives an output signal of the A / D converter and detects a phase error of the clock. A circuit and an oscillator controlled by a phase error signal from a phase error detection circuit and outputting a clock.

  The phase-locked loop circuit of the present invention includes an A / D converter that performs analog / digital conversion of an input signal with a predetermined clock, a DC feedback circuit that removes a DC level of an output signal of the A / D converter, and DC feedback. The above-mentioned phase error detection circuit that receives an output signal of the circuit and detects a phase error and a DC error, and an oscillator that outputs a clock and is controlled by the phase error signal from the phase error detection circuit. The DC level is removed by the DC error signal from the error detection circuit.

  An information reproducing apparatus according to the present invention includes a reading unit that reads digital information recorded on a recording medium, an A / D converter that performs analog / digital conversion on an output signal of the reading unit with a predetermined clock, and an A / D converter. An equalizer that equalizes an output signal, a decoder that performs maximum likelihood decoding of the output signal of the equalizer, an A / D converter or an equalizer output signal, and detects the phase error of the clock An error detection circuit; and an oscillator that is controlled by a phase error signal from the phase error detection circuit and outputs a clock.

  An information reproducing apparatus according to the present invention includes a reading unit that reads digital information recorded on a recording medium, an A / D converter that performs analog / digital conversion on an output signal of the reading unit with a predetermined clock, and an A / D converter. DC feedback circuit that removes the DC level of the output signal, an equalizer that equalizes the output signal of the DC feedback circuit, a decoder that performs maximum likelihood decoding of the output signal of the equalizer, and a DC feedback circuit or equalization A phase feedback detection circuit for detecting a phase error and a DC error and an oscillator for outputting a clock controlled by the phase error signal from the phase error detection circuit. The DC level is removed by the DC error signal from the error detection circuit.

  According to the present invention, the phase synchronization characteristic is stabilized with respect to level fluctuations during reproduction, and reproduction quality can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of an information reproducing apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an optical disk medium, 2 denotes an optical pickup circuit, 3 denotes an A / D converter, 4 denotes a partial response (PR) equalization circuit, 5 denotes a maximum likelihood decoding circuit (Viterbi decoding circuit), and 7 denotes Phase error detection circuit, 8 is a loop filter, 9 is a D / A converter, 10 is a voltage controlled oscillator (VCO), 11 is a pre-equalization circuit, 20 is a servo circuit, 30 is a system control circuit, and 40 is a jitter evaluation. Each circuit is shown.

  The optical pickup circuit 2 collects laser light and irradiates the information recorded on the optical disk medium 1 onto the medium, and reproduces the information by detecting the amount of reflected light or the amount of deflection. At this time, the servo circuit 20 causes the laser light spot to accurately follow the focus direction and the track direction. The reproduction signal read by the optical pickup circuit 2 is equalized by the pre-equalization circuit 11 and then analog / digital converted by the A / D converter 3. Next, the signal is equalized to a predetermined PR signal by the PR equalization circuit 4 and decoded by the maximum likelihood decoding circuit 5. The system control circuit 30 controls these series of operations. The A / D converter 3, the PR equalization circuit 4, and the maximum likelihood decoding circuit 5 described above each synchronize data with a phase of a reproduction clock generated by a voltage controlled oscillator (VCO) 10 shown below. To process.

Next, the configuration of the phase locked loop circuit will be described. The phase error detection circuit 7 receives the output signal from the A / D converter 3 and outputs a normalized phase error signal T _n (normalized with the clock period T) indicating an accurate phase error on the time axis. The normalized phase error signal T _n is input to the VCO 10 via the loop filter 8 and the D / A converter 9 and controls the oscillation frequency that is the output thereof. As a result, the phase of the reproduction clock can be synchronized with the reproduction signal from the optical pickup circuit 2.

Further, the jitter evaluating circuit 40 receives the normalized phase error signal T _n from the phase error detecting circuit 7, by statistical treatment, an average value and variance of the phase error. The obtained dispersion value can be used for jitter evaluation of the optical disc medium 1. Furthermore, since the average value of each obtained transient (for example, a transient from 3T space to 3T mark, 4T mark to 4T space, etc.) represents a recording shift, it can also be used for adjusting the recording strategy. . As described above, in this embodiment, the normalized phase error signal is applied not only to the phase adjustment of the reproduction clock but also to the evaluation of the reproduction quality and the setting of the recording strategy, thereby simplifying the configuration of the entire apparatus. Can do.

  FIG. 2 is a circuit configuration diagram showing an embodiment of the phase error detection circuit 7 in FIG. Here, reference numeral 720 is a register, 711 and 721 are binarization circuits, 712 is an adder, 713 is an adder of modulo 2, 714 is a switch circuit, 722 is a subtractor, and 724 is a normalization circuit (divider). Each is shown.

The input signal is represented by X _n (τ), and τ indicates the phase shift (phase offset). The register 720 delays the input signal X _n (τ) by one sampling period (one clock period T), and signals X _n (τ), X _n-1 (at two consecutive sampling positions n, (n−1). τ) is output. The binarization circuits 711 and 721 convert the input signal X _n (τ) and the delay signal X _n−1 (τ) into binary signals Y of polarity codes “0 (+)” and “1 (−)”, respectively. _n , Y _n-1 . In the actual binarization circuits 711 and 721, when the input signal X _n (τ) and the delay signal X _n−1 (τ) are in 2 ′s complementary format, the most significant bit (MSB) is 2 as it is. Since the value signals Y _n and Y _n−1 are obtained, the circuit configuration can be simplified.

Subsequently, the adder 712 adds the input signal X _n (τ) and the delay signal X _n−1 (τ), and outputs a sum signal A _n (τ). On the other hand, the subtractor 722 subtracts the delayed signal _{X n-1 (τ)} from the input signal _{X n} (tau), and outputs a difference signal _{B n (τ).} The normalization circuit 724 receives the sum signal A _n (τ) and the difference signal B _n (τ), and outputs a quotient signal C _n (τ) represented by the following equation (1).
C _n (τ) = A _n (τ) / 2 / B _n (τ)
= { _Xn (τ) + _Xn-1 (τ)} / 2 / { _Xn (τ) -Xn _-1 (τ)} (1)

On the other hand, the adder 713 of Modulo 2 adds the binarized signals Y _n and Y _n−1 modulo 2 and outputs the selection control signal Z _n . That is, the polarity change of the input signal X _n (τ) and the delay signal X _n−1 (τ) (sign change of the binarized signals Y _n and Y _n−1 ) is detected, and the code “1” is detected at the change point. Otherwise, the code “0” is output. Incidentally, the adder 713 of the actual modulo 2, the sign "0" binary signal Y _n, because it corresponds to "1", and exclusive OR (Ex-OR) circuit.

The switch circuit 714 receives the selection control signal Z _n and switches and outputs the normalized phase error signal T _n (τ) expressed by the following equation (2).
T _n (τ) = C _n (τ) (when Z _n = 1, Y _n ≠ Y _n−1 )
= 0 (in the case of Z _n = 0, Y _n = Y _n-1 ) (2)
Thus, when the sampling position is the polarity change point (selection control signal Z _n = 1), the calculation result of the above expression (1) is output, but the calculation at other positions (Z _n = 0). The result shows no phase error and is not output.

  Note that the configuration of the arithmetic circuit in FIG. 2 is an example, and any arithmetic circuit that can execute the arithmetic expressions (1) and (2) is not limited to this and is all effective.

FIG. 3 is a diagram for geometrically explaining the calculation method of the above-described normalized phase error signal T _n (τ) using signal waveforms. The vertical axis represents the signal level, the horizontal axis represents time, and the input waveform _Xn has a timing position t / T determined from the clock T = −5 / 2, −3/2, −1/2,. Sampling. Among them, the adjacent position where the polarity of the signal level changes is t / T = −1 / 2, 1/2, and the signal levels X _n and X _n−1 are indicated by a symbol (●). The level difference between the two values _Xn and _Xn-1 is represented by the difference signal _Bn . The waveform between _Xn and _Xn-1 is approximated by a straight line (linear function), and the level average of two values _Xn and _Xn-1 is indicated by a symbol (O), and the level is the sum signal A _n / 2. The symbol (◇) is the crossing position (position where the level is zero) between the approximate straight line and the horizontal axis, and the distance from the origin indicates the phase offset τ itself. And it can be understood geometrically that this phase offset τ is obtained by the following equation (3) from the ratio of A _n / 2 and B _n .
τ / T = −A _n / 2 / B _n
= −1 / 2 * (X _n + X _n−1 ) / (X _n −X _n−1 ) (3)

Here, consider a case where the amplitude level (maximum value of the envelope) H of the input signal fluctuates. As the amplitude level H varies, the signal levels X _n and X _n−1 and the operation values A _n and B _n vary at the same rate. However, in this embodiment, since the phase offset τ is obtained from the ratio thereof as shown in the equation (3), the fluctuation is cancelled. Therefore, even if the amplitude level H varies, the calculated value of the phase offset τ does not vary.

The relationship between the normalized phase error signal T _n (τ) obtained by the phase error detection circuit 7 described above and the phase offset τ is expressed by equation (4).
T _n (τ) = − τ / T (4)

FIG. 4 is a diagram showing the phase error detection characteristics of the phase error detection circuit 7 expressed by equation (4). The horizontal axis is the phase offset τ, and the vertical axis is the normalized phase error signal T _n (τ), showing the relationship between the two. τ> 0 indicates that the clock phase is advanced, and τ <0 indicates that the clock phase is delayed. If the phase offset exceeds the period T, the normalized phase error signal T _n (τ) repeats periodically between 1/2 and −1/2. As described above, the phase error detection circuit 7 according to the present embodiment can detect the phase error on the time axis with high accuracy without being affected even if the amplitude level of the input signal varies.

FIG. 5 is a circuit diagram showing another embodiment of the phase error detection circuit 7 according to the present invention. Here, the register 720 delays the input signal X _n (τ) by one sampling period (one clock period T). Reference numeral 750 denotes a read only memory (ROM). In this embodiment, the calculation results of the expressions (1) and (2) executed in the first embodiment are obtained in advance and stored in the ROM 750. That is, various combinations of the input levels X _n and X _n−1 and the value of T _{n corresponding} thereto are stored as a table. Then, the value of T _n corresponding to the levels X _n and X _{n−1 of} the input signal may be read and output. In the present embodiment, time-consuming arithmetic processing such as division processing is not necessary, and there is an advantage that the processing speed is increased.

FIG. 6 is a circuit diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention. Here, reference numeral 719 indicates a register, and other elements common to those in FIG. The register 719 holds the operation result T _n−1 (τ) immediately before one clock. The switch circuit 714 receives the selection control signal Z _n, and outputs the switching following a (5) the normalized phase error signal T _{n (tau)} of the formula.
T _n (τ) = C _n (τ) (when Z _n = 1, Y _n ≠ Y _n−1 )
= T _n-1 (τ) (in the case of Z _n = 0, Y _n = Y _n-1 ) (5)

In the first embodiment, as shown in the equation (2), the output at the position other than the polarity change point (selection control signal Z _n = 0) is set to zero, whereas in this embodiment, the output other than the polarity change point is set. The operation result T _n-1 (τ) immediately before one clock is output at the position. As a result, the value of C _n (τ) obtained at the polarity change point is repeatedly output until the next polarity change point. In the first embodiment, the clock phase correction operation is concentrated on the polarity change points. However, in this embodiment, the correction is performed in a distributed manner, so that more stable phase synchronization control can be expected.

  Next, the input signal from the optical pickup circuit 2 described above may vary not only in the amplitude level but also in the DC (direct current) level. An embodiment of the present invention corresponding to this DC level fluctuation will be described below.

  FIG. 7 is a block diagram showing another embodiment of the information reproducing apparatus according to the present invention. Here, reference numeral 6 indicates a DC feedback circuit, and other elements common to those in FIG.

A signal read from the optical disk medium 1 is digitized by the A / D converter 3 and then added with a function of removing a DC component by the DC feedback circuit 6. Phase error detecting circuit 7 receives the output signal from the DC feedback circuit 6, and outputs a normalized phase error signal T _n and the DC error signal S _n. To normalized phase error signal T _n is VCO 10, it controls so as to synchronize the phase of the recovered clock to the reproduction signal. Meanwhile DC error signal S _n, compared DC feedback circuit 6, controls to output the signal to remove the DC component.

  FIG. 8 is a diagram showing an example of the circuit configuration of the DC feedback circuit 6 in FIG. Here, reference numeral 601 indicates a subtracter, 602 and 608 indicate registers, 603 indicates an amplitude limiter, 604 and 605 indicate attenuators, and 606 and 607 indicate adders. Here, the adder 607 and the register 608 constitute an integrating circuit.

The DC feedback circuit 6 includes two feedback loops. The first loop receives the output signal of the DC feedback circuit 6 itself, limits the amplitude by the amplitude limiter 603, and further feeds back as a DC level via the attenuator 604, the adders 606 and 607, and the register 608. It is a loop. The second loop receives a DC error signal _{S n} from the phase error detecting circuit 7 of FIG. 7, an attenuator 605, an adder 606 and 607, through register 608, a loop for feeding back a DC level is there. The outputs from the first loop and the second loop are added by the adder 606, integrated by the adder 607 and the register 608, and then input from the input signal input to the DC by the subtractor 601. Subtract components.

  Although not shown here, the coefficients “ND” and “NJ” of the attenuators 604 and 605 constituting the DC feedback circuit 6 and the amplitude limit value of the amplitude limiter 603 are obtained from the system control circuit 30 of FIG. Is set by the DC feedback control signal.

  Further, by controlling the operation of the integrating circuit composed of the adder 607 and the register 608, the DC feedback loop can be opened and closed. For example, when the servo operation is out of the way or when the servo is off, or when a track jump occurs, the DC feedback circuit 6 receives the DC feedback control signal from the system control circuit 30 and opens the DC feedback loop. As a result, it is possible to prevent the internal DC level from being disturbed by an abnormal signal input.

  In this embodiment, the output signal of the DC feedback circuit 6 itself, that is, the input signal of the PR equalization circuit 4 is used as the main signal for DC feedback. However, the output signal may be used. Further, in the present embodiment, the example in which the pre-equalization circuit 11 is arranged at the front stage of the A / D converter 3 is shown, but the present invention is not limited to this configuration. May be arranged after the A / D converter 3.

  FIG. 9 is a circuit configuration diagram showing one embodiment of the phase error detection circuit 7 in FIG. Here, the same reference numerals are given to the same elements as those in FIG. 2, and the description thereof will be omitted.

An input signal is represented by X _n (σ, τ), σ is a DC component (DC offset), and τ is a phase shift (phase offset). The adder 712 adds the input signal X _n (σ, τ) and the delayed signal X _n−1 (σ, τ), and outputs a sum signal A _n (σ, τ). The switch circuit 714 receives the selection control signal Z _n and outputs a DC error signal S _n (σ) expressed by the following equation (6).
S _n (σ) = A _n (σ, τ)
= X _n (σ, τ) + X _n−1 (σ, τ) (when Z _n = 1, Y _n ≠ Y _n−1 )
= 0 (in the case of Z _n = 0, Y _n = Y _n-1 ) (6)

The exact value of the DC error signal is A _n (σ, τ) / 2, but the division of “2” is omitted in the equation (6). In that case, the basic operation does not change if the gain factor of the DC feedback loop is corrected by a factor of 1/2.

On the other hand, the subtractor 722 subtracts the delayed signal X _n−1 (σ, τ) from the input signal X _n (σ, τ) and outputs a difference signal B _n (τ). The normalization circuit 724 receives the DC error signal S _n (σ) of the above equation (6) and outputs a normalized phase error signal T _n (τ) represented by the following equation (7).
T _n (τ) = S _n (σ) / 2 / B _n (σ, τ)
= { _Xn ([sigma], [tau]) + _Xn-1 ([sigma], [tau])} / 2 / { _Xn ([sigma], [tau])- _Xn-1 ([sigma], [tau])}
(When Z _n = 1, Y _n ≠ Y _n−1 )
T _n (τ) = 0 (in the case of Z _n = 0, Y _n = Y _n−1 ) (7)

10, 11, 12, and 13 geometrically illustrate the calculation method of the DC error signal S _n (σ) and the normalized phase error signal T _n (τ) using the signal waveform. It is a figure explaining. When a signal is read from the optical disk medium, the amplitude and DC level of the input signal X _n (σ, τ) may fluctuate due to changes in the diameter of the optical system or power supply. As a result, a DC offset σ and a phase offset τ are generated. In each figure, a symbol (●) indicates a sampling point X _n (σ, τ) determined by a clock. The symbol (◯) is the average level of the sampling points X _n and X _n−1 (or X _n ′ and X _n−1 ′), indicates the DC offset σ, and is obtained by the calculation of the above equation (6). This corresponds to the DC error signal S _n (σ) / 2. The symbol (◇) is a point that intersects the horizontal axis (signal level = 0) when linear approximation is performed between sampling points _Xn and _Xn-1 (or _Xn 'and _Xn-1 '). , Indicates the phase offset τ, and corresponds to the normalized phase error signal T _n (τ) obtained by the calculation of the above equation (7).

FIG. 10 shows a case where the DC offset σ = 0 and the phase offset τ = 0. In this case, the positions of X _n and X _n−1 are symmetrical with respect to the origin (X = 0, t = 0), and the average level DC error signal S _n (σ) and the normalized phase error signal T _n (τ). Both are 0.

FIG. 11 shows a case where the DC offset σ ≠ 0 and the phase offset τ = 0. In this case, the DC error signal S _n (σ) corresponds to the average level of X _n and X _n−1 (or X _n ′ and X _n−1 ′), and S _n (σ) = 2σ. The phase error detection circuit 7 outputs an error signal S _n (σ) proportional to the DC offset σ. On the other hand, the normalized phase error signal T _n (τ) corresponds to an intersection corresponding to two slopes of X _n and X _n−1 and X _n ′ and X _n−1 ′, and the intersection position is the origin. It is at a position ± ε symmetrical with respect to (t = 0). That is, the normalized phase error signal T _n (τ) is output as a signal of ± ε / T whose polarity is alternately inverted according to the slope of the input signal X _n , but the time average value thereof is T _n (τ). = 0, corresponding to a phase offset τ = 0.

FIG. 12 shows a case where DC offset σ = 0 and phase offset τ ≠ 0. In this case, the DC error signal S _n (σ) corresponds to two average levels for X _n and X _n−1 , and X _n ′ and X _n−1 ′, which levels are on the horizontal axis (X = 0) at symmetrical positions ± δ. That is, the DC error signal S _n (σ) is output as a signal of ± 2δ whose polarity is alternately inverted according to the gradient of the input signal X _n , but its time average value is S _n (σ) = 0, This corresponds to a DC offset σ = 0. On the other hand, the normalized phase error signal T _n (τ) has its intersection with the horizontal axis irrespective of the slope of the input signal X _n , and T _n (τ) = − τ / T corresponding to the phase offset τ is output. The

Further, FIG. 13 shows a case where the DC offset σ ≠ 0 and the phase offset τ ≠ 0. In this case, the DC error signal S _n (σ) corresponds to two average levels corresponding to the gradient of the input signal X _n , and the signal S _n (σ is alternately inverted in polarity by a width of δ with the DC offset σ as the center. ) = 2 (σ ± δ) is output. The time average value is S _n (σ) = 2σ and corresponds to the DC offset σ. On the other hand, the normalized phase error signal T _n (τ) corresponds to two intersections corresponding to the slope of the input signal X _n , and the signal T _n (inverted polarity alternately with a width of ε around the phase offset −τ. τ) = (− τ ± ε) / T is output. The time average value is T _n (τ) = − τ / T, which corresponds to the phase offset τ.

As discussed in detail above, according to the phase error detecting circuit 7 according to the present embodiment, the input signal X _n in which the DC offset sigma phase offset tau mixed _(sigma, tau), each independently, DC An error signal S _n (σ) and a normalized phase error signal T _n (τ) can be generated. As a result, in the phase locked loop circuit, by forming an independent DC feedback loop therein, not only the phase offset τ can be corrected, but also the DC offset σ can be removed, and more stable phase locked control can be performed. It can be carried out.

  In the above-described phase error detection circuit, the DC error and the normalized phase error are detected only from the sample values before and after the polarity change. Therefore, in the phase locked loop circuit using this, the upper and lower sides (positive and negative) of the input signal are asymmetric. Even if it exists, DC offset and a phase offset can be restrained low.

FIG. 14 is a circuit diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention. Here, the ROM 750 stores the calculation results of the above-described equations (1) and (2), as in FIG. 5, and reads and outputs the normalized phase error signal T _n (τ) therefrom. Further, the adder 712, the modulo 2 adder 713, and the switch circuit 714 generate and output a DC error signal S _n (σ) as in FIG. In this embodiment, as in FIG. 5, since time-consuming arithmetic processing is not required, there is an advantage that the processing speed is increased.

  FIG. 15 is a circuit diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention. Here, reference numeral 715 denotes a polarity inversion circuit, 716 denotes a switch circuit, and 723 denotes an absolute value circuit. In addition, the same code | symbol is attached | subjected to the same element as the said FIG. 9, and the description is abbreviate | omitted.

First, the adder 712, the modulo 2 adder 713, and the switch circuit 714 generate and output a DC error signal S _n (σ) from the sum signal A _n (σ, τ), as in FIGS. The polarity inversion circuit 715 inverts the sign of the DC error signal S _n (σ). The switch circuit 716 receives these signals and the binarized signal Y _n and outputs a phase error signal E _n (τ) shown in the equation (8). That is, the phase error signal E _n (τ) is a signal before normalization with the amplitude of the input signal, and the calculation processing time is short.
E _n (τ) = S _n (σ) (when Y _n = 0)
= −S _n (σ) (when Y _n = 1) (8)

On the other hand, the absolute value circuit 723 detects the absolute value of the difference signal B _n (τ), and the normalization circuit 724 outputs a normalized phase error signal T _n (τ) as shown in equation (9).
T _n (τ) = E _n (τ) / 2 / | B _n (τ) | (9)

FIG. 16 is a block diagram showing an embodiment of an information reproducing apparatus using the phase error detection circuit 7 of FIG. Here, reference numeral 12 denotes a switch circuit, and other elements common to FIG. 7 are assigned the same reference numerals, and the description thereof is omitted. The feature of the present embodiment is that the control circuit 30 controls the switch circuit 12 from the phase error detection circuit 7 to two types of phase error signals E _n (τ), T shown in the equations (8) and (9). _n (τ) is switched and supplied to the loop filter 8.

With this configuration, for example, at the time of initial pull-in operation, or at the time of re-pull-up operation such as when the servo is disconnected or track jumped, the phase error signal E _n (τ) is switched to establish synchronization or synchronization recovery. Reduce time. Thereafter, switching to the normalized phase error signal T _n (τ) is performed, and the phase synchronization performance is stabilized by high-precision control. Thus, by appropriately switching the phase error signal to the loop filter 8, the synchronization time can be shortened and the synchronization performance can be stabilized.

  As described in detail above, according to the phase error detection circuit and the phase-locked loop circuit of this embodiment, and the information reproducing apparatus using the same, the influence of the amplitude level variation, DC level variation and asymmetry of the input signal. Thus, a stable phase synchronization characteristic can be obtained without receiving the light, and the reproduction quality of the optical disk reproduction apparatus or the like can be improved.

  Each embodiment mentioned above is an illustration for explanation of the present invention, and is not the meaning which limits the scope of the present invention only to an embodiment. In particular, the circuit configuration of the arithmetic circuit is merely an example, and any configuration that can acquire a desired arithmetic result is not limited to this and is all effective. Further, those skilled in the art can implement the present invention in various other modes without departing from the gist of the present invention.

1 is a configuration diagram (Example 1) showing an example of an information reproducing apparatus according to the present invention. FIG. FIG. 2 is a circuit configuration diagram showing an embodiment of a phase error detection circuit 7 in FIG. 1. Diagram for explaining a method of calculating the normalized phase error signal T _n. FIG. 6 is a diagram showing a phase error detection characteristic of a phase error detection circuit 7; FIG. 10 is a circuit configuration diagram showing another embodiment of the phase error detection circuit 7 according to the present invention (second embodiment). FIG. 11 is a circuit configuration diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention (third embodiment). The block diagram which shows the other Example of the information reproduction apparatus by this invention (Example 4). The figure which shows an example of the circuit structure of the DC feedback circuit 6 in FIG. FIG. 8 is a circuit configuration diagram showing one embodiment of a phase error detection circuit 7 in FIG. 7. Diagram for explaining the calculation method of the DC error signal S _n and the normalized phase error signal T _n. Diagram for explaining the calculation method of the DC error signal S _n and the normalized phase error signal T _n. Diagram for explaining the calculation method of the DC error signal S _n and the normalized phase error signal T _n. Diagram for explaining the calculation method of the DC error signal S _n and the normalized phase error signal T _n. FIG. 10 is a circuit configuration diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention (Embodiment 5). FIG. 11 is a circuit configuration diagram showing still another embodiment of the phase error detection circuit 7 according to the present invention (Embodiment 6). The block diagram which shows one Example of the information reproducing apparatus using the phase error detection circuit 7 of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Optical disk medium, 2 ... Optical pick-up circuit, 3 ... A / D converter, 4 ... PR equalization circuit, 5 ... Maximum likelihood decoding circuit, 6 ... DC feedback circuit, 7 ... Phase error detection circuit, 8 ... Loop filter , 9 ... D / A converter, 10 ... Voltage controlled oscillator (VCO), 11 ... Pre-equalization circuit, 12 ... Switch circuit, 20 ... Servo circuit, 30 ... System control circuit, 601 ... Subtractor, 602, 608 ... Register, 603 ... Amplitude limiter, 604, 605 ... Attenuator, 606, 607 ... Adder, 711, 721 ... Binary circuit, 712 ... Adder, 713 ... Adder of Modulo 2, 714, 716 ... Switch Circuit, 715 ... Polarity inversion circuit, 719, 720 ... Register, 722 ... Subtractor, 723 ... Absolute value circuit, 724 ... Normalization circuit, 750 ... ROM.

Claims (7)

In a phase error detection circuit that samples an input signal with a predetermined clock and detects a phase error of the clock from the sampled signal level,
For signal levels X _n and X _{n−1 at} two consecutive sampling positions n and (n−1) of the input signal, a ratio C _n (= (A _n / 2)) between the sum _An and the difference B _n / B _n )
A phase error detection circuit that outputs a calculation result C _n of the calculator at a sampling position where the polarities of the signal levels X _n and X _n−1 change as a phase error signal. In a phase error detection circuit that samples an input signal with a predetermined clock and detects a phase error of the clock from the sampled signal level,
A memory for storing in advance a calculation value of a ratio C _n (= (A _n / 2) / B _n ) between the sum _An and the difference B _n for each combination of two signal levels X _n and X _n−1 Prepared,
Two sampling position n of consecutive said input signal, (n-1) signal level at the _{X n,} if the polarity of the _{X n-1} is changed, the signal level _X n to be stored in the _memory, the _{X n-1} A phase error detection circuit which outputs the calculated value of C _n for the combination as a phase error signal. The phase error detection circuit according to claim 1.
Phase error detecting circuit, characterized in that the signal level X _n, the value of the computed A _n of the arithmetic unit at the sampling positions where the polarity of the X _n-1 is changed, and outputs it as DC error signal of the input signal. A phase-locked loop circuit using the phase error detection circuit according to claim 1,
An A / D converter for analog / digital conversion of an input signal with a predetermined clock;
Receiving the output signal of the A / D converter and detecting the phase error of the clock;
A phase-locked loop circuit comprising an oscillator controlled by a phase error signal from the phase error detection circuit and outputting the clock. A phase-locked loop circuit using the phase error detection circuit according to claim 3,
An A / D converter for analog / digital conversion of an input signal with a predetermined clock;
A DC feedback circuit for removing the DC level of the output signal of the A / D converter;
Receiving the output signal of the DC feedback circuit and detecting the phase error and the DC error;
An oscillator that is controlled by a phase error signal from the phase error detection circuit and outputs the clock;
The DC feedback circuit removes a DC level by a DC error signal from the phase error detection circuit. An information reproducing apparatus using the phase error detection circuit according to claim 1,
A reading unit for reading digital information recorded on the recording medium;
An A / D converter that performs analog / digital conversion of an output signal of the reading unit with a predetermined clock;
An equalizer for equalizing the output signal of the A / D converter;
A decoder for maximum likelihood decoding the output signal of the equalizer;
Receiving the output signal of the A / D converter or the equalizer and detecting the phase error of the clock;
An information reproducing apparatus comprising: an oscillator controlled by a phase error signal from the phase error detection circuit and outputting the clock. An information reproducing apparatus using the phase error detection circuit according to claim 3,
A reading unit for reading digital information recorded on the recording medium;
An A / D converter that performs analog / digital conversion of an output signal of the reading unit with a predetermined clock;
A DC feedback circuit for removing the DC level of the output signal of the A / D converter;
An equalizer for equalizing the output signal of the DC feedback circuit;
A decoder for maximum likelihood decoding the output signal of the equalizer;
Receiving the output signal of the DC feedback circuit or the equalizer and detecting the phase error and the DC error;
An oscillator that is controlled by a phase error signal from the phase error detection circuit and outputs the clock;
The information reproducing apparatus according to claim 1, wherein the DC feedback circuit removes a DC level by a DC error signal from the phase error detection circuit.

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