JPH11328875A - Information reproducing device and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent stability of a PLL function from depending on amplitude of a reproduced RF signal or to reduce such dependency. SOLUTION: A timing generator 100 generates six kinds of sampling signals GP-GT based on condition transition selected by a viterbi decoder 130. Sampling signals GU/GT for sampling the maximum value U/the minimum value T of a reproduced RF signal are included in these sampling signals. Since the values of U-T indicate amplitude of the reproduced RF signal, a standardized phase error signal PE is obtained by operation using the value. Generating of a PE is performed by a register holding a sampling value and a PEO106 having circuits and the like performing addition, subtraction, division, and the like. After the generated PE is D/A-converted, it is supplied to a VCO 110, and a read-clock DCK is generated by controlling VCO 110 by the PE.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus such as a magneto-optical disk device and a reproducing method.

[0002]

2. Description of the Related Art In an information reproducing apparatus such as a magneto-optical disk apparatus, a clock is generally generated by locking a PLL based on a reproduced RF signal reproduced from a recording medium, and the operation of a reproducing system is performed at a timing according to the clock. Done. Control for locking the PLL is performed based on the phase error signal. As a method of generating the phase error signal, there is a frequency lock mode which has been relatively widely used conventionally. In addition, the applicant of the present application has proposed a method of generating a phase error signal in a Viterbi determination mode (Heisei 9-101)
No. 689) or MSB determination mode (Heisei 9-107)
476).

In the Viterbi determination mode and the MSB determination mode, a phase error signal is generated based on a signal obtained by performing A / D conversion on a reproduced RF signal. At this time, A
Since the / D conversion value depends on the amplitude of the reproduced RF signal, as a result, the phase error signal depends on the amplitude of the reproduced RF signal.

[0004] Therefore, the loop band of the PLL is the reproduction RF.
It changes according to the amplitude of the signal. Therefore, in order to make the PLL function stably, for example, when a recording medium is mounted on a drive, calibration is performed to optimize the amplifier gain. It was necessary to keep the amplitude of the RF signal constant.

[0005]

In the method of performing calibration, there is a problem that the time required for one calibration becomes long enough to affect the drive performance. Furthermore, when characteristics such as sensitivity of the recording medium change due to factors such as temperature change, it is necessary to perform calibration each time.

In order to cope with these problems, from the viewpoint of simplifying the calibration operation and reducing the required number of times, the stability of the PLL lock is determined by the reproduction R.
It is considered effective to reduce the degree affected by the amplitude of the F signal.

It is therefore an object of the present invention to provide an information reproducing apparatus and a reproducing method in which the stability of the PLL lock does not depend on the amplitude of the reproduced RF signal or the degree thereof is small.

[0008]

According to the first aspect of the present invention, the operation of the apparatus is achieved by generating a phase error signal based on a reproduction signal reproduced from a recording medium and locking a PLL based on the phase error signal. An information reproducing apparatus for generating a clock for instructing a timing, wherein the information reproducing apparatus generates a phase error signal standardized by the amplitude of the reproduced signal.

According to a second aspect of the present invention, there is provided A / D conversion means for A / D converting a reproduced signal, Viterbi decoding means for performing Viterbi decoding based on an output of the A / D conversion means to generate decoded data, Timing generation means for generating sampling timing for performing sampling necessary for generating a phase error signal standardized by the amplitude of a reproduction signal from the output of the A / D conversion means based on the state transition selected by the Viterbi decoding means An information reproducing apparatus that performs sampling in accordance with the output of the timing generating means and generates a phase error signal standardized by the amplitude of the reproduced signal based on the sampling value.

According to a fifth aspect of the present invention, there is provided an A / D converter for A / D-converting a reproduced signal, and a method for converting the reproduced signal from the output of the A / D converter based on a part of the output of the A / D converter. Timing generation means for generating sampling timing for performing sampling required to generate a phase error signal standardized by amplitude, performing sampling in accordance with an output of the timing generation means, and generating a reproduction signal based on the sampling value. An information reproducing apparatus characterized by generating a phase error signal standardized by the amplitude of the information.

According to a ninth aspect of the present invention, a clock for instructing the operation timing of the device is generated by generating a phase error signal based on a reproduction signal reproduced from a recording medium and locking a PLL based on the phase error signal. In the information reproducing method, wherein a phase error signal standardized by the amplitude of the reproduced signal is generated.

According to the invention described above, even if the amplitude of the reproduced RF signal fluctuates due to a change in the setting of an amplifier, a filter, or the like, or a change in the recording medium, such a fluctuation in the amplitude is caused by the phase error signal. Can be avoided or its magnitude can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate understanding of the present invention, an example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. The outline of the 4-value 4-state Viterbi decoding method will be described in the order of the configuration and operation of the Viterbi decoder that realizes the 4-value 4-state Viterbi decoding method, and the Viterbi decoding method other than the 4-value 4-state Viterbi decoding method.

[Overview of Disc Recording / Reproducing Apparatus] An example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. FIG. 1 is a block diagram showing an overall configuration of an example of a magneto-optical disk device having a reproducing system that performs a Viterbi decoding method. At the time of recording, the controller 2 receives user data to be recorded according to a command from the host computer 1, performs encoding based on the user data as information words, and performs RLL (1,
7) Generate a code. This codeword is used as recording data in a laser power control unit (hereinafter referred to as LPC).
4 is supplied. In addition to such processing, the controller 2 performs operations such as decoding processing described later, control of each mode such as recording, reproduction, and erasing, and communication with the host computer 1.

The LPC 4 performs recording by controlling the laser power of the optical pickup 7 to form a pit row having a magnetic polarity on the magneto-optical disk 6 in accordance with the supplied recording data. At the time of this recording, the magnetic head 5 applies a bias magnetic field to the magneto-optical disk 6. Actually, mark edge recording as described later is performed according to a precode output generated as described later based on the recording data.

As will be described later, the recording position, that is, the pit formation position is controlled by means (not shown) for positioning the magnetic head 5 and the optical pickup 7 and the like. For this reason, even during the recording operation, when the optical pickup 7 passes through the address section and the like, the same operation as the reproducing operation described later is performed.

A method for associating each pit formed as described above with each bit in a precode output generated as described later based on recording data will be described with reference to FIG. A recording method in which a pit is formed for, for example, “1” and no pit is formed for “0” during precode output is called a mark position recording method.
On the other hand, a recording method in which the inversion of the polarity at the boundary of each bit in the precode output expressed by the edge of each pit corresponds to, for example, “1” is called a mark edge recording method. During playback, the boundaries of each bit in the playback signal are
It is recognized in accordance with a read clock DCK generated as described later.

Next, the configuration and operation of the reproducing system will be described. The optical pickup 7 irradiates the magneto-optical disk 6 with laser light, receives reflected light generated thereby,
Generate a playback signal. The reproduction signal is composed of a sum signal R ₊ , a difference signal R _−, and a focus error signal and a tracking error signal (not shown). The sum signal R ₊ is supplied to a sum / difference switch 10 after gain adjustment or the like is performed by the amplifier 8. The difference signal R ₋ is supplied to a sum / difference switch 10 after gain adjustment or the like is performed by the amplifier 9. Further, the focus error signal is supplied to a means (not shown) for eliminating the focus error. On the other hand, the tracking error signal is supplied to a servo system or the like (not shown) and used in those operations.

The sum / difference switch 10 is supplied with a sum signal / difference signal switching signal S as described later. Sum signal / differential signal selector switch 10 in accordance with the sum signal / differential signal switching signal S, as follows, the sum signal R ₊ or difference signals R _- supplies the filter unit 11. That is,
In a sector format of the magneto-optical disk 6 described later, a reproduction signal reproduced from a portion formed by embossing is a sum signal / difference signal switch 10.
Is supplied to the filter unit 11 during the period in which the sum signal R ₊ is supplied to the filter unit 11. Further, during a period in which the reproduction signal reproduced from the magneto-optically portion to be recorded is supplied to a sum signal / differential signal switching switch 10, the difference signal R _- supplies the filter unit 11.

The sum signal / difference signal switching signal S is generated, for example, as follows. That is, first, a signal reproduced from a predetermined pattern defined in the sector format is detected from the reproduced signal. As such a predetermined pattern, for example, a sector mark SM described later is used. Then, a sum signal / difference signal switching signal S is generated at a predetermined time point recognized by a method such as counting read clocks, which will be described later, based on the time point at which the detection is performed.

The filter section 11 includes a low-pass filter for performing noise cut and a waveform equalizer for performing waveform equalization. As will be described later, the waveform equalization characteristics used in the waveform equalization process at this time are adapted to the Viterbi decoding method performed by the Viterbi decoder 13. The A / D converter 12 supplied with the output of the filter unit 11 samples the reproduced signal value z [k] according to a read clock DCK supplied as described later.

The Viterbi decoder 13 outputs a reproduced signal value z [k].
, And generates decoded data by the Viterbi decoding method. Such decoded data is a maximum likelihood decoded sequence for the recorded data recorded as described above. Therefore,
If there is no decoding error, the decoded data matches the recorded data.

The decoded data is supplied to the controller 2. As described above, the recording data is a codeword generated from user data by encoding such as channel encoding. Therefore, if the decoding error rate is sufficiently low, the decoded data can be regarded as recording data as a codeword. The controller 2 reproduces user data and the like by performing decoding processing corresponding to the above-described encoding such as channel encoding on the decoded data.

The output of the filter unit 11 is also supplied to a PLL unit 14. The PLL unit 14 generates a read clock DCK based on the supplied signal. The read clock DCK is supplied to the controller 2, the A / D converter 1
2. It is supplied to the Viterbi decoder 13 and the like. The operations of the controller 2, the A / D converter 12, and the Viterbi decoder 13 are performed at timing according to the read clock DCK. Further, the read clock DCK is supplied to a timing generator (not shown). The timing generator
For example, it generates a signal for controlling operation timing of the apparatus such as switching between recording / reproduction operations.

In the reproducing operation as described above, in order to obtain more accurate reproduction data based on the reproduction signal reproduced from the magneto-optical disk 6, the operation of each component of the reproduction system is performed according to the quality of the reproduction signal. Optimization is performed.
Such an operation is called calibration. In the calibration, there is a possibility that the quality and the like of the reproduction signal may change due to the characteristics of the recording medium such as processing accuracy and the like, for example, fluctuations in the power of the recording laser beam, recording / reproduction conditions such as ambient temperature and the like. This is to optimize the parameters of the reproduction system in order to cope with the above.

The contents of the calibration include, for example, adjustment of the reading laser beam power of the optical pickup 7, adjustment of the gains of the amplifiers 8 and 9, adjustment of the waveform equalization characteristics of the filter unit 11, and operation of the Viterbi decoder 13. For example, adjustment of an amplitude reference value to be used. Such calibration is performed by a configuration not shown in FIG. 1 immediately after the power is turned on or when the recording medium is replaced.

[Overview of Sector Format of Recording Medium]
The user data is recorded on the magneto-optical disk 6 using a sector as a recording / reproducing unit. An example of a sector format used in the magneto-optical disk 6 will be described with reference to FIG. As shown in FIG. 3A, one sector is divided into respective areas of a header, an ALPC, a gap, a VFO ₃ , a sync, a data field, and a buffer in the order of recording / reproduction. The numbers attached in FIG.
Indicates the number of bytes. Encoded data such as block encoding is recorded on the magneto-optical disk 6. For example, 8 bits are converted into 12 channel bits and recorded.

As an example of this sector format, a format having a user data amount of 1024 bytes and a format having a user data amount of 512 bytes are prepared. In the format in which the user data amount is 1024 bytes, the number of bytes in the data field is 670 bytes.
Bytes. In the format in which the amount of user data is 512 bytes, the number of bytes in the data field is one.
278 bytes. In these two sector formats, the 63-byte preformatted header and the 18 bytes of the ALPC and gap area are the same.

FIG. 3B shows a 63-byte header in an enlarged manner. The header is a sector mark SM (8 bytes), VF
O field VFO ₁ (26 bytes), address mark AM (1 byte), ID field ID ₁ (5 bytes), VFO field VFO ₂ (16 bytes), address mark AM (1 byte), ID field ID
₂ (5 bytes) and postamble PA (1 byte) are arranged in order.

FIG. 3C shows an enlarged 18 byte ALPC and gap area. 18 bytes are a gap field (5 bytes), a flag field (5 bytes),
It consists of a gap field (2 bytes) and ALPC (6 bytes).

Next, these fields will be described. The sector mark SM is a mark for identifying the start of a sector, and has a pattern formed by embossing that does not occur in the RLL (1, 7) code.
The VFO field is the VFO (V
ariable Frequency Oscillator), and is composed of VFO ₁ , VFO ₂ and VFO ₃ . V
FO ₁ and VFO ₂ are formed by embossing. The VFO ₃ is written magneto-optically when a recording operation is performed on the sector. VFO ₁ , V
FO ₂ and VFO ₃ are patterns (2T patterns) in which channel bits “0” and “1” appear alternately, respectively.
Having. Therefore, if the time corresponding to the time length of one channel bit is T, a reproduced signal whose level is inverted every 2T is obtained when the VFO field is reproduced.

The address mark AM is used to provide byte synchronization to the device for the subsequent ID field and has an embossed pattern that does not occur in the RLL (1,7) code. The ID field includes a sector address, that is, information of a track number and a sector number, and a CRC for error detection for the information.
Has bytes. The ID field consists of 5 bytes. The ID ₁ and ID _2, the same address information is recorded in duplicate. The postamble PA has a pattern (2T) in which channel bits “0” and “1” appear alternately.
Pattern). ID ₁ , ID ₂ and postamble PA are also formed by embossing. Thus, the header area is a preformatted area in which pits are formed by embossing.

FIG. 3C shows the ALPC and the gap area in an enlarged manner. No pit is formed in the gap. The first gap field (5 bytes) is the first field after the preformatted header, which ensures that the device will have time to process after reading the header. The second gap field (2 bytes) is for allowing a displacement of the position of VFO ₃ later.

In the ALPC and gap area, a 5-byte flag field is recorded. In the flag field, a continuous 2T pattern is recorded when sector data is recorded. ALPC (Auto Laser Power Cont
The (rol) field is provided for testing the laser power at the time of recording. Sync field (4 bytes)
Is provided for the device to obtain byte synchronization for the subsequent data field and has a predetermined bit pattern.

The data field is provided for recording user data. The above-mentioned 670-byte data field includes 512-byte user data and 14 bytes.
It consists of 4 bytes of parity for error detection and correction, 12 bytes of sector write flag, and 2 bytes (FF). In the case of a 1278-byte data field, the data field includes 1024-byte user data, 242-byte parity for error detection and correction, and a 12-byte sector write flag. The buffer field at the end of the sector is used as a tolerance for electrical or mechanical errors.

In the above example of the sector format, the header is an area in which pits are formed by embossing. The ALPC and the gap area are not used during reproduction. In addition, VFO
_{3. The} sync field and the data field are areas of magneto-optically recorded data.

[Summary of 4-value 4-state Viterbi decoding method] The Viterbi decoding method performed by the Viterbi decoder 13 will be described below. As described above, the user data is
It is converted into a codeword as recording data by various encoding methods. An appropriate encoding method is adopted according to the characteristics of the recording medium and the recording / reproducing method. In the magneto-optical disk drive, in the block coding, Ru
In many cases, an RLL (Run Length Limited) coding method for limiting the n Length, that is, the number of '0's between' 1 'and' 1 'is used. Conventionally, several RLL coding methods have been used. Generally, an m / n block code in which the number of '0's between' 1 'and' 1 'is at least d and at most k is RLL
(D, k; m, n) code.

For example, in a 2/3 block code,
A block coding method in which the number of '0's between 1' and '1' is at least one and at most seven is RLL (1,7; 2,3)
Sign. Generally, the RLL (1, 7; 2, 3) code is R
Since it is often referred to as an LL (1, 7) code, the RLL (1, 7; 2, 3) code will be simply referred to as an RLL (1, 7) code in the following description. .

A Viterbi decoding method can be used to decode a reproduction signal reproduced from data recorded by a combination of such an RLL encoding method and the above-described mark edge recording method.

Such an RLL encoding method can meet the conditions required for the encoding method from two viewpoints of improving the recording density and ensuring the stability of the reproducing operation. First, as described above, the mark edge recording method associates '1' in the precode output generated as described later based on the recording data with the inversion of the polarity represented by the edge of each pit. '1'
As the number of '0's between' 1 'and' 1 'is increased, the number of bits recorded per pit can be increased. Therefore, the recording density can be increased.

On the other hand, the read clock DCK necessary for adjusting the operation timing of the reproduction system is generated by the PLL section 14 based on the reproduction signal as described above. For this reason, in the recorded data, a value between '1' and '1'
When the number of 0's is increased, the operation of the PLL unit becomes unstable during the reproducing operation, so that the entire reproducing operation becomes unstable.

Considering these two conditions, '1' and '
The number of '0's between 1's must be set within a reasonable range, not too high or too low. The RLL encoding method is effective for setting the number of '0' in the recording data.

By the way, as shown in FIG.
In the combination of the LL (1, 7) encoding method and the mark edge recording method, at least one '0' is inserted between '1' and '1' in precode output generated based on recording data. Since it is included, the minimum inversion width is 2. When such an encoding method in which the minimum inversion width is 2 is used, as a method for decoding recorded data from a reproduced signal affected by intersymbol interference and noise, as described below,
A quaternary 4-state Viterbi decoding method can be applied.

As described above, the waveform equalization processing is performed on the reproduced signal by the filter unit 11. Such a waveform equalization process performed as a preceding stage of the Viterbi decoding method includes:
A partial response method that actively uses intersymbol interference is used. The waveform equalization characteristics used at this time are:
From the partial response characteristics generally represented by (1 + D) ⁿ , the linear recording density and MTF of the recording / reproducing system
(Modulation TransferFunction). Waveform equalization processing using PR (1, 2, 1) for data recorded by a combination of the above-described RLL (1, 7) encoding method and mark edge recording method requires 4
This is the preceding stage of the 4-state Viterbi decoding method.

On the other hand, in the mark edge recording method,
Prior to actual recording on a magneto-optical disk medium, etc.,
Precoding based on the recording data encoded by the above-described RLL encoding or the like is performed. The recording data sequence at each time point k is a [k], and the precode output based on this is b
When [k] is set, precoding is performed as follows.

B [k] = mod 2 {a [k] + b [k−1]} (1) Such a precode output b [k] is actually recorded on a magneto-optical disk medium or the like. On the other hand, the waveform equalization characteristic PR (1,
The waveform equalization processing in (2, 1) will be described. However, in the following description, the waveform equalization characteristic is PR (B, 2A, B) without normalizing the signal amplitude. The value of the reproduced signal when noise is not considered is denoted as c [k]. In addition, the actual playback signal containing noise (ie,
The reproduced signal reproduced from the recording medium) is denoted by z [k].

PR (B, 2A, B) indicates that the contribution of the amplitude at time point k to the value of the reproduced signal at a certain time point k is 2A times the amplitude value, and furthermore, at time points k−1 and k + 1 before and after that. The contribution of the amplitude is B times the amplitude of the signal at each point in time. Accordingly, the maximum value of the value of the reproduction signal is a case where a pulse is detected at any of the time points k-1, k, and k + 1. In such a case, the maximum value of the reproduction signal is as follows.

B + 2A + B = 2A + 2B The minimum value of the reproduced signal is 0. However, in the actual handling, the DC component A +
The following is obtained by subtracting B.

C [k] = B × b [k−2] + 2A × b [k−1] + B × b [k] −AB (2) Accordingly, the reproduced signal c [k when noise is not considered. ]
Takes any value among A + B, A, -A, and -AB. Generally, one of the methods for indicating the property of a reproduced signal
For example, a pattern obtained by superimposing a large number of reproduction signals in units of five time points is called an eye pattern. FIG. 5 shows an example of an eye pattern of an actual reproduction signal z [k] subjected to waveform equalization processing under PR (B, 2A, B) in a magneto-optical disk drive to which the present invention can be applied. . From FIG. 5, the reproduced signal z [k] at each time point
Has a variation due to noise, but is approximately A +
It can be confirmed that any one of B, A, -A, and -AB is obtained. As described later, A + B, A, -A, -AB
Is used as an identification point.

The outline of the Viterbi decoding method for decoding the reproduced signal having undergone the above-described waveform equalization processing is as follows. All possible states are identified based on the step encoding method and the recording method for the recording medium. With each state at a certain point as a starting point, all state transitions that can occur at the next point in time, and the recording data a [k] and the value c [k] of the reproduction signal at the time of each state transition are specified.

All the states and state transitions specified as a result of the step and the state, and the value [recorded data value a [k] / reproduced signal value c [k]] when each state transition occurs.
In the form of a diagram is referred to as a state transition diagram. As will be described later, a state transition diagram in the 4-value 4-state Viterbi decoding method is as shown in FIG. The Viterbi decoder 13 is configured to perform a decoding operation based on this state transition diagram.

Further, as described above, based on the state transition diagram, the most likely state transition based on the reproduction signal z [k] reproduced from the recording medium at each time point k is selected. However, as described above, z [k] is waveform-equalized in a stage before being supplied to the Viterbi decoder 13. Each time such a maximum likelihood state transition is selected, the value of the recording data a [k] described in the state transition diagram is set as a decoded value in accordance with the selected state transition. Decoded data a '[k] as the maximum likelihood decoded value sequence for the data can be obtained.

However, a configuration for converting the decoded data value at each time point k into a maximum likelihood decoded value sequence is a PMU 23 in the Viterbi decoder 13 described later. Therefore, as described above, the decoded data string a '[k] matches the recorded data string a [k] when there is no decoding error. The above steps are described in detail below.

The above steps will be described. First, as a state used here, a state at a certain time point k is defined as follows using a precode output before the time point k. That is, n = b [k], m =
The state when b [k-1] and 1 = b [k-2] is defined as Snml. With such a definition, it is considered that there are 2 ³ = 8 states, but as described above, the states that can actually occur are limited based on the encoding method and the like.

In the recording data string a [k] encoded as the RLL (1,7) code, at least one '0' is included between '1' and '1', so that two or more '1' does not continue. Based on such conditions imposed on the recording data string a [k], certain conditions are imposed on the precode output b [k], and the resulting states are restricted.

Such a limitation will be specifically described. As described above, in a recording data sequence generated by RLL (1, 7) encoding, there cannot be one in which two or more '1's are continuous, that is, the following.

A [k] = 1, a [k−1] = 1, a [k−2] = 1 (3) a [k] = 1, a [k−1] = 1, a [k− 2] = 0 (4) a [k] = 0, a [k−1] = 1, a [k−2] = 1 (5) Based on such conditions imposed on the recording data sequence, Examining the conditions imposed on b [k] according to the equation (1), it can be seen that the two states S010 and S101 cannot occur. Therefore, there are 2 ³ −2 = 6 possible states.

Next, the steps will be described. In order to obtain a state that can occur at the next time point j + 1 from the state at a certain time point j as a starting point, it is necessary to separately examine the case where the value a [j + 1] of the recording data at the time point j + 1 is 1 and 0. There is.

Here, the state at time j is S000
The following is an example of the case. According to the above equation (1), S000, that is, n = b [j] = 0, l = b [j−
1] = 0, m = b [j-2] = 0, and the recording data pre-coded is (7) below.

A [j] = 0, a [j-1] = 0, a [j-2] = 0 (7) [when a [j + 1] = '1'] At this time, b [j + 1] is It is calculated as follows according to equation (1).

B [j + 1] = mod2 ｛a [j + 1] + b [j]｝ = mod2 ｛1 + 0｝ = 1 (8) For the state Snlm at the next time point j + 1, n = b [j
+1], l = b [j], and m = b [j-1]. Then, from (8), b [j + 1] = 1 and b
Since [j] = 0 and b [j-1] = 0, the next time point j + 1
The state in is S100. Therefore, a [j +
1] = '1', it can be specified that a transition of S000 → S100 occurs.

The value of the reproduced signal c [j + 1] is calculated as follows in accordance with the above equation (2).

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 1 + 2A × 0 + B × 0} −AB = − A (9) From the above, when the value of the new reproduction signal value c [j + 1] is −A within the range of the error when the state is the state S000 at the time point j, the state transition S000 → S100 occurs, It can be seen that the value “1” of a [j + 1] is obtained as the decoded data value.

[When a [j + 1] = '0'] At this time,
According to the equation (1), b [j + 1] is calculated as follows.

B [j + 1] = mod2 ｛a [j + 1] + b [j]｝ = mod2 ｛0 + 0｝ = 0 (10) For the state Snlm at the next time point j + 1, n = b [j
+1], l = b [j], and m = b [j-1]. From (10), b [j + 1] = 0, and b
Since [j] = 0 and b [j-1] = 0, the next time point j + 1
State is S000. Therefore, a [j +
1] = '0', it can be specified that a transition of S000 → S100 occurs.

The value of the reproduced signal c [j + 1] is calculated as follows in accordance with the above equation (2).

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 0 + 2A × 0 + B × 0} −AB = − AB (11) From the above, when the value of the new reproduction signal value c [j + 1] is −AB within the range of the error in the state S000 at the time point j, the state transition S000 → S00
0 is generated, and the value of a [j + 1] is “0” as a decoded data value.
Is obtained.

Thus, S000 at time j
, The state transitions that can occur at the next time point j + 1 starting from them and the correspondence between the recording data value a [j + 1] and the reproduction signal value c [j + 1] when such state transitions occur Can be requested.

As described above, for each state, the correspondence between the state transition that can occur starting from the state, the value of the recording data and the value of the reproduction signal at the time when each state transition occurs, is obtained, and the table is shown in the form of the figure. FIG. 6 shows the result. Time points j and j + 1 described above are not special time points. Therefore, the correspondence between the possible state transitions obtained as described above and the values of the recording data and the values of the reproduction signals accompanying them can be applied at any time. Therefore, FIG.
In, the value of the recording data accompanying the state transition occurring at an arbitrary time point k is denoted as a [k], and the value of the reproduced signal is denoted as c [k].

In FIG. 6, the state transition is represented by an arrow. In addition, the sign given to each arrow indicates [record data value a [k] / reproduction signal value c [k]]. State S
While there are two types of state transitions starting from 000, S001, S111, and S110, only one transition can occur starting from states S011 and S100.

Further, in FIG. 6, S000 and S001
Takes a value of c [k] =-A for a [k] = 1, and transits to S100. On the other hand, a
For [k] = 0, a value of c [k] =-AB is taken, and the process transits to S000. Also, S111 and S1
10 is also the same for the same value of a [k + 1].
It takes the value of [k + 1] and transitions to the same state. Therefore, S000 and S001 can be collectively expressed as S0, and S111 and S110 can be collectively expressed as S2. Further, S011 is set to S3, and S100 is set to S3.
FIG. 7 shows an arrangement that is expressed as 1.

As described above, FIG. 7 is a state transition diagram used in the 4-value 4-state Viterbi decoding method. In FIG. 7,
The four states S0 to S3 and the reproduced signal c [k + 1]
Are shown as -AB, -A, A, and A + B. There are two types of state transition starting from the states S0 and S2, whereas only one state transition starting from the states S1 and S3.

On the other hand, a trellis diagram as shown in FIG. 8 is used as a format for expressing a state transition along time. FIG. 8 shows a transition between two time points, but a transition between many more time points can also be shown. As the time elapses, a state in which the image sequentially transits to the right time point is expressed. Therefore, a horizontal arrow represents a transition to the same state, for example, S0 → S0, and a diagonal arrow represents, for example, S1 → S2.
And so on.

The steps of the above-described Viterbi decoding method, that is, a method of selecting the most likely state transition from the actual reproduced signal z [k] including noise, based on the state transition diagram shown in FIG. 7, will be described below. .

In order to select the maximum likelihood state transition, first, for the state at a certain time point k, the sum of the likelihoods of the state transitions between a plurality of time points passed in the process of reaching the state is calculated. It is necessary to select the maximum likelihood decoded sequence by comparing the calculated sums of likelihoods. Such a sum of likelihoods is called a path metric.

In order to calculate a path metric, it is first necessary to calculate the likelihood of a state transition between adjacent time points. Such calculation of the likelihood is performed as follows based on the value of the reproduced signal z [k] with reference to the above state transition diagram. First, as a general explanation, the time k-
Consider the case where the state is Sa in state No. 1. At this time, when the reproduction signal z [k] is input to the Viterbi decoder 31, the likelihood that a state transition to the state Sb occurs is calculated according to the following equation. However, the state Sa and the state Sb are any of the four states described in the state transition diagram of FIG.

(Z [k] −c (Sa, Sb)) ² (12) In the above equation, c (Sa, Sb) is the state transition from the state Sa to the state Sb in the state transition diagram of FIG. This is the value of the described reproduction signal. That is, in FIG. 7 described above, for example, for the state transition S0 → S1, the value is calculated as −A. Therefore, equation (12) is the Euclidean distance between the value of the actual reproduced signal z [k] including noise and the value of the reproduced signal c (Sa, Sb) calculated without considering noise. The path metric at a certain point in time is defined as the sum of likelihoods of state transition between such adjacent points up to that point.

Now, let us consider a case where the state is Sa at the time point k. In this case, at time k-1, the state S
If the state that can transition to a is Sp, the path metric L
(Sa, k) is calculated by the following equation using the path metric at the time point k-1.

L (Sa, k) = L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² (13) That is, when the state Sp is reached at time k−1 The path metric L (Sp, k−1) and the likelihood (z (z) of the state transition Sp → Sa occurring between the time points k−1 and k)
[K] −c (Sp, Sa)) ² and the path metric L (Sa, k) is calculated. The likelihood of the latest state transition such as (z [k] -c (Sp, Sa)) ² is called a branch metric. However, the branch metric here is a branch metric calculation circuit (BMC) 2 in the Viterbi decoder 13 described later.
A branch metric calculated by 0, ie
The branch metric corresponding to the standardized metric is
Note that they are different.

Further, when the state is the state Sa at the time point k, there may be a plurality of states that can transition to the state Sa at the time point k-1. In FIG. 7, states S0 and S2 are such cases. That is, if the state S0 is at time k, the state S
There are two states that can transition to 0: S0 and S3. Further, when the state is the state S2 at the time point k, the time point k−1
The states that can transition to the state S2 in S1 are two of S1 and S2.
Individual. As a general explanation, at time k, state S
If the state is a and the two states that can transition to the state Sa at the time point k−1 are Sp and Sq, the path metric L (Sa, k) is calculated as in the following equation.

L (Sa, k) = min ｛L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² , L (Sq, k−1) + (z [k] −c (Sq, Sa)) ² ｝ (14) That is, at time k−1, the state Sp is in effect, and Sp →
The sum of the likelihoods is calculated for each of the case where the state Sa is reached by the state transition Sa and the case where the state Sq is reached at the time k-1 and the state Sq is reached by the state transition Sq → Sa. Then, the respective calculated values are compared, and the smaller value is set as the path metric L (Sa, k) for the state Sa at the time point k.

The calculation of such a path metric is shown in FIG.
Is specifically applied to the above-described quaternary and four states by using, the respective states S0, S1, S2 and S3 at the time point k.
Path metrics L (0, k), L (1,
k), L (2, k) and L (3, k) are at time k−1
Path metric L for each state S0 to S3 in
It can be calculated as follows using (0, k-1) to L (3, k-1).

L (0, k) = min {L (0, k−1) + (z [k] + A + B) ² , L (3, k−1) + (z [k] + A) ² } (15 ) L (1, k) = L (0, k−1) + (z [k] + A) ² (16) L (2, k) = min ｛L (2, k−1) + (z [k ] -AB) ² L (1, k-1) + (z [k] -A) ² } (1
7) L (3, k) = L (2, k−1) + (z [k] −A) ² (18) As described above, the values of the path metrics calculated in this way are compared. It suffices if the most likely state transition is selected. By the way, in order to select the maximum likelihood state transition, it suffices if the value of the path metric can be compared without calculating the value of the path metric itself. Therefore, in the actual four-value four-state Viterbi decoding method, by using a normalized path metric as defined below instead of the path metric, calculation based on z [k] at each time point k can be easily performed. It is made to do.

M (i, k) = [L (i, k) −z [k] ² − (A + B) ² ] / 2 / (A + B) (19) Equation (19) is applied to each state of S 0 to S 3. When applied, the specific normalized path metric does not include the square calculation as follows. For this reason, addition, comparison,
Calculation in the selection circuit (ACS) 21 can be facilitated.

M (0, k) = min {m (0, k−1) + z [k], m (3, k−1) + α × z [k] −β} (20) m (1, k ) = M (0, k−1) + α × z [k] −β (21) m (2, k) = min ｛m (2, k−1) −z [k], m (1, k−) 1) −α × z [k] −β} (22) m (3, k) = m (2, k−1) + α × z [k] −β (23) However, Expressions (20) to (23) Α and β in the parentheses are as follows.

Α = A / (A + B) (24) β = B × (B + 2 × A) / 2 / (A + B) (25) State transition in the 4-value 4-state Viterbi decoding method based on such a normalized path metric FIG. 9 shows the condition (1). Since there are two expressions for selecting one from two of the four normalized path metrics, there are 2 × 2 = 4 conditions.

[Overview of 4-Valued 4-State Viterbi Decoder] A Viterbi decoder 1 that realizes the 4-valued 4-state Viterbi decoding method described above.
3 will be described below. FIG. 10 shows a Viterbi decoder 13.
1 shows the entire configuration. The Viterbi decoder 13 includes a branch metric calculation circuit (hereinafter, referred to as BMC) 20, an addition, comparison, and selection circuit (hereinafter, referred to as ACS) 2
1, a compression and latch circuit 22 and a path memory unit (hereinafter referred to as PMU) 23. The read clock DCK described above is applied to each of these components.
The operation timing of the entire Viterbi decoder 13 is adjusted by supplying (hereinafter, simply referred to as a clock) in the following description. Hereinafter, each component will be described.

The BMC 20 receives the reproduced signal z
Based on [k], branch metric values BM0, BM1, BM2 and B corresponding to the normalized path metric
Calculate M3. BM0 to BM3 are calculated by the above equation (20).
The following are required to calculate the normalized path metric of (23).

BM0 = z (k) (26) BM1 = α × z [k] −β (27) BM2 = −z (k) (28) BM3 = −α × z [k] −β (29) Α and β required for the calculation are reference values calculated by the BMC 20 according to the above equations (24) and (25). Such a calculation is detected by a method such as envelope detection based on the reproduced signal z [k], for example.
Based on the values of the discrimination points -AB, -A, A, and A + B.

The values of BM0 to BM3 are supplied to the ACS 21. On the other hand, the ACS 21 is supplied with the normalized path metric values M0, M1, M2, and M3 one clock before (but compressed as described later) from the compression and latch circuit 22 described later. . Then, M0 to M3 and BM0 to BM3 are added, and the latest standardized path metric value L is added as described later.
Calculate 0, L1, L2 and L3. Since M0 to M3 are compressed, it is possible to avoid overflow when calculating L0 to L3.

Further, the ACS 21 selects the maximum likelihood state transition based on the latest standardized path metric values L0 to L3, as described later, and stores it in the path memory 23 in accordance with the selection result. The supplied selection signals SEL0 and SEL2 are set to “High” or “Low”.

The ACS 21 supplies L0 to L3 to the compression and latch circuit 22. The compression and latch circuit 22 latches the supplied L0 to L3 after compressing them. Thereafter, the normalized path metric M0 one clock before
To the ACS 21 as .about.M3.

As a compression method at this time, for example, as shown below, the latest standardized path metrics L0 to L3
Therefore, a method of uniformly subtracting one of them, for example, L0, is used.

M0 = L0-L0 (30) M1 = L1-L0 (31) M2 = L2-L0 (32) M3 = L3-L0 (33) As a result, M0 always takes a value of 0. However, in the following description, it is denoted as M0 as it is in order not to impair generality. The difference between the values of M0 to M3 calculated by the equations (30) to (33) is equal to the difference between the values of L0 to L3. As described above, in the selection of the maximum likelihood state transition, only the value difference between the normalized path metrics becomes a problem. Therefore, such a compression method is effective as a method of compressing the value of the normalized path metric without affecting the selection result of the maximum likelihood state transition and preventing overflow. Thus, the ACS 21 and the compression and latch circuit 22 form a loop related to the calculation of the normalized path metric.

The above-mentioned ACS 21 will be described in more detail with reference to FIG. The ACS 21 includes six adders 51, 52, 53, 54, 56, 58 and two comparators 55, 57. On the other hand, as described above, A
CS 21 is supplied with compressed standardized path metric values M0 to M3 one clock before and branch metric values BM0 to BM3 corresponding to the standardized path metric.

The adder 51 is supplied with M0 and BM0. The adder 51 adds these to calculate L00 as follows.

L00 = M0 + BM0 (34) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above-described equation (26) based on the reproduced signal z [k] input at the time point k, that is, the value of z [k] itself. Therefore, equation (34)
Is obtained by calculating the value of m (0, k-1) + z [k] in the above equation (20) under the effect of the above-described compression. That is, the state S0 at the time point k-1
This is a calculated value corresponding to the case where the state transition S0 finally arrives at the time point k by the state transition S0 → S0.

On the other hand, M3 and BM1 are added to the adder 52.
Is supplied. The adder 51 adds these to calculate the following L30.

L30 = M3 + BM1 (35) As described above, M3 is in the state S3 at the time point k-1.
, Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, B
M1 is calculated based on the reproduced signal z [k] input at the time point k in accordance with the above equation (27), that is, α × z [k] −β. Therefore, the value of equation (35) is calculated by the above equation (2) under the action of compression as described above.
0) in m (3, k-1) + α × z [k] −β. That is, this is a calculated value corresponding to the case where the state is S3 at the time point k−1 and finally reaches the state transition S0 by the state transition S3 → S0 at the time point k.

The above-mentioned L00 and L30 correspond to the comparator 55
Supplied to The comparator 55 compares the values of L00 and L30, and determines the smaller one as the latest standardized path metric L0.
Then, the polarity of the selection signal SEL0 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (20). That is, when L00 <L30 (in this case, S0 → S0 is selected), L00 is output as L0, and SEL0 is set to, for example, 'Low'. If L30 <L00 (in this case, S3 → S0 is selected), L30 is output as L0, and S30 is output.
EL0 is set to, for example, 'High'. SEL0 is supplied to the A-type path memory 24 corresponding to the state S0, as described later.

As described above, the adders 51 and 52 and the comparator 55 are the most likely state transitions at the time point k from S0 → S0 and S3 → S0 according to the above equation (20). Is performed. Then, it outputs the latest standardized path metric L0 and the selection signal SEL0 according to the selection result.

The adder 56 has M0 and BM1
Is supplied. The adder 51 adds these to calculate the following L1.

L1 = M0 + BM1 (36) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
1 is calculated based on the reproduced signal z [k] input at the time point k in accordance with the above equation (27), that is, α × z [k] −β. Therefore, the value of equation (36) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (0, k-1) + α × z [k] −β of 1) is calculated.

That is, this is a calculated value corresponding to the case where the state S0 is at time k-1 and the state transition S1 is finally reached by the state transition S0 → S1 at time k. In response to equation (21) not selecting a value,
The output of the adder 56 is used as it is as the latest standardized path metric L1.

The adder 53 is supplied with M2 and BM2. The adder 53 adds these to calculate the following L22.

L22 = M2 + BM2 (37) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above equation (28) based on the reproduced signal z [k] inputted at the time point k, that is, -z [k]. Therefore, the value of the expression (37) is obtained by calculating the value of m (2, k-1) -z [k] in the above expression (22) under the effect of the above-described compression. . That is, the calculated value corresponds to the case where the state S2 is at the time point k−1 and the state transition S2 is finally reached by the state transition S2 → S2 at the time point k.

On the other hand, the adder 54 has M1 and BM3
Is supplied. The adder 53 adds these values to calculate L12 as described below.

L12 = M1 + BM3 (38) As described above, M1 is in the state S1 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, equation (38)
Is obtained by calculating the value of m (1, k−1) −α × z [k] −β in the above equation (22) under the effect of the above-described compression. That is, the calculated value corresponds to the case where the state S1 is at the time point k−1 and the state transition S2 is finally reached by the state transition S1 → S2 at the time point k.

The above-mentioned L22 and L12 are output from the comparator 57.
Supplied to The comparator 57 compares the values of L22 and L12, and determines the smaller one as the latest standardized path metric L2.
At the same time, the polarity of the selection signal SEL2 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (22).

That is, when L22 <L12 (in this case, S2 → S2 is selected), L22 is output as L2, and SEL2 is set to, for example, 'Low'. When L12 <L22 (in this case, S1 → S2 is selected), L12 is output as L2, and S12 is output.
EL2 is set to, for example, 'High'. SEL2 is supplied to the A-type path memory 26 corresponding to the state S2 as described later.

As described above, the adders 53 and 54 and the comparator 57 correspond to the above-mentioned equation (22) to determine the maximum likelihood state transition at the time point k from S1 → S2 and S2 → S2. Select Then, it outputs the latest standardized path metric L2 and the selection signal SEL2 according to the selection result.

The adder 58 has M2 and BM3
Is supplied. The adder 58 adds these to calculate the following L3.

L3 = M2 + BM3 (39) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, the value of equation (39) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (2, k-1) + α × z [k] −β of 3) is calculated.

That is, this is a calculated value corresponding to the case where the state S0 is at the time point k-1 and the state transition S3 is finally reached by the state transition S2 → S3 at the time point k. In response to equation (23) not selecting a value,
The output of the adder 58 is used as it is as the latest standardized path metric L3.

As described above, the path memory unit (hereinafter referred to as PMU) 23 operates in accordance with SEL0 and SEL2 output from the ACS 21, thereby decoding the recording data a [k] as the maximum likelihood decoding sequence. Data a '[k] is generated. PMU23
In order to cope with the state transition between the four states shown in FIG. 7, it is composed of two A-type path memories and two B-type path memories.

The A-type path memory has two transitions (that is, a transition from itself and a transition from another state) as transitions to the state, and uses the state as a starting point. The configuration is such that it corresponds to a state having two transitions (ie, a transition leading to itself and a transition leading to another single state). Therefore, the A-type path memory corresponds to S0 and S2 among the four states shown in FIG.

On the other hand, the B-type path memory is configured to cope with a state in which there is only one transition to the state and only one transition starting from the state. Therefore, the B-type path memory corresponds to S1 and S3 among the four states shown in FIG.

In order for the two A-type path memories and the two B-type path memories to operate in accordance with the state transition diagram shown in FIG. 7, the PMU 23 transfers the decoded data as shown in FIG. It is configured to be. That is, the A-type path memory 24 corresponds to S0, and the A-type path memory 26 corresponds to S2. Also, the B-type path memory 25
Corresponds to S1, and the B-type path memory 27 corresponds to S3.

With this configuration, the state transitions that can occur starting from S0 are S0 → S0 and S0 → S1, and the state transitions that can occur starting from S2 are S2 → S2 and S2 → S3. I do. Also, the only state transition that can occur starting from S1 is S1 → S2,
This also matches that the state transition that can occur starting from No. 3 is only S3 → S0.

FIG. 12 shows a detailed configuration of the A-type path memory 24. The A-type path memory 24 includes a number of flip-flops and selectors corresponding to the path memory length,
They are connected alternately. FIG. 10 shows a configuration corresponding to a decoded data length of 14 bits. That is,
Those having fourteen selectors 31 ₁ to 31 ₁₄ and 15 flip-flops 30 ₀ - 30 _14. Each of the selectors 31 _{1 to} 31 ₁₄ receives two pieces of data, and selectively supplies one of them to a subsequent stage. Further, since the clock is supplied to the flip-flop 30 ₀ - 30 _14, the operation timing of the entire A type path memory 24 is combined.

As described above with reference to FIG. 7, the transition to the state S0 is S0 → S0, that is, the transition inherited from itself, and S3 → S0. As a configuration corresponding to such a situation, each selector includes data supplied from the preceding flip-flop, that is, decoded data corresponding to S0 → S0, and B-type path memory 27 corresponding to state S3.
, Ie, decoded data PM3 corresponding to S3 → S0.

Further, each selector operates from ACS 21 to S
EL0 is supplied. Then, according to the polarity of SEL0, one of the two supplied decoded data is supplied to the subsequent flip-flop. Further, the decoded data supplied to the subsequent flip-flop in this manner is in the state S
The B-type path memory 25 corresponding to 1 is also supplied as PM0.

[0123] That is, for example, the selector 31 _14, the data supplied from the preceding flip-flops 30 _13, B
14-bit P supplied from the pattern path memory 27
And the data in the 14th bit position of M3. Then, the data selected as follows from these two data, and supplies the subsequent flip-flop 30 _14. As described above, SEL0 sets 'L' in accordance with the selection result.
ow 'or' High '.

[0124] When the SEL0, for example, 'Low' is adapted to data from the preceding flip-flop 30 ₁₃ is selected. When SEL0 is “High”, for example, PM
The data in the 14th bit position of No. 3 is selected. The selected data is supplied to the subsequent flip-flops 30 _14, also, as the data of 14-th bit position of PM0, is supplied to the B type path memory 25 corresponding to the state S1.

Another selector 31 in the A-type path memory 24
Also in _{1-31 13,} depending on the polarity of the SEL0, similar operations are performed. Therefore, as a whole, when SEL0 is, for example, "Low", the A-type path memory 24 performs a serial shift in the A-type path memory 24 in which each flip-flop inherits the data of the flip-flop located at the preceding stage. . Further, when SEL0 is, for example, “High”, a parallel load that inherits the 14-bit decoded data PM3 supplied from the B-type path memory 27 is performed. In any case, the inherited decoded data is stored in the B-type path memory 2.
5 is supplied as 14-bit decoded data PM0.

[0126] In addition, the flip-flop 30 ₀ on the first stage, always in synchronization with the clock '0' is input. This operation is a state transition S0 → S0 and S0 leading to S0.
In any of 2 → S0, as shown in FIG. 7, since the decoded data is “0”, the latest decoded data always corresponds to “0”.

As described above, the configuration of the A-type path memory 26 corresponding to S2 is the same as that of the A-type path memory 2.
4 is exactly the same. However, the selection signal input from the ACS 21 is SEL2. In addition, as shown in FIG. 6, transitions to the state S2 include S2 → S2, that is, transitions inherited from itself, and S1 → S2. Therefore, the PM1 is stored in the B-type path memory 25 corresponding to the state S1.
Supplied. Further, the state that can occur starting from the state S2 is S2, that is, the state itself, and the fact that the state is S3.
Supply.

The A-type path memory 26 corresponding to S2
In this case, '0' is always input to the flip-flop serving as the first processing stage in synchronization with the clock. This operation is performed in the state transition S2 → S2 and S1 → S0 leading to S2, as shown in FIG.
Therefore, the latest decoded data corresponds to always being '0'.

On the other hand, the detailed configuration of the B-type path memory 25 is shown in FIG. The B-type path memory 25 has a number of flip-flops connected to the path memory length. FIG. 13 shows a configuration corresponding to a decoded data length of 14 bits. That is, it has 15 flip-flops 32 _{0 to} 32 ₁₄ . By supplying a clock to the flip-flops 32 _{0 to} 32 ₁₄ , the operation timing of the entire B-type path memory 25 is adjusted.

Each of the flip-flops 32 _{1 to} 32 ₁₄ has
14-bit decoded data is supplied as PM0 from the A-type path memory 24 corresponding to the state S0. For example, the first bit of PM0 is supplied to the flip-flop 32 ₁ . Each of the flip-flops 32 _{1 to} 32 ₁₄ holds the supplied value for one clock. Then, it outputs it to the A-type path memory 26 corresponding to the state S2 as 14-bit decoded data PM1. For example, flip-flop 3
2 ₁ outputs the second bit of PM1.

Another selector 32 in the B-type path memory 25
Also in _{1-32 13,} similar operation is performed. Therefore, the entire B-type path memory 25 receives the 14-bit decoded data PM supplied from the A-type path memory 24.
0, and supplies 14-bit decoded data PM1 to the A-type path memory 26.

[0132] In addition, the flip-flop 32 _0, always in synchronization with the clock '1' is input. Such actions are:
As shown in FIG. 7, when the latest state transition is S0 → S1, this corresponds to that the decoded data is “1”.

As described above, the configuration of the B-type path memory 27 corresponding to the state S3 is completely the same as that of the B-type path memory 25. However, as shown in FIG. 7, since the transition to the state S3 is from S2 to S3, PM2 is supplied from the A-type path memory 26 corresponding to the state S2. Further, in response to the state that can occur starting from the state S3 being S0, the A-type path memory 24 corresponding to the state S0
To supply PM3. B type path memory 2
Also in 7, the flip-flop as the first processing stage is always supplied with "1" in synchronization with the clock. This operation is performed as shown in FIG. 7, when the latest state transition is S2 →
The case of S3 corresponds to the fact that the decoded data is '1'.

As described above, each of the four path memories in the PMU 23 generates decoded data. The four pieces of decoded data generated in this way match each other if an accurate Viterbi decoding operation is always performed. By the way, in the actual Viterbi decoding operation, 4
A mismatch may occur in the pieces of decoded data. Such inconsistency is caused by an inaccurate Viterbi decoding operation due to factors such as an error in detecting the above-described identification points A and B due to the influence of noise included in the reproduced signal. .

In general, the probability of occurrence of such inconsistency can be reduced by setting the number of processing stages of the path memory sufficiently large in accordance with the quality of the reproduced signal. That is, when the quality of the reproduction signal such as C / N is good, the probability of occurrence of mismatch between decoded data is small even if the number of processing stages of the path memory is relatively small. On the contrary,
When the quality of the reproduced signal is not good, it is necessary to increase the number of processing stages of the path memory in order to reduce the probability of occurrence of the above-described mismatch.

In the case where the number of processing stages of the path memory is relatively small with respect to the quality of the reproduced signal and the probability of occurrence of mismatch between decoded data cannot be sufficiently reduced, for example, a majority decision is performed from the four decoded data. A configuration (not shown) that selects a more accurate one by a method such as
23 are provided after the four path memories.

[Viterbi decoding method other than 4-value 4-state Viterbi decoding method] In the 4-value 4-state Viterbi decoding method described above, the waveform equalization characteristic used in the filter unit 11 is PR.
(1, 2, 1) and RLL is used as recording data.
Used when the (1,7) code is adopted. For example, a recording linear density of 0.4, which is being standardized by ISO,
In the case of 0 μm, laser wavelength of 685 nm, and NA = 0.55, the waveform equalization characteristic is set to PR (1, 2, 1) and quaternary 4
It is optimal to use the state Viterbi decoding method. On the other hand,
Other types of Viterbi decoding methods may be used depending on the waveform equalization characteristics or the encoding method for generating the recording data.

For example, when the waveform equalization characteristic is PR (1, 1) and an RLL (1, 7) code is used as recording data, a ternary 4-state Viterbi decoding method is used. Further, the waveform equalization characteristic is PR (1, 3, 3, 1)
In the case where the RLL (1, 7) code is used as the recording data, a 7-value 6-state Viterbi decoding method is used. Among such Viterbi decoding methods, a waveform equalization characteristic that is one of the elements for selecting which method to use is preferably one that has a high degree of compatibility with intersymbol interference on a reproduced signal. Therefore, as described above, it is optimized in consideration of the linear recording density and the MTF.

Further, the deviation of the waveform equalization characteristic from the theoretical value,
Also, the value of the discrimination point may be different from the theory due to amplitude fluctuation of the reproduction signal, asymmetric distortion, and the like. In consideration of such a case, the Viterbi decoding method may be modified and used. For example, in the four-value four-state Viterbi decoding method, considering that it is difficult to accurately set the waveform equalization characteristics to PR (1, 2, 1), it is assumed that six discrimination points will be described later. The 6-value 4-state Viterbi decoding method described above may be used.

In the above-described example of the magneto-optical disk device, the PLL unit 14 analogously locks the PLL based on the 2T signal reproduced from the 2T pattern recorded in the VFO field in the sector format. Is used. On the other hand, the present invention presupposes the Viterbi determination mode and the MSB determination mode,
The phase error signal generated by these methods is standardized with reference to the amplitude of the reproduced RF signal, and the PLL is locked based on the standardized phase error signal.

Hereinafter, a fourth embodiment of the present invention will be described.
An example of a generation 5.25 inch magneto-optical disk device will be described. One embodiment of the present invention is an application of the present invention on the premise that phase error detection is performed in a Viterbi determination mode. The Viterbi determination mode is a method of obtaining a sampling timing for detecting a phase error based on state data, that is, a series of state data values representing a state transition itself selected by the ACS in the Viterbi decoding method. Therefore, in order to perform the Viterbi determination mode, it is necessary to use a Viterbi decoder having a function of generating state data.

Here, in the fourth-generation 5.25 inch magneto-optical disk device, the four-state four-state state transition shown in FIG. 14 replaces the four-state four-state state transition shown in FIG. Viterbi decoding is performed on the premise of the figure. In FIG. 14, a 2-bit expression similar to the expression method of the state data value is used. That is, S0, S1, S2 in FIG.
S3 is described as S00, S01, S11, and S10, respectively. Further, the reference numerals attached to the arrows indicating the state transitions indicate [decoded value / identification point value]. Note that P, Q, R, S, T, and U corresponding to each state transition will be described later.

The state transition diagram of 6 values and 4 states is used in an actual magneto-optical disk device or the like, as an ideal partial response characteristic, that is, the above-described PR (B, 2).
A, B) is difficult to obtain, and it is more appropriate to use asymmetric partial response characteristics PR (α, β, γ). That is, RLL (1,
7) Encoding such as RLmin = 2 such as encoding is performed, and the partial response characteristic at the time of reproduction is PR (α,
β, γ), there are six types of identification point values (FIG. 14).
C001, C011, C110, C101, C00 in
0 and C111), resulting in 6 values and 4 states.

The factors that make it difficult to obtain the ideal partial response characteristics include the limitation of the operation accuracy of the waveform equalizer, asymmetry caused by the recording laser power being too large or too small, ie, the asymmetry of the waveform, And a phase error of a read clock used when the A / D converter performs sampling from the reproduced signal.

FIG. 15 shows an overall configuration of an embodiment of the present invention. The same components as those in the example of the magneto-optical disk device described above with reference to FIG. Although the recording system and the servo system are not shown, they may be the same as those of the above-described magneto-optical disk device.

The sampled reproduced RF signal value z [k], which is the output of the A / D converter 12, is output to the Viterbi decoder 1
30 and the shift register 107. The Viterbi decoder 130 selects the maximum likelihood state transition based on the reproduced RF signal value z [k], and generates state data vm [k] representing a sequence of the selected state transition and decoded data. Then, the state data vm [k] is supplied to the timing generator 100, and the decoded data is supplied to the controller 2.

The timing generator 100 generates six types of sampling signals VG _P , VG _Q , V _{G R} , V _{G S} , V _{G T} , and V _G based on the state data vm [k].
_U , and these sampling signals are used to detect phase error and offset (Phase Error and Offset, hereinafter, P
EO). On the other hand, the shift register 107 holds the reproduction RF signal value z [k] for a predetermined time, and thereafter supplies it to the PEO block 106.

As will be described later, the PEO block 106 performs sampling from the reproduced RF signal value z [k] according to six types of sampling signals. Then, a standardized phase error signal PE as described later is generated based on the sampling value, and the standardized phase error signal PE is supplied to the D / A converter 108. The PEO block 106 has a function of detecting a DC offset, and a predetermined signal (not shown) expressing the DC offset.
Is output. The D / A converter 108 performs D / A conversion on the supplied signal and supplies the signal to the VCO 110 via the filter 109. Thus, the read clock DCK is generated by controlling the frequency of the VCO 110 by the phase error signal PE.

The read clock DCK is supplied to the A / D converter 1
2. Viterbi decoder 130, timing generator 10
0, shift register 107, PEO block 106, D
/ A converter 108, controller 2 and the like. The operation timings of these components follow the read clock DCK.

The Viterbi decoder 130 will be described in more detail with reference to FIG. The Viterbi decoder 130 outputs
It has MC 132, ACS 133, SMU 134, and merge block 135. BMC132 and ACS
133, for example, the BMC 20 and the ACS 2 in the example of the magneto-optical disk device described above with reference to FIG.
1 may be used. However, in order to match the notation method of the state described above, the selection signal generated by the ACS 133 is set to SE.
L00 and SEL11.

The SMU 134 is based on the selection signals SEL00 and SEL11 supplied from the ACS 133,
State data expressing the selected state transition itself is generated and supplied to the merge block 135. The merge block 135 generates decoded data based on the supplied state data.

The SMU 134 will be described in more detail. The PMU 23 described above with reference to FIG. 10 and the like performs processing in units of 1-bit decoded data values, whereas the SMU 134 performs processing in units of 2-bit state data values. .

As shown in FIG. 17, the SMU 134
Has two A-type status memories 150 and 151 and two B-type status memories 152 and 153. A-type status memories 150 and 151 correspond to states S00 and S11, respectively. The B-type status memories 152 and 153 store the statuses S01 and S1, respectively.
Corresponds to 10. The connection between these four status memories is in accordance with the state transition diagram shown in FIG.

Next, the A-type status memory 150 corresponding to the state S00 will be described with reference to FIG.
The A-type status memory 150 has n processing stages. That is, n selectors 201 ₀ ... 201
_n-1 and n registers 202 ₀ ... 202 _n-1 are connected alternately. Each selector 201 _{0 to} 201
_The select signal SEL00 is supplied to _n-1 . Further, as described above, the state data inherited from the B-type status memory 153 corresponding to S10 is supplied to each selector as SMin having n bits. Also,
As described above, each register has B corresponding to S01.
The state data inherited by the type status memory 152 is n
It is output as SMout consisting of bits. Each of the registers 202 _{0 to} 202 _n-1 has a read clock D
CK is supplied.

The operation of each selector will be described. FIG.
As shown in FIG. 5, the state one clock before, which can transition to S00, is one of S00 and S10. When the state one clock before is S00, a transition that inherits itself is performed. Therefore, the first-stage selector 20
1 to _0, as the latest state data value in the state data generated by the serial shift, 00 are input.
In addition, the selector 201 _0, as a parallel load,
The latest status data value SMin in the status data supplied from the B-type status memory 153 corresponding to S10
[1] is supplied. The selector 201 ₀ supplies one of these two state data values to the register 202 ₀ at the subsequent stage according to the above-mentioned selection signal SEL00.

Further, each of the selectors 201 ₁ to 201 ₁ to
201 _n-1 is two data, ie, one state data value supplied from the B-type status memory 153 corresponding to S10 as a parallel load and one state supplied from the preceding register as a serial shift. And data values. Then, from these two state data, the state data value determined to be the maximum likelihood is supplied to the subsequent register according to the selection signal SEL00. All of the selectors 201 _{0 to} 201 _n-1 have the same selection signal SEL0.
Since it follows 0, the state data as the series of the maximum likelihood state data value selected by the ACS 21 is inherited.

Further, each of the registers 202 _{0 to} 202 _n-1
Updates the held state data value by capturing the supplied state data value according to the clock as described above. Further, as described above, the output of each register is supplied to the status memory corresponding to a state to which a transition can be made after one clock. That is, since the transition can be made to S00 itself, it is supplied to the subsequent selector as a serial shift. The data is supplied to the B-type status memory 153 corresponding to S01 as a parallel load.
From the register 202 _{n-1 at the} last stage, the state data value VM0
0 is output. By outputting state data value VM00 in accordance with read clock DCK, state data is generated as a whole.

The A-type status memory 151 corresponding to the state S11 is configured similarly to the A-type status memory 150, and outputs the state data value VM11 from the last register.

On the other hand, the B-type status memory 152 corresponding to the state S01 will be described with reference to FIG.
The B-type status memory corresponds to a state in which it does not inherit itself in FIG. 14 and only one state can transition after one clock. Therefore, no serial shift is performed, and no selector is provided. Therefore, n registers 212 ₀ , 212 ₁ ,..., 21
2 _n-1 are provided, and the read clock DCK
Is supplied to adjust the operation timing.

Each register 212 ₀ , 212 ₁ ,... 2
12 _n−1 is an SM having n bits of status data inherited from the A-type status memory 150 corresponding to S00.
supplied as in. However, the register 212 ₀ on the first processing stage, always 00 are inputted in synchronism with the read clock DCK. In this operation, as shown in FIG. 14, the latest state transition up to S01 is always S00 → S
It corresponds to 01. Each register 212 _0-
212 _n-1 updates the held state data value by taking in the supplied state data value according to the read clock DCK.

The output of each register is the A-type status memory 15 corresponding to the state S11 which can transition after one clock as the state data SMout of n bits.
1 is supplied. The state data value VM01 is output from the register 212 _{n-1 at the} last stage. State data value VM0
By outputting 1 in accordance with the clock, state data is generated as a whole.

The B-type status memory 153 corresponding to the state S10 is configured similarly to the B-type status memory 152, and outputs the state data value VM10 from the last register.

Incidentally, in the Viterbi decoding method, the state data values VM00, V
M11, VM01 and VM10 match each other if the memory length n of the status memory is made sufficiently large. In such a case, any of the state data values generated by the four status memories may be output to the subsequent stage as sm [k + n]. The memory length n is determined in consideration of the C / N of the reproduced signal, frequency characteristics, and the like.

In this case, if the timing for sampling P to U is obtained based on the status data which is the final output of the SMU block 134, the loop band of the PLL becomes low. In consideration of this point, the maximum likelihood state at that time may be determined from the middle stage of the SMU block 134, and the timing for sampling P to U may be obtained based on the determined maximum likelihood state. Such a method is often used for phase error detection in the actual Viterbi determination mode.

If the memory length n is too large, S
In consideration of a problem such as an increase in the decoding delay time due to the operation time of the MU 134, the memory length n is not increased so much, and the most accurate value is prepared in case the four state data values do not match. It may be configured to include a circuit for selecting a proper state data value.

Next, the merge block 135 will be described. The merge block 135 has a storage unit such as a ROM, for example, and stores a decoding matrix table shown in FIG. 20 in the storage unit. Then, it refers to the decoding matrix and generates decoded data based on the state data. From the state transition diagram shown in FIG. 14, it can be seen that the decoded data value corresponds to two continuous state data values. For example, sm [k + n] is '01' and sm [k + n
-1] is '00', the decoded data value is '1'
Corresponds. Such a correspondence is summarized in the decoding matrix table of FIG.

Next, generation of the phase error signal will be described in more detail. In the state transition diagram shown in FIG.
Six types of identification point values C001, C011, C110, C
101, C000 and C111 undergo state transition S00 → S
01, S01 → S11, S11 → S10, S10 → S0
0, S00 → S00 and S11 → S11, respectively. In addition, P, Q,
Each value of R, S, T, and U indicates a reproduced RF signal value when each state transition occurs. Specifically, it is as follows.

P: Corresponds to S00 → S01, the reproduced RF signal value at the rise time Q: Corresponds to S01 → S11, and the reproduced RF signal value one clock after the rise time R: Corresponds to S11 → S10 Playback R when falling
F signal value S: Corresponds to S10 → S00, reproduction RF signal value one clock after the falling point T: Corresponds to S00 → S00, minimum value of reproduction RF signal value U: Corresponds to S11 → S11, reproduction Maximum value of RF signal value Based on the state transition detected by the Viterbi decoder, it is possible to obtain timings for sampling these six types of values. As described above, a sampling signal indicating such timing is generated by the timing generator 100 and supplied to the PEO block 106.

The generation of the sampling signal will be described more specifically with reference to FIG. FIG. 21A shows the reproduction RF
4 shows an example of a signal. Here, the sampling points according to the clock in the A / D converter 12 are shown with black circles. The state selected at each time point is shown below the reproduced RF signal. Further, the display of P, Q, R, and S attached to each sampling point is specified as described above based on the state selected at each time point.

Further, sampling signals VG _P , VG for taking in sampling values corresponding to P, Q, R, S
_Q, VG _R, VG _S is FIG. 21B, FIG. 21C, FIG. 21D,
It can be seen that what is shown in FIG. 21E is sufficient. In one embodiment of the present invention, FIG.
21G and sampling signal VG _T shown in FIG. 21G, respectively.
Accordance and VG _U, minimum T, and S11 → S11 in the reproduction RF signal value corresponding to the state transition S00 → S00
Is taken in.

In general, the larger the phase error, the larger the difference between the sampling values sampled from the trapezoidal portion including the rising portion and the falling portion. Therefore, by QR and PS shown in FIG. 21A,
The phase error can be expressed. That is, for example, the following calculated value based on the sampling value can be used as the phase error signal.

(A) QR (b) PS (c) P + Q-DC level (d) R + S-DC level When an actual phase error signal is detected, (a) to (d)
And calculating the calculated value as a phase error signal, calculating a plurality of values as the phase error signal, calculating a plurality of the signals by time division, and calculating the calculated value as the phase error signal. And other methods can be used. Generally, the sum of (a) and (b) is used as the phase error signal PE as in the following equation (40).

PE = (PS) + (Q−R) (40) Such a phase error signal PE depends on the amplitude of the reproduced RF signal. For example, if the amplitude of the reproduction RF signal is set to be large by the settings of the amplifiers 8 and 9 and the filter unit 11 in FIG. 15, the reproduction RF signal value sampled from the reproduction RF signal (the output of the A / D converter 12) ) Grows larger,
As a result, the value of the phase error signal PE generated according to the equation (40) increases. Conversely, if the amplitude of the reproduced RF signal is small, the value of the phase error signal PE generated according to Expression (40) becomes small. Thus, the playback R
Since the gain of the PLL changes depending on the magnitude of the F signal, the PLL becomes unstable unless the amplitude of the reproduced RF signal is properly managed.

Therefore, the phase error signal is normalized by the amplitude of the reproduced RF signal. In the 6-value 4-state Viterbi decoding method, as described above, the amplitude of the reproduced RF signal can also be obtained by sampling according to the timing obtained from the state data output from the Viterbi decoder. That is,
Since the value of T and the value of U sampled as described above with reference to FIG. 21 indicate the minimum value and the maximum value of the amplitude, respectively, the amplitude of the reproduced RF signal is calculated as follows. You.

Amplitude = U−T (41) Therefore, Expression (40) can be normalized as follows using Expression (41).

PE = {(PS) + (Q−R)} / (UT) (42) The PEO block 106 generates a standardized phase error signal PE calculated by the equation (42). . Therefore, P
The EO block 106 includes, for example, P, Q, R, S, T,
What is necessary is just to have the structure which has the register holding each sampling value of U, the arithmetic circuit which performs subtraction, addition, division, etc., etc. PLL using standardized phase error signal PE
Is locked, the loop band of the PLL can be determined without concern for the amplitude of the reproduced RF signal.

Further, as described above, in the Viterbi determination mode, each reproduced RF signal value sampled by the A / D converter 12 corresponds to any of the sampling points P to U, but the Viterbi decoder 130 generates It is determined based on the state data to be performed. Therefore, it is necessary to store the reproduced RF signal value for a delay time from when the reproduced RF signal value is input to the Viterbi decoder 130 to when the state data is generated. Such storage of the reproduction RF signal value is as follows.
In one embodiment of the present invention, this is performed by the shift register 107 in FIG.

One embodiment of the present invention described above is a six-value four
The present invention is applied to a magneto-optical disk device that performs a state Viterbi decoding method. On the other hand, a magneto-optical disk device that performs another type of Viterbi decoding method such as the above-described four-value four-state Viterbi decoding method, three-value four-state Viterbi decoding method, and seven-value six-state Viterbi decoding method, The present invention can be applied.

While the above-described embodiment of the present invention is applied to the case where the phase error is detected in the Viterbi determination mode, the present invention is applied to the case where the phase error is detected in the MSB determination mode. Other embodiments of the present invention to which the present invention is applied are also possible.

Another embodiment of the present invention will be described below with reference to FIG. 22, the same components as those in FIG. 1 or FIG. 15 are denoted by the same reference numerals. Although the recording system and the servo system are not shown, they may be the same as those of the above-described magneto-optical disk device. Further, in the other embodiment of the present invention, similarly to the above-described embodiment of the present invention, the above-described six-value and four-state is assumed.

The sampled reproduced RF signal value z [k], which is the output of the A / D converter 12, is output to the Viterbi decoder 2
30 and the shift register 207. At the same time, the MSB (Most Significant) of the reproduced RF signal value z [k]
ant Bit) is supplied to the timing generator 200. The Viterbi decoder 230 selects the most likely state transition based on the reproduced RF signal value z [k], generates decoded data based on the selected state transition, and supplies the decoded data to the controller 2. Also, the shift register 207
The reproduction RF signal value z [k] is held for a predetermined time, and then
It is supplied to the O block 207. For this reason, the PEO block 207 outputs the reproduced RF signal value z [k−k
p].

On the other hand, the timing generator 200
As described later, the change of the MSB (from “1” to “0” or “0”)
→ Sampling signals MG _P , MG _Q , MG _R , MG _S , MG _T , which perform sampling necessary for generation of a phase error signal by detecting a point in time at which “1” occurs.
It generates MG _U, a signal indicating the generated timing PE
It is supplied to the O block 206.

As will be described later, the PEO block 206 performs sampling from the reproduced RF signal value z [k] according to six types of sampling signals. Then, a standardized phase error signal PE as described later is generated based on the sampling value, and the standardized phase error signal PE is supplied to the D / A converter 108. D / A converter 108
Converts the supplied signal into a digital signal and supplies it to the VCO 110 via the filter 109. In this way, VC
The read clock DCK is generated by controlling the frequency of O110 by the phase error signal PE.

The read clock DCK is supplied to the A / D converter 1
2. Viterbi decoder 230, timing generator 20
0, shift register 207, PEO block 206, D
/ A converter 108, controller 2 and the like. The operation timings of these components follow the read clock DCK.

The sampling signals MG _P , MG _Q ,
_{MG R, MG S, MG T} , generation of MG _U, and will be described in more detail the generation of the phase error signal associated with them. In the MSB determination mode, the timing of the rise and fall of the reproduction RF signal is determined by the MSB of the reproduction RF signal value.
Is obtained based on the timing of the change. For example, A /
When the D converter 12 is a 2's complement representation, the MSB
Rises from '1' to '0',
When the MSB changes from “0” to “1”, it can be determined that the rising of the reproduction RF signal has occurred.

The generation of the sampling signal will be specifically described with reference to FIG. FIG. 23A shows an example of the reproduced RF signal. Here, the sampling points according to the clock in the A / D converter 12 are shown with black circles. The state selected at each time point is shown below the reproduced RF signal.

Since the reproduced signal value one clock before the point when the change of the MSB from '0' to '1' is detected can be recognized as the sampling value P at the rising point, the value of P is sampled. sampling signal MG _P of approximately 1 clock width from the rise time is set (see FIG. 23C). Furthermore, since the sampling value at the time of one clock after the rising time can be recognized is Q, in order to sample the value of Q, sets the sampling signal MG _Q was approximately 1 clock delay from MG _P (see FIG. 23D).

On the other hand, the value of R can be sampled because the reproduction signal value at the point one clock before the point when the change of the MSB from '1' to '0' is detected can be recognized as the sampling value R at the falling point. sampling signal MG _R of approximately one clock width is set from the rising point to (Fig. 23
E). Furthermore, since the sampling value at the time of one clock after the rising time can be recognized and S, in order to sample the value of S, to set the sampling signal MG _S was approximately 1 clock delay from MG _R (see FIG. 23F).

The sampling values P, Q, R, and S sampled in this manner have the same meanings as the respective sampling values given the same reference numerals in the above-described Viterbi determination mode. Therefore, the phase error can be calculated by the same calculation as in the above-described Viterbi determination mode. For example, the phase error PE in the MSB determination mode can be obtained by a calculation formula similar to the above formula (40).

PE = (PS) + (Q−R) (40) ′ Similarly to the case of the above-mentioned Viterbi determination mode, the equation (4)
0) ′ is the phase error signal PE
Since it depends on the amplitude of the signal, there is a problem that the PLL becomes unstable unless the amplitude of the reproduced RF signal is properly managed.

Thus, the phase error signal is normalized by the amplitude of the reproduced RF signal. In the 6-value 4-state Viterbi decoding method, at the timing other than the rising and falling, either the maximum amplitude value or the minimum amplitude value of the reproduced RF signal is sampled. Therefore, it can be seen that the sampling values sampled at times other than the sampling time for taking in the values of P, Q, R, and S are as follows. First, the MSB at the time of sampling is “0”.
Then, such a sampling value is the minimum amplitude value T of the RF signal. MSB at the time of sampling
Is “1”, such a sampling value is the maximum amplitude value U of the RF signal.

The phase error signal can be normalized using the values of T and U sampled as described above. That is, for example, a standardized phase error signal PE in the MSB determination mode can be obtained by a calculation formula similar to the above formula (42).

PE = {(PS) + (Q−R)} / (UT) (42) ′ The PEO block 206 calculates the standardized phase error signal PE calculated by the equation (42) ′. Generate. By employing a configuration in which the PLL is locked using the standardized phase error signal PE, the loop band of the PLL can be determined without concern for the amplitude of the reproduced RF signal.

Note that, in another embodiment of the present invention, the present invention is applied to a device that performs the Viterbi decoding method. However, the MSB determination mode is not based on the state transition selected when performing the Viterbi decoding method. Since there is no Viterbi decoder 230, the Viterbi decoder 230 is not limited to one having a function of generating state data, but may be one that generates only decoded data. Even if a decoding method other than the Viterbi decoding method such as a bit-by-bit decoding method is performed, the MSB
The present invention can be applied to a device configured to lock the PLL using the determination mode.

Also, the present invention relates to an information reproducing apparatus for decoding read data from a reproduced signal reproduced from data recorded on a recording medium, wherein the PLL is locked based on a phase error signal. The present invention can be applied to an information reproducing apparatus configured to generate a clock for instructing the operation timing. That is, in addition to the magneto-optical disk (MO), for example, the phase-change disk P
The present invention can be applied to optical disk devices such as rewritable disks such as D and CD-E (CD-Erasable), write-once disks such as CD-R, and read-only disks such as CD-ROM.

Further, the present invention is not limited to this embodiment, and various applications and modifications can be considered without departing from the gist of the present invention.

[0197]

As described above, the present invention generates a phase error signal based on a reproduction signal reproduced from a recording medium, and locks a PLL based on the phase error signal, thereby enabling the operation timing of the apparatus to be adjusted. In an information reproducing apparatus that generates a commanding clock, a phase error signal standardized by the amplitude of a reproduced signal is generated.

Therefore, even if the amplitude of the reproduced RF signal fluctuates due to a change in setting of an amplifier, a filter, or the like, exchange of a recording medium, or the like, such amplitude fluctuation affects the magnitude of the phase error signal. Can be avoided or the extent can be reduced. Therefore, it is possible to prevent the amplitude fluctuation from affecting the operation of the PLL or to reduce the degree thereof.

Therefore, in order to ensure the stability of the operation of the PLL, when the recording medium is exchanged or the like, for example, by adjusting the operation parameters of the components such as the amplifier and the filter in the operation such as calibration, the reproduction RF signal is adjusted. This eliminates the need to manage the signal amplitude. For this reason, it is possible to simplify operations such as calibration and to reduce the number of times.

As a result, the time spent for controlling the operation of the apparatus can be reduced, which can contribute to the improvement of the performance of the apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an example of a magneto-optical disk device that performs a 4-value 4-state Viterbi decoding method.

FIG. 2 is a schematic diagram for explaining a mark position recording method and a mark edge recording method.

FIG. 3 is a schematic diagram for explaining an example of a sector format of a magneto-optical disk.

FIG. 4 is a schematic diagram showing that the minimum magnetization reversal width is 2 in the RLL (1, 7) encoding method.

FIG. 5 shows a reproduction signal reproduced from data recorded by a combination of an RLL (1, 7) code and a mark edge recording method, with a partial response characteristic PR (1, 2, 2).
FIG. 6 is a schematic diagram for explaining an eye pattern when waveform equalization is performed under 1).

FIG. 6 is a schematic diagram for explaining a process of creating a state transition diagram of the 4-value 4-state Viterbi decoding method.

FIG. 7 is a schematic diagram illustrating an example of a state transition diagram of a 4-value 4-state Viterbi decoding method.

FIG. 8 is a schematic diagram illustrating an example of a trellis diagram in a 4-level 4-state Viterbi decoding method.

FIG. 9 is a schematic diagram showing conditions of state transition based on a standardized metric in a four-value four-state Viterbi decoding method.

FIG. 10 is a block diagram illustrating an overall configuration of a Viterbi decoder that performs 4-level 4-state Viterbi decoding.

11 is a block diagram showing in detail a configuration of a part of the Viterbi decoder shown in FIG.

FIG. 12 is a block diagram showing the configuration of another part of the Viterbi decoder shown in FIG. 10 in detail.

FIG. 13 is a block diagram showing the configuration of yet another portion of the Viterbi decoder shown in FIG. 10 in detail.

FIG. 14 is a schematic diagram illustrating an example of a state transition diagram of a 6-value 4-state Viterbi decoding method.

FIG. 15 is a block diagram for describing an overall configuration of an embodiment of the present invention.

FIG. 16 is a block diagram illustrating an example of a Viterbi decoder used in an embodiment of the present invention.

17 is a block diagram illustrating an example of a configuration of a status memory unit (SMU) in the Viterbi decoder of FIG.

18 is a block diagram for describing a partial configuration of the SMU shown in FIG.

FIG. 19 is a block diagram illustrating another configuration of another part of the SMU shown in FIG. 17;

FIG. 20 is a schematic diagram illustrating an example of a matrix table referred to in a merge block according to an embodiment of the present invention.

FIG. 21 is a schematic diagram illustrating sampling for generating a phase error signal in a Viterbi determination mode.

FIG. 22 is a block diagram for describing an overall configuration of another embodiment of the present invention.

FIG. 23 is a schematic diagram illustrating sampling for generating a phase error signal in the MSB determination mode.

[Explanation of symbols]

12 ... A / D converter, 130 ... Viterbi decoder,
100 timing generator, 106 P
EO, 200 ... timing generator, 206
..PEO

Claims (9)

[Claims] 1. A phase error signal is generated based on a reproduction signal reproduced from a recording medium, and a phase error signal is generated based on the phase error signal.
An information reproducing apparatus wherein a clock for commanding the operation timing of the apparatus is generated by locking the LL to generate a phase error signal standardized by the amplitude of the reproduced signal. Playback device. 2. An A / D conversion means for A / D converting a reproduced signal; a Viterbi decoding means for performing Viterbi decoding based on an output of the A / D conversion means to generate decoded data; Timing generating means for generating sampling timing required for generating a phase error signal standardized by the amplitude of the reproduction signal from the output of the A / D conversion means based on the state transition selected by An information reproducing apparatus, comprising: performing sampling in accordance with an output of the timing generation means, and generating a phase error signal standardized by an amplitude of the reproduction signal based on the sampling value. 3. The information reproducing apparatus according to claim 2, wherein the sampling timing includes a timing for sampling a maximum value and a minimum value of the reproduction signal. 4. The method according to claim 3, wherein an amplitude of the reproduced signal is calculated as a difference between a maximum value and a minimum value of the sampled reproduced signal, and an operation for normalizing the phase error signal is performed based on the calculated amplitude. An information reproducing apparatus characterized in that the information is reproduced. 5. An A / D converter for A / D-converting a reproduction signal, and the A / D converter based on a part of an output of the A / D converter.
Timing generation means for generating sampling timing required for generating a phase error signal standardized by the amplitude of the reproduction signal from the output of the D conversion means, and sampling according to the output of the timing generation means. And generating a phase error signal standardized by the amplitude of the reproduction signal based on the sampling value. 6. The information reproducing apparatus according to claim 5, wherein a part of the output of the A / D converter is an MSB of the output of the A / D converter. 7. The information reproducing apparatus according to claim 5, wherein the sampling timing includes a timing for sampling a maximum value and a minimum value of a reproduction signal. 8. The method according to claim 7, wherein an amplitude of the reproduced signal is calculated as a difference between a maximum value and a minimum value of the sampled reproduced signal, and an operation for normalizing the phase error signal is performed based on the calculated amplitude. An information reproducing apparatus characterized in that the information is reproduced. 9. A clock for instructing an operation timing of a device is generated by generating a phase error signal based on a reproduction signal reproduced from a recording medium and locking a PLL based on the phase error signal. The information reproducing method according to claim 1, wherein a phase error signal standardized by an amplitude of the reproduced signal is generated.