JP4254799B2 - Information playback device - Google Patents

Description

  The present invention relates to an information reproducing apparatus applicable to a reproducing apparatus that reproduces data from a disc-shaped recording medium and performs Viterbi decoding.

  In digital signal reproducing apparatuses, it is becoming practical to use Viterbi decoding to detect a reproduced digital signal. Viterbi decoding is a decoding method that selects a most likely decoded data value from possible decoded data values, that is, generates a decoded data sequence. The Viterbi decoder has a path memory for n channel clocks. In general, the longer the memory length of the path memory, the higher the accuracy of the decoded data.

  However, when the memory length is increased, there is a high possibility that the inaccuracy of the calculated value of the metric is increased due to the influence of the defect when the disk has a defect. In addition, the delay due to the Viterbi decoder increases, the time difference between the data entering the disk controller and the data being read from the disk increases, and the control of reading data from the disk may become complicated.

  For example, when the reproduction process is performed in real time and the delay between reading data from the disk and the time for the disk controller to decode the decoded data is very small, the disk controller is in a predetermined area on the disk (on the disk). It is possible to move to the next operation after recognizing that the predetermined area) in the data format has been read. However, in the case where the delay in the reproduction system from when the disk is read to when the read data is given to the disk controller is long, it is necessary for the disk controller to start the next operation before confirming reading of a predetermined area. If the system is operating normally, there is no problem with this method, but if the disk controller cannot confirm the signal that should be read out, take the necessary measures to perform normal operation. There is a need. Thus, a problem that the memory length is too long also causes a problem.

  As described above, if the memory length of the path memory is too short, the reliability of the decoded data will be low, and if it is too long, the system will be susceptible to disk defects or the delay due to decoding will increase. There are complications. Therefore, it is necessary to set the memory length optimally.

  Accordingly, an object of the present invention is to provide an information reproducing apparatus capable of optimizing the memory length in the Viterbi decoder according to reproduction conditions such as characteristics of a recording medium to be recorded / reproduced. is there.

In order to solve the above problems, the present invention provides an information reproducing apparatus that decodes a reproduction signal reproduced from a recording medium by a Viterbi decoding method,
The reproduction signal is supplied to the Viterbi decoding means,
In Viterbi decoding means, to generate a decoded data as a sequence of the maximum likelihood state transition and the corresponding decoded data values to be selected as the setting of the memory length of the path memory,
When decoding the reproduction signal of the first area, which is an area where pits are formed by embossing , select the output of a predetermined register,
A recordable data area, in case of decoding the reproduction signal of the second region, so that memory length indicated by the control data, so as to select the output of register, controls the output selector ,
The memory length of the path memory when decoding the reproduction signal of the first area is set to be shorter than the memory length of the path memory when decoding the reproduction signal of the second area An information reproducing apparatus.

The present invention is an information reproducing apparatus for decoding a reproduction signal reproduced from a recording medium by a Viterbi decoding method,
The reproduction signal is supplied to the Viterbi decoding means,
In Viterbi decoding means, to generate a status data as a sequence of the maximum likelihood state transition and the corresponding status data values to be selected as the setting of the memory length of the state memory,
When decoding the reproduction signal of the first area, which is an area where pits are formed by embossing , select the output of a predetermined register,
A recordable data area, in case of decoding the reproduction signal of the second region, so that memory length indicated by the control data, so as to select the output of register, controls the output selector ,
The memory length of the path memory when decoding the reproduction signal of the first area is set to be shorter than the memory length of the path memory when decoding the reproduction signal of the second area An information reproducing apparatus.

  Since the memory length of the path memory or the state memory is variable in the Viterbi decoding method according to the present invention, the memory length can be easily optimized according to the reproduction conditions. In other words, the quality of the playback data is affected by various factors such as recording conditions and disc sensitivity. Therefore, by adopting a configuration in which the memory length can be varied, playback signals of various quality can be viewed from the entire system. An optimum memory length can be obtained.

  Even in the case of the same optical disk, the frequency characteristic of the reproduction signal changes in the radial direction, so that even if the cut-off frequency of the filter and the boost frequency are matched with each other, some deviation occurs. In this case, the optimum memory length is different in the radial direction. Even in such a case, the present invention can change the memory length at the radial position, so that Viterbi decoding can be performed satisfactorily.

  An embodiment of the present invention will be described below. FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. At the time of recording, the controller 2 receives user data to be recorded in accordance with a command from the host computer 1, performs encoding based on the user data as an information word, and generates an RLL (1, 7) code as a code word. This code word is supplied as recording data WDATA to a laser power control unit (hereinafter referred to as LPC) 4.

  WGATE is a recording control signal that is active during a recording operation period, and RGATE is a reproduction control signal that is active during a reproducing operation period. These control signals are also supplied to the LPC 4. In addition to such processing, the controller 2 performs operations such as decoding processing, which will be described later, control of each mode such as recording, reproduction, and deletion, and communication with the host computer 1.

  The LPC 4 performs recording by controlling the laser power of the optical pickup 7 to form pit rows having magnetic polarity on the magneto-optical disk 6 in accordance with the supplied recording data. During this recording, the magnetic head 5 applies a bias magnetic field to the magneto-optical disk 6. Actually, mark edge recording as described later is performed in accordance with a precode output generated as described later based on the recording data.

  A method of associating each pit formed as described above with each bit in the precode output generated as described later based on the recording data will be described with reference to FIG. A recording method in which pits are formed for, for example, “1” and pits are not formed for “0” during precode output is referred to as a mark position recording method. On the other hand, a recording method in which the polarity inversion at the boundary of each bit in the precode output expressed by the edge of each pit corresponds to, for example, “1” is referred to as a mark edge recording method. At the time of reproduction, the boundary of each bit in the reproduction signal is recognized according to a read clock DCK generated as described later.

Next, the configuration and operation of the reproduction system will be described. The optical pickup 7 irradiates the magneto-optical disk 6 with laser light and receives reflected light generated thereby to generate a reproduction signal. The reproduction signal is composed of four types of signals: a sum signal R ₊ , a difference signal R _{−, a} focus error signal (not shown), and a tracking error signal. The sum signal R ₊ is supplied to the changeover switch 10 after gain adjustment or the like is performed by the amplifier 8. The difference signal R ₋ is supplied to the changeover switch 10 after gain adjustment and the like by the amplifier 9. Further, the focus error signal is supplied to a means (not shown) for eliminating the focus error. On the other hand, the tracking error signal is supplied to a servo system (not shown) and used in their operation.

A changeover signal S as described later is supplied to the changeover switch 10. The changeover switch 10 supplies the sum signal R ₊ or the difference signal R ₋ to the filter unit 11 in accordance with the changeover signal S. That is, in a sector format of the magneto-optical disk 6 as will be described later, during a period in which a reproduction signal reproduced from a first signal recording area (referred to as a header area) formed by embossing is supplied to the changeover switch 10. The sum signal R ₊ is supplied to the filter unit 11. Further, the difference signal R ₋ is supplied to the filter unit 11 during a period in which a reproduction signal reproduced from the second signal recording area (referred to as a data area) recorded magneto-optically is supplied to the changeover switch 10. .

  The switching signal S is generated as follows, for example. That is, first, a signal reproduced from a predetermined pattern defined in the sector format is detected from the reproduced signal. As such a predetermined pattern, for example, a sector mark SM described later is used. Then, the switching signal S is generated at a predetermined time point recognized by a method such as counting a read clock described later with reference to the time point when such detection is made. Further, the switching signal S is supplied not only to the selector switch 10 but also to the Viterbi decoder 13, and is controlled to switch the memory length of the path memory between the header area and the data area.

  The filter unit 11 includes a low-pass filter that performs noise cut and a waveform equalizer that performs waveform equalization. As will be described later, the waveform equalization characteristics used in the waveform equalization processing at this time are adapted to the Viterbi decoding method performed by the Viterbi decoder 13. The A / D converter 12 supplied with the output of the filter unit 11 samples the reproduction signal value z [k] according to the read clock DCK supplied as described later. The Viterbi decoder 13 generates decoded data by the Viterbi decoding method based on the reproduction signal value z [k]. Such decoded data is a maximum likelihood decoded sequence for the recorded data recorded as described above. Therefore, when there is no decoding error, the decoded data matches the recorded data.

  The decoded data is supplied to the controller 2. As described above, the recording data is a codeword generated from user data by encoding such as channel encoding. Therefore, if the decoding error rate is sufficiently low, the decoded data can be regarded as recorded data as a code word. The controller 2 reproduces user data and the like by performing decoding processing corresponding to the above-described encoding such as channel encoding on the decoded data. Further, the controller 2 controls calibration.

  The output of the filter unit 11 is also supplied to the PLL unit 14. The PLL unit 14 generates a read clock DCK based on the supplied signal. As an example, the PLL unit 14 is configured to detect a phase error using a signal having a constant frequency recorded in the magneto-optical disk 6. The read clock DCK is supplied to the controller 2, the A / D converter 12, the Viterbi decoder 13, and the like. The operations of the controller 2, the A / D converter 12, and the Viterbi decoder 13 are performed at a timing according to the read clock DCK. Further, the read clock DCK is supplied to a timing generator (not shown). The timing generator generates a signal for controlling the operation timing of the apparatus such as switching between recording / reproducing operations.

  Further, a CPU 15 connected to the controller 2 is provided. The CPU 15 supplies a control signal for laser power setting to the LPC 4 to control positioning of the optical pickup 7 or the like. A register 16 is coupled to the CPU 15. The register 16 stores control data for setting the gains of the amplifiers 8 and 9 in the reproduction system, the equalization characteristics of the filter 11, and the memory length of the path memory of the Viterbi decoder 13 from the CPU 15. The control data is generated by the controller 2 by calibration and is stored in the register 16 via the CPU 15. The above-described gain and memory length are optimized by the control data Reg output from the register 16.

  In the reproduction operation as described above, in order to obtain more accurate reproduction data based on the reproduction signal reproduced from the magneto-optical disk 6, reproduction system parameters (that is, the gains of the amplifiers 8 and 9, the characteristics of the filter unit 11). The memory length of the Viterbi decoder 13) is optimized. Such an operation is calibration. For calibration, the quality of the playback signal may change depending on the characteristics of the recording medium, such as processing accuracy, and the recording / playback conditions, such as fluctuations in the power of the recording laser beam, ambient temperature, etc. This is for optimizing the parameters of the reproduction system to cope with the above. Calibration is performed in the controller 2 immediately after the power is turned on or when the recording medium is replaced.

  Next, an outline of the track format and sector format of the magneto-optical 6 will be described. FIG. 3 shows an example of a track format. An opening 6a is provided at the center of the disc, and a reflection zone 6b, a control track PEP (Phase Encoded Part) zone 6c, a transition zone 6d, an inner control track SFP (Standard Formatted Part) 6e, an inner manufacture are provided on the innermost circumference side. Zone 6f is provided. Further, an outer manufacture zone 6g, an outer SFP zone 6h, and a lead-out zone 6i are provided on the outermost peripheral side. A space between the inner peripheral area and the outer peripheral area is a user zone 6j that can be used for data recording / reproduction.

  The PEP 6c is provided by phase information. The SFPs 6e and 6h provide medium information (sensitivity, reflectance, etc.) and system information (track number, etc.). Furthermore, the inner manufacture zone 6f and the outer manufacture zone 6g are areas for test lights. At the time of calibration, a test write of data is performed using these zones 6f and 6g.

User data is recorded in the user zone of the magneto-optical disk 6 by using sectors as recording / reproducing units. An example of a sector format used in the magneto-optical disk 6 will be described with reference to FIG. As shown in FIG. 4A, one sector is divided into header, ALPC, gap, VFO ₃ , sync, data field, and buffer areas in the order of recording / reproduction. The numbers given in FIG. 4 represent the number of bytes. On the magneto-optical disk 6, data that has been encoded such as block encoding is recorded. For example, 8 bits are converted into 12 channel bits and recorded.

  In an example of this sector format, a format with a user data amount of 1024 bytes and a format with a user data amount of 512 bytes are prepared. In the format in which the user data amount is 1024 bytes, the number of bytes in the data field is 670 bytes. Further, in the format in which the user data amount is 512 bytes, the number of bytes in the data field is 1278 bytes. In these two sector formats, the 63-byte pre-formatted header, ALPC, and 18 bytes in the gap area are the same.

FIG. 4B shows an enlarged 63-byte header. The header includes a sector mark SM (8 bytes), a VFO field VFO ₁ (26 bytes), an address mark AM (1 byte), an ID field ID ₁ (5 bytes), a VFO field VFO ₂ (16 bytes), and an address. The mark AM (1 byte), the ID field ID ₂ (5 bytes), and the postamble PA (1 byte) are arranged in this order.

  FIG. 4C shows an 18-byte ALPC and gap area in an enlarged manner. The 18 bytes are composed of a gap field (5 bytes), a flag field (5 bytes), a gap field (2 bytes), and ALPC (6 bytes).

Next, these fields will be described. The sector mark SM is a mark for identifying the start of the sector, and has a pattern formed by embossing that does not occur in the RLL (1, 7) code. The VFO field is used to synchronize the VFO (Variable Frequency Oscillator) (or VCO) in the PLL unit 14 and includes VFO ₁ , VFO _2, and VFO ₃ . VFO ₁ and VFO ₂ are formed by embossing. VFO ₃ is written magneto-optically when a recording operation is performed on the sector. VFO ₁ , VFO _2, and VFO ₃ each have a pattern (2T pattern) in which channel bits “0” and “1” appear alternately. Therefore, when the time corresponding to the time length of one channel bit is T, a reproduction signal whose level is inverted every 2T is obtained when the VFO field is reproduced.

The address mark AM is used to give the device byte synchronization for the subsequent ID field and has an embossed pattern that does not occur in the RLL (1,7) code. The ID field includes sector addresses, that is, track number and sector number information, and an error detection CRC byte for these pieces of information. The ID field consists of 5 bytes. The same address information is recorded _twice by ID ₁ and ID ₂ . The postamble PA has a pattern (2T pattern) in which channel bits “0” and “1” appear alternately. ID ₁ , ID ₂ and postamble PA are also formed by embossing. Thus, the header area is a preformatted area in which pits are formed by embossing.

FIG. 4C shows an enlarged ALPC and gap area. No pit is formed in the gap. The first gap field (5 bytes) is the first field after the preformatted header, which ensures the time it takes for the device to complete processing after reading the header. The second gap field (2 bytes) is for allowing a shift in the position of the subsequent VFO ₃ .

  A 5-byte flag field is recorded in the ALPC and gap area. When the sector data is recorded in the flag field, a continuous 2T pattern is recorded. An ALPC (Auto Laser Power Control) field is provided for testing the laser power during recording. The sync field (4 bytes) is provided for the device to obtain byte synchronization for the following data field and has a predetermined bit pattern.

  The data field is provided for recording user data. The above-mentioned 670-byte data field is composed of 512-byte user data, 144-byte error detection, correction parity, etc., a 12-byte sector write flag, and 2 bytes (FF). In the case of a data field of 1278 bytes, it consists of 1024 bytes of user data, 242 bytes of error detection and correction parity, and a 12-byte sector write flag. The last buffer field of the sector is used as a tolerance for electrical or mechanical errors.

In the example of the sector format described above, the header area is an area where pits are formed by embossing. The ALPC and gap area are areas that are not used during reproduction. Furthermore, the VFO ₃ , the sync field, and the data field are data areas that are magneto-optically recorded.

  FIG. 5 is a flowchart schematically showing the calibration process. However, FIG. 5 shows only the memory length calibration related to the present invention in the parameters of the reproduction system. The gains of the amplifiers 8 and 9, the characteristics of the filter unit 11, and the like can be obtained by a known method. In FIG. 5, for example, when the power is turned on (step S2), the memory length of the path memory is set to the initial value (step S3), and the process is started. Predetermined data is recorded with a predetermined laser power in a test area defined on the magneto-optical disk 6 (for example, the inner manufacture zone 6f described above) (step S3).

  The data recorded in the test area is reproduced, and Viterbi decoding is performed with the initial memory length (generally the shortest memory length). Then, the error rate of the data reproduced in the controller 2 is measured (step S4). Since the expected value (recorded data) is known as a method for measuring the error rate at the time of calibration, a verification method can be used. Of course, the error rate may be measured by other methods. The error rate is a bit unit or a byte unit. By comparing the error rate with a threshold value, it is determined whether or not accurate decoding is performed based on the memory length at that time (step S5). If it is determined that accurate decoding has been performed, calibration is completed (step S6).

  If it is determined in step S5 that the memory length is not appropriate from the error rate, the memory length is changed in step S7 (generally, it is made longer). Since the memory length is naturally finite, it is determined in step S8 whether the memory length exceeds the maximum. Even if the memory length exceeds the maximum, if the error rate is greater than the threshold value, there is a possibility that the magneto-optical disk 6 may be abnormal, so an alarm such as displaying a disk error message is generated (step) S8). In this way, the memory length of the Viterbi decoder 13 can be set appropriately when the power is turned on, the disk is replaced, and the like.

  The calibration described above is a process for appropriately setting the memory length for the data area on the disk. On the disc, there is a header area formed by embossing in addition to the data area. In the case of the header area, since the quality of the reproduction signal is better than that of the data area, the memory length can be made shorter than that of the data area. Therefore, in one embodiment and another embodiment of the present invention, the memory length is switched between the data area and the header area. Furthermore, even in the case of the same magneto-optical disk, the quality of the reproduction signal may differ in the radial direction of the disk. In that case, the recording area of the disk may be divided into a plurality of areas (zones), the optimum memory length is measured in each zone, and the memory length may be switched according to the zone.

  Hereinafter, the Viterbi decoding method performed by the Viterbi decoder 13 will be described. Here, the 4-value 4-state Viterbi decoding method will be described first. As described above, user data is converted into codewords as recording data by various encoding methods. As the encoding method, an appropriate one is adopted according to the properties of the recording medium and the recording / reproducing method. In the magneto-optical disk apparatus, the Run Length, that is, the RLL (Run Length Limited) encoding method that limits the number of “0” between “1” and “1” is often used in block encoding. Conventionally, several RLL encoding methods are used. In general, an m / n block code in which the number of “0” s between “1” and “1” is a minimum of d and a maximum of k is referred to as an RLL (d, k; m, n) code.

  For example, in a 2/3 block code, a block coding method in which the number of “0” s between “1” and “1” is 1 at a minimum and 7 at a maximum is RLL (1, 7; 2, 3) A code. In general, since the RLL (1, 7; 2, 3) code is often referred to as an RLL (1, 7) code, in the following description, when simply expressed as an RLL (1, 7) code, RLL (1 , 7; 2, 3) Let us denote the code.

  A Viterbi decoding method can be used to decode a reproduction signal reproduced from data recorded by a combination of such an RLL encoding method and the mark edge recording method described above.

  Such an RLL encoding method can meet the conditions required for the encoding method from the two viewpoints of improving the recording density and ensuring the stability of the reproduction operation. First, as described above, the mark edge recording method corresponds to the inversion of the polarity expressed by the edge of each pit in the precode output generated as described later based on the recording data. As the number of “0” s between “1” and “1” is increased, the number of bits recorded per pit can be increased. Therefore, the recording density can be increased.

  On the other hand, as described above, the read clock DCK necessary for adjusting the operation timing of the reproduction system is generated by the PLL unit 14 based on the reproduction signal. For this reason, if the number of “0” s between “1” and “1” is increased in the recorded data, the operation of the PLL unit becomes unstable during the reproducing operation, and thus the entire reproducing operation is unstable. Become.

  Considering these two conditions, the number of “0” between “1” and “1” needs to be set within an appropriate range which is neither too much nor too little. The RLL encoding method is effective for setting the number of “0” in the recording data.

  By the way, as shown in FIG. 6, in the combination of the RLL (1, 7) encoding method and the mark edge recording method described above, '1' and '1' in the precode output generated based on the recording data. Since at least one '0' is included between the two, the minimum inversion width is 2. As described later, a quaternary value is used as a method for decoding recorded data from a reproduction signal affected by intersymbol interference and noise when such an encoding method with a minimum inversion width of 2 is used. A four-state Viterbi decoding method can be applied.

As described above, the waveform equalization processing is performed on the reproduced signal by the filter unit 11. For such waveform equalization processing performed as a preceding stage of the Viterbi decoding method, a partial response method that positively uses intersymbol interference is used. The waveform equalization characteristic used at this time is determined in consideration of the linear recording density of the recording / reproducing system and the MTF (Modulation Transfer Function) from among the partial response characteristics generally represented by (1 + D) ⁿ . The waveform equalization processing using PR (1, 2, 1) for the data recorded by the combination of the RLL (1, 7) encoding method and the mark edge recording method described above is a quaternary 4-state Viterbi decoding method. The first stage.

  On the other hand, in the mark edge recording method, prior to actual recording on a magneto-optical disk medium or the like, precoding based on recording data encoded by the above-described RLL encoding or the like is performed. If the recording data string at each time point k is a [k] and the precode output based on this is b [k], the precoding is performed as follows.

b [k] = mod2 {a [k] + b [k-1]} (1)
Such a precode output b [k] is actually recorded on a magneto-optical disk medium or the like. On the other hand, the waveform equalization processing with the waveform equalization characteristic PR (1, 2, 1) performed by the waveform equalizer in the filter unit 11 will be described. However, in the following description, the waveform equalization characteristic is PR (B, 2A, B) without normalizing the amplitude of the signal. Further, the value of the reproduction signal when noise is not taken into consideration is expressed as c [k]. Further, an actual reproduction signal including noise (that is, a reproduction signal reproduced from the recording medium) is expressed as z [k].

  In PR (B, 2A, B), the contribution of the amplitude at the time point k is 2A times the amplitude value with respect to the value of the reproduction signal at a certain time point k, and further the contribution of the amplitude at the preceding and succeeding time points k-1 and k + 1. Is B times the amplitude of the signal at each time point. Therefore, the maximum value of the value of the reproduction signal is when a pulse is detected at each of the time points k−1, k, and k + 1. In such a case, the maximum value of the reproduction signal value is as follows.

B + 2A + B = 2A + 2B
Also, the minimum value of the reproduction signal is 0. However, in actual handling, as c [k], the following is used by subtracting A + B of the DC component.

c [k] = B * b [k-2] + 2A * b [k-1] + B * b [k]
-AB (2)
Accordingly, the reproduction signal c [k] when noise is not taken into consideration takes one of the values A + B, A, -A, and -A-B. In general, as one method for indicating the characteristics of a reproduction signal, for example, a unit obtained by superposing a large number of reproduction signals in units of five time points is referred to as an eye pattern. FIG. 7 shows an example of an eye pattern for an actual reproduction signal z [k] subjected to waveform equalization processing under PR (B, 2A, B) in a magneto-optical disk apparatus to which the present invention can be applied. . From FIG. 7, it can be confirmed that the value of the reproduction signal z [k] at each time point is any one of A + B, A, -A, and -AB. As will be described later, the values of A + B, A, -A, and -A-B are used as identification points.

  The outline of the Viterbi decoding method for decoding the reproduction signal subjected to the waveform equalization processing as described above is as follows. Step (1) Identify all possible states based on the encoding method and the recording method for the recording medium. Step (2) Starting from each state at a certain point in time, all state transitions that can occur at the next point in time, and the recording data a [k] and the value c [k] of the reproduction signal when each state transition occurs are specified. . Fig. 5 shows all states and state transitions identified as a result of steps (1) and (2), and [recorded data value a [k] / reproduced signal value c [k]] when each state transition occurs. This is expressed as a state transition diagram. As will be described later, the state transition diagram in the quaternary 4-state Viterbi decoding method is as shown in FIG. The Viterbi decoder 13 is configured to perform a decoding operation based on this state transition diagram.

  Step (3) As described above, on the premise of the state transition diagram, the most likely state transition based on the reproduction signal z [k] reproduced from the recording medium at each time point k is selected. However, as described above, z [k] is waveform equalized in the previous stage supplied to the Viterbi decoder 13. Each time such a most likely state transition is selected, the recording data a [k] described in the state transition diagram is used as a decoded value in correspondence with the selected state transition. Decoded data a ′ [k] as a maximum likelihood decoded value sequence for the data can be obtained. However, the configuration for obtaining the maximum likelihood decoded value sequence from the decoded data value at each time point k is a PMU 23 in the Viterbi decoder 13 described later. Therefore, as described above, the decoded data string a ′ [k] matches the recorded data string a [k] when there is no decoding error. The above steps (1) to (3) will be described in detail below.

The above step (1) will be described. First, as a state used here, a state at a certain time point k is defined as follows using the precode output at time point k and before. That is, the state when n = b [k], m = b [k−1], and l = b [k−2] is defined as Snml. With such a definition, it is considered that there are 2 ³ = 8 states, but as described above, the states that can actually occur are limited based on the encoding method or the like. In the recording data sequence a [k] encoded as the RLL (1, 7) code, at least one “0” is included between “1” and “1”. 'Is not continuous. A certain condition is imposed on the precode output b [k] based on such a condition imposed on the recording data string a [k], and a limit is imposed on a state that can be generated as a result.

  Such restrictions will be specifically described. As described above, in the recording data string generated by the RLL (1, 7) encoding, there cannot be two or more consecutive “1” s, that is, the following.

a [k] = 1, a [k-1] = 1, a [k-2] = 1 (3)
a [k] = 1, a [k-1] = 1, a [k-2] = 0 (4)
a [k] = 0, a [k-1] = 1, a [k-2] = 1 (5)
If the conditions imposed on b [k] are examined according to the above-described equation (1) based on such conditions imposed on the recording data string, it can be seen that the two states S010 and S101 cannot occur. . Therefore, there are 2 ³ −2 = 6 possible states.

  Next, step (2) will be described. In order to obtain a state that can occur at the next time point j + 1 starting from the state at a certain time point j, it is necessary to examine separately when the value a [j + 1] of the recording data at the time point j + 1 is 1 and 0. There is.

  Here, the state S000 will be described as an example. According to the above equation (1), the recording data to be precoded as S000, that is, n = b [j] = 0, l = b [j-1] = 0, m = b [j-2] = 0, The following two are conceivable.

a [j] = 0, a [j-1] = 0, a [j-2] = 1 (6)
a [j] = 0, a [j-1] = 0, a [j-2] = 0 (7)
[When a [j + 1] = 1]
At this time, b [j + 1] is calculated as follows according to the equation (1).

b [j + 1] = mod2 {a [j + 1] + b [j]}
= Mod2 {1 + 0}
= 1 (8)
Therefore, the value of the reproduction signal c [j] is calculated as follows according to the above-described equation (2).

c [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]}
-AB
= {B × 1 + 2A × 0 + B × 0} −A−B
= -A (9)
The state Snlm at the next time point j + 1 is n = b [j + 1], l = b [j], and m = b [j-1]. As described above, b [j + 1] = 1, b [j] = 0, and b [j−1] = 0, so that the state at the next time point j + 1 is S100. Therefore, when a [j + 1] = 1, it can be specified that the transition of S000 → S100 occurs.

[When a [j + 1] = 0]
At this time, b [j + 1] is calculated as follows according to the equation (1).

b [j + 1] = mod2 {a [j + 1] + b [j]}
= Mod2 {0 + 0}
= 0 (10)
Therefore, the value of the reproduction signal c [j + 1] is calculated as follows according to the above-described equation (2).

c [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]}
-AB
= {B × 0 + 2A × 0 + B × 0} −A−B
= -A-B (11)
The state Snlm at the next time point j + 1 is n = b [j + 1], l = b [j], and m = b [j-1]. As described above, b [j + 1] = 0, b [j] = 0, and b [j-1] = 0, so that the state at the next time point is S000. Therefore, when a [j + 1] = 0, it can be specified that the transition S000 → S000 occurs.

  In this way, for each state other than S000 at time point j, the state transition that can occur at the next time point j + 1 starting from them, the recorded data value a [j + 1] and the reproduction when such state transition occurs The correspondence with the signal value c [j + 1] can be obtained.

  FIG. 8 shows the correspondence between the state transitions that can occur from each state and the values of the recording data and the reproduction signal when each state transition occurs, and is shown in the form of FIG. Time points j and j + 1 described above are not special time points. Therefore, the correspondence between the state transitions that can be obtained as described above and the values of the recording data and the reproduction signal associated therewith can be applied at any point in time. For this reason, in FIG. 8, the value of the recording data associated with the state transition occurring at an arbitrary time point k is expressed as a [k], and the value of the reproduction signal is expressed as c [k].

  In FIG. 8, the state transition is represented by an arrow. Further, the reference numerals attached to the respective arrows indicate [recording data value a [k] / reproduction signal value c [k]]. There are two types of state transitions starting from states S000, S001, S111, and S110, whereas only one type of transition can occur starting from states S011 and S100.

  Further, in FIG. 8, S000 and S001 both take a value of c [k] = − A for a [k] = 1, and transition to S100. On the other hand, for a [k] = 0, the value is c [k] = − A−B, and the process transitions to S000. Similarly, S111 and S110 take the same value of c [k + 1] for the same value of a [k + 1] and transition to the same state. Therefore, S000 and S001 can be collectively expressed as S0, and S111 and S110 can be collectively expressed as S2. Further, FIG. 9 shows a summary of S011 as S3 and S100 as S1.

  As described above, FIG. 9 is a state transition diagram used in the quaternary 4-state Viterbi decoding method. FIG. 9 shows four states S0 to S3 and four values -A-B, -A, A, and A + B as values of the reproduction signal c [k + 1]. There are two state transitions starting from states S0 and S2, whereas there are only one state transition starting from states S1 and S3.

  On the other hand, a trellis diagram as shown in FIG. 10 is used as a format for expressing state transitions along time. Although FIG. 10 shows a transition between two time points, a transition between a larger number of time points can also be shown. As time elapses, the state of transition to the right time point is expressed. Accordingly, a horizontal arrow represents a transition to the same state such as S0 → S0, and a diagonal arrow represents a transition to a different state such as S1 → S2.

  A method of selecting the most likely state transition from the actual reproduced signal z [k] including noise on the premise of step (3) of the Viterbi decoding method described above, that is, the state transition diagram shown in FIG. 9 will be described below. .

  In order to select the most likely state transition, first, for the state at a certain time point k, the sum of the likelihoods of the state transitions between multiple time points that have passed through in the process of reaching that state is calculated, and further, It is necessary to compare the likelihood sums and select the most likely decoded sequence. Such a sum of likelihoods is called a path metric.

  In order to calculate the path metric, it is first necessary to calculate the likelihood of state transition between adjacent time points. Such likelihood calculation is performed as follows based on the value of the reproduction signal z [k] with reference to the state transition diagram described above. First, as a general explanation, consider the case where the state Sa is at the time point k-1. At this time, when the reproduction signal z [k] is input to the Viterbi decoder 31, the likelihood that the state transition to the state Sb occurs is calculated according to the following equation. However, the state Sa and the state Sb are any of the four states described in the state transition diagram of FIG.

(Z [k] -c (Sa, Sb)) ² (12)
In the above equation, c (Sa, Sb) is the value of the reproduction signal described in the state transition diagram of FIG. 9 for the state transition from the state Sa to the state Sb. That is, in FIG. 9 described above, for example, a value calculated as −A for the state transition S0 → S1. Therefore, Expression (12) is a Euclidean distance between the value of the actual reproduction signal z [k] including noise and the value of the reproduction signal c (Sa, Sb) calculated without considering the noise. The path metric at a certain time point is defined as the sum of the likelihoods of state transitions between such adjacent time points up to that time point.

  By the way, consider the case where the state Sa is at the time point k. In this case, if the state that can transition to the state Sa at the time point k−1 is Sp, the path metric L (Sa, k) is calculated as follows using the path metric at the time point k−1. .

L (Sa, k)
= L (Sp, k-1) + (z [k] -c (Sp, Sa)) ² (13)
That is, the path metric L (Sp, k−1) when the state Sp is reached at the time point k−1 and the likelihood of the state transition Sp → Sa occurring between the time points k−1 and k (z [k ] -C (Sp, Sa)) ² is added to calculate the path metric L (Sa, k). The likelihood of the latest state transition such as (z [k] -c (Sp, Sa)) ² is referred to as a branch metric. However, the branch metric here is different from the branch metric calculated by the branch metric calculation circuit (BMC) 20 in the Viterbi decoder 13 described later, that is, the branch metric corresponding to the normalized metric. Care must be taken.

  In addition, when the state Sa is at the time point k, there may be a plurality of states that can transition to the state Sa at the time point k-1. In FIG. 9, states S0 and S2 are such cases. That is, when the state is the state S0 at the time point k, there are two states, S0 and S3, that can transition to the state S0 at the time point k-1. In addition, when the state is the state S2 at the time point k, there are two states S1 and S2 that can transition to the state S2 at the time point k-1. As a general explanation, when there are two states, Sp and Sq, at the time point k and the state Sa can transition to the state Sa at the time point k−1, the path metric L (Sa, k) is It is calculated as follows:

L (Sa, k)
= Min {L (Sp, k-1) + (z [k] -c (Sp, Sa)) ² ,
L (Sq, k−1) + (z [k] −c (Sq, Sa)) ² } (14)
That is, when the state Sp is reached at the time point k-1 and the state Sa is reached by the state transition of Sp → Sa, and when the state Saq is reached at the time point k-1 and the state Sa is reached by the state transition of Sq → Sa. Compute the sum of likelihoods for each of. Then, the calculated values are compared, and the smaller value is set as the path metric L (Sa, k) for the state Sa at the time point k.

  When such calculation of the path metric is specifically applied to the four-value four-state described above with reference to FIG. 9, the path metrics L (0, k), S for the respective states S0, S1, S2, and S3 at the time point k. L (1, k), L (2, k) and L (3, k) are path metrics L (0, k−1) to L (3, k) for the states S0 to S3 at the time point k−1. -1) can be used to calculate as follows:

L (0, k) = min {L (0, k−1) + (z [k] + A + B) ² ,
L (3, k−1) + (z [k] + A) ² } (15)
L (1, k) = L (0, k−1) + (z [k] + A) ² (16)
L (2, k) = min {L (2, k-1) + (z [k] -AB) ²
L (1, k−1) + (z [k] −A) ² } (17)
L (3, k) = L (2, k−1) + (z [k] −A) ² (18)
As described above, it is only necessary to compare the path metric values calculated in this way and select the most likely state transition. By the way, in order to select the most likely state transition, it is only necessary to compare the path metric values without calculating the path metric values themselves. Therefore, in the actual 4-value 4-state Viterbi decoding method, the calculation based on z [k] at each time point k is facilitated by using a standardized path metric as defined below instead of the path metric. To be made.

m (i, k)
= [L (i, k) -z [k] ^2- (A + B) ² ] / 2 / (A + B) (19)
When Expression (19) is applied to each state of S0 to S3, a specific standardized path metric does not include square calculation as follows. For this reason, the calculation in the addition, comparison, and selection circuit (ACS) 21 described later can be facilitated.

m (0, k) = min {m (0, k-1) + z [k],
m (3, k−1) + α × z [k] −β} (20)
m (1, k) = m (0, k−1) + α × z [k] −β (21)
m (2, k) = min {m (2, k-1) -z [k],
m (1, k−1) −α × z [k] −β} (22)
m (3, k) = m (2, k−1) + α × z [k] −β (23)
However, α and β in the formulas (20) to (23) are as follows.

α = A / (A + B) (24)
β = B × (B + 2 × A) / 2 / (A + B) (25)
FIG. 11 shows conditions for state transition in such a 4-value 4-state Viterbi decoding method based on the normalized path metric. Since there are two formulas for selecting one of the four standardized path metrics, there are 2 × 2 = 4 conditions.

[Outline of 4-value 4-state Viterbi decoder]
The Viterbi decoder 13 that implements the above-described four-value four-state Viterbi decoding method will be described below. FIG. 12 shows the overall configuration of the Viterbi decoder 13. The Viterbi decoder 13 includes a branch metric calculation circuit (hereinafter referred to as BMC) 20, an addition, comparison and selection circuit (hereinafter referred to as ACS) 21, a compression and latch circuit 22, and a path memory unit (hereinafter referred to as PMU). 23). By supplying the above-described read clock DCK (hereinafter simply referred to as a clock) to each of these components, the operation timing of the entire Viterbi decoder 13 is matched. Further, for each of the path memories 24 to 27 of the PMU 23, control data Reg for optimally setting the memory length of the data area and a switching signal for switching the memory length of the path memory between the header area and the data area. S is supplied. Hereinafter, each component will be described.

  The BMC 20 calculates branch metric values BM0, BM1, BM2, and BM3 corresponding to the normalized path metric based on the input reproduction signal z [k]. BM0 to BM3 are as follows required to calculate the normalized path metric of the above-described equations (20) to (23).

BM0 = z (k) (26)
BM1 = α × z [k] −β (27)
BM2 = −z (k) (28)
BM3 = −α × z [k] −β (29)
Α and β necessary for this calculation are reference values calculated by the BMC 20 according to the above-described equations (24) and (25). Such calculation is performed based on the values of the discrimination points -AB, -A, A, and A + B that are detected by a method such as envelope detection based on the reproduction signal z [k] and supplied to the BMC 20.

  The values of BM0 to BM3 are supplied to the ACS 21. On the other hand, the ACS 21 is supplied with values of standardized path metrics one clock before (compressed as described later) M0, M1, M2, and M3 from the compression and latch circuit 22 as described later. . Then, M0 to M3 and BM0 to BM3 are added to calculate the latest normalized path metric values L0, L1, L2, and L3 as described later. Since M0 to M3 are compressed, an overflow when calculating L0 to L3 can be avoided.

  Further, the ACS 21 selects the most likely state transition based on the latest standardized path metric values L0 to L3, as described later, and is supplied to the path memory 23 corresponding to the selection result. The selection signals SEL0 and SEL2 are set to “High” or “Low”.

  The ACS 21 supplies L0 to L3 to the compression and latch circuit 22. The compression and latch circuit 22 compresses the supplied L0 to L3 and then latches them. Thereafter, it is supplied to the ACS 21 as standardized path metrics M0 to M3 one clock before.

  As a compression method at this time, for example, as shown below, one of the latest standardized path metrics L0 to L3, for example, L0 is uniformly subtracted.

M0 = L0−L0 (30)
M1 = L1-L0 (31)
M2 = L2-L0 (32)
M3 = L3-L0 (33)
As a result, M0 always takes a value of 0, but in the following description, it is expressed as M0 as it is in order not to impair generality. The difference between the values of M0 to M3 calculated by the equations (30) to (33) is equal to the difference between the values of L0 to L3. As described above, in selecting the most likely state transition, only the value difference between the standardized path metrics becomes a problem. Accordingly, such a compression method is effective as a method for preventing overflow by compressing the value of the normalized path metric without affecting the selection result of the most likely state transition. In this way, the ACS 21 and the compression and latch circuit 22 form a loop related to the calculation of the normalized path metric.

  The ACS 21 described above will be described in more detail with reference to FIG. The ACS 21 is composed of six adders 51, 52, 53, 54, 56, 58 and two comparators 55, 57. On the other hand, as described above, the ACS 21 is supplied with the compressed standardized path metric values M0 to M3 one branch before and the branch metric values BM0 to BM3 corresponding to the standardized path metrics.

  The adder 51 is supplied with M0 and BM0. The adder 51 adds these to calculate L00 as follows.

L00 = M0 + BM0 (34)
As described above, M0 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S0 is reached at time point k-1. BM0 is a value calculated according to the above equation (26) based on the reproduction signal z [k] input at the time point k, that is, the value of z [k] itself. Therefore, the value of the equation (34) is obtained by calculating the value of m (0, k−1) + z [k] in the above equation (20) under the action of compression as described above. That is, the calculated value corresponds to the state S0 at the time point k-1 and finally the state transition S0 by the state transition S0 → S0 at the time point k.

  On the other hand, M3 and BM1 are supplied to the adder 52. The adder 51 adds these to calculate L30 as follows.

L30 = M3 + BM1 (35)
As described above, M3 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S3 is reached at time point k-1. Further, BM1 is calculated according to the above equation (27) based on the reproduction signal z [k] input at the time point k, that is, α × z [k] −β. Therefore, the value of the equation (35) is calculated as the value of m (3, k−1) + α × z [k] −β in the above equation (20) under the action of compression as described above. It will be a thing. That is, the calculated value corresponds to the state S3 at the time point k-1 and finally the state transition S0 by the state transition S3 → S0 at the time point k.

  The above L00 and L30 are supplied to the comparator 55. The comparator 55 compares the values of L00 and L30, sets the smaller one as the latest normalized path metric L0, and switches the polarity of the selection signal SEL0 as described above according to the selection result. Such a configuration corresponds to the selection of the minimum value in equation (20). That is, when L00 <L30 (in this case, S0 → S0 is selected), L00 is output as L0, and SEL0 is set to “Low”, for example. If L30 <L00 (S3 → S0 is selected at this time), L30 is output as L0, and SEL0 is set to “High”, for example. As described later, SEL0 is supplied to the A-type path memory 24 corresponding to the state S0.

  As described above, the adders 51 and 52 and the comparator 55 select the most likely state transition at the time point k from S0 → S0 and S3 → S0 corresponding to the above equation (20). Perform the action. Then, the latest standardized path metric L0 and the selection signal SEL0 are output according to the selection result.

  The adder 56 is supplied with M0 and BM1. The adder 51 adds these to calculate the following L1.

L1 = M0 + BM1 (36)
As described above, M0 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S0 is reached at time point k-1. Further, BM1 is calculated according to the above equation (27) based on the reproduction signal z [k] input at the time point k, that is, α × z [k] −β. Therefore, the value of the equation (36) is calculated as the value of the right side m (0, k−1) + α × z [k] −β of the equation (21) under the action of compression as described above. It will be a thing. That is, the calculated value corresponds to the state S0 at the time point k-1 and finally the state transition S1 by the state transition S0 → S1 at the time point k. Corresponding to the fact that Expression (21) does not select a value, the output of the adder 56 is directly used as the latest normalized path metric L1.

  The adder 53 is supplied with M2 and BM2. The adder 53 adds these to calculate L22 as follows.

L22 = M2 + BM2 (37)
As described above, M2 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S2 is reached at time point k-1. Also, BM0 is calculated according to the above equation (28) based on the reproduction signal z [k] input at the time point k, that is, −z [k]. Therefore, the value of Expression (37) is the value of m (2, k−1) −z [k] in Expression (22) described above under the action of compression as described above. . That is, the calculated value corresponds to the state S2 at the time point k-1 and finally the state transition S2 by the state transition S2 → S2 at the time point k.

  On the other hand, M1 and BM3 are supplied to the adder 54. The adder 53 adds these to calculate L12 as follows.

L12 = M1 + BM3 (38)
As described above, M1 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S1 is reached at time point k-1. Further, BM3 is calculated according to the above equation (29) based on the reproduction signal z [k] input at the time point k, that is, −α × z [k] −β. Therefore, the value of the equation (38) is calculated as the value of m (1, k−1) −α × z [k] −β in the above equation (22) under the action of compression as described above. Will be. That is, the calculated value corresponds to the state S1 at the time point k-1 and finally the state transition S2 by the state transition S1 → S2 at the time point k.

  The above L22 and L12 are supplied to the comparator 57. The comparator 57 compares the values of L22 and L12, sets the smaller one as the latest standardized path metric L2, and switches the polarity of the selection signal SEL2 as described above according to the selection result. Such a configuration corresponds to the selection of the minimum value in Equation (22). That is, when L22 <L12 (in this case, S2 → S2 is selected), L22 is output as L2, and SEL2 is set to “Low”, for example. If L12 <L22 (S1 → S2 is selected at this time), L12 is output as L2, and SEL2 is set to “High”, for example. SEL2 is supplied to the A-type path memory 26 corresponding to the state S2, as will be described later.

  As described above, the adders 53 and 54 and the comparator 57 select the most likely state transition at the time point k from S1 → S2 and S2 → S2 corresponding to the above equation (22). . Then, the latest standardized path metric L2 and the selection signal SEL2 are output according to the selection result.

  Further, M2 and BM3 are supplied to the adder 58. The adder 58 adds these to calculate the following L3.

L3 = M2 + BM3 (39)
As described above, M2 is a compressed standardized path metric corresponding to the sum of the state transitions that have passed through when state S2 is reached at time point k-1. Further, BM3 is calculated according to the above equation (29) based on the reproduction signal z [k] input at the time point k, that is, −α × z [k] −β. Therefore, the value of the equation (39) is calculated as the value of the right side m (2, k−1) + α × z [k] −β of the equation (23) under the action of the compression as described above. It will be a thing. That is, the calculated value corresponds to the state S0 at the time point k-1 and finally the state transition S3 by the state transition S2 → S3 at the time point k. Corresponding to the fact that Expression (23) does not select a value, the output of the adder 58 is directly used as the latest standardized path metric L3.

  As described above, the path memory unit (hereinafter referred to as PMU) 23 operates in accordance with SEL0 and SEL2 output from the ACS 21, whereby the decoded data a ′ as the maximum likelihood decoding sequence for the recorded data a [k]. [K] is generated. The PMU 23 includes two A-type path memories and two B-type path memories in order to cope with the state transition between the four states shown in FIG.

  An A-type path memory has two transitions (that is, a transition from itself and a transition from one other state) as transitions to that state, and two transitions starting from that state. That is, it is configured to cope with a state having (ie, a transition reaching itself and a transition reaching another state). Therefore, the A-type path memory corresponds to S0 and S2 among the four states shown in FIG.

  On the other hand, the B-type path memory is configured to correspond to a state in which there is only one transition leading to that state and only one transition starting from that state. Therefore, the B-type path memory corresponds to S1 and S3 among the four states shown in FIG.

  In order for these two A-type path memories and two B-type path memories to perform the operation according to the state transition diagram shown in FIG. 9, the PMU 23 delivers the decoded data as shown in FIG. Composed. That is, the A-type path memory 24 corresponds to S0, and the A-type path memory 26 corresponds to S2. Further, the B-type path memory 25 corresponds to S1, and the B-type path memory 27 corresponds to S3. According to this configuration, the state transitions that can occur from S0 are S0 → S0 and S0 → S1, and the state transitions that can occur from S2 are S2 → S2 and S2 → S3. In addition, the state transition that can occur from S1 is only S1 → S2, and the state transition that can occur from S3 is only S3 → S0.

The detailed configuration of the A-type path memory 24 is shown in FIG. The A-type path memory 24 is formed by alternately connecting a number of flip-flops and selectors corresponding to the path memory length. That is, it has (n-1) selectors 31 _{1 to} 31 _n-1 and n flip-flops 30 ₀ to 30 _n-1 . Each of the selectors 31 _{1 to} 31 _n-1 receives two pieces of data and selectively supplies one of them to the subsequent stage. Further, the operation timing of the entire A-type path memory 24 is adjusted by supplying a clock to the flip-flops 30 ₀ to 30 _n−1 .

  As described above with reference to FIG. 9, the transition to the state S0 is S0 → S0, that is, a transition inherited from itself, and S3 → S0. As a configuration corresponding to such a situation, each selector includes data supplied from the preceding flip-flop, that is, decoded data corresponding to S0 → S0, and data supplied from the B-type path memory 27 corresponding to the state S3, that is, The decrypted data PM3 corresponding to S3 → S0 is received. Further, each selector is supplied with SEL0 from ACS21. Then, according to the polarity of SEL0, one of the two supplied decoded data is supplied to the subsequent flip-flop. In addition, the decoded data supplied to the flip-flop at the subsequent stage is also supplied as PM0 to the B-type path memory 25 corresponding to the state S1.

For example, the selector 31 _n-1 receives the data supplied from the preceding flip-flop 30 _n-2 and the data at the 14th bit position of PM3 consisting of n bits supplied from the B-type path memory 27. Then, the data selected from the two data as follows is supplied to the flip-flop 30 _n-1 at the subsequent stage. As described above, SEL0 is set to “Low” or “High” depending on the selection result. When SEL0 is, for example, “Low”, data from the preceding flip-flop 30 _n-2 is selected. Further, when SEL0 is, for example, “High”, the data at the 14th bit position of PM3 is selected. The selected data is supplied to the subsequent flip-flop 30 _n-1 and supplied to the B-type path memory 25 corresponding to the state S1 as data at the 14th bit position of PM0.

In the other selectors 31 _{1 to} 31 _n−2 in the A-type path memory 24, the same operation is performed according to the polarity of SEL0. Therefore, as a whole of the A-type path memory 24, when SEL0 is “Low”, for example, in the A-type path memory 24, each flip-flop performs a serial shift that inherits the data of the flip-flop located in the preceding stage. . When SEL0 is, for example, “High”, parallel loading is performed to inherit the decoded data PM3 consisting of n bits supplied from the B-type path memory 27. In either case, the inherited decoded data is supplied to the B-type path memory 25 as n-bit decoded data PM0.

Further, the flip-flop 30 ₀ on the first stage, always '0' is input in synchronization with the clock. In such an operation, in any of the state transitions S0 → S0 and S2 → S0 leading to S0, as shown in FIG. 9, since the decoded data is “0”, the latest decoded data is always “0”. It corresponds.

Furthermore, when taking out the decoded output, an output selector 33 is provided. The output selector 33, n pieces of output from the output of the first flip-flop 30 ₀ to the output of the last flip-flop 30 _n-1 is supplied. The output selector 33 selects one of the n inputs as a decoded output according to the select signal. A select signal for controlling the output selector 33 is generated by the select signal generation circuit 34. Control data Reg and switching signal S from the register 16 are supplied to the select signal generation circuit 34.

  The select signal selects the output of a predetermined flip-flop when decoding the reproduction signal of the header area, and the predetermined flip-flop so that the data area has the memory length indicated by the control data Reg The output selector 33 is controlled so as to select the output of the group. Thus, the memory length can be set independently for the header area and the data area, and the memory length at the time of reproducing the data area can be set by calibration.

  As described above, the configuration itself of the A-type path memory 26 corresponding to S2 is the same as that of the A-type path memory 24. However, the selection signal input from the ACS 21 is SEL2. As shown in FIG. 9, transitions to state S2 include S2 → S2, that is, a transition inherited from itself and S1 → S2. Therefore, PM1 is supplied from the B-type path memory 25 corresponding to the state S1. Further, PM2 is supplied to the B-type path memory 27 corresponding to the state S3 in response to the fact that the state that can occur from the state S2 is S2, that is, itself and S3.

  Also in the A-type path memory 26 corresponding to S2, '0' is always input to the flip-flop serving as the first processing stage in synchronization with the clock. In such an operation, in any of the state transitions S2 → S2 and S1 → S0 leading to S2, as shown in FIG. 9, since the decoded data is “0”, the latest decoded data is always “0”. It corresponds.

On the other hand, the detailed configuration of the B-type path memory 25 is shown in FIG. The B-type path memory 25 is formed by connecting n flip-flops corresponding to the path memory length of the data area. In the example illustrated in FIG. 15, the B-type path memory 25 includes n flip-flops 32 _{0 to} 32 _n−1 . By supplying a clock to the flip-flops 32 _{0 to} 32 _n−1 , the operation timing of the entire B-type path memory 25 is matched.

Each of the flip-flops 32 _{1 to} 32 _n−1 is supplied with n-bit decoded data as PM0 from the A-type path memory 24 corresponding to the state S0. For example, the first bit of PM0 is supplied to the flip-flop 32 ₁ . Each of the flip-flops 32 _{1 to} 32 _n-1 holds the supplied value for one clock. Then, it is output as n-bit decoded data PM1 to the A-type path memory 26 corresponding to the state S2. For example, the flip-flop 32 ₁ outputs the second bit of PM1.

Similar operations are performed in the other selectors 32 _{1 to} 32 _n−2 in the B-type path memory 25. Therefore, the B-type path memory 25 as a whole receives the n-bit decoded data PM0 supplied from the A-type path memory 24 and supplies the A-type path memory 26 with n-bit decoded data PM1.

Further, the flip-flop 32 _0, always "1" is input in synchronization with the clock. This operation corresponds to the fact that the decoded data is “1” when the latest state transition is S0 → S1, as shown in FIG.

Further, when taking out the decoded output, an output selector 35 is provided. The output selector 35, n pieces of output from the output of the first flip-flop 32 ₀ to the output of the last flip-flop 32 _n-1 is supplied. The output selector 35 selects one of the n inputs as a decoded output according to the select signal. A select signal for controlling the output selector 35 is generated by a select signal generation circuit 36. Control data Reg and switching signal S from the register 16 are supplied to the select signal generation circuit 36. The output selector 35 selects one input as a decoded output by the select signal. That is, as in the case of the A-type path memory 24 described above, when decoding the reproduction signal of the header area, the output of a predetermined flip-flop is selected, and when decoding the reproduction signal of the data area, it is indicated by the control data Reg. The output of the flip-flop to be selected is selected. The memory length of the B-type path memory 25 can be switched by the output selector 35.

  Further, as described above, the B-type path memory 27 corresponding to the state S3 has the same configuration as the B-type path memory 25. However, as shown in FIG. 9, since the transition to the state S3 is S2 → S3, PM2 is supplied from the A-type path memory 26 corresponding to the state S2. Further, PM3 is supplied to the A-type path memory 24 corresponding to the state S0 in response to the fact that the state that can occur from the state S3 is S0. Also in the B-type path memory 27, “1” is always input to the flip-flop as the first processing stage in synchronization with the clock. This operation corresponds to the fact that the decoded data is “1” when the latest state transition is S2 → S3, as shown in FIG.

  As described above, each of the four path memories in the PMU 23 generates decoded data. The four pieces of decoded data generated in this way coincide with each other when an accurate Viterbi decoding operation is always performed. By the way, in the actual Viterbi decoding operation, mismatching may occur in four pieces of decoded data. Such inconsistency is caused by an inaccurate Viterbi decoding operation due to factors such as an error in detecting the above-described discrimination points A and B due to the influence of noise included in the reproduction signal. . Therefore, when there is a possibility that there is a mismatch between the decoded data, a configuration (not shown) such as selecting a more accurate one from the four decoded data by a method such as a majority decision is used. It is provided in the subsequent stage of the path memory.

[Viterbi decoding methods other than quaternary 4-state Viterbi decoding methods]
In the quaternary 4-state Viterbi decoding method described above, the waveform equalization characteristic used in the filter unit 11 is PR (1, 2, 1), and the RLL (1, 7) code is adopted as the recording data. Used for. For example, when the recording linear density is 0.40 μm, the laser wavelength is 685 nm, and NA = 0.55, it is optimal to set the waveform equalization characteristic to PR (1, 2, 1) and use the 4-value 4-state Viterbi decoding method. It becomes. On the other hand, other types of Viterbi decoding methods may be used depending on the waveform equalization characteristics or the encoding method for generating the recorded data.

  For example, when the waveform equalization characteristic is PR (1, 1) and an RLL (1, 7) code is used as recording data, a ternary 4-state Viterbi decoding method is used. When the waveform equalization characteristic is PR (1, 3, 3, 1) and the RLL (1, 7) code is used as the recording data, the 7-value 6-state Viterbi decoding method is used. Among such Viterbi decoding methods, a waveform equalization characteristic that is one of the elements for selecting which one to use is employed that has a good degree of compatibility with the intersymbol interference on the reproduced signal. Therefore, as described above, it is optimal in consideration of the linear recording density and MTF.

[4-value 4-status Viterbi decoding method using status data values]
The Viterbi decoder 13 in an example of the magneto-optical disk device described above generates decoded data as a sequence of decoded data values corresponding to the most likely state transition selected based on the reproduction signal value. On the other hand, it is also possible to generate state data representing the selected state transition itself by using a state data value representing the state itself instead of the decoded data value. In such a case, a status memory unit (hereinafter referred to as SMU) that generates a series of state data values as described later is used instead of the path memory unit PMU in the above-described example of the magneto-optical disk device. It is done. As will be described later, in another embodiment of the present invention, the present invention is applied to Viterbi decoding using state data.

  For example, in the 4-value 4-state Viterbi decoding method, since 4 states can be expressed by 2 bits, such 2-bit data can be used as the state data value. Therefore, S0, S1, S2, and S3 in FIG. 9 can be expressed using 2-bit status data values 00, 01, 11, and 10, respectively. Therefore, in the following description, S0, S1, S2, and S3 in FIG. 7 are expressed as S00, S01, S11, and S10, respectively, and as a state transition diagram of the four-value four-state Viterbi decoding method, FIG. Instead, FIG. 16 is used.

  Further, in the following description, it is assumed that the waveform equalization characteristics are normalized, that is, PR (1, 2, 1) instead of the above-described PR (B, 2A, B). Therefore, the value of the discrimination point, that is, the reproduction signal value c [k] obtained by calculation without considering noise is 0, 1, 3, 4 instead of -A-B, -A, A, A + B in FIG. It is expressed.

  Further, in the equations (20) to (24) for calculating the normalized path metric, a total of six addition portions corresponding to the latest state transition (for example, in equation (20), corresponding to S0 → S0). z [k] and [alpha] * z [k]-[beta] corresponding to S3-> S0 are also expressed as follows according to the state notation method in FIG. Such an addition part is different from the branch metric defined by the equation (13). However, in the following description, for the sake of brevity, the addition part is indicated as a branch metric.

  First, a 2-bit state data value representing the state before the transition and the state after the transition are written and arranged into a string of four numbers. Next, the branch metric that can occur during one read clock is expressed as a sequence of three numbers by making the two numbers (ie, the second and third) closer to the center into one number. . For example, the branch metric accompanying the state transition S11 → S10 is expressed as bm110. In this way, branch metrics corresponding to the six types of state transitions in FIG. 16 can be expressed as shown in FIG.

  FIG. 18 is a block diagram showing the overall configuration of another embodiment of the present invention. In another embodiment of the present invention, the present invention is applied to a magneto-optical disk apparatus. The same components as those in the example of the magneto-optical disk device described above with reference to FIG. The recording system and the servo system (not shown) are the same as those in the embodiment shown in FIG. The configuration and operation of the reproduction system from the optical pickup 7 to the A / D converter 12 are the same as those in the embodiment shown in FIG.

  The Viterbi decoder 130 generates decoded data and a mismatch detection signal NM generated as described later based on the reproduction signal value z [k] supplied from the A / D converter 12, and sends it to the controller 2. Supply. The controller 2 performs a decoding process based on the supplied decoded data, reproduces user data, address data, and the like, and controls calibration similarly to the above-described example of the magneto-optical disk device. Further, a counting means is provided in the controller 2 and counts the number of mismatches between the state data based on the mismatch detection signal NM.

  The CPU 15 connected to the controller 2 supplies a control signal for laser power setting to the LPC 4 and controls the positioning of the optical pickup 7 and the like as in the above-described embodiment. The register 16 connected to the CPU 15 stores control data for setting the gains of the amplifiers 8 and 9 as playback system parameters, the equalization characteristics of the filter 11, and the memory length of the path memory of the Viterbi decoder 13. The control data is generated by the controller 2 through calibration as described with reference to FIG. 5 and is stored in the register 16 via the CPU 15. Note that the memory length setting is not limited to that based on the result of calibration. For example, the memory length may be set based on a count of mismatch of state data in a merge block described later. One magneto-optical disk may be divided into a plurality of zones in the radial direction, and an appropriate memory length may be set in each zone.

  The Viterbi decoder 130 includes a BMC 132, an ACS 133, an SMU 134, and a merge block 135. Each of these components is supplied with a read clock DCK (hereinafter referred to as a clock) from the PLL 14 and the operation timing is adjusted. In order to switch the memory length to the SMU 134, the switching signal S and the control data Reg from the register 16 are supplied.

  The BMC 132 calculates a branch metric based on the reproduction signal value z [k], and supplies the calculated branch metric to the ACS 133.

  The ACS 133 will be described with reference to FIG. The ACS 133 is configured to include the components in the ACS 21 described above and the components in the compression and latch circuit 22. Since such a configuration is provided corresponding to each state, it is configured by four blocks. The standardized path metric values output by the sub-blocks are connected so as to be transferred according to the state transition diagram shown in FIG.

  Among these, A-type sub-blocks described later correspond to states S00 and S11 that can inherit the state. In FIG. 19, the A-type sub-blocks 140 and 142 are illustrated so as to correspond to the states S00 and S11, respectively. In addition, states S01 and S10 that cannot inherit themselves correspond to B-type sub-blocks described later. In FIG. 19, the B-type sub-blocks 141 and 143 are illustrated so as to correspond to the states S01 and S10, respectively.

  The A-type sub-block 142 includes constituent elements of the above-described ACS 21 (see FIG. 13) that generate a selection signal. That is, it has two adders for updating the values of two normalized path metrics and one comparator. Further, the A-type sub-block 140 has means for holding the updated path metric value, which performs the same operation as the compression and latch circuit 22.

  The branch metric bm000 corresponding to S00 → S00 and the branch metric bm100 corresponding to S10 → S00 are supplied from the BMC 132 to the A-type sub-block 140 according to the clock. Further, the value of the normalized path metric M10 updated one clock before is supplied from the B-type sub-block 143 corresponding to S10. The A-type sub-block 140 calculates the total likelihood when the latest transition is S10 → S00 by adding the value of bm000 to the value of the normalized path metric M10 updated one clock before. .

  Further, the A-type sub-block 140 adds the value of bm000 to the value of the normalized path metric M00 one clock before latched by itself, thereby the likelihood when the latest transition is S00 → S00. Calculate the sum.

  Then, the A-type sub-block 140 compares the sum of the two likelihoods calculated in this way, and selects the most likely state transition. The sum of likelihoods corresponding to the selected state transition is latched as the updated value of the normalized path metric M00, and the selection signal SEL00 corresponding to the selection result is output. The updated value of the normalized path metric M00 is latched by the A-type sub-block 140 itself and supplied to the B-type sub-block 141 corresponding to S01.

  The A type sub block 142 corresponding to the state S11 is configured in the same manner as the A type sub block 140. However, the supplied branch metrics are bm111 and bm011 corresponding to the state transitions S11 → S11 and S01 → S11 in FIG. Also, the updated standardized path metric M11 is latched by the A-type subblock 142 itself and supplied to the B-type subblock 143 corresponding to the state S10.

  The B-type sub-block 141 includes components that do not generate a selection signal in the above-described ACS 21 (see FIG. 13). That is, it has one adder for updating one path metric value. Further, the B-type sub-block 141 has a function of holding the updated path metric value having the same function as the compression and latch circuit 22.

  The B-type sub-block 141 is supplied with the branch metric bm001 corresponding to S00 → S01 from the BMC 132 according to the clock. Further, the value of the normalized path metric M00 updated one clock before is supplied from the A-type sub-block 140 corresponding to S00. The B-type sub-block 141 calculates the total likelihood when the latest transition is S00 → S01 by adding the value of bm001 to the value of the normalized path metric M00 updated one clock before. The calculation result is latched as the updated normalized path metric M01. The value of the normalized path metric M01 is supplied to the A-type sub block 142 corresponding to S11 at a timing according to the clock.

  The B-type sub-block 143 corresponding to the state S10 is configured in the same manner as the B-type sub-block 141. However, the supplied branch metric is bm110 corresponding to the state transition S11 → S10. The updated standardized path metric M10 is latched by itself and supplied to the A-type sub-block 140 corresponding to the state S00.

  Each sub-block supplies the normalized path metric value updated at each time point according to the clock to the normalized path metric comparison circuit 144. That is, the A-type sub-block 140, the B-type sub-block 141, the A-type sub-block 142, and the B-type sub-block 143 send the values of the normalized path metrics M00, M01, M11, and M10 to the normalized path metric comparison circuit 144, respectively. Supply. The standardized path metric comparison circuit 144 outputs a 2-bit signal MS corresponding to the minimum value among these four standardized path metrics and supplies it to the merge block 135 described later.

  Next, the SMU 134 will be described with reference to FIG. The PMU 23 in the above-described magneto-optical disk apparatus performs processing in units of 1-bit decoded data values, whereas the SMU 134 performs processing in units of 2-bit status data values. is there.

  As shown in FIG. 20, the SMU 134 has two A-type status memories 150 and 151 and two B-type status memories 152 and 153. Further, select signals SEL00 and SEL11, a clock, and signal lines for transferring state data with other status memories are connected. A-type status memories 150 and 151 correspond to states S00 and S11, respectively. B-type status memories 152 and 153 correspond to states S01 and S10, respectively. The connection between these four status memories follows the state transition diagram of FIG. Further, a switching signal S for switching the memory length of these status memories 150 to 153 between the header area and the data area and control data Reg for optimally setting the memory length in the header area are supplied to each status memory. Is done.

The A type status memory 150 corresponding to the state S00 will be described in more detail with reference to FIG. The A-type status memory 150 has n processing stages. That is, n selectors 201 ₀ ... 201 _n−1 and n registers 202 ₀ ... 202 _n−1 are alternately connected. A select signal SEL00 is supplied to each of the selectors 201 _{0 to} 201 _n-1 . Further, as described above, the state data inherited from the B-type status memory 153 corresponding to S10 is supplied to each selector as SMin consisting of n bits. Further, as described above, the state data inherited by the B-type status memory 152 corresponding to S01 is output to each register as SMout composed of n-1 state data values. A clock is supplied to each of the registers 202 _{0 to} 202 _n−1 .

On the other hand, the operation of each selector will be described. As shown in FIG. 16, the state one clock before that can transit to S00 is either S00 or S10. When the state one clock before is S00, a transition that inherits itself is made. Therefore, the first stage of the selector 201 _0, as the latest state data value in the state data generated by the serial shift, 00 "is input. The selector 201 _0, as the parallel load, the most recent status data values SMin in state data supplied from the B type status memory 153 (1) is supplied. The selector 201 ₀ supplies one of these two status data values to the subsequent register 202 ₀ in accordance with the selection signal SEL00.

Each of the selectors 201 _{1 to} 201 _n-1 in the second and subsequent stages includes two pieces of data, that is, one state data value supplied from the B-type status memory 153 corresponding to S10 as a parallel load, and a serial shift. As one status data value supplied from the preceding register. Then, of these two pieces of state data, the state data value determined to be most likely is supplied to the subsequent register according to the selection signal SEL00. Since all of the selectors 201 _{0 to} 201 _n-1 follow the same selection signal SEL00, the state data as a series of maximum likelihood state data values selected by the ACS 133 is inherited.

Further, each of the registers 202 _{0 to} 202 _n-1 updates the held state data value by taking in the state data value supplied as described above according to the clock. Further, as described above, the output of each register is supplied to a status memory corresponding to a state that can transition after one clock. That is, since it can transit to S00 itself, it is supplied to the subsequent selector as a serial shift. The parallel load is supplied to the B-type status memory 152 corresponding to S01. The nth state data value is output from the last stage register 202 _n−1 .

Further, when the status data value VM00 is extracted from the A-type status memory 150, an output selector 203 is provided. The output selector 203, n pieces of output from the outputs of the first register 202 ₀ to the output of the last register 202 _n-1 is supplied. A select signal for controlling the output selector 203 is generated by the select signal generation circuit 204. Control data Reg and switching signal S from the register 16 are supplied to the select signal generation circuit 204. The output selector 203 selects one input as VM00 by the select signal.

  The select signal selects the output of a predetermined register when decoding the reproduction signal of the header area, and in the data area, the select register outputs the memory length indicated by the control data Reg. The output selector 203 is controlled to select the output. Thus, the memory length can be set independently for the header area and the data area, and the memory length at the time of reproducing the data area can be set by calibration.

  The A type status memory 151 corresponding to the state S11 is configured in the same manner as the A type status memory 150. However, state data is supplied from the B-type status memory 152 corresponding to S01 as a parallel load corresponding to the state transition S01 → S11 in FIG. Further, state data is supplied to the B-type status memory 153 corresponding to S10 as a parallel load corresponding to the state transition S11 → S10 in FIG.

On the other hand, with reference to FIG. 22, the B-type status memory 152 corresponding to the state S01 will be described in more detail. The B-type status memory does not inherit itself in FIG. 16, and corresponds to a state in which only one state can transition after one clock. For this reason, no serial shift is performed and no selector is provided. Therefore, n registers 212 ₀ , 212 ₁ ,... 212 _n-1 are provided, and a clock is supplied to each register to match the operation timing.

State data inherited from the A-type status memory 150 corresponding to S00 is supplied to each of the registers 212 ₀ , 212 ₁ ,... 212 _n−1 as SMin composed of n−1 state data values. However, the register 212 ₀ on the first processing stage, always in synchronization with the clock '00' is inputted. This operation corresponds to the fact that the latest state transition that can transit to S01 is always S00, as shown in FIG. Each of the registers 212 _{0 to} 212 _n-1 updates the held state data value by taking in the supplied state data value according to the clock. The output of each register made according to the clock is supplied to the A-type status memory 151 corresponding to the state S11 that can transition after one clock as the state data SMout consisting of n-1 state data values. The nth state data is output from the last stage register 212 _n−1 .

Further, an output selector 213 is provided when the state data VM01 is taken out. The output selector 213, n pieces of output from the outputs of the first register 212 ₀ to the output of the last register 212 _n-1 is supplied. A select signal for controlling the output selector 213 is generated by the select signal generation circuit 214. Control data Reg and switching signal S from the register 16 are supplied to the select signal generation circuit 214. The output selector 213 selects one input as VM01 by the select signal.

  The select signal selects the output of a predetermined register when decoding the reproduction signal of the header area, and in the data area, the select register outputs the memory length indicated by the control data Reg. The output selector 213 is controlled so as to select the output. Thus, the memory length can be set independently for the header area and the data area, and the memory length at the time of reproducing the data area can be set by calibration.

  The B type status memory 153 corresponding to the state S10 is configured similarly to the B type status memory 152. However, state data is supplied from the A-type status memory 151 corresponding to S11 as a parallel load corresponding to the state transition S11 → S10 in FIG. Further, state data is supplied to the A-type status memory 150 corresponding to S00 as a parallel load corresponding to the state transition S10 → S00 in FIG. Further, “11” is always input to the register as the first processing stage in synchronization with the clock. As shown in FIG. 16, this operation corresponds to the fact that the state one clock before that can transit to S10 is S11.

  By the way, in the Viterbi decoding method, the status data values generated by the status memories are essentially the same. Therefore, the four status data values VM00, VM11, VM01 and VM10 generated by the four status memories in the SMU 134 should match. However, when the signal quality of the reproduction RF signal is deteriorated due to poor data recording conditions or a physical defect in the recording medium, the four state data values VM00, VM11, VM01 and The VMs 10 may not match each other. On the premise that such a mismatch between state data values occurs with a certain degree of probability, a configuration is often provided that selects the most accurate state data value when a mismatch occurs. The merge block 135 to be described later includes such a configuration.

  If the number of mismatches between the state data values can be counted when the memory length of the status memory is constant, the count value can be used for evaluating the quality of the state data and the decoded data generated based on the count. The count value can also be used to evaluate the signal quality of the reproduction signal and the degree of adaptation to the reproduction signal, such as the operation parameters of each component in the reproduction system. In the embodiment of the present invention, the memory length of the path memory or the state memory may be switched based on the result of this evaluation. The merge block 135 described later includes a configuration for performing such counting.

  The merge block 135 will be described with reference to FIG. The merge block 135 includes a state selection circuit 250 that selects an accurate state data value VM00, VM11, VM01, and VM10 supplied from the SMU 134 at a timing according to a clock, a register 251 that delays the output of the state selection circuit 250 by one clock, The decoding matrix unit 252 and the mismatch detection circuit 253 for detecting the mismatch of the state data values VM00, VM11, VM01 and VM10 are provided.

  The state selection circuit 250 refers to the 2-bit signal MS supplied from the ACS 133 as described above, selects the most appropriate one of VM00, VM11, VM01, and VM10, and selects the selected state data value. Is output as a VM. The state selection circuit 250 selects a VM as shown in FIG. In this way, the probability that the most correct state data value is selected can be increased.

  The VM selected as described above is supplied to the register 251 and the decoding matrix unit 252. The register 251 supplies the supplied VM to the decoding matrix unit 252 with a delay of one clock. In the following description, the output of the register 251 is expressed as VMD. Accordingly, the decoding matrix unit 252 is supplied with the state data value VM and the state data value VMD one clock before. The decoding matrix unit 252 outputs the decoded data value based on the VM and the VMD according to the decoding matrix (decoding table) shown in FIG. The decoding matrix may be held as a ROM table, or may have a hardware configuration. By performing such an operation at a timing according to the clock, decoded data is generated.

  The decoding matrix in FIG. 25 will be described. It can be seen from the state transition diagram of FIG. 16 that the decoded data value corresponds to two consecutive state data values. For example, when the state data value VM at time t is “01” and the state data value VMD at time t−1 one clock before is “00”, “1” corresponds to the decoded data value. FIG. 25 summarizes such correspondence.

  On the other hand, the mismatch detection circuit 253 can be configured using, for example, an exclusive OR circuit. The mismatch detection circuit 253 is supplied with VM00, VM11, VM01 and VM10, and a mismatch between these four state data values is detected. The detection result is output as a mismatch detection signal NM. The mismatch detection signal NM is enabled or active except when all four state data values match. In one embodiment of the present invention, the mismatch detection circuit 253 is provided in the merge block 135. However, provided that the status data output from the SMU 134 can be supplied at other positions. May be.

  The mismatch detection signal NM is output every time four status data values are supplied, that is, at a timing according to the clock, and is supplied to a predetermined counting means provided in the controller 2. With such a configuration, the number of mismatches occurring between the four status data values is counted for a predetermined period, for example, one sector. The reason why the mismatch detection circuit 253 is provided is to evaluate the reliability of the decoded data, the quality of the reproduced signal, and the like based on the counting result.

  In the above-described embodiment of the present invention, the present invention is applied to a magneto-optical disk apparatus that performs a four-value four-state Viterbi decoding method. On the other hand, the present invention can also be applied to magneto-optical disk apparatuses that perform other types of Viterbi decoding methods such as the above-described ternary 4-state Viterbi decoding method and 7-value 6-state Viterbi decoding method. In such a case, the SMU has a number of status memories equal to the number of states.

  In addition, the present invention can be applied to an information reproducing apparatus that can use a Viterbi decoding method for decoding read data from a reproduction signal reproduced from data recorded on a recording medium. That is, in addition to the magneto-optical disk (MO), for example, a rewritable disk such as a phase change disk PD, CD-E (CD-Erasable), a write-once disk such as a CD-R, and a read-only disk such as a CD-ROM. It is possible to apply to an optical disc device such as the above. For example, even in the case of the phase change type disk PD, the address and the like are recorded by embossing, and the data is recorded in the data area by the phase change.

  Further, the present invention is not limited to this embodiment, and various applications and modifications can be considered without departing from the gist of the present invention.

1 is a block diagram showing an overall configuration of an embodiment in which the present invention is applied to a magneto-optical disk apparatus. It is a basic diagram for demonstrating the mark position recording method and the mark edge recording method. It is a basic diagram for demonstrating an example of the track format of a magneto-optical disk. It is a basic diagram for demonstrating an example of the sector format of a magneto-optical disc. It is a flowchart for demonstrating an example of a calibration operation | movement. FIG. 5 is a schematic diagram showing that a minimum magnetization reversal width is 2 in the RLL (1,7) encoding method. When the reproduction signal reproduced from the data recorded by the combination of the RLL (1, 7) code and the mark edge recording method is waveform-equalized under the partial response characteristic PR (1, 2, 1), It is a basic diagram for demonstrating a pattern. It is a basic diagram for demonstrating the process which produces the state transition diagram of a 4 value 4 state Viterbi decoding method. It is a basic diagram which shows an example of the state transition diagram of a 4 value 4 state Viterbi decoding method. It is a basic diagram which shows an example of the trellis diagram in a 4 value 4 state Viterbi decoding method. In the 4-value 4-state Viterbi decoding method, it is a basic diagram which shows the conditions of the state transition based on a normalization metric. It is a block diagram which shows the whole structure of the Viterbi decoder which performs 4-value 4 state Viterbi decoding. It is a block diagram which shows in detail the structure of a part of Viterbi decoder shown in FIG. It is a block diagram which shows in detail the structure of the other part of the Viterbi decoder shown in FIG. FIG. 13 is a block diagram showing in detail the configuration of still another part of the Viterbi decoder shown in FIG. 12. FIG. 10 is a schematic diagram illustrating an example of a state transition diagram of a four-value four-state Viterbi decoding method using a different notation method from FIG. 9. It is a basic diagram for demonstrating the notation method of a branch metric. It is a block diagram which shows the whole structure of the other embodiment of this invention. It is a block diagram which shows an example of a structure of ACS (addition, comparison, selection circuit) used for other embodiment of this invention. It is a block diagram which shows an example of a structure of SMU (status memory unit) used for other embodiment of this invention. It is a block diagram for demonstrating the structure of a part of SMU. It is a block diagram for demonstrating the other one part structure of SMU. It is a block diagram which shows an example of a structure of the merge block used for other form of implementation of this invention. It is a basic diagram for demonstrating selection operation | movement of the state data value in a merge block. It is a basic diagram which shows an example of the table referred when decoding data is produced | generated in a merge block.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Controller, 4 ... Laser power control part (LPC), 6 ... Magneto-optical disk, 7 ... Optical pick-up, 10 ... Changeover switch, 11 ... Filter part, 12 ... A / D converter, 13 ... Viterbi decoder, 14 ... PLL unit, 20 ... branch metric calculation circuit (BMC), 21 ... addition, comparison and selection circuit (ACS), 22 ..Compression and latch circuit, 23... Path memory unit (PMU), 24... A type path memory, 25... B type path memory, 26. Type path memory 33... Output selector 34... Select signal generation circuit 35... Output selector 36 .. select signal generation circuit 130 .. Viterbi decoder 132. Calculation circuit (BMC), 133 ... Addition, comparison and selection circuit (ACS), 134 ... Status memory unit (SMU), 135 ... Merge block, 150 ... Type A status Memory 151, A type status memory, 152 ... B type status memory, 153 ... B type status memory, 203 ... Output selector, 204 ... Select signal generation circuit, 213 ... Output Selector, 214... Select signal generation circuit

Claims (4)

An information reproducing apparatus configured to decode a reproduction signal reproduced from a recording medium by a Viterbi decoding method,
The reproduction signal is supplied to the Viterbi decoding means,
In the Viterbi decoding means, to generate a decoded data as a sequence of the maximum likelihood state transition and the corresponding decoded data values to be selected as the setting of the memory length of the path memory,
When decoding the reproduction signal of the first area, which is an area where pits are formed by embossing , select the output of a predetermined register,
A recordable data area, in case of decoding the reproduction signal of the second region, so that memory length indicated by the control data, so as to select the output of register, controls the output selector ,
The memory length of the path memory when decoding the reproduction signal of the first area is set shorter than the memory length of the path memory when decoding the reproduction signal of the second area. An information reproducing apparatus characterized by the above. An information reproducing apparatus configured to decode a reproduction signal reproduced from a recording medium by a Viterbi decoding method,
The reproduction signal is supplied to the Viterbi decoding means,
In the above Viterbi decoder, it generates the state data of the sequence of the maximum likelihood state transition and the corresponding status data values to be selected as the setting of the memory length of the state memory,
When decoding the reproduction signal of the first area, which is an area where pits are formed by embossing , select the output of a predetermined register,
A recordable data area, in case of decoding the reproduction signal of the second region, so that memory length indicated by the control data, so as to select the output of register, controls the output selector ,
The memory length of the path memory when decoding the reproduction signal of the first area is set shorter than the memory length of the path memory when decoding the reproduction signal of the second area. An information reproducing apparatus characterized by the above. Data is experimentally recorded in the second area of the recording medium, the recorded data is reproduced, and the number of mismatches occurring between a plurality of state data values in the merge block during reproduction is counted for each sector. 3. The information reproducing apparatus according to claim 1, wherein the quality of the reproduction signal is determined based on the counting result, and the memory length is set according to the determination result. The recording medium is a disk-shaped recording medium;
The recording area of the disc-shaped recording medium is divided into a plurality of zones in the radial direction,
3. The information reproducing apparatus according to claim 1, wherein the memory length is set in each of the zones.

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