JPH10269648A - Information reproducing device and information reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a state data for expressing a max. likelihood state transition in a viterbi decoding method of parallel processing and to detect a phase error based on the state data. SOLUTION: The state and as a series of state data values expressing the state itself of them is generated by an SMU(status memory unit) 134 corresponding to the max. likelihood state transition selected at every two read clocks by an ACS 133 in a viterbi decoder 130 for parallel processing. From such a state data, the rise and fall of a regenerative RF signal are recognized with reference to a state transition chart to obtain sampling timing for detecting a phase error. Based on a regenerative signal value (a sampling value by an A/D converter 12) fetched by this timing, a phase error signal PE is generated by a PEC 137, and this phase error signal PE is used for oscillation of a VCO 140.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus such as a magneto-optical disk device and a reproducing method.

[0002]

2. Description of the Related Art In an information reproducing apparatus such as a magneto-optical disk apparatus, a Viterbi decoding method is widely used as a method for decoding a reproduced signal reproduced from a recording medium. Recently, it has been required to increase the recording density of a recording medium and improve the data transfer rate for an information reproducing apparatus.

[0003] In a Viterbi decoder, ACS is generally a critical path. That is, the time required for the calculation processing by the ACS prevents reduction in the processing time of the entire Viterbi decoder. Therefore, as means for improving the operation speed of the Viterbi decoder, a system clock for controlling the operation timing of the Viterbi decoder is a clock having a frequency half that of the read clock, and two read clocks sampled from the reproduced RF signal are used. Conventionally, a Viterbi decoder for calculating the reproduction signal values of the minute in parallel has been used.

[0004]

In such a conventional parallel processing Viterbi decoder, based on the result of the parallel calculation processing, a decoded data value of '1' or '0' corresponding to a state transition is obtained. A sequence is generated. Therefore, no state data expressing the state transition itself is generated.

For this reason, it is not possible to detect phase information, that is, a phase error of a read clock used as a sampling clock in an A / D converter preceding the Viterbi decoder, based on the state data.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a Viterbi decoding method in which, when a calculation based on a reproduced signal value is performed by parallel processing, state data representing a maximum likelihood state transition selected based on a result of the parallel processing. And, based on the generated state data, generate decoded data,
An object of the present invention is to provide an information reproducing apparatus and a reproducing method capable of detecting a phase error.

[0007]

According to the present invention, there is provided an information reproducing apparatus for reproducing an information signal recorded on a recording medium, wherein the decoding device decodes a reproduced signal reproduced from the recording medium. As means, in an information reproducing apparatus using the Viterbi decoding method, a clock and a half of the clock are used.
Means for generating a half clock that oscillates at a frequency of .times..times..times..times..times..times..times..times. A Viterbi decoder comprising state data generating means for generating state data for each half clock representing the maximum likelihood state transition itself, and decoded data output means for outputting decoded data based on the state data. An information reproducing apparatus characterized by having:

According to a fifth aspect of the present invention, there is provided an information reproducing method for reproducing an information signal recorded on a recording medium, wherein a Viterbi decoding method is used as a decoding means for decoding a reproduced signal reproduced from the recording medium. And a step of generating a clock and a half clock that oscillates at half the frequency of the clock, and two consecutive reproduced signal values based on the reproduced signal value sampled according to the clock. Generating a state data for each half clock expressing the maximum likelihood state transition itself by performing parallel processing under a timing according to the half clock, using And outputting a Viterbi decoding method.

According to the invention described above, it is possible to generate state data expressing the maximum likelihood state transition selected by the parallel processing.

[0010] Decoded data can be generated from the state data generated in this manner. Further, the timing of phase error detection can be obtained based on the state data. A phase error can be detected based on such a phase error detection timing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate understanding of the present invention, an example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. The outline of the 4-value 4-state Viterbi decoding method will be described in the order of the configuration and operation of the Viterbi decoder that realizes the 4-value 4-state Viterbi decoding method, and the Viterbi decoding method other than the 4-value 4-state Viterbi decoding method.

[Overview of Disc Recording / Reproducing Apparatus] An example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. FIG. 1 is a block diagram showing an overall configuration of an example of a magneto-optical disk device having a reproducing system that performs a Viterbi decoding method. At the time of recording, the controller 2 receives user data to be recorded according to a command from the host computer 1. Then, the controller 2 supplies the user data to the encoder 3. In addition to such processing, the controller 2 performs operations such as decoding processing described later, control of each mode such as recording, reproduction, and erasing, and communication with the host computer 1. The encoder 3
Applying encoding such as block encoding to the supplied data,
Generate a codeword. This code word is used as recording data as a laser power control unit (hereinafter referred to as LPC) 4
Supplied to

The LPC 4 performs recording by controlling the laser power of the optical pickup 7 to form a pit row having a magnetic polarity on the magneto-optical disk 6 in accordance with the supplied recording data. At the time of this recording, the magnetic head 5 applies a bias magnetic field to the magneto-optical disk 6. Actually, mark edge recording as described later is performed according to a precode output generated as described later based on the recording data.

As will be described later, the recording position, that is, the pit formation position is controlled by means (not shown) for positioning the magnetic head 5 and the optical pickup 7 and the like. For this reason, even during the recording operation, when the optical pickup 7 passes through the address section and the like, the same operation as the reproducing operation described later is performed.

A method for associating each pit formed as described above with each bit in a precode output generated as described later based on recording data will be described with reference to FIG. A recording method in which a pit is formed for, for example, "1" and no pit is formed for "0" in the precode output is called a mark position recording method.
On the other hand, a recording method in which the inversion of the polarity at the boundary of each bit in the precode output expressed by the edge of each pit corresponds to, for example, “1” is called a mark edge recording method. During playback, the boundaries of each bit in the playback signal are
It is recognized in accordance with a read clock DCK generated as described later.

Next, the configuration and operation of the reproducing system will be described. The optical pickup 7 irradiates the magneto-optical disk 6 with laser light, receives reflected light generated thereby,
Generate a playback signal. The reproduction signal is composed of a sum signal R ₊ , a difference signal R _−, and a focus error signal and a tracking error signal (not shown). The sum signal R ₊ is supplied to the changeover switch 10 after the gain is adjusted by the amplifier 8. Also, the difference signal R
_- the gain adjustment and the like are supplied to a switch 10 switching after being made by the amplifier 9. Further, the focus error signal is supplied to a means (not shown) for eliminating the focus error. On the other hand, the tracking error signal is
It is supplied to a servo system and the like (not shown) and used in those operations.

The changeover switch 10 is supplied with a changeover signal S as described later. Changeover switch 10, in accordance with the switching signal S, as follows, the sum signal R ₊ or difference signals R _- supplies the waveform equalizer 11. That is, in a sector format of the magneto-optical disk 6 described later, during a period in which a reproduction signal reproduced from a portion formed by embossing is supplied to the changeover switch 10, the sum signal R ₊ is converted to the waveform equalizer 11 To supply.
Further, during a period in which a reproduction signal reproduced from a portion recorded magneto-optically is supplied to the changeover switch 10, the difference signal R ₋ is supplied to the waveform equalizer 11.

The switching signal S is generated, for example, as follows. That is, first, a signal reproduced from a predetermined pattern defined in the sector format is detected from the reproduced signal. As such a predetermined pattern, for example, a sector mark SM described later is used. Then, the switching signal S is generated by a method such as counting read clocks, which will be described later, based on the point in time when the detection is performed.

The waveform equalizer 11 performs a waveform equalization process (filtering) on the supplied reproduced signal. As will be described later, the waveform equalization characteristics used in this waveform equalization process are adapted to the Viterbi decoding method performed by the Viterbi decoder 13. The Viterbi decoder 13 generates decoded data from the supplied signal by a Viterbi decoding method. Such decoded data is a maximum likelihood decoded sequence for the recorded data recorded as described above. Therefore, when there is no decoding error, the decoded data matches the recorded data.

The decoded data is supplied to the controller 2. As described above, the recording data is a codeword generated from user data by encoding such as channel encoding. Therefore, if the decoding error rate is sufficiently low, the decoded data can be regarded as recording data as a codeword. The controller 2 reproduces the user data by subjecting the decoded data to a decoding process corresponding to the encoding such as the channel encoding described above.

The output of the waveform equalizer 11 is also supplied to a PLL unit 14. The PLL unit 14 generates a read clock DCK based on the supplied signal. The read clock DCK is supplied to the controller 2, the A / D converter 1
2. It is supplied to the Viterbi decoder 13 and the like. The operations of the controller 2, the A / D converter 12, and the Viterbi decoder 13 are performed at timing according to the read clock DCK. Further, the read clock DCK is supplied to a timing generator (not shown). The timing generator
For example, it generates a signal for controlling operation timing of the apparatus such as switching between recording / reproduction operations.

In the reproducing operation as described above, in order to obtain more correct reproduction data based on the reproduction signal reproduced from the magneto-optical disk 6, the operation of each component of the reproduction system is performed according to the quality of the reproduction signal. Optimization is performed.
Such an operation is called calibration. The calibration is for coping with the possibility that the quality of the reproduced signal and the like may change depending on the characteristics of the recording medium such as processing accuracy and the recording / reproducing conditions such as the ambient temperature. The contents of the calibration are
For example, adjustment of the laser beam power of the optical pickup 7, adjustment of the gains of the amplifiers 8 and 9, adjustment of the waveform equalization characteristics of the waveform equalizer 11, adjustment of the amplitude reference value used in the operation of the Viterbi decoder 13, and the like. is there. Such calibration is performed by a configuration not shown in FIG. 1 immediately after the power is turned on or when the recording medium is replaced.

[Overview of Sector Format of Recording Medium]
The user data is recorded on the magneto-optical disk 6 using a sector as a recording / reproducing unit. An example of a sector format used in the magneto-optical disk 6 will be described with reference to FIG. As shown in FIG. 3A, one sector is divided into respective areas of a header, an ALPC, a gap, a VFO ₃ , a sync, a data field, and a buffer in the order of recording / reproduction. The numbers attached in FIG.
Indicates the number of bytes. Encoded data such as block encoding is recorded on the magneto-optical disk 6. For example, 8 bits are converted into 12 channel bits and recorded.

As an example of this sector format, a format having a user data amount of 1024 bytes and a format having a user data amount of 512 bytes are prepared. In the format in which the user data amount is 1024 bytes, the number of bytes in the data field is 670 bytes.
Bytes. In the format in which the amount of user data is 512 bytes, the number of bytes in the data field is one.
278 bytes. In these two sector formats, the preformatted header of 63 bytes and the 18 bytes of the ALPC and gap area are the same.

FIG. 3B shows a 63-byte header in an enlarged manner. The header is a sector mark SM (8 bytes), VF
O field VFO ₁ (26 bytes), address mark AM (1 byte), ID field ID ₁ (5 bytes), VFO field VFO ₂ (16 bytes), address mark AM (1 byte), ID field ID
₂ (5 bytes) and postamble PA (1 byte) are arranged in order.

FIG. 3C shows an enlarged 18 byte ALPC and gap area. 18 bytes are a gap field (5 bytes), a flag field (5 bytes),
It consists of a gap field (2 bytes) and ALPC (6 bytes).

Next, these fields will be described. The sector mark SM is a mark for identifying the start of a sector, and has a pattern formed by embossing that does not occur in the RLL (1, 7) code.
The VFO field is the VFO (V
ariable Frequency Oscillator), and is composed of VFO ₁ , VFO ₂ and VFO ₃ . V
FO ₁ and VFO ₂ are formed by embossing. The VFO ₃ is written magneto-optically when a recording operation is performed on the sector. VFO ₁ , V
FO ₂ and VFO ₃ are patterns (2T patterns) in which channel bits “0” and “1” appear alternately, respectively.
Having. Therefore, if the time corresponding to the time length of one channel bit is T, a reproduced signal whose level is inverted every 2T is obtained when the VFO field is reproduced.

The address mark AM is used to provide byte synchronization to the device for the subsequent ID field and has an embossed pattern that does not occur in the RLL (1,7) code. The ID field includes a sector address, that is, information of a track number and a sector number, and a CRC for error detection for the information.
Has bytes. The ID field consists of 5 bytes. The ID ₁ and ID _2, the same address information is recorded in duplicate. The postamble PA has a pattern (2T) in which channel bits “0” and “1” appear alternately.
Pattern). ID ₁ , ID ₂ and postamble PA are also formed by embossing. Thus, the header area is a preformatted area in which pits are formed by embossing.

FIG. 3C shows the ALPC and the gap area in an enlarged manner. No pit is formed in the gap. The first gap field (5 bytes) is the first field after the preformatted header, which ensures that the device will have time to process after reading the header. The second gap field (2 bytes) is for allowing a displacement of the position of VFO ₃ later.

In the ALPC and gap area, a 5-byte flag field is recorded. In the flag field, a continuous 2T pattern is recorded when sector data is recorded. ALPC (Auto Laser Power Cont
The (rol) field is provided for testing the laser power at the time of recording. Sync field (4 bytes)
Is provided for the device to obtain byte synchronization for the subsequent data field and has a predetermined bit pattern.

The data field is provided for recording user data. The above-mentioned 670-byte data field includes 512-byte user data and 14 bytes.
It consists of 4 bytes of parity for error detection and correction, 12 bytes of sector write flag, and 2 bytes (FF). In the case of a 1278-byte data field, the data field includes 1024-byte user data, 242-byte parity for error detection and correction, and a 12-byte sector write flag. The buffer field at the end of the sector is used as a tolerance for electrical or mechanical errors.

In the above example of the sector format, the header is an area in which pits are formed by embossing. The ALPC and gap areas are not used during reproduction. In addition, VFO
_{3. The} sync field and the data field are areas of magneto-optically recorded data.

[Summary of 4-value 4-state Viterbi decoding method] The Viterbi decoding method performed by the Viterbi decoder 13 will be described below. As described above, the user data is
It is converted into a codeword as recording data by various encoding methods. An appropriate encoding method is adopted according to the characteristics of the recording medium and the recording / reproducing method. In the magneto-optical disk drive, in the block coding, Ru
In many cases, an RLL (Run Length Limited) coding method for limiting the n Length, that is, the number of '0's between' 1 'and' 1 'is used. Conventionally, several RLL coding methods have been used. Generally, an m / n block code in which the number of '0's between' 1 'and' 1 'is at least d and at most k is RLL
(D, k; m, n) code.

For example, in a 2/3 block code,
A block coding method in which the number of '0's between 1' and '1' is at least one and at most seven is RLL (1,7; 2,3)
Sign. Generally, the RLL (1, 7; 2, 3) code is R
Since it is often referred to as an LL (1, 7) code, the RLL (1, 7; 2, 3) code will be simply referred to as an RLL (1, 7) code in the following description. .

A Viterbi decoding method is used to decode a reproduced signal to be reproduced and obtain read data from data recorded by a combination of the RLL encoding method and the mark edge recording method described above. be able to.

Such an RLL encoding method can meet the conditions required for the encoding method from the two viewpoints of improving the recording density and ensuring the stability of the reproducing operation. First, as described above, the mark edge recording method associates '1' in the precode output generated as described later based on the recording data with the inversion of the polarity represented by the edge of each pit. '1'
As the number of '0's between' 1 'and' 1 'is increased, the number of bits recorded per pit can be increased. Therefore, the recording density can be increased.

On the other hand, the read clock DCK necessary for adjusting the operation timing of the reproduction system is generated by the PLL section 14 based on the reproduction signal as described above. For this reason, in the recorded data, a value between '1' and '1'
When the number of 0's is increased, the operation of the PLL unit becomes unstable during the reproducing operation, so that the entire reproducing operation becomes unstable.

Considering these two conditions, '1' and '
The number of '0's between 1's must be set within a reasonable range, not too high or too low. The RLL encoding method is effective for setting the number of '0' in the recording data.

By the way, as shown in FIG.
In the combination of the LL (1, 7) encoding method and the mark edge recording method, "1" and "1" in the recording data (excluding precode output when precoding is performed as described later) are performed. Since at least one '0' is included in between, the minimum inversion width is 2. When such an encoding method with a minimum inversion width of 2 is used, in order to correctly decode recorded data from a reproduced signal affected by intersymbol interference and noise, as described later, 4 A 4-state Viterbi decoding method can be applied.

As described above, the waveform equalization processing is performed on the reproduced signal by the waveform equalizer 11. Such a waveform equalization process performed as a preceding stage of the Viterbi decoding method includes:
A partial response method that actively uses intersymbol interference is used. The waveform equalization characteristics used at this time are:
From the partial response characteristics generally represented by (1 + D) ⁿ , the linear recording density and MTF of the recording / reproducing system
(Modulation TransferFunction). Waveform equalization processing using PR (1, 2, 1) for data recorded by a combination of the above-described RLL (1, 7) encoding method and mark edge recording method requires 4
This is the preceding stage of the 4-state Viterbi decoding method.

On the other hand, in the mark edge recording method,
Prior to actual recording on a magneto-optical disk medium, etc.,
Precoding based on the recording data encoded by the above-described RLL encoding or the like is performed. The recording data sequence at each time point k is a [k], and the precode output based on this is b
When [k] is set, precoding is performed as follows.

B [k] = mod 2 {a [k] + b [k−1]} (1) Such a precode output b [k] is actually recorded on a magneto-optical disk medium or the like. On the other hand, the equalization characteristics PR (1,
The waveform equalization process performed by the waveform equalizer 11 under (2, 1) will be described. However, in the following description, without equalizing the signal amplitude, the equalization characteristic is set to PR (B,
2A, B). The value of the reproduced signal when noise is not considered is denoted as c [k]. Further, an actual reproduced signal including noise (that is, a reproduced signal reproduced from a recording medium) is denoted by z [k].

PR (B, 2A, B) indicates that the contribution of the amplitude at time point k to the value of the reproduced signal at a certain time point k is 2A times the amplitude value. The contribution of the amplitude is B times the amplitude of the signal at each point in time. Accordingly, the maximum value of the value of the reproduction signal is a case where a pulse is detected at any of the time points k-1, k, and k + 1. In such a case, the maximum value of the reproduction signal is as follows.

B + 2A + B = 2A + 2B The minimum value of the reproduced signal is 0. However, in the actual handling, the DC component A +
The following is obtained by subtracting B.

C [k] = B × b [k−2] + 2A × b [k−1] + B × b [k] −AB (2) Therefore, the reproduced signal c [k when noise is not considered. ]
Takes any value among A + B, A, -A, and -AB. Generally, one of the methods for indicating the property of a reproduced signal
For example, a pattern obtained by superimposing a large number of reproduction signals in units of five time points is called an eye pattern. FIG. 5 shows an example of an eye pattern of an actual reproduction signal z [k] subjected to waveform equalization processing under PR (B, 2A, B) in a magneto-optical disk drive to which the present invention can be applied. . From FIG. 5, the reproduced signal z [k] at each time point
Has a variation due to noise, but is approximately A +
It can be confirmed that any one of B, A, -A, and -AB is obtained. As described later, A + B, A, -A, -AB
Is used as an amplitude reference value.

An outline of a Viterbi decoding method for decoding a reproduced signal having undergone the above-described waveform equalization processing is as follows. All possible states are identified based on the step encoding method and the recording method for the recording medium. With each state at a certain point as a starting point, all state transitions that can occur at the next point in time, and the recording data a [k] and the value c [k] of the reproduction signal at the time of each state transition are specified. A representation of all states and state transitions specified as a result of the step and the state and [recorded data value a [k] / reproduced signal value c [k]] at the time of each state transition. Is called a state transition diagram. As will be described later, a state transition diagram in the 4-value 4-state Viterbi decoding method is as shown in FIG. Then, to perform a decoding operation based on this state transition diagram,
The Viterbi decoder 13 is configured.

Further, as described above, based on the state transition diagram, the most likely state transition based on the reproduction signal z [k] reproduced from the recording medium at each time point k is selected. However, as described above, z [k] is waveform-equalized in a stage before being supplied to the Viterbi decoder 13. Each time such a maximum likelihood state transition is selected, the value of the recording data a [k] described in the state transition diagram is set as a decoded value in accordance with the selected state transition. Decoded data a '[k] as the maximum likelihood decoded value sequence for the data can be obtained. However, the configuration for obtaining the maximum likelihood decoded value sequence from the decoded data values at each time point k is based on the PMU 23 in the Viterbi decoder 13 described later.
It is. Therefore, as described above, the decoded data sequence a ′
[K] is a record data sequence a when there is no decoding error.
[K]. The above steps are described in detail below.

The above steps will be described. First, as a state used here, a state at a certain time point k is defined as follows using a precode output before the time point k. That is, n = b [k], m =
The state when b [k-1] and 1 = b [k-2] is defined as Snml. With such a definition, it is considered that there are 2 ³ = 8 states, but as described above, the states that can actually occur are limited based on the encoding method and the like. RLL
Recording data sequence a encoded as a (1,7) code
In [k], at least one '0' is included between '1' and '1', so that two or more '1's do not continue.
Based on such conditions imposed on the recording data string a [k], certain conditions are imposed on the precode output b [k], and the resulting states are restricted.

Such a limitation will be specifically described. As described above, in a recording data sequence generated by RLL (1, 7) encoding, there cannot be one in which two or more '1's are continuous, that is, the following.

A [k] = 1, a [k−1] = 1, a [k−2] = 1 (3) a [k] = 1, a [k−1] = 1, a [k− 2] = 0 (4) a [k] = 0, a [k−1] = 1, a [k−2] = 1 (5) Based on such conditions imposed on the recording data sequence, Examining the conditions imposed on b [k] according to the equation (1), it can be seen that the two states S010 and S101 cannot occur. Therefore, there are 2 ³ −2 = 6 possible states.

Next, the steps will be described. In order to obtain a state that can occur at the next time point j + 1 from the state at a certain time point j as a starting point, it is necessary to separately examine the case where the value a [j + 1] of the recording data at the time point j + 1 is 1 and 0. There is.

Here, the state S000 will be described as an example. According to the above equation (1), S000, that is, n = b
[J] = 0, l = b [j-1] = 0, m = b [j-2]
The recording data pre-coded as = 0 is the following 2
Individuals can be considered.

A [j] = 0, a [j−1] = 0, a [j−2] = 1 (6) a [j] = 0, a [j−1] = 0, a [j− 2] = 0 (7) [when a [j + 1] = 1] At this time, according to equation (1),
b [j + 1] is calculated as follows.

B [j + 1] = mod2 {a [j + 1] + b [j]} = mod2 {1 + 0} = 1 (8) Therefore, the value of the reproduced signal c [j] is calculated according to the above equation (2). Is calculated as follows.

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 1 + 2A × 0 + B × 0} −AB = − A (9) Also, for the state Snlm at the next time point j + 1, n =
b [j + 1], 1 = b [j], and m = b [j-1]. Then, as described above, b [j + 1] = 1, b
Since [j] = 0 and b [j-1] = 0, the next time point j
The state at +1 is S100. Therefore, a [j
+1] = 1, it can be specified that a transition of S000 → S100 occurs.

[When a [j + 1] = 0] At this time, b [j + 1] is calculated as follows according to the equation (1).

B [j + 1] = mod2 {a [j + 1] + b [j]} = mod2 {0 + 0} = 0 (10) Therefore, the value of the reproduced signal c [j + 1] is calculated according to the above equation (2). Is calculated as follows.

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 0 + 2A × 0 + B × 0} −AB = − AB (11) Further, regarding the state Snlm at the next time point j + 1,
n = b [j + 1], 1 = b [j], and m = b [j-1]. Then, as described above, b [j + 1] = 0, b
Since [j] = 0 and b [j-1] = 0, the state at the next time point is S000. Therefore, a [j + 1]
If = 0, it can be specified that a transition of S000 → S000 occurs.

In this way, S000 at time j
, The state transitions that can occur at the next time point j + 1 starting from them and the correspondence between the recording data value a [j + 1] and the reproduction signal value c [j + 1] when such state transitions occur Can be requested.

As described above, for each state, the correspondence between the state transition that can occur starting from the state, the value of the recording data and the value of the reproduction signal at the time that each state transition occurs is determined, and the correspondence is shown in the form of a diagram. FIG. 6 shows the result. Time points j and j + 1 described above are not special time points. Therefore, the correspondence between the possible state transitions obtained as described above and the values of the recording data and the values of the reproduction signals accompanying them can be applied at any time. Therefore, FIG.
In, the value of the recording data accompanying the state transition occurring at an arbitrary time point k is denoted as a [k], and the value of the reproduced signal is denoted as c [k].

In FIG. 6, the state transition is represented by an arrow. In addition, the sign given to each arrow indicates [record data value a [k] / reproduction signal value c [k]]. State S
While there are two types of state transitions starting from 000, S001, S111, and S110, only one transition can occur starting from states S011 and S100.

Further, in FIG. 6, S000 and S001
Takes a value of c [k] =-A for a [k] = 1, and transits to S100. On the other hand, a
For [k] = 0, a value of c [k] =-AB is taken, and the process transits to S000. Also, S111 and S1
10 is also the same for the same value of a [k + 1].
It takes the value of [k + 1] and transitions to the same state. Therefore, S000 and S001 can be collectively expressed as S0, and S111 and S110 can be collectively expressed as S2. Further, S011 is set to S3, and S100 is set to S3.
FIG. 7 shows an arrangement that is expressed as 1.

As described above, FIG. 7 is a state transition diagram used in the 4-value 4-state Viterbi decoding method. In FIG. 7,
The four states S0 to S3 and the reproduced signal c [k + 1]
Are shown as -AB, -A, A, and A + B. There are two types of state transition starting from the states S0 and S2, whereas only one state transition starting from the states S1 and S3.

On the other hand, a trellis diagram as shown in FIG. 8 is used as a format for expressing a state transition along time. FIG. 8 shows a transition between two time points, but a transition between many more time points can also be shown. As the time elapses, a state in which the image sequentially transits to the right time point is expressed. Therefore, a horizontal arrow represents a transition to the same state, for example, S0 → S0, and a diagonal arrow represents, for example, S1 → S2.
And so on.

The steps of the above-described Viterbi decoding method, that is, a method of selecting the maximum likelihood state transition from the actual reproduced signal z [k] including noise, based on the state transition diagram shown in FIG. 7, will be described below. .

In order to select the maximum likelihood state transition, first, for the state at a certain time point k, the sum of the likelihoods of the state transitions between a plurality of time points passed in the process of reaching the state is calculated. It is necessary to select the maximum likelihood decoded sequence by comparing the calculated sums of likelihoods. Such a sum of likelihoods is called a path metric.

In order to calculate a path metric, it is first necessary to calculate the likelihood of a state transition between adjacent time points. Such calculation of the likelihood is performed as follows based on the value of the reproduced signal z [k] with reference to the above state transition diagram. First, as a general explanation, the time k-
Consider the case where the state is Sa in state No. 1. At this time, when the reproduction signal z [k] is input to the Viterbi decoder 31, the likelihood that a state transition to the state Sb occurs is calculated according to the following equation. However, the state Sa and the state Sb are any of the four states described in the state transition diagram of FIG.

(Z [k] −c (Sa, Sb)) ² (12) In the above equation, c (Sa, Sb) represents the state transition from the state Sa to the state Sb in the state transition diagram of FIG. This is the value of the described reproduction signal. That is, in FIG. 7 described above, for example, for the state transition S0 → S1, the value is calculated as −A. Therefore, equation (12) is the Euclidean distance between the value of the actual reproduced signal z [k] including noise and the value of the reproduced signal c (Sa, Sb) calculated without considering noise. The path metric at a certain point in time is defined as the sum of likelihoods of state transition between such adjacent points up to that point.

Now, consider the case where the state Sa is at time k. In this case, at time k-1, the state S
If the state that can transition to a is Sp, the path metric L
(Sa, k) is calculated by the following equation using the path metric at the time point k-1.

L (Sa, k) = L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² (13) That is, when the state Sp is reached at the time point k−1 The path metric L (Sp, k−1) and the likelihood (z (z) of the state transition Sp → Sa occurring between the time points k−1 and k)
[K] −c (Sp, Sa)) ² and the path metric L (Sa, k) is calculated. The likelihood of the latest state transition such as (z [k] -c (Sp, Sa)) ² is called a branch metric. However, as will be described later, it should be noted that the branch metric calculated by the branch metric calculation circuit (BMC) 20 in the Viterbi decoder 13, that is, the branch metric corresponding to the normalized metric is different. is necessary.

When the state Sa is at the time point k, there may be a plurality of states that can transition to the state Sa at the time point k-1. In FIG. 7, states S0 and S2 are such cases. That is, if the state S0 is at time k, the state S
There are two states that can transition to 0: S0 and S3. Further, when the state is the state S2 at the time point k, the time point k−1
The states that can transition to the state S2 in are two of S1 and S2.
Individual. As a general explanation, at time k, state S
If the state is a and the two states that can transition to the state Sa at the time point k−1 are Sp and Sq, the path metric L (Sa, k) is calculated as in the following equation.

L (Sa, k) = min ｛L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² , L (Sq, k−1) + (z [k] −c (Sq, Sa)) ² ｝ (14) That is, at time k−1, the state Sp is in effect, and Sp →
The sum of the likelihoods is calculated for each of the case where the state Sa is reached by the state transition Sa and the case where the state Sq is reached at the time k-1 and the state Sq is reached by the state transition Sq → Sa. Then, the respective calculated values are compared, and the smaller value is set as the path metric L (Sa, k) for the state Sa at the time point k.

The calculation of such a path metric is shown in FIG.
Is specifically applied to the above-described quaternary and four states by using, the respective states S0, S1, S2 and S3 at time k
Path metrics L (0, k), L (1,
k), L (2, k) and L (3, k) are at time k−1
Path metric L for each state S0 to S3 in
It can be calculated as follows using (0, k-1) to L (3, k-1).

L (0, k) = min {L (0, k−1) + (z [k] + A + B) ² , L (3, k−1) + (z [k] + A) ² } (15 ) L (1, k) = L (0, k−1) + (z [k] + A) ² (16) L (2, k) = min ｛L (2, k−1) + (z [k ] -AB) ² L (1, k-1) + (z [k] -A) ² 17 (17) L (3, k) = L (2, k-1) + (z [k] -A) ² (18) As described above, the value of the path metric calculated in this way is compared, and the maximum likelihood state transition may be selected. By the way, in order to select the maximum likelihood state transition, it suffices if the value of the path metric can be compared without calculating the value of the path metric itself. Therefore, in the actual four-value four-state Viterbi decoding method, by using a normalized path metric as defined below instead of the path metric, calculation based on z [k] at each time point k can be easily performed. It is made to do.

M (i, k) = [L (i, k) −z [k] ² − (A + B) ² ] / 2 / (A + B) (19) Equation (19) is applied to each of S0 to S3. When applied, the specific normalized path metric does not include the square calculation as follows. For this reason, addition, comparison,
Calculation in the selection circuit (ACS) 21 can be facilitated.

M (0, k) = min {m (0, k−1) + z [k], m (3, k−1) + α × z [k] −β} (20) m (1, k ) = M (0, k−1) + α × z [k] −β (21) m (2, k) = min ｛m (2, k−1) −z [k], m (1, k−) 1) −α × z [k] −β} (22) m (3, k) = m (2, k−1) + α × z [k] −β (23) However, Expressions (20) to (23) Α and β in the parentheses are as follows.

Α = A / (A + B) (24) β = B × (B + 2 × A) / 2 / (A + B) (25) State transition in the 4-value 4-state Viterbi decoding method based on such a normalized path metric FIG. 9 shows the condition (1). Since there are two expressions for selecting one from two of the four normalized path metrics, there are 2 × 2 = 4 conditions.

[Overview of 4-Valued 4-State Viterbi Decoder] A Viterbi decoder 1 that realizes the 4-valued 4-state Viterbi decoding method described above.
3 will be described below. FIG. 10 shows a Viterbi decoder 13.
1 shows the entire configuration. The Viterbi decoder 13 includes a branch metric calculation circuit (hereinafter, referred to as BMC) 20, an addition, comparison, and selection circuit (hereinafter, referred to as ACS) 2
1, a compression and latch circuit 22 and a path memory unit (hereinafter referred to as PMU) 23. The read clock DCK described above is applied to each of these components.
The operation timing of the entire Viterbi decoder 13 is adjusted by supplying (hereinafter, simply referred to as a clock) in the following description. Hereinafter, each component will be described.

The BMC 20 receives the reproduced signal z
Based on [k], branch metric values BM0, BM1, BM2 and B corresponding to the normalized path metric
Calculate M3. BM0 to BM3 are calculated by the above equation (20).
The following are required to calculate the normalized path metric of (23).

BM0 = z (k) (26) BM1 = α × z [k] −β (27) BM2 = −z (k) (28) BM3 = −α × z [k] −β (29) Α and β required for the calculation are reference values having the meanings shown in the above equations (23) and (24). The values of α and β are calculated by predetermined means based on the reproduction signal z [k] and supplied to the BMC 20. As an example of the calculation method, the values of A and B are obtained from the reproduced signal z [k] by a method such as envelope detection, and the values of Expressions (23) and (2) are obtained.
The values of α and β are calculated according to 4).

The values of BM0 to BM3 are supplied to the ACS 21. On the other hand, the ACS 21 is supplied with the values of the normalized path metric one clock before (however, those subjected to compression as described later) M0, M1, M2, and M3 from the compression and latch circuit 22 described later. . Then, M0 to M3 and BM0 to BM3 are added, and the latest standardized path metric value L is added as described later.
Calculate 0, L1, L2 and L3. Since M0 to M3 are compressed, it is possible to avoid overflow when calculating L0 to L3.

Further, the ACS 21 selects the maximum likelihood state transition based on the latest standardized path metric values L0 to L3, as described later, and stores it in the path memory 23 in accordance with the selection result. The supplied selection signals SEL0 and SEL2 are set to “High” or “Low”.

The ACS 21 supplies L0 to L3 to the compression and latch circuit 22. The compression and latch circuit 22 latches the supplied L0 to L3 after compressing them. Thereafter, the normalized path metric M0 one clock before
To the ACS 21 as .about.M3.

As a compression method at this time, for example, as shown below, the latest standardized path metrics L0 to L3
Therefore, a method of uniformly subtracting one of them, for example, L0, is used.

M0 = L0-L0 (30) M1 = L1-L0 (31) M2 = L2-L0 (32) M3 = L3-L0 (33) As a result, M0 always takes a value of 0. However, in the following description, it is denoted as M0 as it is in order not to impair generality. The difference between the values of M0 to M3 calculated by the equations (30) to (33) is equal to the difference between the values of L0 to L3. As described above, in the selection of the maximum likelihood state transition, only the value difference between the normalized path metrics becomes a problem. Therefore, such a compression method is effective as a method of compressing the value of the normalized path metric without affecting the selection result of the maximum likelihood state transition and preventing overflow. Thus, the ACS 21 and the compression and latch circuit 22 form a loop related to the calculation of the normalized path metric.

The above-mentioned ACS 21 will be described in more detail with reference to FIG. The ACS 21 includes six adders 51, 52, 53, 54, 56, 58 and two comparators 55, 57. On the other hand, as described above, A
CS 21 is supplied with compressed standardized path metric values M0 to M3 one clock before and branch metric values BM0 to BM3 corresponding to the standardized path metric.

The adder 51 is supplied with M0 and BM0. The adder 51 adds these to calculate L00 as follows.

L00 = M0 + BM0 (34) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above-described equation (26) based on the reproduced signal z [k] input at the time point k, that is, the value of z [k] itself. Therefore, equation (34)
Is obtained by calculating the value of m (0, k-1) + z [k] in the above equation (20) under the effect of the above-described compression. That is, the state S0 at the time point k-1
This is a calculated value corresponding to the case where the state transition S0 finally arrives at the time point k by the state transition S0 → S0.

On the other hand, M3 and BM1 are added to the adder 52.
Is supplied. The adder 51 adds these to calculate the following L30.

L30 = M3 + BM1 (35) As described above, M3 is in the state S3 at the time point k-1.
, Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, B
M1 is calculated based on the reproduced signal z [k] input at the time point k in accordance with the above equation (27), that is, α × z [k] −β. Therefore, the value of equation (35) is calculated by the above equation (2) under the action of compression as described above.
0) in m (3, k-1) + α × z [k] −β. That is, this is a calculated value corresponding to the case where the state is S3 at the time point k−1 and finally reaches the state transition S0 by the state transition S3 → S0 at the time point k.

The above-mentioned L00 and L30 correspond to the comparator 55
Supplied to The comparator 55 compares the values of L00 and L30, and determines the smaller one as the latest standardized path metric L0.
Then, the polarity of the selection signal SEL0 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (20). That is, when L00 <L30 (in this case, S0 → S0 is selected), L00 is output as L0, and SEL0 is set to, for example, 'Low'. If L30 <L00 (in this case, S3 → S0 is selected), L30 is output as L0, and S30 is output.
EL0 is set to, for example, 'High'. SEL0 is supplied to the A-type path memory 24 corresponding to the state S0, as described later.

As described above, the adders 51 and 52 and the comparator 55 are the most likely state transitions at the time point k from S0 → S0 and S3 → S0 in accordance with the above equation (20). Is performed. Then, it outputs the latest standardized path metric L0 and the selection signal SEL0 according to the selection result.

The adder 56 has M0 and BM1.
Is supplied. The adder 51 adds these to calculate the following L1.

L1 = M0 + BM1 (36) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
1 is a value calculated according to the above equation (27) based on the reproduced signal z [k] input at the time point k, that is, α × z [k] −β. Therefore, the value of equation (36) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (0, k-1) + α × z [k] −β of 1) is calculated. That is, the calculated value corresponds to the case where the state S0 is at the time point k−1 and the state transition S1 is finally reached by the state transition S0 → S1 at the time point k. In response to the expression (21) not selecting a value, the output of the adder 56 is used as it is as the latest standardized path metric L1.

The adder 53 is supplied with M2 and BM2. The adder 53 adds these to calculate the following L22.

L22 = M2 + BM2 (37) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above equation (28) based on the reproduced signal z [k] inputted at the time point k, that is, -z [k]. Therefore, the value of Expression (37) is a value obtained by calculating the value of m (2, k-1) -z [k] in Expression (22) under the effect of the compression described above. . That is, the calculated value corresponds to the case where the state S2 is at the time point k−1 and the state transition S2 is finally reached by the state transition S2 → S2 at the time point k.

On the other hand, the adder 54 has M1 and BM3
Is supplied. The adder 53 adds these values to calculate L12 as described below.

L12 = M1 + BM3 (38) As described above, M1 is in the state S1 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, equation (38)
Is a value obtained by calculating the value of m (1, k−1) −α × z [k] −β in the above equation (22) under the effect of the above-described compression. That is, the calculated value corresponds to the case where the state S1 is at the time point k−1 and the state transition S2 is finally reached by the state transition S1 → S2 at the time point k.

The above-mentioned L22 and L12 are connected to the comparator 57.
Supplied to The comparator 57 compares the values of L22 and L12, and determines the smaller one as the latest standardized path metric L2.
At the same time, the polarity of the selection signal SEL2 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (22). That is, when L22 <L12 (in this case, S2 → S2 is selected), L22 is output as L2, and SEL2 is set to, for example, 'Low'. When L12 <L22 (in this case, S1 → S2 is selected), L12 is output as L2, and S12 is output.
EL2 is set to, for example, 'High'. SEL2 is supplied to the A-type path memory 26 corresponding to the state S2 as described later.

As described above, the adders 53 and 54 and the comparator 57 correspond to the above-mentioned equation (22) to determine the maximum likelihood state transition at time k from S1 → S2 and S2 → S2. Select Then, according to the selection result, the latest standardized path metric L2 and the selection signal SEL2
Is output.

The adder 58 includes M2 and BM3
Is supplied. The adder 58 adds these to calculate the following L3.

L3 = M2 + BM3 (39) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, the value of equation (39) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (2, k-1) + α × z [k] −β of 3) is calculated. That is, the calculated value corresponds to the case where the state S0 is at the time point k−1 and the state transition S3 is finally reached by the state transition S2 → S3 at the time point k. In response to the expression (23) not selecting a value, the output of the adder 58 is used as it is as the latest standardized path metric L3.

As described above, the path memory unit (hereinafter abbreviated as PMU) 23 operates according to SEL0 and SEL2 output from the ACS 21 to decode the recording data a [k] as the maximum likelihood decoding sequence. Data a '[k] is generated. PMU23
In order to cope with the state transition between the four states shown in FIG. 7, it is composed of two A-type path memories and two B-type path memories.

The A-type path memory has two transitions (ie, a transition from itself and a transition from another state) as transitions to the state, and uses the state as a starting point. The configuration is such that it corresponds to a state having two transitions (ie, a transition leading to itself and a transition leading to another single state). Therefore, the A-type path memory corresponds to S0 and S2 among the four states shown in FIG.

On the other hand, the B-type path memory is configured to cope with a state in which there is only one transition to the state and only one transition starting from the state. Therefore, the B-type path memory corresponds to S1 and S3 among the four states shown in FIG.

In order for the two A-type path memories and the two B-type path memories to operate in accordance with the state transition diagram shown in FIG. 7, the PMU 23 transfers the decoded data as shown in FIG. It is configured to be. That is, the A-type path memory 24 corresponds to S0, and the A-type path memory 26 corresponds to S2. Also, the B-type path memory 25
Corresponds to S1, and the B-type path memory 27 corresponds to S3. With this configuration, state transitions that can occur starting from S0 are S0 → S0 and S0 → S1, and
S2 → S2 and S2
This corresponds to 2 → S3. In addition, the state transition that can occur with S1 as the starting point is only S1 → S2, and the state transition that can occur with S3 as the starting point is only S3 → S0.

FIG. 12 shows a detailed configuration of the A-type path memory 24. The A-type path memory 24 includes a number of flip-flops and selectors corresponding to the path memory length,
They are connected alternately. FIG. 12 shows a configuration corresponding to a decoded data length of 14 bits. That is,
Those having fourteen selectors 31 ₁ to 31 ₁₄ and 15 flip-flops 30 ₀ - 30 _14. Each of the selectors 31 _{1 to} 31 ₁₄ receives two pieces of data, and selectively supplies one of them to a subsequent stage. Further, since the clock is supplied to the flip-flop 30 ₀ - 30 _14, the operation timing of the entire A type path memory 24 is combined.

As described above with reference to FIG. 7, the transition to the state S0 is S0 → S0, that is, the transition inherited from itself, and S3 → S0. As a configuration corresponding to such a situation, each selector includes data supplied from the preceding flip-flop, that is, decoded data corresponding to S0 → S0, and B-type path memory 27 corresponding to state S3.
, Ie, decoded data PM3 corresponding to S3 → S0. Further, each selector has A
SEL0 is supplied from CS21. And SEL0
, One of the two supplied decoded data is supplied to the subsequent flip-flop. Further, the decoded data supplied to the subsequent flip-flop in this manner is also stored in the B-type path memory 25 corresponding to the state S1 in the PM.
Supplied as 0.

[0109] That is, for example, the selector 31 _14, the data supplied from the preceding flip-flops 30 _13, B
14-bit P supplied from the pattern path memory 27
And the data in the 14th bit position of M3. Then, the data selected as follows from these two data, and supplies the subsequent flip-flop 30 _14. As described above, SEL0 sets 'L' in accordance with the selection result.
ow 'or' High '. SEL0 When, for example, 'Low' is adapted to data from the preceding flip-flop 30 ₁₃ is selected. If SEL0 is, for example, 'Hig
At the time of h ', the data at the 14th bit position of PM3 is selected. The selected data is supplied to the subsequent flip-flops 30 _14, also 1 PM0
The data at the fourth bit position is supplied to the B-type path memory 25 corresponding to the state S1.

Another selector 31 in the A-type path memory 24
Also in _{1-31 13,} depending on the polarity of the SEL0, similar operations are performed. Therefore, when SEL0 is, for example, "Low", the A-type path memory 24 as a whole performs a serial shift in the A-type path memory 24 in which each flip-flop inherits the data of the flip-flop located at the preceding stage. . Further, when SEL0 is, for example, “High”, a parallel load that inherits the 14-bit decoded data PM3 supplied from the B-type path memory 27 is performed. In any case, the inherited decoded data is stored in the B-type path memory 2.
5 is supplied as 14-bit decoded data PM0.

[0111] In addition, the flip-flop 30 ₀ on the first stage, always in synchronization with the clock '0' is input. This operation is a state transition S0 → S0 and S0 leading to S0.
In any of 2 → S0, as shown in FIG. 7, since the decoded data is “0”, the latest decoded data always corresponds to “0”.

As described above, the configuration of the A-type path memory 26 corresponding to S2 is the same as that of the A-type path memory 2.
4 is exactly the same. However, the selection signal input from the ACS 21 is SEL2. Further, as shown in FIG. 7, transitions to the state S2 include S2 → S2, that is, transitions inherited from the self, and S1 → S2. Therefore, the PM1 is stored in the B-type path memory 25 corresponding to the state S1.
Supplied. Further, in response to the state that can occur starting from the state S2 being S2, ie, itself, and S3, the PM2 is stored in the B-type path memory 27 corresponding to the state S3.
Supply. Also, the A-type path memory 26 corresponding to S2
In this case, '0' is always input to the flip-flop serving as the first processing stage in synchronization with the clock. This operation is performed when the decoded data is “0” as shown in FIG. 7 in any of the state transitions S2 → S2 and S1 → S0 leading to S2.
Therefore, the latest decoded data corresponds to always being '0'.

On the other hand, FIG. 13 shows a detailed configuration of the B-type path memory 25. The B-type path memory 25 has a number of flip-flops connected to the path memory length. FIG. 13 shows a configuration corresponding to a decoded data length of 14 bits. That is, it has 15 flip-flops 32 _{0 to} 32 ₁₄ . By supplying a clock to the flip-flops 32 _{0 to} 32 ₁₄ , the operation timing of the entire B-type path memory 25 is adjusted.

Each of the flip-flops 32 _{1 to} 32 ₁₄ has
14-bit decoded data is supplied as PM0 from the A-type path memory 24 corresponding to the state S0. For example, the first bit of PM0 is supplied to the flip-flop 32 ₁ . Each of the flip-flops 32 _{1 to} 32 ₁₄ holds the supplied value for one clock. Then, it outputs it to the A-type path memory 26 corresponding to the state S2 as 14-bit decoded data PM1. For example, flip-flop 3
2 ₁ outputs the second bit of PM1.

Another selector 32 in the B-type path memory 25
Also in _{1-32 13,} similar operation is performed. Therefore, the entire B-type path memory 25 receives the 14-bit decoded data PM supplied from the A-type path memory 24.
0, and supplies 14-bit decoded data PM1 to the A-type path memory 26.

[0116] In addition, the flip-flop 32 _0, always in synchronization with the clock '1' is input. Such actions are:
As shown in FIG. 7, when the latest state transition is S0 → S1, this corresponds to that the decoded data is “1”.

As described above, the configuration of the B-type path memory 27 corresponding to the state S3 is completely the same as that of the B-type path memory 25. However, as shown in FIG. 7, since the transition to the state S3 is from S2 to S3, PM2 is supplied from the A-type path memory 26 corresponding to the state S2. Further, in response to the state that can occur starting from the state S3 being S0, the A-type path memory 24 corresponding to the state S0
To supply PM3. B type path memory 2
Also in 7, the flip-flop as the first processing stage is always supplied with "1" in synchronization with the clock. This operation is performed as shown in FIG. 7, when the latest state transition is S2 →
The case of S3 corresponds to the fact that the decoded data is '1'.

As described above, each of the four path memories in the PMU 23 generates decoded data. The four pieces of decoded data generated in this way match each other if an accurate Viterbi decoding operation is always performed. By the way, in the actual Viterbi decoding operation, 4
A mismatch may occur between Viterbi decoded data. Such inconsistency is caused by factors such as an error in the detection of the reference values α and β described above due to the influence of noise included in the reproduced signal. In such a case, a configuration (not shown) for selecting a more appropriate one from the four decoded data by, for example, a majority decision method is provided at the subsequent stage of the four path memories in the PMU 23.

[Viterbi decoding method other than 4-value 4-state Viterbi decoding method] In the 4-value 4-state Viterbi decoding method described above, the waveform equalization characteristic used in the waveform equalizer 11 is PR.
(1, 2, 1) and RLL is used as recording data.
Used when the (1,7) code is adopted. For example, a recording linear density of 0.40 μm, a laser wavelength of 685 nm,
When NA = 0.55, the waveform equalization characteristic is set to PR (1,
2, 1), it is optimal to use a 4-value 4-state Viterbi decoding method. On the other hand, other types of Viterbi decoding methods may be used depending on the waveform equalization characteristics or the encoding method for generating the recording data.

For example, when the waveform equalization characteristic is PR (1, 1) and an RLL (1, 7) code is used as recording data, a ternary 4-state Viterbi decoding method is used. Further, the waveform equalization characteristic is PR (1, 3, 3, 1)
In the case where the RLL (1, 7) code is used as the recording data, a 7-value 6-state Viterbi decoding method is used. Among such Viterbi decoding methods, a waveform equalization characteristic that is one of the elements for selecting which method to use is preferably one that has a high degree of compatibility with intersymbol interference on a reproduced signal. Therefore, as described above, it is optimized in consideration of the linear recording density and the MTF.

On the other hand, in the above-mentioned Viterbi decoding method,
2 consecutive samples sampled during 2 read clocks
State transition diagram that handles state reproduction signal values in parallel and expresses state transitions that occur between two read clocks (see FIG. 18 described later).
), The decoded data value becomes 2
A conventional parallel processing Viterbi decoder is configured so as to output each of them. For this reason, as compared with the above-mentioned general Viterbi decoder, the configuration of the BMC, ACS, PMU and the like is different as described later, but it is the same that the state transition itself is not recognized.

On the other hand, a method of generating state data representing the state transition itself by using a state data value representing the state itself instead of the decoded data value is also possible. For example, in a four-value four-state Viterbi decoding method, four states can be represented by two bits, and such two-bit data can be used as state data. Therefore, S0, S1, S2, and S3 in FIG. 7 are represented by 2-bit state data values, 00, 01, 11, and 1, respectively.
It can be expressed using 0. Therefore, in the following description, S0, S1, S2, and S3 in FIG. 7 are represented as S00, S01, S11, and S10, respectively, and the state transition diagram of the four-value four-state Viterbi decoding method is shown in FIG. FIG. 14 is used instead.

In the following description, it is assumed that the normalized waveform, ie, PR (1,2,1), is used as the waveform equalization characteristic instead of the above-mentioned PR (B, 2A, B). For this reason, the amplitude reference value, that is, the reproduced signal value c [k] obtained by the calculation without considering the noise is −− in FIG.
0, 1, instead of AB, -A, A, A + B
Expressed as 3 and 4.

[Outline of Parallel Processing] Prior to the description of an embodiment of the present invention, a Viterbi decoding method of parallel processing will be described by taking a 4-value 4-state Viterbi decoding method by parallel processing as an example.

First, the description method of the branch metric will be described. In the trellis diagram shown in FIG.
A four-level, four-state Viterbi decoding method that occurs during one read clock (that is, occurs between time k-1 and time k). A code indicating a branch metric associated with each state transition on each arrow indicating a state transition. Is attached. Such a notation method is as follows.

First, the state before the transition and the state after the transition are written and arranged to form a sequence of four numbers. Next, each branch metric occurring during one read clock is described as a sequence of three numbers by setting the two numbers (ie, the second and third numbers) near the center to one number. . In this way, for example, the branch metric associated with the state transition from S11 to S10 is described as bm110.

Further, in the parallel processing, a value of a branch metric associated with a state transition occurring between two read clocks is calculated. A method of expressing such a branch metric will be described. As shown in FIG.
A state transition occurring during a read clock is a combination of two state transitions occurring during one read clock. FIG.
States that the transitions that can occur between two read clocks are 1
It can be seen that there are 0 types. The branch metrics associated with these ten types of state transitions can be represented as follows based on the representation of the branch metrics associated with the state transition occurring during one read clock.

That is, a sequence of three numbers indicating the branch metrics associated with the state transition in the first half (ie, from time k-2 to time k−1) as described above, and the second half (ie, from time k−1 to time k−1) A sequence of three numbers that describes the branch metric associated with the state transition (at the time point k) is written and arranged as described above to form a sequence of six numbers.
Then, by omitting the two numbers (ie, the third and fourth numbers) closer to the center, each branch metric accompanying a state transition occurring between two clocks is described as a sequence of four numbers. Thus, for example, time k
S01 → S11 → S1 generated from −2 to time point k
The branch metric accompanying the state transition of 0 is bm11
It can be seen that it is written as 10. By such a notation method, branch metrics associated with ten types of state transitions that can occur between two read clocks are indicated as shown in FIG.

FIG. 18 is a state transition diagram showing a state transition occurring between two read clocks. FIG. 18 shows the ten state transitions described above. The sign attached to the arrow indicating each state transition has the following meaning. However, as described above, the value c of the reproduced signal in this code
[K] and the like are calculated values without considering noise.

[Decoded value 'a [k-1]' at time k-1 + decoded value 'a [k]' at time k / reproduced signal value c [k-1] at time k-1 + time k The values of the reproduced signal c [k]] are represented by 10 branch metrics as shown in FIG.
As shown in FIG. 6, since this is a combination of two state transitions occurring during one read clock, the following calculation is performed.

Bm0000 = (z [k-1] -0) ² + (z [k] -0) ² (50) bm0001 = (z [k-1] -0) ² + (z [k] -1 ) ² (51) bm0011 = (z [k-1] -1) ² + (z [k] -3) ² (52) bm0111 = (z [k-1] -3) ² + (z [k] ^{-4) 2 (53) bm1111 =} (z [k-1] -4) ² + (z [k] ^{-4) 2 (54) bm0110 =} (z [k-1] -3) ² + (z [ k] ^{-3) 2 (55) bm1110 =} (z [k-1] -4) ² + (z [k] ^{-3) 2 (56) bm1100 =} (z [k-1] -3) ² + ( z [k] -1) ² (57) bm1000 = (z [k-1] -1) ² + (z [k] -0) ² (58) bm1001 = (z [k-1] -1) ² + (z [k] -1) ² (59) below In the bright, is calculated according to the equations above, the branch metric associated with state transitions that can occur between the two read clock, simply referred to as branch metric. Based on such a branch metric, the value of the path metric is updated every two read clocks according to the following equation.

M00 [k] = min ｛m00 [k-2] + bm0000, m11 [k-2] + bm1100, m10 [k-2] + bm1000｝ (60) m01 [k] = min ｛m10 [k -2] + bm1001, m00 [k-2] + bm0001｝ (61) m11 [k] = min ｛m11 [k-2] + bm1111, m00 [k-2] + bm0011, m01 [k-2] + bm0111｝ (62) m10 [k] = min ｛m01 [k−2] + bm0110, m11 [k−2] + bm1100６３ (63) Equation (60) will be described. As shown in FIG. 16 and FIG. 17, the time k-
2 to the time point k from the time point k-1 to the time point k.
The state transition leading to 00 is S00 → S00 → S00,
S11 → S10 → S00 and S10 → S00 → S0
There are three of zero. The branch metrics associated with these three state transitions are bm0000 and bm, respectively.
1000, bm1100. On the other hand, the path metrics respectively corresponding to the starting points of these three state transitions are:
m00 [k-2], m11 [k-2] and m1
0 [k-2].

Therefore, in equation (60), of the three calculated values obtained by adding the branch metric and the path metric corresponding to each of the three state transitions, the smallest value is obtained. The value that is the value (that is, the one with the highest likelihood) is set as the latest path metric. The same applies to other expressions. However, equation (61),
(62) and (63) are equations for calculating the path metric when S01, S11 and S10 are reached at the time point k, respectively.

In the actual BMC and ACS, a normalized path metric and a branch metric for calculating the value of the normalized path metric are used to simplify the calculation. Also, a configuration is provided for compressing the calculated value in order to prevent the calculated value from overflowing. However, in the following description, in order to avoid complicating the description, the standardized path metric and the branch metric for calculating the value of the standardized path metric are all described as a path metric and a branch metric.

According to the present invention, the following operation is performed by generating state data representing the state transition itself, instead of the decoded data, in response to the state transition selected by the parallel calculation processing as described above. Is made possible. First, decoded data is generated based on the state data. Further, a phase error is detected based on the state data.

FIG. 19 is a block diagram showing an overall configuration of an embodiment of the present invention. In one embodiment of the present invention, the present invention is applied to a magneto-optical disk drive. The same components as those of the example of the magneto-optical disk device described above with reference to FIG. 1 are denoted by the same reference numerals. The recording system and the servo system (not shown) are the same as those of the above-described magneto-optical disk device.

The structure and operation of the reproducing system will be described. The optical pickup 7, the amplifiers 8 and 9, the changeover switch 10, and the waveform equalizer 11 are the same as in the example of the magneto-optical disk device described above with reference to FIG.

A / D converter 12 at the subsequent stage of waveform equalizer 11
, The read clock DCK is supplied from the VCO 140 as described later. The A / D converter 12 performs sampling from the waveform-equalized reproduction signal supplied from the waveform equalizer 11 according to the read clock DCK. Then, the sampled value is supplied to the subsequent Viterbi decoder 130 as a reproduction signal value.

The Viterbi decoder 130 generates decoded data based on the supplied reproduced signal value, as described later,
Supply to the controller 2. As in the example of the magneto-optical disk device described above with reference to FIG. 1, the controller 2 performs a decoding process based on the supplied decoded data, and reproduces user data, address data, and the like.

The Viterbi decoder 130 includes a parallelization switch 131 for parallelizing the reproduction signal value, a BMC 132, and an ACS1.
33, a status memory unit (hereinafter, referred to as SMU) 134 and a merge block 135. As described later, a half clock, that is, a clock having half the frequency of the read clock DCK is supplied from the VCO 140 to each of these components, and the operation timing is adjusted. As described above, the parallelization switch 131 supplies A in accordance with the read clock DCK.
The reproduction signal value sampled by the / D converter 12 is supplied. The parallelization switch 131 alternately supplies such a reproduced signal value to two input positions of the BMC 132 at the subsequent stage. Thus, the read clock DCK
, Two consecutive reproduced signal values z [k−1] and z [k] are input to the BMC 132 in parallel.

The two reproduced signal values z [k
-1] and z [k] are supplied to a shift register 136 in order to detect a phase error in a Viterbi determination mode as described later.

Based on z [k-1] and z [k] input in parallel as described above, the BMC 132 calculates ten branch metrics bm0000 to bm1001 according to the above equations (50) to (59). Is calculated. Then, the calculated values of the ten branch metrics are calculated using ACS.
133. The ACS 133 calculates the maximum likelihood based on the supplied values of the ten branch metrics and the value of the path metric one half clock before, which is latched by the predetermined means, according to the above equations (60) to (63). Select the appropriate state transition. And two reproduced signal values z
Each time [k-1] and z [k] are supplied, the value of the path metric is updated, and the selection signals SEL00, SE
L01, SEL10, and SEL11 are generated, and SMU13 is generated.
4

The SMU 134 receives the supplied selection signal SE.
Based on L00 to SEL11, as described later,
State data representing the selected state transition itself is generated and supplied to the merge block 135. The merge block 135 generates decoded data based on the supplied state data as described later.

On the other hand, a configuration for performing the Viterbi determination mode will be described. The Viterbi determination mode is a method of obtaining the timing of the phase error detection by obtaining the rising or falling timing of the reproduction RF signal from the output of the SMU 134, as described later. As described above, the two reproduced signal values z [k−1] and z [k] supplied from the parallelization switch 131
36. The shift register 136 delays the supplied z [k−1] and z [k], and supplies the delayed z [k−1] and z [k] to a phase error detection unit (hereinafter referred to as PEC) 137.
The delay time is determined with reference to the delay time required until the output of the SMU 134.

The PEC 137 is supplied with status data which is the output of the SMU 134. As described below,
The PEC 137 performs phase error detection based on the delayed reproduction signal values z [k−1] and z [k] supplied from the shift register 136 with reference to the state data. Then, a phase error signal PE is generated.

The generated phase error signal PE is D / A-converted by the D / A converter 138 and then supplied to the VCO 140 through the loop filter 139. VC
O140 oscillates based on the phase error signal supplied in this manner, and generates a read clock DCK and a half clock.

Hereinafter, the SMU 134 will be described in more detail. The above-mentioned selection signals SEL00 to SEL11 are signals for transmitting the result of the selection performed according to the equations (60) to (63) to the SMU 134 at the subsequent stage. In equations (61) and (63), the state transitions leading to states S01 and S10 are selected from two candidates, so that SEL01 and SEL10 are 1-bit signals. Also, in equations (60) and (62), the state transitions leading to states S01 and S11 are selected from three candidates, so that SEL00 and SEL11 are 2-bit signals.

As shown in FIG. 20, the SMU 134
A-type sub-blocks 150 and 153 and two B-type sub-blocks 151 and 152.
In addition, signal lines for passing select data SEL00 to SEL11, half clocks and status data to and from other sub-blocks are connected. The A-type sub-blocks 150 and 153 have states S00 and S1, respectively.
Corresponds to 1. Also, the B-type sub-blocks 151 and 152
Correspond to states S10 and S01, respectively. These four
The connection between the sub-blocks is based on the state transition diagram of FIG.

Referring to FIG. 21, A-type sub-block 150 corresponding to state S00 will be described in more detail.
The A-type sub-block 150 has n processing stages. That is, n selectors 201 ₀ , 201 ₁ ... 20
1 _n and n registers 202 ₀ , 202 ₁ ... 20
2 _n are connected alternately. Each selector 201 _{0 0}
The select signal SEL00 is supplied to 201 _n .
Further, as described above, the state data inherited from the A-type sub-block 153 corresponding to S11 is stored in the second and subsequent selectors 201 _{1 to} 201 _n in SMin0.

[0],
SMin0 [1]... Are supplied as SMin0 [n-1]. Also, the B-type sub-block 1 corresponding to S10
The state data inherited from 51 is SMin1

[0], SM
supplied as in1 [1]... SMin1 [n-1]. Further, a half clock is supplied to each of the registers 202 _{0 to} 202 _n .

Next, the operation of each selector will be described. As shown in FIG. 18, 1 c can transition to S00 - Fukurokku previous state S00, S10 and so three of the S11, the selector 201 ₀ of the first stage, 00, 10,
11 is input. The selector 201 ₀ is connected to the SEL
According 00, supplies one of the such three status data values to the subsequent register 202 _0.

Further, each of the selectors 201 ₁ to 201 ₁ to
201 _n receives three pieces of data, that is, two state data values supplied as a parallel load, and one state data value supplied from a preceding register as a serial shift. Then, from the three state data, the state data value determined to be the maximum likelihood is supplied to the subsequent register according to the selection signal SEL00. All the selectors 201 _{0 to} 201 _n have the same selection signal SEL00.
, The state data as the maximum likelihood state data value sequence selected by the ACS 133 is inherited.

Further, each of the registers 202 ₀ -202
_n updates the held state data value by taking in the supplied state data value according to the half clock as described above. As described above, the output of each register is supplied to a sub-block corresponding to a state that can transition after one half clock. That is, since the transition can be made to S00 itself, it is supplied to the subsequent selector as a serial shift. Further, as parallel loading, S01
, And the A-type sub-block 153 corresponding to S11.

Referring to FIG. 22, the B-type sub-block 151 will be described in more detail. The B-type sub-block 151 has n processing stages. Ie, n number of selectors 211 _0, 211 _1, and · · · 211 _n, n number of registers 212 _0, 212 _1, and a · · · 212 _n are alternately arranged. Since the B-type sub-block corresponds to a state in which it does not inherit itself in FIG. 18, no serial shift is performed. Therefore, each register 212 ₀
212 _n from the no output to the register 212 ₀ -212 _n. Each selector 201 _{0 to} 201 _n has:
The select signal SEL10 is supplied.

Furthermore, each selector 211 _{1 in the} second and subsequent stages
The ~211 _n, as described above, B corresponding to S01
The state data inherited from the type sub-block 152 is SMi.
n0

[0], SMin0 [1] ... SMin0 [n-
1]. The state data inherited from the B-type sub-block 153 corresponding to S11 is SMin1.

[0], SMin1 [1] ... SMin1 [n-1]
Supplied as Further, each of the registers 212 _{0 to} 21 ₀
2 _n is supplied with a half clock.

Next, the operation of each selector will be described. As shown in FIG. 18, 1 c can transition to S10 - Fukurokku previous state S01, since S11 2 pieces of the, to the selector 201 ₀ of the first stage, 01,11 is entered.
The selector 211 _0, according to SEL10, supplies one of the such two status data values to the subsequent register 212 _0.

Further, each of the selectors 201 ₁ to 201 ₁ to
201 _n receives two state data supplied as a parallel load as described above. Then, from these two state data, according to the selection signal SEL10,
The state data determined to be the maximum likelihood is supplied to a register at the subsequent stage. Since the selectors 211 _{0 to} 211 _n all follow the same selection signal SEL00, the state data as the maximum likelihood state data value series selected by the ACS 133 is inherited.

Further, each of the registers 212 _{0 to} 212
_n updates the held state data by taking in the state data value supplied in accordance with the half clock as described above. As described above, the output of each register is supplied to a sub-block corresponding to a state that can transition after one half clock. That is, A-type sub-block 150 corresponding to S00 and B-type sub-block 150 corresponding to S01.
It is supplied as a parallel load for the mold sub-block 152.

When the number n of registers in the four sub-blocks in the SMU 134 is sufficiently large, the values of the registers in the n-th register in the four sub-blocks all match. In such a case, decoded data may be generated based on state data generated by any of the four sub-blocks. On the other hand, as n increases, the delay time caused by performing the Viterbi decoding method increases. Therefore, the number of stages n of the register needs to be appropriately set according to the C / N and frequency characteristics of the reproduced signal input to the Viterbi decoder 130.

As described above, 1 is set by the SMU 134.
Generation of decoded data based on the state data generated for each half clock is performed by the merge block 135. One half clock corresponds to two read clocks DCK. For this reason, the merge block 135 associates the supplied state data with the decoded data of every two bits described in the state transition diagram of FIG.

As an example of such a correspondence, the state data value at the time point k + n-1 displayed by the half clock is sm [k + n-1] = 00, and the state data value at the next time point k + n is sm [k + n] = Consider the case of 11. Here, n indicates a delay time until the output of the SMU 134 is obtained. From FIG. 18, the decoded data values in such a case are “1” and “0” in the order of time. FIG. 23 shows the correspondence between the state data value and the decoded data value according to the state transition diagram of FIG. 18 in this manner. FIG.
, The decoded data that is older in time is shown as vd0, and the newer data is shown as vd1.

On the other hand, the phase error detection in the Viterbi determination mode will be described in more detail. Based on the state data, the rising and falling timings of the reproduced RF signal can be obtained as follows. Therefore, with the above-described configuration, phase error detection based on such timing can be performed.

The state transition for each read clock DCK occurs according to the state transition diagram shown in FIG. In FIG. 14, if a transition from the state S00 to the state S11 occurs at the time point j, the state S
It turns out that it changes to 11. The value of the reproduced signal associated with such a transition is expressed as z [j] = within an error range due to noise.
1, z [j + 1] = 3. Therefore, based on the state data, such a time point j can be recognized as a rising time point of the reproduced RF signal. This is illustrated in FIG.
This will be specifically described with reference to FIG.

FIG. 24 shows an example of the reproduced RF signal supplied to the A / D converter 12, in which sampling points according to the read clock DCK are indicated by black circles. The state selected at each time point is shown below the reproduced RF signal. FIG. 24A shows a case where there is no phase error. FIG. 24B shows a case where the phase of the read clock DCK is advanced, and FIG. 24C shows a case where the phase of the read clock DCK is delayed. Also, broken lines are added every other read clock (that is, at intervals of two read clocks) to make it easier to see the phase error.

In FIGS. 24A to 24C, P is a sampling value which is a reproduction signal value at the time of rising as described above. That is, since the reproduction signal value P after one read clock of S00 is 1 within the range of the error due to noise, the state S
A transition to 01 has occurred. And such a state S01
Since the sampling value Q, which is the reproduced signal value after one read clock after the above, is 3 within the range of the error due to noise, the state S
A transition to 11 has occurred. Therefore, it can be confirmed that the reproduced RF signal rises during the period when P and Q are sampled.

On the other hand, in FIG.
When a transition from the state S11 to the state S10 occurs at a certain time point j displayed by CK, the next time point j +
It can be seen that the state always transitions to the state S00 at 1. In this case, the value of the reproduced signal is z [j] = 3 and z [j + 1] = 1 within the range of an error due to noise. Therefore, based on the state data, such a time point j can be recognized as a falling time point of the reproduction RF signal. This will be specifically described with reference to FIG.

In FIGS. 24A to 24C, R is a sampling value which is a reproduction signal value at the time of falling as described above. That is, since the reproduced signal value R after one read clock in S11 is 3 within the range of the error due to noise, the state S
A transition to 10 has occurred. And such a state S10
Since the sampling value Q, which is the reproduction signal value after one read clock after the above, is 1 within the range of the error due to noise, the state S
A transition to 00 has occurred. Therefore, it can be confirmed that the reproduction RF signal falls during the period in which R and S are sampled. P, Q, R, S
The relationship between and the state transition is as follows.

P: rising point (state S01 → S1)
1) Reproduction signal value Q: One read clock after the rising point (state S11
→ Reproduced signal value at S10) R: Reproduced signal value at fall time (state S11 → S10) S: One read clock after the fall time (state S10)
As shown in FIG. 24A, when the phase of the read clock DCK exactly matches the phase of the reproduced signal, as shown in FIG. 24A, from FIG. 14, both P and S fall within the range of error due to noise. And is equal to the value 1 of the identification point. Further, both the value of Q and the value of R are shown in FIG.
Therefore, it is equal to the value 3 of the discrimination point within the range of error due to noise. Therefore, P = S and Q = R.

On the other hand, as shown in FIG. 24B, when the phase of the read clock DCK is ahead of the phase of the reproduction signal, the sampling timing is earlier than in the case of FIG. 24A. Therefore, for P and Q, FIG.
A value smaller than the case of 4A is sampled, and for R and S, a larger value than the case of FIG. 24A is sampled. Accordingly, since P <S and Q <R, PS <0 and QR <0.

On the other hand, as shown in FIG. 24C, when the phase of the read clock DCK is behind the phase of the reproduction signal, the sampling timing is later than in the case of FIG. 24A. Therefore, for P and Q, FIG.
A larger value is sampled than in the case of 4A, and for R and S, smaller values are sampled than in the case of FIG. 24A. Accordingly, since P> S and Q> R, PS> 0 and QR> 0.

Therefore, the value of [(PS) + (QR)] can be used as the phase error. That is, the value of the above-described phase error signal PE is as follows.

PE = (PS) + (Q−R) (64) When the phase of the read clock DCK is ahead of the phase of the reproduction signal, PE <0. When the phase of the read clock DCK is behind the phase of the reproduction signal, PE> 0. As mentioned above, such a PE
Is supplied to the VCO 140 as a phase error signal,
Used for CO140 oscillation.

The P which generates such a phase error signal PE
The EC 137 will be described. As shown in FIG.
The EC 137 includes four registers 301, 302, 30
3 and 304, and reproduction signal value changeover switches 311 to 314 and registers 301 to 3 provided at the preceding stage, respectively.
An arithmetic unit 305 that performs subtraction and addition based on the value supplied from the CPU 04, and a unit (not shown) that generates a signal that controls capture by the registers 301 to 304 based on the output of the SMU 134. PEC137
Is supplied with the output of the above-described shift register 136, that is, two delayed parallel reproduced signal values.

In the following description, of the two reproduced signal values, the old one is z0 and the new one is z1. Each register is supplied with a register selected from z0 and z1 as described later. Furthermore, each register 3
01, 302, 303, and 304 have P, Q,
Signals G _P, G _Q,
G _{R and} G _S are supplied. A selection from among such z0, z1, signal _{G P, G Q, G R} , by the command of the G _S, the respective registers 301, 302, 303, 304, P respectively, Q, R, S Is properly latched.

[0174] and selected from such z0, z1, signal G _P, G _Q, the command G _R, G _S, based on the output of SMU134 supplied to PEC137 as described above, the following Is generated as follows. First, in all possible cases (ie, all the transitions shown in the state transition diagram of FIG. 18) as a combination of the output of the SMU 134 supplied to the PEC 13 at a certain time and the output one half clock before it, The state transition for each read clock is specified according to the state transition diagram of FIG. Then, among the state transitions for each one read clock, a timing corresponding to the phase error detection timing, that is, the timing for taking in the values of P, Q, R, and S may be found. At this time, the phase error detection timing can be obtained at a rate of at most two with respect to one output value of the SMU 134.

For example, it can be seen from FIG. 18 that sm [k] = 11 and sm [k-1] = 00 may occur as the state data values at the time points k and k−1 displayed by the half clock. At this time, from the state transition diagram of FIG. 14, the state transition for each read clock is S00 → S01.
→ S11 is understood. According to the above-described method of determining P, Q, R, and S, such a transition is performed in the first half (S00 → S
01) corresponds to the rising point (that is, the timing to take in the value of P), and the latter half (S01 → S11) corresponds to the point one read clock after the rising point P (that is, the timing to take in the value of Q). I understand. Therefore, at this time, the value of z0 may be supplied to the register 301 as the value of P, and the value of z1 may be supplied to the register 302 as the value of Q.

In this way, as shown in FIG.
It can be seen that a maximum of two phase error detection timings can be obtained for the combination of m [k + n] and the output sm [k + n-1] of the SMU one half clock before it. Here, n indicates a delay time until the output of the SMU 134 is generated.

Therefore, in the configuration shown in FIG. 26, for example, sm [k + n] = 11 and sm [k + n−1] =
00, z0 is stored in the register 3 as described above.
01, and z1 into the register 302, the following operation is performed. That is, G _P,
G _Q are as for example 'High' is intended to direct the uptake and in accordance with the command reproduced signal value selector switch 311 selects the z0 according to instructions T _P, the switch 312 switch further reproduced signal value is T _Q Select z1. At this time, G _{R and} G _S are set to, for example, 'low', and commands are issued so that the registers 303 and 304 do not take in.

Signals G _{P to} G for instructing such fetching
Signal T _P through T _S for commanding _S and switching, as described above, provided in the PEC137, the constructed, not shown, such as an AND circuit means to operate in accordance with FIG. 25, the output of SMU134 Generated based on In this manner, the values of P, Q, R, and R are stored in the registers 30 corresponding to the respective phase error detection timings.
1 to 304 can be taken in correctly. Then, the values of the registers 301 to 304 are updated each time the fetch is performed.

The arithmetic unit 305 for performing subtraction and addition based on the values of P, Q, R, and S is provided by the above equation (6).
The value of the phase error signal PE is calculated according to 4). As described above, the D / A converter 138 and the loop filter 1
39, the phase error signal PE is supplied to the VCO 140 and used for the oscillation of the VCO 140.
LL is locked. The arithmetic unit 305 also outputs the reproduction RF
During the period when a signal is obtained, the value of PE is always calculated.

By the way, a configuration for adapting the amplitude reference value based on the state data generated by applying the present invention may be added. In such a case, more accurate state data can be obtained by using an amplitude reference value adapted to the quality of the reproduced RF signal in the BMC 132.

In the embodiment of the present invention described above, the present invention is applied to a magneto-optical disk drive that performs a 4-value 4-state Viterbi decoding method. On the other hand, 3
The present invention can be applied to a magneto-optical disk device that performs another type of Viterbi decoding method such as a 4-value Viterbi decoding method and a 7-value 6-state Viterbi decoding method. Further, the present invention can be applied to an information reproducing apparatus that can use a Viterbi decoding method to decode read data from a reproduction signal reproduced from data recorded on a recording medium. That is, in addition to the magneto-optical disk (MO), for example, a phase-change disk PD, a CD-E (CD-Erasa
ble), a write-once disk such as a CD-R, and a read-only disk such as a CD-ROM. Further, the present invention is not limited to this embodiment, and various applications and modifications can be considered without departing from the gist of the present invention.

[0182]

As described above, according to the present invention, in the Viterbi decoding method, the calculation based on the reproduced signal value is performed by parallel processing, and the surviving state selected based on the result of the parallel processing, that is, the maximum likelihood state transition By generating state data representing the following, the following processing can be performed.

First, decoded data can be generated every two bits based on state data representing such a surviving state.

Further, a phase error detection timing can be obtained based on state data representing such a surviving state. A phase error signal is generated in accordance with the phase error detection timing, and a PLL is generated based on the phase error signal.
Can be locked, so that an appropriate read clock and half clock can be generated.

Further, the amplitude reference value may be adapted based on state data generated by applying the present invention. In such a case, since the amplitude reference value adapted to the quality of the reproduction RF signal is used in the BMC, accurate state data can be obtained even when the quality of the reproduction RF signal is not constant due to factors such as amplitude fluctuations of the reproduction RF signal. Can be obtained. Therefore, it is possible to more accurately generate the decoded data and the phase error detection timing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an example of a magneto-optical disk device that performs a 4-value 4-state Viterbi decoding method.

FIG. 2 is a schematic diagram for explaining a mark position recording method and a mark edge recording method.

FIG. 3 is a schematic diagram for explaining an example of a sector format of a magneto-optical disk.

FIG. 4 is a schematic diagram showing that the minimum magnetization reversal width is 2 in the RLL (1, 7) encoding method.

FIG. 5 shows a reproduction signal reproduced from data recorded by a combination of an RLL (1, 7) code and a mark edge recording method, with a partial response characteristic PR (1, 2, 2).
FIG. 6 is a schematic diagram for explaining an eye pattern when waveform equalization is performed under 1).

FIG. 6 is a schematic diagram for explaining a process of creating a state transition diagram of the 4-value 4-state Viterbi decoding method.

FIG. 7 is a schematic diagram illustrating an example of a state transition diagram of a 4-value 4-state Viterbi decoding method.

FIG. 8 is a schematic diagram illustrating an example of a trellis diagram in a 4-level 4-state Viterbi decoding method.

FIG. 9 is a schematic diagram showing conditions of state transition based on a standardized metric in a four-value four-state Viterbi decoding method.

FIG. 10 is a block diagram illustrating an overall configuration of a Viterbi decoder that performs 4-level 4-state Viterbi decoding.

11 is a block diagram showing in detail a configuration of a part of the Viterbi decoder shown in FIG.

FIG. 12 is a block diagram showing the configuration of another part of the Viterbi decoder shown in FIG. 10 in detail.

FIG. 13 is a block diagram showing the configuration of yet another portion of the Viterbi decoder shown in FIG. 10 in detail.

FIG. 14 is a schematic diagram illustrating an example of a state transition diagram of a four-value four-state Viterbi decoding method using a notation different from that in FIG. 7;

FIG. 15 is a schematic diagram for explaining a method of expressing a branch metric that may occur during one read clock.

FIG. 16 is a schematic diagram for explaining a branch metric that can occur during two read clocks as a combination of branch metrics that can occur during one read clock.

FIG. 17 is a schematic diagram for describing notation of a branch metric that may occur between two read clocks.

FIG. 18 is a schematic diagram illustrating an example of a state transition diagram expressing a state transition for every two read clocks.

FIG. 19 is a block diagram showing the overall configuration of one embodiment of the present invention.

FIG. 20 is a block diagram for describing in detail a configuration of a status memory unit in one embodiment of the present invention.

21 is a status memory unit 1 shown in FIG.
34 is a block diagram for describing in detail a part of the configuration in FIG. 34. FIG.

FIG. 22 shows the status memory unit 1 shown in FIG.
34 is a block diagram for describing in detail another part of the configuration in FIG. 34. FIG.

FIG. 23 is a schematic diagram for explaining a correspondence between a state data value and a decoded data value.

FIG. 24 is a schematic diagram for describing sampling for detecting a phase error.

FIG. 25 is a schematic diagram for explaining a correspondence between a state data value and a sampling timing for detecting a phase error.

FIG. 26 is a diagram illustrating a phase error detector 13 according to an embodiment of the present invention;
7 is a block diagram for explaining the configuration of FIG. 7 in detail.

[Explanation of symbols]

2 ... Controller, 3 ... Encoder, 4 ...
Laser power control unit (LPC), 5: magnetic head, 6: magneto-optical disk, 7: optical pickup, 10: changeover switch, 11: waveform equalizer, 12: A / D converter, 13 Viterbi decoder, 14 PLL unit, 20 branch metric calculation circuit (BMC), 21 addition, comparison and selection circuit (ACS), 22. .Compression and latch circuits,
23: Path memory unit (PMU), 24:
A type path memory, 25 ... B type path memory, 26 ...
A type path memory, 27 ... B type path memory, 51
..Adders, 52 ... Adders, 53 ... Adders, 5
4 ... adder, 55 ... comparator, 56 ... adder, 57 ... comparator, 58 ... adder, 30 _0-3
0 _14: flip-flop, 31 _{1 to} 31 _14: selector, 32 _{0 to} 32 _14: flip-flop, 13
DESCRIPTION OF SYMBOLS 1 ... Parallelization switch, 132 ... Branch metric calculation circuit (BMC), 133 ... Addition, comparison and selection circuit (ACS), 134 ... Status memory unit, 135 ... Ma Diblock, 136 ...
Shift register, 137... Phase error detector, 140
... VCO, 150 ... A type sub-block, 151
... B-type sub-block, 152 ... A-type sub-block, 153 ... B-type sub-block, 201 _{0 to} 201
_n-1 ... selector, 202 _{0 to} 202 _n-1 ... register, 211 _{0 to} 211 _n-1 ... selector, 212 ₀
... 212 _n-1 ... register, 301-304 ... register, 305 ... arithmetic unit, 311-314 ... reproduction signal value switch

Claims (5)

[Claims] An information reproducing apparatus for reproducing an information signal recorded on a recording medium, wherein the information reproducing apparatus uses a Viterbi decoding method as decoding means for decoding a reproduction signal reproduced from the recording medium. A clock, a means for generating a half clock having a frequency half that of the clock, and a unit of two consecutive reproduced signal values based on a reproduced signal value sampled according to the clock. State data generating means for performing parallel processing under a timing according to the half clock to generate state data for each half clock representing the maximum likelihood state transition itself; and decoding data based on the state data. An information reproducing apparatus, comprising: a Viterbi decoder comprising: decoded data output means for outputting a decoded data. 2. The parallel data processing device according to claim 1, wherein the state data generating means performs parallel calculation processing in units of the two consecutive reproduction signal values, and outputs the output result of the parallel calculation processing means. Based on the above
An information reproducing apparatus comprising: selecting means for selecting a maximum likelihood state transition for each clock; and state data generating means for generating state data expressing the maximum likelihood state transition itself selected by the selecting means. apparatus. 3. The method according to claim 1, wherein a phase error signal indicating a phase error of a PLL is generated based on the state data generated by the state data generating means.
An information reproducing apparatus comprising a phase error detecting means. 4. The phase error detecting means according to claim 3, wherein said phase error detecting means generates a phase error detecting timing for detecting a phase error of a PLL based on said state data; Latch means for latching a signal value used for detecting a phase error; and compensating the two consecutive reproduced signal values for a delay time required for output of the state data generating means. And a means for calculating a value representing a phase error based on the value latched by the latch means. 5. An information reproducing method for reproducing an information signal recorded on a recording medium, wherein the information reproducing method uses a Viterbi decoding method as a decoding means for decoding a reproduction signal reproduced from the recording medium. And a step of generating a clock and a half clock having a frequency that is half the frequency of the clock. Based on a reproduced signal value sampled in accordance with the clock, two consecutive reproduced signal values are used as processing units. Performing parallel processing under the timing according to the half clock to generate state data for each half clock representing the maximum likelihood state transition itself; and outputting decoded data based on the state data. Performing an Viterbi decoding method comprising the steps of: