JP2006040458A - Phase error detection circuit, phase-locked loop circuit, and information reproducing device employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase error detection circuit which stabilizes a phase lock characteristic without being affected by DC level variations of an input signal in a clock reproducing PLL circuit. <P>SOLUTION: A regenerative signal which is read from an optical disk medium 1 by an optical pickup circuit 2 and equalized by a pre-equalizer circuit 20, is digitized by an A/D converter 3, equalized to a predetermined PR signal by a PR equalizer circuit 4 after a DC component is removed therefrom by a DC feedback circuit 6, and decoded by a most-likelihood decoder circuit 5. A phase error detection circuit 7 receives an output signal of the DC feedback circuit 6 and outputs a phase error detecting signal and a DC error detecting signal. The phase error detecting signal is inputted to a VCO 10 via a loop filter 8 and a D/A converter 9, and a phase of a clock which is that output signal, is synchronized to the regenerative signal. Meanwhile the DC error detecting signal is inputted to the DC feedback circuit 6 and a DC component is removed from an output signal of the DC feedback circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information reproduction system using a Partial Response Maximum Likelihood (hereinafter abbreviated as “PRML”) method, and more particularly to a phase error detection circuit for generating a synchronization signal, and the phase error detection thereof. The present invention relates to a phase locked loop (hereinafter abbreviated as “PLL”) circuit using a circuit, and an information reproducing apparatus using the PLL circuit.

  Conventionally, for example, in an information reproducing apparatus represented by a hard disk device or an optical disk device, for example, as known from the following Patent Document 1, when reading digitized recorded information on the recording medium, it is detected as an analog signal. The detected signal is input by a predetermined clock and is read out by A / D conversion. A phase error of the read signal is detected according to an FDTS (Fixed Delay Tree Search) algorithm, and a VCO (Voltage) is detected based on the phase error signal. By controlling the oscillation frequency of the Controlled Oscillator, the clock phase is synchronized with the data.

Japanese Patent Laid-Open No. 2002-25201 (page 5, FIG. 2)

  However, in the above-described prior art apparatus, the phase error detector that controls the oscillation of the VCO detects the sampling error of the sampled signal and the phase error of the correct sampling timing that is originally expected. However, no consideration was given to fluctuations in the center level of the readout signal, in other words, the direct current (DC) level. That is, only the ideal PR characteristic (DC level is zero) has been considered in the above-described conventional device.

  By the way, in the information reproducing apparatus described above, for example, in an optical disk apparatus, when reading digitized recording information on the recording medium, the surface of the recording medium is irradiated with light emitted from a light emitting source such as an LED, The reflected light is detected by a pickup composed of a light receiving element such as a phototransistor, and this is read out by A / D conversion. At this time, depending on the change over time of the optical disk device or the power supply level for driving it, The analog signal detected by the pickup also changes its DC level. Therefore, due to this varying DC level, signal processing including A / D conversion performed at a predetermined sampling timing (recovered clock) is influenced by the result of phase error detection, resulting in phase synchronization characteristics. As a result, the jitter of the clock increases.

  That is, in the conventional apparatus, the phase error of the sampling timing is detected and the timing for reproduction (reproduction clock) is correctly controlled. However, the fluctuation of the DC level is not considered at all. (That is, only an ideal PR characteristic (DC level is considered as zero) is taken into account). Therefore, for example, when the DC level of the input analog signal fluctuates, sampling timing (reproduction) for signal processing There was a problem that the clock) could not be controlled correctly.

  Therefore, in the present invention, in view of the problems in the prior art described in detail above, in an information reproducing apparatus that performs processing by converting a detected analog signal into an analog signal at a predetermined sampling timing (reproduced clock), sampling is simply performed. A phase error detection circuit capable of obtaining a more suitable phase synchronization characteristic by considering not only the phase error of the timing but also the fluctuation of the DC level, and the phase using the phase error detection circuit It is an object of the present invention to provide a synchronous loop circuit and to provide an information reproducing apparatus using the PLL circuit.

  In order to achieve the above object, according to the present invention, first, a circuit that receives an analog / digital converted digital signal by sampling an analog input signal with a predetermined clock and detects a phase error of the clock. A means for detecting a sampling phase error with respect to the analog input signal based on the digital input signal, and a means for detecting a variation in a DC component of the analog input signal based on the digital input signal. A phase error detection circuit is provided.

  According to the present invention, more specifically, a circuit that receives an analog / digital converted input signal at a predetermined clock and detects a phase error of the clock, the input signal and the input signal Based on the result of the sign change detecting means, the means for adding the signal delayed by one sample time, the means for detecting the sign change between the input signal and the delayed signal, The first means for outputting, the means for inverting the sign of the output signal of the first means, the output signal of the first means or the inverting means is selected according to the sign of the input signal, and output And a second means for providing a phase error detection circuit.

  Further, according to the present invention, the means for analog / digital conversion of the input signal with a predetermined clock, the means for controlling the direct current level of the output signal of the analog / digital conversion means, and the output signal of the direct current level control means Receiving means for detecting the phase error of the clock, the oscillation means for outputting the clock controlled by the output signal of the phase error detection means, and the output signal of the DC level control means for detecting the DC level The DC level control means is controlled by an output signal of the DC level detection means, and the phase error loop using the phase error detection circuit in the phase error detection means and the DC level detection means. A circuit is provided.

  In addition, according to the present invention, means for reading digital information recorded on the recording medium, means for analog / digital conversion of the output signal of the read means with a predetermined clock, and output signal of the analog / digital conversion means Means for controlling the direct current level, means for equalizing the output signal of the direct current level control means, means for maximum likelihood decoding the output signal of the equalization means, and the direct current level control means or the equalization means Means for receiving an output signal and detecting a phase error of the clock; an oscillating means for outputting the clock controlled by the output signal of the phase error detecting means; and an output signal of the DC level control means or the equalizing means And a means for detecting the direct current level, the direct current level control means being controlled by an output signal of the direct current level detection means, the phase error detection means and the direct current level Bell detecting means, the information reproducing apparatus using the phase error detection circuit is provided.

  According to the present invention, the means for reading the digital information recorded on the recording medium, the means for analog / digital conversion of the output signal of the read means with a predetermined clock, and the output signal of the analog / digital conversion means There is provided an information reproducing apparatus including means for equalization and means for maximum likelihood decoding of an output signal of the equalization means, and the analog / digital conversion means uses the phase locked loop circuit.

  That is, the phase error detection circuit according to the present invention calculates an average value of around one sample of a digitized read signal and outputs a calculation result only at a sign change point, and a DC error signal and read out. And phase error detection means for calculating a phase error from the sign of the signal.

  Further, the PLL circuit according to the present invention is configured to control the VCO based on the phase error signal and to cancel the fluctuation of the DC level by integrating the DC error signal and subtracting it from the read signal. And

  According to the phase error detection circuit of the present invention as described above, the DC level and the phase error of the input signal can be detected independently, and the phase synchronization capable of forming independent feedback loops. A loop circuit can be provided, and further, by using this, it is possible to provide an information reproducing apparatus with stable phase synchronization characteristics regardless of DC level fluctuations.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an embodiment of an information reproducing apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an optical disk medium, 2 denotes an optical pickup circuit, 3 denotes an A / D converter, 4 denotes a PR equalization circuit, 5 denotes a maximum likelihood decoding circuit, and 6 denotes a DC feedback circuit. 7 is a phase error detection circuit, 8 is a loop filter, 9 is a D / A converter, 10 is a voltage controlled oscillator (VCO), 11 is a pre-equalization circuit, 20 is a servo circuit, 30 Respectively indicate system control circuits.

  In the information reproducing apparatus having the configuration described above, the optical pickup circuit 2 collects the laser beam on the information recorded on the optical disk medium 1 and irradiates the medium on the medium, and detects the reflected light amount or the deflection. Then play it. At this time, the servo circuit 20 accurately follows the focus direction and the track direction. The reproduction signal read out by the optical pickup circuit 2 is equalized by the pre-equalization circuit 11 and then digitized by the A / D converter 3. Then, the DC component is removed by the DC feedback circuit 6, equalized to a predetermined PR signal by the PR equalization circuit 4, and then decoded by the maximum likelihood decoding circuit 5. The system control circuit 30 controls these series of operations, which is the same as in the prior art. The A / D converter 3, the PR equalization circuit 4, and the maximum likelihood decoding circuit 5 described above each synchronize data with a phase of a reproduction clock generated by a voltage controlled oscillator (VCO) 10 shown below. To process.

  In the present invention, as is apparent from FIG. 1 described above, the phase error detection circuit 7 receives an output signal from the DC feedback circuit 6 described in detail below, and receives the phase error detection signal and the DC error detection. Signal. Further, among these output signals, the phase error detection signal is input to the VCO 10 via the loop filter 8 and the D / A converter 9, and thereby the phase of the clock that is the output signal is reproduced as a reproduction signal. Synchronize with. On the other hand, the DC error detection signal is input to the DC feedback circuit 6 and is used to remove a DC component from the output signal from the DC feedback circuit 6.

  FIG. 2 is a block diagram showing a detailed circuit configuration of an example of the DC feedback circuit 6 according to the present invention described above. In FIG. 2, reference numeral 601 indicates a subtracter, 602, 611, and 621 indicate registers, 603, 612, and 622 indicate adders, 613 and 623 indicate attenuators, and 614 indicates an amplitude limiter. Yes. As is clear from the circuit configuration in the figure, the register 611 and the adder 612 constitute an integration circuit, and the register 621 and the adder 622 constitute an integration circuit.

  That is, the feature of the DC feedback circuit 6 is that it has two feedback loops as shown in the figure. Specifically, the first loop receives the main signal from the DC feedback circuit 6, limits the amplitude of the signal by the amplitude limiter 614, and further passes through the attenuator 613, the adder 612, and the register 611. This is a loop that feeds back as a DC level. The second loop is a loop that receives a DC error signal from the phase error detection circuit 7 and feeds it back as a DC level via an attenuator 623, an adder 622, and a register 621. The outputs from the first loop and the second loop are added by the adder 603 and then input to the “−” input terminal of the subtractor 601, so that the “+” input of the subtractor 601 is input. Subtract from the input signal input to the terminal.

  The DC feedback circuit 6 whose configuration has been described above receives a DC feedback control signal from the system control circuit 30 (see FIG. 1) and is a component thereof, although not shown here. The coefficient “ND” of the attenuator 613, the coefficient “NJ” of the attenuator 623, and the amplitude limit value of the amplitude limiter 614 are set.

  Further, by controlling the operation of the integrating circuit composed of the register 611 and the adder 612 and the integrating circuit composed of the register 621 and the adder 622, the DC feedback loop can be opened and closed. For example, when the servo operation is interrupted or the servo is disconnected, or when a track jump occurs, the DC feedback circuit 6 receives the DC feedback control signal from the system control circuit 30 and opens the DC feedback loop. That is, according to this, it is possible to prevent the internal DC level from being disturbed by an abnormal signal input.

  FIG. 3 is a block diagram showing a detailed circuit configuration of an example of the phase error detection circuit 7 according to the present invention. In FIG. 3, reference numeral 720 is a register, 711 and 721 are binarization circuits, 712 is an adder, 713 is a modulo 2 adder, 714 and 716 are switch circuits, and 715 is a polarity inversion circuit. , Respectively.

That is, in the phase error detection circuit 7 according to the present invention, in the configuration described above, the register 720 delays the input signal X _n (δ, τ) by 1 bit (one clock period), and delay signal X _n−1 (δ, τ) is output. The binarization circuits 711 and 721 respectively convert the input signal X _n (δ, τ) and the delayed signal X _n−1 (δ, τ) into two polar codes “0 (+)” and “1 (−)”. valued signal _{Y n,} to convert _{Y n-1.} In the actual binarization circuits 711 and 721, when the input signal X _n (δ, τ) and the delay signal X _n−1 (δ, τ) are in 2 ′s complementary format, the most significant bit ( MSB) becomes the binarized signals Y _n and Y _{n−1 as} they are, so that the circuit configuration can be simplified.

Subsequently, the adder 712 adds the input signals X _n (δ, τ) and X _n−1 (δ, τ). On the other hand, the adder 713 of the modulo 2, and a binary signal Yn and _{Y n-1,} is added modulo 2, with it, and outputs a selection control signal _{Z n.} That is, the polarity change point of the input signal X _n (δ, τ) (sign change point of the binarized signal Y _n ) is detected, and the adder 731 of the actual modulo 2 detects the binarized signal Xn (τ ) Corresponds to the codes “0” and “1”, and is configured by an exclusive OR (Ex-OR) circuit.

The switch circuit 714 receives the selection control signal Z _n and outputs a DC error signal S _n (δ) expressed by the following equation (Equation 1).

The switch circuit 716 receives the binarized signal Y _n and outputs a phase error signal E _n (τ) represented by the following equation (Equation 2).

  In the example of FIG. 3, the process of dividing by “2” in (Expression 1) is omitted. However, when the process of dividing by “2” is omitted, the gain is only doubled. Yes, the basic operation does not change.

Subsequently, FIG. 4, FIG. 5 and FIG. 6 attached are analog input signals X _n (δ, τ) for explaining the operation of the phase error detection circuit 7 according to the present invention whose detailed circuit configuration is explained above. ) Shows the waveform. In these drawings, the black circle (●) indicates the actual sampling point, and the white circle (◯) indicates the DC error signal S _n (δ) obtained by the phase error detection circuit 7 described above. ) Detection points. As described above, for example, in the optical pickup circuit 2 that receives reflected light or transmitted light from the surface of an optical disk that is an information recording medium, a change with time of a phototransistor constituting a light receiving element, a change in a driving power source thereof, and the like. Therefore, the input signal X _n (δ, τ), which is the detection signal, is changed at the DC level.

First, FIG. 4 shows a case where DC offset δ = 0 and phase offset τ = 0. As can be seen from the figure, in this case, the DC error signal S _n (δ) becomes 0 (zero) together with the phase error signal E _n (τ).

Next, FIG. 5 shows a case where DC offset δ> 0 and phase offset τ = 0. In this case, the DC error signal S _n (δ) becomes S _n (δ) = δ, as can be seen from the figure, and the error signal proportional to the DC offset δ is output from the phase error detection circuit 7. The On the other hand, at this time, as the phase error signal E _n (τ), a signal having an amplitude corresponding to the gradient of the input signal X _n (δ, τ) and having the polarity inverted alternately, E _n (τ) = ± δ is output. Therefore, the average value is 0 (zero). In the above description, only the case of DC offset δ> 0 has been described. However, the same applies to the case of DC offset δ <0. In this case, S _n (δ) = δ <0, but the phase error The signal is again E _n (τ) = 0.

Further, FIG. 6 shows a case where DC offset δ = 0 and phase offset τ> 0. In this case, the DC error signal S _n (δ) has an amplitude corresponding to the slope of the input signal X _n (δ, τ), and a signal whose polarity is alternately inverted, S _n (δ) = ± ε is output. As described above, the average value is 0 (zero). On the other hand, the phase error signal E _n (τ) is output as E _n (τ) = ε regardless of the gradient of the input signal X _n (δ, τ). Although the case where the phase offset τ> 0 has been described above, the same applies to the case where the phase offset τ <0. In this case, S _n (δ) = 0, E _n (τ) = ε <0.

As described in detail above, according to the phase error detection circuit 7 of the present invention, the DC error is independently generated from the input signal X _n (δ, τ) in which the DC offset δ and the phase offset τ are mixed. The signal S _n (δ) and the phase error signal E _n (τ) can be detected. As a result, in the phase-locked loop circuit according to the present invention, the DC offset can be suppressed by forming an independent DC feedback loop therein, and the phase offset can also be suppressed low.

  In the above-described phase error detection circuit according to the present invention, DC and phase error are detected only from the sample values before and after the polarity change. In the phase locked loop circuit using this, the upper and lower sides (positive and negative) of the input signal are asymmetric. Even so, the DC offset and the phase offset can be kept low.

  In the above-described embodiment, the output signal of the DC feedback circuit 6 itself, that is, the input signal of the PR equalizing circuit 4 is used as the D and C feedback main signal. However, the output signal may be used. In the above embodiment, the example in which the pre-equalization circuit 20 is arranged in the preceding stage of the A / D converter 3 is shown. However, the present invention is not limited to such a configuration, and for example, the pre-equalization circuit 20 is arranged. The equalization circuit 20 may be arranged at the subsequent stage of the A / D converter 3. In the following, other embodiments adopting such a configuration will be described.

  FIG. 7 is a block diagram showing another embodiment of the information reproducing apparatus according to the present invention. The difference of this embodiment from the embodiment of FIG. 1 is that the pre-equalization circuit 20 is deleted and the main signal and the input signal of the phase error detection circuit 7 are used as the output signal of the PR equalization circuit 4 as can be seen from the figure. Therefore, the phase error detection and the DC feedback operation are the same. This eliminates the need for the analog processing circuit called the pre-equalization circuit 20 and has the effect of simplifying the circuit configuration.

  FIG. 8 is a block diagram showing still another embodiment of the information reproducing apparatus according to the present invention. In FIG. 8, reference numeral 12 denotes a switch circuit. In addition, the same reference numerals as those in FIGS. 1 and 7 denote the same components. The feature of this embodiment is that the switch circuit 12 is controlled by the system control circuit 30 so that the input signal of the phase error detection circuit 7 can be switched.

  According to still another embodiment described above, the input signal of the phase error detection circuit 7 is, for example, in the initial pull-in operation, or in the re-pull-in operation such as when the servo is disconnected or the track jumps. Is used as an input signal to the PR equalization circuit 4 to shorten the time until synchronization is established or synchronized. Thereafter, the input signal of the phase error detection circuit 7 can be switched to the output signal of the PR equalization circuit 4 to stabilize the phase synchronization performance. Thus, by switching the input signal of the phase error detection circuit 7, it is possible to achieve both reduction of the synchronization time and stability of the synchronization performance.

  As described in detail above, the phase error detection circuit and the phase locked loop circuit according to the present invention, and the information reproducing apparatus using the circuit, are affected by the DC level fluctuation and asymmetry of the analog input signal. Therefore, a stable phase synchronization characteristic can be obtained, and it can be suitably applied particularly to an optical disc reproducing apparatus.

  Each embodiment of the present invention described above is an example for explaining the present invention, and therefore, the scope of the present invention is not limited to the embodiment. Further, those skilled in the art can implement the present invention in various other modes without departing from the gist of the present invention.

It is a block diagram which shows one Example of the information reproduction apparatus by this invention. (Example 1) It is a block diagram which shows one Example of the DC feedback circuit by this invention. It is a block diagram which shows one Example of the phase error detection circuit by this invention. It is a wave form diagram which shows operation | movement of the phase error detection circuit by this invention. It is a wave form diagram which shows the operation | movement at the time of DC offset of the phase error detection circuit by this invention. It is a wave form diagram which shows the operation | movement at the time of phase offset of the phase error detection circuit by this invention. It is a block diagram which shows the other Example of the information reproduction apparatus by this invention. (Example 2) It is a block diagram which shows the further another Example of the information reproduction apparatus by this invention. Example 3

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical disk medium, 2 ... Optical pick-up circuit, 3 ... A / D converter, 4 ... PR equalization circuit, 5 ... Maximum likelihood decoding circuit (Viterbi decoding circuit), 6 ... DC feedback circuit, 601 ... Subtractor, 602, 611, 621 ... register, 603, 612, 622 ... adder, 613, 623 ... attenuator, 614 ... amplitude limiter, 7 ... phase error detection circuit, 711, 721 ... binarization circuit, 712 ... adder , 713 ... Modulo 2 adder, exclusive OR (Ex-OR) circuit, 714, 716 ... switch circuit, 715 ... polarity inversion circuit, 720 ... register, 8 ... loop filter,
DESCRIPTION OF SYMBOLS 9 ... D / A converter, 10 ... Voltage controlled oscillator (VCO), 11 ... Pre-equalization circuit, 12 ... Switch circuit, 20 ... Servo circuit, 30 ... System control circuit.

Claims (6)

A circuit that samples an analog input signal with a predetermined clock, receives an analog / digital converted digital signal, and detects a phase error of the clock,
Means for detecting a sampling phase error with respect to the analog input signal based on the digital input signal;
A phase error detection circuit comprising: means for detecting a change in a DC component of the analog input signal based on the digital input signal. A circuit that receives an analog / digital converted input signal at a predetermined clock and detects a phase error of the clock;
Means for adding the input signal and a signal obtained by delaying the input signal by one sample time;
Means for detecting a sign change between the input signal and the delayed signal;
First means for outputting the result of the adding means based on the result of the sign change detecting means;
Means for inverting the sign of the output signal of the first means;
And a second means for selecting and outputting the output signal of the first means or the inverting means according to the sign of the input signal. Means for analog / digital conversion of an input signal with a predetermined clock;
Means for controlling the DC level of the output signal of the analog / digital conversion means;
Means for receiving an output signal of the DC level control means and detecting a phase error of the clock;
Controlled by an output signal of the phase error detection means, and oscillating means for outputting the clock;
Means for receiving an output signal of the DC level control means and detecting the DC level;
The direct current level control means is controlled by an output signal of the direct current level detection means,
A phase-locked loop circuit using the phase error detection circuit according to claim 1 for the phase error detection means and the DC level detection means. Means for analog / digital conversion of an input signal with a predetermined clock;
Means for controlling the DC level of the output signal of the analog / digital conversion means;
Means for receiving an output signal of the DC level control means and detecting a phase error of the clock;
Controlled by an output signal of the phase error detection means, and oscillating means for outputting the clock;
Means for receiving an output signal of the DC level control means and detecting the DC level;
The direct current level control means is controlled by an output signal of the direct current level detection means,
A phase-locked loop circuit using the phase error detection circuit according to claim 2 for the phase error detection means and the DC level detection means. Means for reading digital information recorded on a recording medium;
Means for analog / digital conversion of the output signal of the reading means with a predetermined clock;
Means for controlling the DC level of the output signal of the analog / digital conversion means;
Means for equalizing the output signal of the DC level control means;
Means for maximum likelihood decoding the output signal of the equalization means;
Means for receiving an output signal of the DC level control means or the equalization means and detecting a phase error of the clock;
Controlled by an output signal of the phase error detection means, and oscillating means for outputting the clock;
Means for receiving an output signal of the DC level control means or the equalization means and detecting the DC level;
The direct current level control means is controlled by an output signal of the direct current level detection means,
An information reproducing apparatus using the phase error detection circuit according to claim 1 or 2 for the phase error detection means and the DC level detection means. Means for reading digital information recorded on a recording medium;
Means for analog / digital conversion of the output signal of the reading means with a predetermined clock;
Means for equalizing the output signal of the analog / digital conversion means;
Means for maximum likelihood decoding the output signal of the equalization means,
5. An information reproducing apparatus using the phase-locked loop circuit according to claim 3 or 4 as the analog / digital conversion means.

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