JP2005339597A - Reproduction clock generation circuit of information signal, and information recording reproduction apparatus using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reproduction clock generation circuit which can pull in a PLL stably and at high speed. <P>SOLUTION: The reproduction clock generation circuit is constituted so as to detect an initial phase error of output of a transversal filter and a reproduction clock, change a coefficient of FIR according to the initial phase error, give a phase shift which negates the initial phase error, and move the phase error near zero instantly. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for reproducing digital data recorded on an information medium, and more particularly to reproduction signal processing for synchronizing reproduction signals when reproducing data.

  Conventionally, a data recording / reproducing apparatus such as an optical disk apparatus reproduces an information signal with the configuration shown in FIG. In FIG. 10, reference numeral 1 denotes an optical disk as an information carrier. A spindle motor 2 rotates the optical disk at a constant speed. A pickup 3 irradiates the optical disc 1 with a beam, receives reflected light, performs photoelectric conversion, and outputs information from an information track on the optical disc 1 as a reproduction signal. An amplifier 4 amplifies the output of the pickup 3. An A / D converter 5 converts the output of the amplifier 4 into a digital value. Reference numeral 6 denotes a phase error detector that receives the digital reproduction signal converted by the A / D converter 5 and is supplied with a reproduction clock that is the output of the VCO 9, and detects the phase difference between the digital reproduction signal and the reproduction clock. 7A and 7B are loop filters to which the phase error, which is the output of the phase error detector, is input. The A / D converter 5, the phase error detector 6, the loop filters 7A and 7B, the D / A converter 8, and the VCO 9 Stabilization of the loop characteristics of the PLL loop constituted by and cutting unnecessary high frequency components. Reference numeral 13 denotes a switch for selecting the loop filters 7A and 7B, and reference numeral 8 denotes a D / A converter for converting the output of the switch into an analog voltage. Reference numeral 9 denotes a so-called VCO which is a voltage controlled oscillator whose oscillation frequency changes depending on the output of the D / A converter. A data separator 10 processes the digital reproduction signal digitized by the A / D converter 5 and outputs it as a binary signal. The data normally recorded on the optical disk 1 is modulated in accordance with the characteristics of the disk. For example, modulated data such as 1-7 modulation is recorded. A demodulator 11 demodulates the 17 modulation. An ECC (error correction code) block 12 decodes a Reed-Solomon code that corrects an error in demodulated data.

  The example of the PLL shown in FIG. 10 shows the concept of JP-A-6-76486. This publication describes a configuration in which the PLL time constant is changed between the start of the PLL and the steady state. In FIG. 10, when the loop filter 7A side is selected by the switch 13, the time constant of the loop characteristics of the PLL is small and the PLL has a high-speed response characteristic. In addition, when the loop filter 7B is selected by the switch 13, the time constant of the loop characteristics of the PLL is large and the PLL is highly stable.

Usually, in an optical disc apparatus, the pickup is moved to the data area to be reproduced (seek operation), the data to be reproduced is cued, and the PLL operation is started at the first part (preamble) of the head data. Data can be played after locking. Many optical disc apparatuses have a concept of a sector as a data recording / reproducing unit. The PLL operation is started at the first part of the sector, and data is reproduced after the PLL is locked. Therefore, there is a need for a PLL that can be locked immediately after the PLL operation starts. On the other hand, there are many cases where the reproduction signal is disturbed by the influence of dust, scratches, etc. attached to the disk surface. This disturbance of the reproduction signal is also a disturbance for the PLL, and the PLL is required to have a characteristic that the operation is not disturbed by the disturbance. For this reason, in Japanese Patent Laid-Open No. 6-76486, a PLL with a small time constant having a quick response is formed when the PLL of the first part of the sector is pulled in, and a PLL with a large time constant having a high stability after being locked.
Japanese Patent Laid-Open No. 06-76486

  However, in this configuration, if a reproduction signal noise occurs due to dust on the disk surface or a defect on the medium immediately before switching from the loop filter 7A to the loop filter 7B, the PLL is greatly shaken due to the speed of response, and a large phase error In some cases, a transition is made to a slow-response PLL with In this case, a burst error occurs until the phase error is drawn by the slow-response PLL.

  In addition, in order to configure a fast response PLL, a broadband loop characteristic is required. For this reason, the preamble portion which is a PLL pull-in region needs many sample points of phase error. For this reason, the preamble part normally uses the shortest mark or a shorter mark close to it in the modulation method. For 1-7 modulation, 2T or 3T is selected.

  Further, in order to draw the PLL at a desired frequency at a high speed in the preamble, the preamble is composed of marks having a certain period. For example, in the case of 1-7 modulation, a 3T repetition pattern is used.

  Because of these restrictions, the preamble pattern is limited, and the PRML system is used as the data separator, and in particular, when a system such as PR1221 having a multi-value level is employed, there are levels that cannot be generated in this 3T sequence, This will hinder the determination of the coefficient of the adaptive equalization filter.

  In addition, if a long preamble is used in order to stably pull in reliably, a region that cannot be used as user data increases, which is disadvantageous in terms of capacity.

  The object of the first invention according to the present application is to provide a reproduction clock signal generation circuit that generates a reproduction clock signal based on a reproduction signal from a recording medium. Accordingly, it is an object of the present invention to provide a regenerated clock generation circuit capable of stably pulling in a PLL at a high speed.

  A second object of the present invention is to provide a regenerative clock generation circuit capable of pulling in a PLL stably and at high speed without depending on the loop gain of the PLL, variations in the medium, and the like.

  In addition, an object of the third invention according to the present application is to provide an information recording / reproducing apparatus using a reproduction clock generation circuit capable of stably and rapidly pulling in a PLL without pulling in a wrong frequency. is there.

In order to achieve the above object, the first invention according to the present application,
In a circuit for generating a reproduction clock signal based on a reproduction signal from a recording medium,
A transversal filter that operates with the reproduction clock that passes the reproduction signal, a phase error detector that detects a phase difference between the output of the transversal filter and the reproduction clock signal, and a band limit of the phase error detector. A loop filter to perform, a voltage controlled oscillator for generating the recovered clock signal, an initial phase error detector for detecting an initial phase error between the output of the transversal filter and the recovered clock, and a voltage controlled oscillator by the loop filter output Control means for controlling the initial phase error at the start of phase synchronization, and changing the coefficient of the transversal filter according to the initial phase error detection value.

  In the above configuration, the transversal filter, the phase error detector, the loop filter, and the voltage controlled oscillator form a phase-locked loop (PLL) configuration. When the PLL starts, the initial phase detector detects the phase error at the start, and this start The PLL pull-in time can be shortened by changing the coefficient of the transversal filter according to the phase error at the time, shifting the phase of the output signal of the transversal filter, and instantaneously reducing the phase difference from the recovered clock.

  In order to achieve the above object, a second invention according to the present application is directed to a circuit that generates a reproduction clock signal based on a reproduction signal from a recording medium, and that operates with the reproduction clock that passes the reproduction signal. Type transversal filter, a phase error detector that detects a phase difference between the output of the adaptive transversal filter and the recovered clock signal, a loop filter that limits a band of the phase error detector, and the recovered clock signal And the adaptive transversal filter is characterized in that the tap coefficients of the adaptive transversal filter are symmetric. Phase lock with filter, phase error detector, loop filter and voltage controlled oscillator By configuring the loop (PLL) and making the adaptive equalization coefficient symmetrical, the phase shift of the signal does not occur in the adaptive transversal filter, and the phase error can be detected after the adaptive transversal filter. Thus, stable PLL operation is possible even if the reproduction signal varies.

  In order to achieve the above object, a third invention according to the present application is directed to a phase shift transversal filter, and an initial phase detection for detecting an initial phase error between the output of the adaptive transversal filter and the recovered clock. And an initial phase error detection at the start of phase synchronization, and changing the coefficient of the phase shift transversal filter in accordance with the initial phase error detection value.

  In the above configuration, by providing a phase shift transversal filter that performs phase shift in addition to the adaptive transversal filter, the phase error at the start is detected by the initial phase detector at the start of the PLL, and the phase error at the start The PLL pull-in time can be shortened by changing the coefficient of the phase shift transversal filter according to the above, shifting the phase of the output signal of the transversal filter, and instantaneously reducing the phase difference from the recovered clock. In addition, phase error detection can be performed after the adaptive transversal filter, and stable PLL operation can be performed even if the reproduction signal varies.

  In order to achieve the above object, a fourth invention according to the present application is a circuit that generates a reproduction clock signal based on a reproduction signal from a recording medium, and is adapted to operate with the reproduction clock that passes the reproduction signal. Type transversal filter, a phase error detector that detects a phase difference between the output of the adaptive transversal filter and the recovered clock signal, a loop filter that limits a band of the phase error detector, and the recovered clock signal A voltage-controlled oscillator for generating a voltage, an initial phase detector for detecting an initial phase error between the output of the adaptive transversal filter and the recovered clock, and a control means for controlling the voltage-controlled oscillator by the loop filter output, Initial phase error detection is performed at the start of synchronization, and the coefficients of the transversal filter are adaptive. The coefficients symmetrical by operation, characterized in that interpolating generated by a shift amount corresponding to the initial phase error detection value.

  In the above configuration, the adaptive transversal filter is used not only for waveform shaping of the reproduced signal but also for phase shift, and while maintaining the symmetry of the tap coefficient for adaptive operation, it reflects the phase shift. By setting the coefficient of the adaptive transversal filter, the phase error at the start is detected by the initial phase detector at the start of the PLL, and the coefficient of the adaptive transversal filter is changed according to the phase error at the start. The PLL pull-in time can be shortened by shifting the phase of the output signal of the type transversal filter and instantaneously reducing the phase difference from the recovered clock. In addition, phase error detection can be performed after the adaptive transversal filter, and stable PLL operation can be performed even if the reproduction signal varies.

  In order to achieve the above object, a fifth invention according to the present application is characterized in that the transversal filter has an even number of taps, and a tap coefficient is symmetrical when an initial phase error is detected.

  In the above configuration, the phase shift amount by the transversal filter can be moved within a range of ± 0.5 clock centered on zero by performing simple calculation of adjacent tap coefficients regardless of the sign of the initial phase.

  As described above, according to the present invention, the initial phase at the start of the PLL in the preamble is detected, the coefficient of the transversal filter is changed in the initial phase, and the phase of the reproduction signal is shifted, so that the PLL can be operated at high speed. It can be pulled in. Further, since it is not necessary to widen the PLL band more than necessary, it is possible to stably pull in at high speed without being adversely affected by scratches and defects. In addition, since frequency pull-in is not required in the preamble, pull-in can be performed at high speed even when a preamble pattern other than a constant periodic pattern is used. Therefore, the preamble pattern can be shortened, and a medium / device with high format efficiency can be provided.

  Further, since the phase error can be detected from the signal after adaptive equalization, the phase error quality is good and the PLL accuracy is improved.

(First embodiment)
FIG. 1 shows a block diagram of a first embodiment to which the present invention is applied. The same number is attached | subjected to the block equivalent to FIG. 10 which is a prior art example.

  Reference numeral 14 denotes an FIR filter which is a transversal filter, and the coefficient of each tap can be adjusted.

  An adder 21 adds the outputs of the loop filter 7 and the loop filter 27. An initial phase error detector 22 detects the phase difference between the FIR 14 and the recovered clock that is the output of the VCO 9, particularly the initial phase error at the start of the PLL, and transmits it to the FIR 14.

  An A / D converter 25 converts the push-pull signal detected by the pickup 3 into a digital value. A wobble phase / frequency error detector 25 detects and outputs a phase difference between the wobble signal included in the push-pull signal and the reproduction clock output from the VCO 9 and a frequency error. Reference numeral 27 denotes a loop filter of the VCO control system using this wobble, which limits the band and stabilizes the loop.

FIG. 5 is a detailed block diagram of the FIR 14. Reference numerals 101 and 102 denote so-called clock synchronization registers which are one-clock delay units that operate with a reproduction clock (not shown). Reference numerals 103, 104, and 105 multiply the reproduction signal input by the digital multiplier and the signal delayed by 101 and 102 by a coefficient. This is a multiplier for multiplying so-called tap coefficients. The tap coefficient is set by the coefficient setting unit 107. Reference numeral 106 denotes an adder that sums the outputs of the multipliers 103, 104, and 105. In this embodiment, a 3-tap FIR is used. The FIR tap coefficient setting is expressed by coefficients in the order of the multipliers 103, 104, and 105. For example, the initial coefficient setting is (0: 1: 0). The coefficient 103 is 0, the coefficient 104 is 1, and the coefficient 105 is 0. The coefficient setting unit changes the tap coefficient set for each multiplier according to the initial phase error that is input. When the initial phase error is zero, the tap coefficient is set to (0: 1: 0). For example, when the initial phase error is 0.1 (the phase error is +36 degrees / 360 degrees, and the reproduced signal is 36 degrees ahead of the clock), the tap coefficients are (0: 0, 9: 0, 1). And the phase of the reproduction signal is shifted by 36 degrees in the delay direction and output. Conversely, when the initial phase error is −0.1, the tap coefficients are (0, 1: 0, 9: 0). For example, when the initial phase error is −0.25 (90 degrees behind the phase error), the tap coefficient (0.25: 0.75: 0) is set, and the output signal can be advanced by 90 degrees. When the input obtained by converting the initial phase error input to the coefficient setting unit 107 to 1 per clock is x and the tap coefficients set to each multiplier are y1, y2, and y3, when x> = 0,
y1 = 0
y2 = (1- | x |)
y3 = x
When x <0,
y1 = x
y2 = (1- | x |)
y3 = 0
And

  FIG. 2 is a schematic diagram of the format of a medium used in the information recording / reproducing apparatus embodying the present invention. The data reproduction clock of the apparatus of this embodiment is 30 MHz and the data density is 0.15 μm / bit. The linear velocity of the medium is 3 m / s. FIG. 2a shows the structure of the preamble and the data area. The preamble part is composed of a fixed pattern of 600 clocks and a sync pattern, and the sync pattern is arranged at the end of the preamble part. The fixed pattern is a repetitive sequence of 4T-4T-2T-2T-3T-3T, that is, 000011110011000111. The grooves constituting the track of the medium meander periodically with a small amplitude. This wobble track is shown in FIG. This wobble track has address information by FM modulation or other well-known methods so that the track position on the medium can be specified. a ′ and b ′ are schematic views in which the preamble portion is enlarged. One wobble cycle is 60 clocks, and the preamble portion corresponds to a length of 10 wobbles. A sync mark for obtaining the timing of the data start clock is arranged at the end of the preamble portion.

  At the time of data recording, the preamble portion and the data portion are recorded in the format shown in FIG. 2 using the reproduction clock synchronized with the wobble signal as a clock. A set of this preamble and data portion constitutes one sector, which corresponds to 2 KB of user data. The data that is actually modulated and recorded is 1-7 modulated, and a resynchronization mark for resynchronization and ECC parity data are added, for a total of 30000 clocks. Normally, several hundreds of wobbles are required to represent one address. However, by counting each wobble, a position resolution equal to or lower than the address can be obtained, and several ten wobble units such as 2 KB as in this embodiment. Can be located. Of course, by setting the sector capacity of this embodiment to a unit of 32 KB or 64 KB, the sector can be made one-to-one with the wobble address.

  When a playback command is received from the host device, the controller of the device performs an access operation so that the data in the designated sector can be played back. Access a little before the designated sector, and first, a wobble PLL operation is performed to synchronize the reproduction clock with the wobble.

  The outputs of the PLL loop filter 7, the pull-in drive 24, and the loop filter 27 are initialized, and it is assumed that zero is output for simplicity. The VCO oscillates with an internal frequency control circuit or a free-run frequency, and the frequency is close to the number of data clocks. When reaching a little before the designated sector, a timing controller (not shown) activates the loop filter 27. (C high active in FIG. 3) Thereby, a reproduction clock synchronized with the wobble of the disk can be obtained. In FIG. 3c, the high period takes time for the wobble PLL to be sufficiently retracted. A timing controller (not shown) detects that the designated sector is reached based on the wobble address information, and moves the PLL main body from the wobble signal to the reproduction signal. The output of the loop filter 27 is held by setting c in FIG. 3 to L, and the loop filter 7 is activated by setting d in FIG. 3 to H. At the same time, by setting e in FIG. 4 to H, the initial phase error detector 22 measures the initial phase. Since the phase error signal contains a large amount of noise (H in the example of FIG. 4 for 2 μs), the initial phase error detector averages the phase error during the period when e in FIG. Detect errors. In FIG. 4, f indicates the phase error, and the initial phase error detector 22 detects the average value of the initial phase error at the falling point of e in FIG. To detect. The initial phase error of 70 degrees is 70/360 = 0.194 when converted to one clock. The coefficient setting unit inside the FIR 14 sets each tap coefficient as (0: 0.806: 0.194) according to the initial phase error of 0.194.

  By setting the tap coefficient of FIR14 to (0: 0.806: 0.194), the signal output from FIR14 becomes a signal delayed in phase by 70 degrees, and the phase error can be brought close to zero instantaneously. . (Timing of the tap coefficient setting arrow in FIG. 4) Thereafter, the phase error is controlled to be close to zero by the PLL.

  In the above-described embodiment, after applying the wobble PLL, the output of the wobble PLL is simultaneously turned on and the reproduction signal system PLL loop is turned on, the initial phase immediately after that is detected, and the tap coefficient of the FIR is changed. Alternatively, the wobble PLL is applied, and the initial phase error is detected at the initial timing of the preamble portion (timing e in FIG. 4) (during this time during the wobble PLL), and then the tap coefficient is changed. A sequence of wobble PLL output hold and reproduction signal system PLL loop on may be taken.

  By applying an appropriate coefficient to the transversal filter according to the initial phase error, the PLL can be pulled in in a short time.

(Second embodiment)
FIG. 6 is a block diagram showing the configuration of the second embodiment to which the present invention is applied. The FIR 14 in the first embodiment is replaced with an equalization filter 15. A detailed block diagram of the equalization filter 15 is shown in FIG.

  In FIG. 7, the equalizing filter 15 is divided into two parts, and 15a is equivalent to the FIR 14 in the first embodiment, and the description thereof is omitted.

  15b is composed of a 5-tap FIR type adaptive filter, and the reproduction signal x (n) is composed of four delay units (111, 112, 113, 114) and five coefficient multipliers (115, 116, 117). , 118, 119), and the sum (125) of the multiplier outputs is the filter output y (n).

  For the sake of simplicity, an adaptive operation in which the operation of the coefficient symmetrization circuit 127 is ignored will be described first.

  The error signal generation circuit calculates the difference between the ideal waveform and the filter output, multiplies a predetermined coefficient, and outputs the result to the coefficient update circuit.

  The ideal waveform is compared with the ideal waveform based on the result of a data separator such as Viterbi decoding at the subsequent stage when the test pattern known in advance is reproduced and when it is determined at the time of reproduction.

  The coefficient update circuit (120, 121, 122, 123, 124) multiplies the output signal of the error signal generation circuit (126) by the input signal of each coefficient multiplication circuit, adds it to the current coefficient, and the next coefficient. And

  As this operation continues, the coefficients are optimized, and the error approaches 0, and the adaptive operation converges.

  Next, the coefficient symmetrization circuit 127 will be described.

  The coefficient symmetrization circuit 127 has a function of making each tap coefficient symmetrical in the form of (0.1: 0.2: 0.4: 0.2: 0.1).

When the output of each coefficient update circuit is j1, j2, j3, j4, j5 and the output of each coefficient symmetrization circuit is k1, k2, k3, k4, k5, k1 = k5 = (j1 + j5) / 2
k2 = k4 = (j2 + j4) / 2
k3 = j3
Perform the process.

  When a playback command is received from the host device, the controller of the device performs an access operation so that the data in the designated sector can be played back. Access a little before the designated sector, and first, a wobble PLL operation is performed to synchronize the reproduction clock with the wobble.

  The outputs of the PLL loop filter 7, the pull-in drive 24, and the loop filter 27 are initialized, and it is assumed that zero is output for simplicity. The VCO oscillates with an internal frequency control circuit or a free-run frequency, and the frequency is close to the number of data clocks. When reaching a little before the designated sector, a timing controller (not shown) activates the loop filter 27. (C high active in FIG. 3) Thereby, a reproduction clock synchronized with the wobble of the disk can be obtained. In FIG. 3c, the high period takes time for the wobble PLL to be sufficiently retracted. A timing controller (not shown) detects that the designated sector is reached based on the wobble address information, and moves the PLL main body from the wobble signal to the reproduction signal. The output of the loop filter 27 is held by setting c in FIG. 3 to L, and the loop filter 7 is activated by setting d in FIG. 3 to H. At the same time, by setting e in FIG. 4 to H, the initial phase error detector 22 measures the initial phase. Since the phase error signal contains a large amount of noise (H in the example of FIG. 4 for 2 μs), the initial phase error detector averages the phase error during the period when e in FIG. Detect errors. In FIG. 4, f indicates the phase error, and the initial phase error detector 22 detects the initial phase error average value of the initial phase error at the falling edge of e in FIG. To detect. The initial phase error of 70 degrees is 70/360 = 0.194 when converted to one clock. In the coefficient setting unit 15a in the equalization filter 15, each tap coefficient is set to (0: 0.806: 0.194) according to the initial phase error of 0.194.

  By setting the tap coefficient of FIR14 to (0: 0.806: 0.194), the signal output from FIR14 becomes a signal delayed in phase by 70 degrees, and the phase error can be brought close to zero instantaneously. . (Timing of the tap coefficient setting arrow in FIG. 4) Thereafter, the phase error is controlled to be close to zero by the PLL.

Thereafter, when it is confirmed that the lock is completely achieved by monitoring the phase error signal, the adaptive operation of 15b in the equalization filter 15 is started. (The operation / non-operation mode of the adaptive operation can be switched by a control signal not shown)
Since each tap coefficient is always symmetric by the processing of the coefficient symmetrization circuit, no phase shift is given to the signal passing through the adaptive filter 15b. Therefore, the reproduced signal after the adaptive filter is equal to the phase shift of the transversal filter 15a. Can always keep. Thereby, even when the PLL loop is ON, the PLL loop can be stably applied.

  By performing the adaptive equalization in this way, there is no change such as the phase delay advance of the adaptive filter 15b, and the phase error detector 6 or the initial phase error detector 22 uses the output signal of the equalization filter 15 for the phase error. Even if is detected, a correct phase error can be detected, and the PLL can be stably applied.

(Third embodiment)
FIG. 8 is a detailed block diagram of the equalization filter 15 in the third embodiment to which the present invention is applied. The block diagram of the entire apparatus is the same as FIG.

  The reproduced signal enters the equalization filter 15 having a direct adaptation function, and performs an adaptation operation and a phase shift operation only by changing the coefficient of the adaptation filter.

  Since the adaptive filter operation and the coefficient symmetrization circuit operation described in the second embodiment are the same, the description thereof is omitted.

  Reference numeral 128 denotes a coefficient shift circuit which performs an operation according to the input initial phase error on the coefficient output from the coefficient symmetrization circuit and sets the coefficient in each of the multipliers 115 to 119.

The initial phase error is x
When the output of each coefficient symmetrizing circuit is k1, k2, k3, k4, k5 and the output of each coefficient shifting circuit is m1, m2, m3, m4, m5, when x> = 0,
m1 = (1− | x |) × k1 + | x | × k2
m2 = (1− | x |) × k2 + | x | × k3
m3 = (1− | x |) × k3 + | x | × k4
m4 = (1− | x |) × k4 + | x | × k5
m5 = (1− | x |) × k5
When x <0,
m1 = (1− | x |) × k1
m2 = (1− | x |) × k2 + | x | × k1
m3 = (1− | x |) × k3 + | x | × k2
m4 = (1− | x |) × k4 + | x | × k3
m5 = (1− | x |) × k5 + | x | × k4
Is output.

  By setting the equalization filter 15 to the above-described configuration, an operation equivalent to the operation described in the second embodiment can be performed. That is, the phase shift function corresponding to the initial phase error and the adaptive operation of the equalization filter can be realized by one equalization filter 15.

  By adopting the configuration of the present embodiment, it is possible to reduce the circuit that realizes the equalization filter 15, and it is effective in reducing the chip area, cost, and power consumption when an IC is realized. In addition, since the number of stages of delay elements is smaller than that in the second embodiment, even when a phase error is detected at the subsequent stage of the equalizing filter 15, a high-speed and high-precision PLL can be configured with little detection delay.

(Fourth embodiment)
FIG. 9 is a detailed block diagram of the equalization filter 15 in the fourth embodiment to which the present invention is applied. The block diagram of the entire apparatus is the same as FIG.

  Unlike the third embodiment, the number of taps is four and an even number. In the present embodiment, the initial default tap coefficients are symmetrical. For example, each tap coefficient is (0.1: 0.4: 0.4: 0.1).

  Similar to the second embodiment, the coefficient symmetrization circuit 127 has a function of making each tap coefficient symmetrical.

When the output of each coefficient update circuit is j1, j2, j3, j4, and the output of each coefficient symmetrization circuit is k1, k2, k3, k4, k1 = k4 = (j1 + j4) / 2
k2 = k3 = (j2 + j3) / 2
Perform the process.

  Reference numeral 128 denotes a coefficient shift circuit that performs an operation corresponding to the input initial phase error on the coefficient output from the coefficient symmetrization circuit and sets the coefficient in each of the multipliers 115 to 118.

The initial phase error is x
When the output of each coefficient symmetrization circuit is k1, k2, k3, k4 and the output of each coefficient shift circuit is m1, m2, m3, m4, m1 to m4 can be determined regardless of the sign of x.
m1 = (0.5−x) × k1 + (0.5 + x) × k2
m2 = (0.5−x) × k2 + (0.5 + x) × k3
m3 = (0.5−x) × k3 + (0.5 + x) × k4
m4 = (0.5−x) × k4 + (0.5 + x) × k5
Is output.

  By adopting the configuration of this embodiment, it is not necessary to switch the calculation of the coefficient shift circuit according to the sign of the initial phase error, and the calculation circuit is simplified, so that the chip area when IC is reduced, the cost is reduced, Effective in reducing power consumption.

1 is a block diagram of an optical disk reproduction signal processing system according to a first embodiment of the present invention. 1 is a conceptual diagram of a format of an optical disc according to an embodiment of the present invention. 1 is a conceptual diagram of a format of an optical disc according to an embodiment of the present invention. FIG. 3 is an operation explanatory diagram of the PLL according to the first embodiment of the present invention. The detailed block diagram of FIR14 which concerns on the 1st Example of this invention. The block diagram of the optical disk reproduction signal processing system concerning the 2nd example of the present invention. The detailed block diagram of the equalization filter 15 which concerns on the 2nd Example of this invention. The detailed block diagram of the equalization filter 15 which concerns on the 3rd Example of this invention. The detailed block diagram of the equalization filter 15 which concerns on the 4th Example of this invention. The block diagram of the conventional optical disk reproduction signal processing system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Spindle motor 3 Pickup 4 Amplifier 5 A / D converter 6 Phase error detector 7 Loop filter 8 D / A converter 9 VCO
10 Data separator 11 Demodulator 12 ECC
14 FIR filter 15 Equalization filter 21 Adder 22 Initial phase error detector 25 A / D converter 26 Wobble phase / frequency error detector 27 Loop filter 107 Coefficient setter 127 Coefficient symmetrization circuit 128 Coefficient shift circuit

Claims (5)

In a circuit for generating a reproduction clock signal based on a reproduction signal from a recording medium,
A transversal filter that operates with the recovered clock that passes the recovered signal;
A phase error detector for detecting a phase difference between the output of the transversal filter and the recovered clock signal;
A loop filter for band limiting the phase error detector;
A voltage controlled oscillator for generating the recovered clock signal;
An initial phase error detector for detecting an initial phase error between the output of the transversal filter and the recovered clock;
Having a control means for controlling the voltage controlled oscillator by the loop filter output,
An information signal reproduction clock generation circuit which detects an initial phase error at the start of phase synchronization and changes a coefficient of the transversal filter in accordance with an initial phase error detection value. In a circuit for generating a reproduction clock signal based on a reproduction signal from a recording medium,
An adaptive transversal filter operating with the recovered clock that passes the recovered signal;
A phase error detector for detecting a phase difference between the output of the adaptive transversal filter and the recovered clock signal;
A loop filter for band limiting the phase error detector;
A voltage controlled oscillator for generating the recovered clock signal;
Having a control means for controlling the voltage controlled oscillator by the loop filter output,
An information signal reproduction clock generation circuit characterized in that tap coefficients of the adaptive transversal filter are symmetrical. A phase shift transversal filter;
An initial phase detector for detecting an initial phase error between the output of the adaptive transversal filter and the recovered clock;
3. The information signal reproduction clock generation circuit according to claim 2, wherein initial phase error detection is performed at the start of phase synchronization, and a coefficient of the phase shift transversal filter is changed in accordance with an initial phase error detection value. . In a circuit for generating a reproduction clock signal based on a reproduction signal from a recording medium,
An adaptive transversal filter operating with the recovered clock that passes the recovered signal;
A phase error detector for detecting a phase difference between the output of the adaptive transversal filter and the recovered clock signal;
A loop filter for band limiting the phase error detector;
A voltage controlled oscillator for generating the recovered clock signal;
An initial phase detector for detecting an initial phase error between the output of the adaptive transversal filter and the recovered clock; and a control means for controlling a voltage controlled oscillator by the loop filter output;
Initial phase error detection is performed at the start of phase synchronization, and a coefficient of the transversal filter is generated by interpolating a symmetrical coefficient by an adaptive equalization operation with a shift amount corresponding to an initial phase error detection value. Regenerative clock generation circuit.   5. The information signal reproduction clock generation circuit according to claim 1, wherein the transversal filter has an even number of taps, and a tap coefficient is symmetric when an initial phase error is detected.

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