JP4162665B2 - Synchronization signal detection circuit and disk reproducing apparatus - Google Patents

Description

  The present invention relates to a synchronization signal detection circuit and a disk reproducing device, and is particularly suitable for use when intersymbol interference occurs in a signal waveform.

A disk reproduction device such as a CD drive or a DVD drive is provided with a synchronization signal detection circuit for detecting a synchronization signal from a reproduction signal. Here, the synchronization signal often has a longer signal period than a normal signal. In this case, the synchronization signal detection circuit slices the reproduction signal at zero level to detect the signal width, The longest signal width period is detected as the synchronization signal period. Note that the inventions described in Patent Documents 1 and 2 below are known as synchronization signal detection circuits.
JP 7-326139 A JP-A-8-138328

  However, when the synchronization signal is detected by slicing at zero level as described above, the synchronization signal period cannot be correctly detected when intersymbol interference occurs in the reproduced signal waveform, particularly when a high-density disk is handled. Problem arises. In other words, when intersymbol interference occurs in the reproduced signal, a signal width longer than the signal width that should appear originally is detected by the slice at zero level, and therefore a period that is not a synchronization signal period is erroneously detected as a synchronization signal period Can happen.

  Therefore, an object of the present invention is to provide a synchronization signal detection circuit and a disk reproducing apparatus that can solve such a problem and can detect a synchronization signal smoothly and properly even if intersymbol interference occurs in the reproduction signal waveform.

  In view of the above problems, the present invention has the following features.

  According to the first aspect of the present invention, there is provided a signal width detection unit for detecting a signal width L when a signal waveform is sliced at positive and negative signal levels different from zero level, and a signal detected by the signal width detection unit. A synchronization signal width setting unit that sets, as a reference synchronization signal width W, a signal width L that is maximum within a period T1 that is longer than the longest synchronization signal generation interval assumed during the synchronization signal detection processing of the width L; The signal width L detected by the detection unit is compared with the reference synchronization signal width W set by the synchronization signal width setting unit, and the period of the signal width L that matches the reference synchronization signal width W is set as the synchronization signal period. In the synchronization signal detection circuit having the synchronization signal detection unit that detects the synchronization signal, the synchronization signal detection unit is the shortest synchronization signal that is assumed during the synchronization signal detection process among the signal widths L detected by the signal width detection unit Occurrence interval When the maximum signal width MAX_L in the period T2 is detected as the maximum signal width L_L in the period T2, and the maximum signal width MAX_L matches the reference synchronization signal width W, the period corresponding to the maximum signal width MAX_L is detected. Is detected as a synchronization signal period.

  According to a second aspect of the present invention, in the synchronization signal detection circuit according to the first aspect, the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and the maximum in the period T1. The signal width L is updated and set as the reference synchronization signal width W.

  According to a third aspect of the present invention, a signal width detection unit that detects a signal width L when the reproduced signal waveform is sliced at positive and negative signal levels different from the zero level, and the signal width detection unit detects the signal width L. A synchronization signal width setting unit for setting, as a reference synchronization signal width W, a signal width L that is maximum within a period T1 that is longer than the longest synchronization signal generation interval assumed during the synchronization signal detection processing of the signal width L; The signal width L detected by the width detection unit is compared with the reference synchronization signal width W set by the synchronization signal width setting unit, and the period of the signal width L that matches the reference synchronization signal width W is determined as the synchronization signal. In a disk reproducing apparatus that detects a synchronization signal inserted in a recording signal by a synchronization detection circuit having a synchronization signal detection unit that detects as a period, the synchronization signal detection unit is detected by the signal width detection unit signal The maximum signal width L_L_L_L is detected as a maximum signal width MAX_L in the period T2 within the period T2 smaller than the shortest synchronization signal generation interval assumed in the synchronization signal detection process, and the maximum signal width MAX_L is the reference. When matching with the synchronization signal width W, a period corresponding to the maximum signal width MAX_L is detected as a synchronization signal period.

  According to a fourth aspect of the present invention, in the third aspect, the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and sets the maximum signal width L within the period T1. The reference synchronization signal width W is updated and set.

  The “period T1” in the present invention is indicated as a “reference synchronization signal width detection period” in the following embodiment. In addition, the “period T2” in the above-described invention is indicated as a “maximum width detection period” in the following embodiment. Further, the “allowable fluctuation value α” in the present invention is indicated as “margin α” in the following embodiment.

  According to the present invention, since the synchronization signal is detected based on the signal width L when the signal waveform is sliced at a signal level different from the zero level in the synchronization signal detection circuit, intersymbol interference occurs in the signal waveform. Even if it occurs, the synchronization signal period can be properly detected.

  According to the second or ninth aspect of the invention, since the reference synchronization signal width W is updated and set, the synchronization signal period can be set smoothly even when the synchronization signal period fluctuates, such as during synchronization pull-in or PLL pull-in. Can be detected.

  In addition, according to the inventions of claims 3 and 4 or claims 10 and 11, the synchronization signal detection process can be facilitated.

  According to the invention of claim 5 or 12, since the variation allowable value α is set according to the size of the reference synchronization signal width W or the disk rotation speed, the synchronization signal period is set at the time of synchronization pull-in or PLL pull-in. Even when it fluctuates, the synchronization signal period can be detected smoothly.

  According to the invention of claim 6 or 13, since the synchronization signal is always included in the period T1, the reference synchronization signal width W can be set appropriately.

  According to the invention of claim 7 or 14, since it is possible to avoid two synchronization signals being included in the period T2, it is possible to suppress the detection omission of the synchronization signal.

The effects and significance of the present invention will become more apparent from the following description of embodiments. However, the embodiment described below is merely an example of the present invention, and the significance of the present invention or each constituent element is not limited to those described in the following embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, the present invention is applied to an optical disc apparatus that performs recording / reproduction on a high density optical disc such as a next generation DVD (Digital Versatile Disc). FIG. 1 shows a format of data recorded on a disc.

  FIG. 2 shows a configuration of the optical disc apparatus according to the embodiment. In FIG. 2, only the reproduction system is shown, and the recording system is not shown. Also, a focus servo circuit, a tracking servo circuit, etc. are not shown.

  As shown in FIG. 2, the optical disc apparatus according to the present embodiment includes an optical pickup 101, an amplifier circuit 102, an ADC (Analog-Digital Converter) 103, a data interpolation circuit 104, an equalizer 105, a Viterbi decoder 106, A phase comparator 107, an LPF (loop filter) 108, an adder 109, a digital VCO (Voltage Controlled Oscillator) 110, a synchronization signal detection circuit 111, a frequency error detection circuit 112, and an LPF (loop filter) 113. A spindle motor servo circuit 114 and a spindle motor 115.

  The optical pickup 101 irradiates a disk with laser light to write data and receives reflected light from the disk to read data. The amplification circuit 102 amplifies the reproduction RF signal supplied from the optical pickup 101 and outputs it to the ADC 103. The ADC 103 samples the reproduced RF signal at a sampling timing corresponding to an asynchronous clock (hereinafter referred to as a system clock) having a frequency higher than that of the resample clock generated by the digital VCO 110, converts the sample value into digital data, and converts the data into digital data. Output to the interpolation circuit 104.

  The data interpolation circuit 104 uses the digital data input from the ADC 103 and the resample clock and resample phase information input from the digital VCO 110 to use the data value (resample timing) at the data interpolation timing (hereinafter referred to as “resample timing”). Data) and the calculated resample data is output to the equalizer 105 and the phase comparator 107. That is, as shown in FIG. 3, the interpolated value at the resample timing (timing indicated by ● in the figure) shifted by the phase corresponding to the resample phase information from the rise timing of the resample clock is the AD before and after the resample timing. Calculation is performed based on the data (digital data input from the ADC 103), and this is output to the equalizer 105 and the phase comparator 107 as resample data at the resample timing.

  The equalizer 105 performs waveform equalization processing on the resampled data supplied from the data interpolation circuit 104 and outputs the result to the Viterbi decoder 106. The Viterbi decoder 106 performs Viterbi decoding processing on the digital data supplied from the equalizer 105 to generate and output binary data of 1 and 0.

  The phase comparator 107 discriminates the edge of the reproduced RF signal waveform based on the resampled data supplied from the data interpolation circuit 104, that is, the intersection position of the reproduced RF signal waveform and the slice level shown in FIG. The phase difference between the normal resample timing set based on the above and the resample timing generated by the digital VCO 110 is detected. Then, digital data (phase difference data ΔP) corresponding to the phase difference is output to the LPF 108.

  The LPF 108 cuts off the high-frequency component of the phase difference data and turns it into a direct current, and outputs this to the adder 109. The adder 109 adds the phase difference data ΔP supplied from the LPF 108 and the frequency shift data ΔF (described later) supplied from the LPF 113 and outputs the result to the digital VCO 110.

  The digital VCO 110 adjusts the period of the resample clock so as to compensate for the phase difference and the frequency shift in accordance with the data (phase difference data + frequency shift data) supplied from the adder 109, The resample phase information is output to the data interpolation circuit 104. The adjusted resample clock is output to the spindle motor servo circuit 114.

  The synchronization signal detection circuit 111 detects the synchronization signal period from the digital data input from the ADC 103 and outputs the detection result to the frequency error detection circuit 112. Details of the synchronization signal detection circuit 111 will be described later.

  The frequency error detection circuit 112 detects the frequency of the synchronization signal from the synchronization signal period detection signal supplied from the synchronization signal detection circuit 111, and outputs the difference ΔF between this frequency and the reference frequency to the LPF 113 as frequency shift data. . The LPF 113 cuts off the high frequency component of the frequency shift data and turns it into a direct current, and outputs this to the adder 109.

  The spindle motor servo circuit 114 calculates the difference between the frequency of the resample timing supplied from the digital VCO 110 and the target frequency, and uses this as frequency shift data to rotate the disk to approximate the frequency of the resample timing to an appropriate value. Generate a servo signal. For example, if the difference is a positive value, the rotation of the disk is slower than the appropriate value, so that the rotation needs to be accelerated. Conversely, if the difference is a negative value, the rotation of the disk needs to be delayed. The spindle motor servo circuit 114 adjusts the rotation roughly at a rotational speed corresponding to the disk radial position, and then controls the rotational speed to an appropriate rotational speed with reference to the difference. However, it is also possible to rotate at CAV (constant angular velocity) regardless of the radial position from the beginning, and adjust the value to an appropriate value by referring to the difference.

  The spindle motor 115 rotationally drives the disk according to the servo signal supplied from the spindle motor servo circuit 114.

  Next, a synchronization detection method in the synchronization signal detection circuit 111 will be described with reference to FIG.

  In such synchronization detection, first, the reproduction signal waveform is sliced at two threshold levels Th1 and Th2, and a signal period (signal width L) at each slice is detected. That is, when sliced at the positive threshold level Th1, the period from when the amplitude value of the reproduction signal becomes equal to or greater than Th1 to less than Th1 is detected as the signal width L, and sliced at the negative threshold level Th2 In this case, a period from when the amplitude value of the reproduction signal becomes equal to or less than Th2 to exceed Th2 is detected as the signal width L. Specifically, the number of system clocks included in the period is counted, and the counted number is set as the signal width L. Then, the lengths of a plurality of signal widths L acquired in a preset period (maximum width detection period) are compared, and the longest signal width L is acquired as the maximum signal width MAX_L in the maximum width detection period. .

  The maximum signal width MAX_L acquired in this way is compared with the signal width W ± α obtained by adjusting the reference synchronization signal width W with the margin α. Here, the reference synchronization signal width W is appropriately set during the synchronization signal detection process (this will be described later). Then, it is determined whether the maximum signal width MAX_L is in the range of W−α to W + α, and it is determined whether the maximum signal width MAX_L is the synchronization signal period according to the determination result. Specifically, the difference between the maximum signal width MAX_L and the reference synchronization signal width W is obtained, and when this difference is within a range of ± α, the maximum signal width MAX_L is set as the synchronization signal period. When this difference is not within the range of ± α, the maximum signal width MAX_L is not set as the synchronization signal period.

  In the example shown in FIG. 4, three signal widths L are detected, and the signal width L of 13T is set as the maximum signal width MAX_L. Then, the maximum signal width MAX_L is compared with the reference synchronization signal width W, and when the difference is within a range of ± α, the maximum signal width MAX_L is detected as the synchronization signal period. As described in the prior art, when the reproduction signal waveform is sliced at zero level, as shown in the figure, the period other than the true synchronization signal period is the longest period. It is erroneously detected as the synchronization signal period. On the other hand, when synchronization detection is performed as in the present embodiment, the possibility that the true synchronization signal detection period is properly detected as the synchronization signal period is raised.

  FIG. 5 shows a configuration example of the synchronization signal detection circuit 111.

  In this configuration example, the synchronization signal detection circuit 111 includes a data slice unit 11, a signal width detection unit 12, a maximum width detection unit 13, a synchronization signal width setting unit 14, an α setting unit 15, and a synchronization signal detection unit. 16 is composed.

  The data slicing unit 11 compares the AD data input from the ADC 103 with the threshold levels Th <b> 1 and Th <b> 2 and supplies the comparison result to the signal width detection unit 12. The signal width detection unit 12 detects the signal width L (the number of system clocks) as described above based on the data supplied from the data slice unit 11, and outputs the detection result to the maximum width detection unit 13. The maximum width detector 13 compares the length of the signal width L supplied from the signal width detector 12 for each maximum width detection period, and detects the longest signal width L as the maximum signal width MAX_L.

  The synchronization signal width setting unit 14 compares the maximum signal width MAX_L supplied from the maximum width detection unit 13 during the synchronization signal width setting period, and sets the maximum maximum signal width MAX_L as the reference synchronization signal width W.

  The α setting unit 15 sets a margin α for the reference synchronization signal width W. Here, the margin α may be fixed, but is more preferably adjusted according to the rotational speed of the disk. That is, it may be adjusted so that it decreases as the rotational speed of the disk increases. For example, the reference synchronization signal width W set by the synchronization signal width setting unit 14 is monitored as appropriate, and the margin α is adjusted so as to increase as the reference synchronization signal width W increases.

  The synchronization signal detector 16 detects the synchronization signal period by comparing the maximum signal width MAX_L supplied from the maximum width detector 13 with the reference synchronization signal width W and the margin α. That is, the synchronization signal detection unit 16 obtains a difference between the maximum signal width MAX_L and the reference synchronization signal width W, and uses the supplied maximum signal width MAX_L as a synchronization signal only when the obtained difference is within a range of ± α. Detect as period.

  FIG. 6 shows a timing chart when synchronization is detected. In the example shown in the figure, the period during which the system clock is continuously counted for 1000 clocks is the maximum width detection period, and the period during which the system clock is continuously counted for 3000 clocks at the start of synchronization detection is the synchronization signal width setting period. (Initialization period).

  Note that the length of the maximum width detection period is set such that two synchronization signals are not included in the period. For example, as shown in FIG. 2, when referring to the synchronization signal when pulling in the PLL using the digital VCO 110, one frame period (1 shown in FIG. 1) at the disk rotation speed set as the earliest at the time of PLL pull-in. Frame period).

  Further, the synchronization signal width setting period (initialization period) is set to a length that always includes one synchronization signal. For example, when referring to the synchronization signal at the time of PLL pull-in, it is set to a period longer than one frame period (one frame period shown in FIG. 1) at the disk rotation speed set as the slowest at the time of PLL pull-in. .

  Referring to FIG. 6, when synchronization detection is started, first, the maximum signal width MAX_L is detected in each maximum width detection period (for 1000 clocks) within the initialization period (for 3000 clocks). The signal width MAX_L is set as the reference synchronization signal width W. Thereafter, detection of the synchronization signal is started using the reference synchronization signal width W and the margin α. When such a synchronization signal is detected, the number of clocks from the start position of each maximum width detection period to the position of the maximum signal width MAX_L is stored. If the maximum signal width MAX_L is detected as a synchronization signal, the synchronization detection signal is output at the timing when the number of clocks stored has elapsed from the start position of the next maximum width detection period. That is, the synchronization detection signal is output after being delayed by the maximum width detection period.

  FIG. 7 shows a flowchart for detecting the maximum signal width and a flowchart for detecting the reference synchronization signal width.

  Referring to FIG. 9A, when the maximum signal width is detected, the reproduced signal waveform is sliced at threshold levels Th1 and Th2, and the signal width L is sequentially acquired (S10). Each time the signal width L is acquired, the signal width L is compared with the signal width L that has been the longest (S11). If the signal width L is larger than this (S11: YES), it is replaced with the maximum value MAX_L of the signal width L (S12). ). This replacement is repeated from the start to the end of the maximum width detection period (S13). That is, in the example of FIG. 6, the system clock count (ClkCNT) from the start of detection of the maximum signal width is repeated until it reaches 1000 clocks (MAXCNT). When the maximum width detection period ends, the maximum value MAX_L of the signal width remaining at that time is output as it is as the maximum signal width MAX_L.

  Referring to FIG. 5B, when the reference synchronization signal width is detected, the reproduction signal waveform is sliced at threshold levels Th1 and Th2, and the signal width L is sequentially acquired (S20). Each time the signal width L is acquired, the signal width L is compared with the signal width L that has been the longest (S21). If the signal width L is larger than this (S21: YES), the signal width L is replaced with the maximum value W of the signal width L (S22) ). This replacement is repeated from the start to the end of the reference synchronization signal width detection period (S23). That is, in the example of FIG. 6, the system clock count (ClkCNT) from the start of detection of the maximum signal width is repeated until it reaches 3000 clocks (INICNT). When the reference synchronization signal width detection period ends, the maximum signal width W remaining at that time is output as it is as the reference synchronization signal width W.

  FIG. 8 shows a flowchart when the synchronization signal is detected.

  When the synchronization signal detection is started, first, the reference synchronization signal width setting process shown in FIG. 7B is executed, and the reference synchronization signal width W is set (S101). Then, the margin α is set based on the set reference synchronization signal width W (S102). Thus, the initial period ends, and the synchronization signal detection period starts. When the margin α is fixed, S102 is omitted.

  Therefore, when the synchronization signal detection period is started, the maximum signal width detection process of FIG. 7A is executed, and the maximum signal width MAX_L is acquired (S103). The acquired maximum signal width MAX_L is compared with the reference synchronization signal width W set in S101 (S104). If the maximum signal width MAX_L is “W−α <MAX_L <W + α”, the maximum signal width MAX_L Is detected as a synchronization signal period (S105). If the maximum signal width MAX_L is not “W−α <MAX_L <W + α”, the period of the maximum signal width MAX_L is not detected as the synchronization signal period (S108), and the process returns to S103.

  When the period of the maximum signal width MAX_L is detected as the synchronization signal period in S105, the position POS (the number of clocks from the start position) from the start position of the maximum width detection period to the maximum signal width MAX_L is the synchronization signal output timing. (S106). Then, the synchronization detection signal is output at the timing when the position reaches the position POS from the start position of the next maximum width detection period (S107).

Thereafter, the process returns to S103, and the same process is executed for the next maximum width detection period. Such processing is repeated until the synchronization detection operation is completed.

According to the present embodiment, since the maximum signal width when the reproduced signal waveform is sliced at the threshold levels Th1 and Th2 is detected as the synchronization signal period, when the intersymbol interference occurs in the reproduced signal waveform as shown in FIG. In addition, the synchronization signal period can be accurately detected.

  In the present embodiment, the magnitudes of the threshold levels Th1 and Th2 greatly affect the detection accuracy of the synchronization signal. The threshold levels Th1 and Th2 may be set within a range in which the synchronization detection accuracy can be increased while repeating the experiment and verification on the sample disk. FIG. 9 shows the verification results for the HDDVD-ROM. This is an experiment of the detection error rate of the synchronization signal when the positive slice level (Th1) and the negative slice level (Th2) are similarly separated from the zero level by the level shown on the horizontal axis. The horizontal axis represents the signal level when normalized with 8 bits.

  In the case of the figure, if the signal level of the slice level (Th1) (Th2) with respect to the zero level is set to about 140 to 165, errors at the time of synchronization detection can be suppressed. The same experiment is performed on other sample disks, and the size of the slice level may be set to an appropriate value based on these experiments. In addition, the threshold level may be appropriately adjusted from the peak value and the bottom value of the reproduction signal.

  In the above embodiment, the reference synchronization signal width W is set in the initialization period and is used in the synchronization signal detection period after the initialization period. However, the reference synchronization signal width W is detected in the synchronization signal detection period after the initialization period. It is also possible to update appropriately in the period, and to perform synchronization signal detection using the reference synchronization signal width W after the update. Such updating can be performed every fixed period, or when synchronization detection fails or when synchronization detection cannot be performed continuously for a certain period or longer.

  FIG. 10 shows a timing chart when the reference synchronization signal width W is updated every fixed period.

  Here, the reference synchronization signal width W is updated every 3000 clock periods (reference synchronization signal width detection period) during the synchronization signal detection period after the initialization period. That is, in parallel with the synchronization detection, the maximum signal width MAX_L acquired during the 3000 clock period is compared, and the longest maximum signal width MAX_L is the reference synchronization signal used in the next 3000 clock period following the 3000 clock period. Set as width W.

  FIG. 11 shows a flowchart when the synchronization signal is detected in such a case. In the flowchart, in S201, the reference synchronization signal width W is updated every reference synchronization signal width detection period (3000 clock period in the example of FIG. 10). Further, the margin α is reset based on the updated reference synchronization signal width W. In the reference synchronization signal width detection period, the synchronization signal period is detected using the updated reference synchronization signal width W and margin α (S103 to S107).

  As mentioned above, although embodiment which concerns on this invention was described, this invention is not limited to the said embodiment.

For example, in the above embodiment, the number of system clocks counted from the time when the amplitude value of the reproduction signal is equal to or higher than the positive threshold level Th1 to the time when it is lower than Th1 and the negative threshold level Th2 or lower. The count number of the system clocks counted until Th2 is exceeded is acquired as the signal width L. As shown in FIG. By adding, a more precise signal width L_DETAIL may be obtained, and based on this, the maximum signal width MAX_L and the reference synchronization signal width W may be set, and the synchronization signal period may be detected. In this case, when the signal width L_DETAIL is acquired by the number of clocks as in the above embodiment, EDGE_LENGTH1 and EDGE_LENGTH2 are:
EDGE_LENGTH1 = B1 / (A1 + B1)
EDGE_LENGTH2 = B2 / (A2 + B2)
As required. A1 and B1, A2 and B2 are differences (absolute values) of reproduced signals with respect to Th1 and Th2 at the system clock timing before and after the edge position, respectively. In this case, EDGE_LENGTH1 and EDGE_LENGTH2 represent the width from the signal width L (system clock unit) shown in the figure to the front and rear edge positions as the number of system clocks below the decimal point.

  As described above, if the setting of the maximum signal width MAX_L and the reference synchronization signal width W and the detection of the synchronization signal period are performed based on the signal width L_DETAIL, the reference synchronization signal width W and the maximum signal width MAX_L are set. The comparison can be performed more precisely, and the synchronization signal detection accuracy can be further increased.

  In the above embodiment, an example in which the present invention is applied to an optical disk apparatus that performs recording / reproduction on a high-density optical disk such as a next-generation DVD (Digital Versatile Disc) has been described. The present invention can also be applied to a drive device that performs reproduction or other drive devices such as a magneto-optical disk device and a magnetic disk device. However, the present invention is effective when applied to a drive device that handles a disk in which intersymbol interference occurs.

  Furthermore, in the above embodiment, the configuration example (FIG. 2) in which the synchronization signal is referred to when pulling in the PLL using the digital VCO 110 has been shown, but the present invention may be applied to other configuration examples using the synchronization signal. Of course it is possible.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims.

The figure which shows the format of the recording data which concerns on embodiment The figure which shows the structural example of the optical disk apparatus which concerns on embodiment The figure which shows the figure explaining the production | generation method of the resample data which concerns on embodiment The figure which shows notionally the synchronous detection method which concerns on embodiment The figure which shows the structural example of the synchronizing signal detection circuit which concerns on embodiment Timing chart at the time of synchronization detection according to the embodiment Flow chart when detecting maximum signal width and detecting reference sync signal width according to the embodiment Flowchart at the time of synchronization detection according to the embodiment The figure explaining the setting method of the threshold level which concerns on embodiment Timing chart when detecting synchronization according to another embodiment Flowchart at the time of synchronization detection according to another embodiment The figure explaining the acquisition method of the signal width concerning other embodiments

Explanation of symbols

DESCRIPTION OF SYMBOLS 111 Synchronization signal detection circuit 11 Data slice part 12 Signal width detection part 13 Maximum width detection part 14 Synchronization signal width setting part 15 (alpha) setting part 16 Synchronization signal detection part

Claims (4)

A signal width detection unit for detecting a signal width L when the signal waveform is sliced at positive and negative signal levels different from the zero level, and a synchronization signal detection among the signal widths L detected by the signal width detection unit A synchronization signal width setting unit that sets a maximum signal width L as a reference synchronization signal width W within a period T1 that is longer than the longest synchronization signal generation interval assumed at the time of processing, and is detected by the signal width detection unit A synchronization signal detection unit that compares the signal width L with the reference synchronization signal width W set by the synchronization signal width setting unit and detects a period of the signal width L that matches the reference synchronization signal width W as a synchronization signal period. In a synchronization signal detection circuit having
The synchronization signal detection unit has a signal width L that is maximum within a period T2 that is smaller than the shortest synchronization signal generation interval assumed during the synchronization signal detection process among the signal widths L detected by the signal width detection unit. A synchronization signal that is detected as a maximum signal width MAX_L in the period T2, and a period corresponding to the maximum signal width MAX_L is detected as a synchronization signal period when the maximum signal width MAX_L matches the reference synchronization signal width W. Detection circuit.   2. The synchronization signal width setting unit according to claim 1, wherein the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and updates the maximum signal width L as the reference synchronization signal width W within the period T1. A synchronization signal detection circuit, wherein the synchronization signal detection circuit is set. A signal width detection unit for detecting a signal width L when the reproduction signal waveform is sliced at positive and negative signal levels different from the zero level, and a synchronization signal among the signal widths L detected by the signal width detection unit A synchronization signal width setting unit that sets a maximum signal width L within a period T1 that is longer than the longest synchronization signal generation interval assumed during detection processing as a reference synchronization signal width W, and is detected by the signal width detection unit. The sync signal detection is performed by comparing the signal width L with the reference sync signal width W set by the sync signal width setting unit, and detecting a period of the signal width L that matches the reference sync signal width W as a sync signal period. In a disk reproducing apparatus for detecting a synchronization signal inserted in a recording signal by a synchronization detection circuit comprising a unit,
The synchronization signal detection unit has a signal width L that is maximum within a period T2 that is smaller than the shortest synchronization signal generation interval assumed during the synchronization signal detection process among the signal widths L detected by the signal width detection unit. The maximum signal width MAX_L in the period T2 is detected, and when the maximum signal width MAX_L matches the reference synchronization signal width W, a period corresponding to the maximum signal width MAX_L is detected as a synchronization signal period. apparatus.   4. The synchronization signal width setting unit according to claim 3, wherein the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and updates a signal width L that is maximum within the period T1 as a reference synchronization signal width W. A disc playback apparatus characterized by setting.

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