JP3439680B2 - Digital modulation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation circuit for recording a digital signal on a recording medium. 2. Description of the Related Art FIG. 7 is a schematic block diagram of a magneto-optical disk recording / reproducing apparatus. According to this, a recording signal including a video signal, an audio signal, and a data signal is first input to the multiplexer circuit 11 and becomes a multiplexed bit stream. Next, the data is input to the MPEG encoder 12 and compressed using the signal redundancy so that long-time recording can be performed on a limited recording capacity of a recording medium (such as a magneto-optical disk). Then, the error correction code is input to the error correction code adding circuit 13, and an error correction code is added for correcting a code error generated when recording and reproducing on a recording medium (such as a magneto-optical disk) by the error correction circuit 24 at the time of reproduction. Further, the spectrum is converted by the modulation circuit 14 in accordance with the band of the recording medium (magneto-optical disk 17). In particular, to record address data in the low band, to prevent crosstalk with this signal,
It is necessary to suppress low frequency components of the data. Recording amplifier 15
Supplies a recording current to the magnetic head 16 in order to generate a magnetic field required for recording on a recording medium (magneto-optical disk 17). Thereafter, the laser beam 19 is applied to the magneto-optical disk 17 to raise the temperature of the magnetic layer and to heat it to around the Curie point (temperature at which the magnetic material loses coercive force). The recording magnetic field from the magnetic head 16 causes the magneto-optical disk 17
Is magnetized, and data is recorded on the magneto-optical disk 17. At the time of reproduction, the laser beam 19 is applied to the magneto-optical disk 1
7, the reflected light is separated by the polarizing plate 20 into a longitudinal wave component and a transverse wave component. The pickup 18 detects a longitudinal wave component and a transverse wave component of the reflected light to detect a phase difference of the reflected light. The reflected light is affected by the magnetic field when data is recorded on the magneto-optical disk 17, and the longitudinal wave component and the transverse wave component have different reflectances and have a phase difference from the incident light. By detecting this phase difference, recorded data can be reproduced. The detected signal is reproduced by the reproduction amplifier 21.
The signal is amplified to a level required for signal processing, and the equalizer circuit 22 reduces interference between reproduced waveforms. The demodulation circuit 23 is a recording medium (magneto-optical disk 17)
The spectrum adjusted to the band of is returned to the original spectrum. The error correction circuit 24 corrects a code error of data caused by a defect or the like in the recording medium (magneto-optical disk 17) by using a correction code added at the time of recording.
The MPEG decoder 25 expands the signal compressed at the time of recording to the original signal. The demultiplexer circuit 26 separates the input signal into a video signal, an audio signal, and a data signal. FIG. 8 is a block diagram showing one embodiment of a conventional modulation circuit in such a magneto-optical disk recording / reproducing apparatus.
First, the data output from the error correction code adding circuit 13 is input to the convolution circuits (1a, 1b, 1c,..., 1p). 9 is a diagram for explaining the function of the convolution circuit.
DSV (Digital)
4 bits of data are added as an initial value T for controlling (SumValue), and convolution is performed for each word, resulting in C0 to C90. The initial value T has the following 16 values. _{T 0 = 0000 T 1 = 0001} T 2 = 0010 T 3 = 0011 T 4 = 0100 T 5 = 0101 T 6 = 0110 T 7 = 0111 T 8 = 1000 T 9 = 1001 T 10 = 1010 T 11 = 1011 T 12 = 1100 T ₁₃ = 11101 T ₁₄ = 1110 T ₁₅ = 1111 And 92 words (T and C0 to C90)
The NRZI modulation circuit (6a, 6b, 6c,..., 6p) performs NRZI modulation on the data having become as described above for each word. That is, for example, T = 0001 (T ₁ ), D0 = 0
Assuming that 110, D1 = 0001, and D2 = 0111, 9
One word code When this is performed by the convolution circuit 1b for convolution for each word, It becomes. Further, in the NRZI modulation circuit 6b, NR
With ZI modulation, It becomes. [0007] The output of the modulation memory (2a, 2b, 2)
c,..., 2p) and is stored until the DSV for 92 words is calculated. After determining the value of the initial value T that minimizes the DSV, the 92 words to which the initial value T is added are stored in the recording amplifier. 15 is output. NRZI modulation circuit (6a, 6
b, 6c,..., 6p) are input to DSV calculation circuits (7a, 7b, 7c,..., 7p), and the DSV for each word is calculated. Then, in the DSV comparators (8a, 8b, 8c,..., 8p), the DSV for each word is stored in the DSV memory (9a ', 9b', 9c ',
., 9p '), and is compared with the DSV one word before, and when it is larger, the DSV comparator (8a, 8p)
, 8p) are DSV memories (9a ', 9).
b ', 9c',..., 9p '). Therefore, the DSV memory always stores the maximum value of DSV. This processing is performed for 92 words.
The maximum value of the DSV of the word is output to the selector 10. In the selector 10, each DSV memory (9a ', 9b', 9
c ′,..., 9p ′) are compared with each other, and the modulation memories (2a, 2b, 2c,
, 2p) is output to the recording amplifier 15. [0009] When digital data is recorded on a recording medium such as a magneto-optical disk, the digital data is generally modulated and coded, and the modulation code is a DC-free code such as NRZI modulation. Often not.
In addition, the circuit scale tends to be large because complicated signal processing is performed even for a DC-free modulation code. For example, in the above conventional example, considering the initial value T in all cases (16 cases for one word and 4 bits), modulation is performed with each value, DSV is calculated, and the modulated data of the initial value T at which DSV becomes small By selecting, low frequency components were suppressed. For that, a convolution circuit,
NRZI modulation circuit, modulation memory, DSV calculation circuit, DS
V comparators and DSV memories must be prepared in parallel in 16 systems, and the circuit scale becomes extremely large.
The power consumption was increasing. Therefore, such as portable devices,
In an apparatus that requires reduction in power consumption and miniaturization, it is difficult to fit in a limited space, and since power consumption is large, a recording time cannot be lengthened, which is a serious problem. SUMMARY OF THE INVENTION In view of the above problems, the present invention divides data into certain lengths so that DC components do not accumulate, and synchronizes the data at breaks to make it DC-free. Insert a signal. At this time, several kinds of the synchronizing signals are prepared. Among them, the synchronizing signal having the smallest DSV is selected, and the digital data is recorded. However, the NRZI modulation circuit used repeatedly is largely reduced. The DC component is removed with an extremely small circuit scale and power consumption. Specifically, by utilizing the characteristics of NRZI + modulation, convolution,
The processing of the NRZI modulation performed in parallel with the 16 systems is changed to the processing of one system, and the 16 modulation memories are also reduced to one to suppress low frequency components. According to a first aspect of the present invention, a convolution means for performing a convolution by adding a predetermined initial value to each recording data consisting of digital data of a fixed length, and sequentially inverting a part of output data of the convolution means. A plurality of convolution values, a plurality of outputs of the conversion means, NRZI modulation of a plurality of outputs, a plurality of calculation means for calculating a DSV for each predetermined unit, a maximum value of the DSV in each of the plurality of calculation means And a plurality of maximum value calculating means for calculating
Selecting means for selecting the smallest one of the maximum values of the convolution means, and among the output data of the convolution means, the part of the data inputted to the calculating means which has calculated the minimum DSV selected by the selecting means. Means for inverting data of the same portion as the inverted convolution value and performing NRZI modulation. (Embodiment) FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. The signal processing of the modulation circuit 14 is performed every four words and 91 words. The 91-word code from the error correction code adding circuit 13 input to the modulation circuit 14 is input to the convolution circuit 1. Then, as shown in FIG. 9, data of one word (4 bits) is added as an initial value T to the head of every 91 words, and convolution is performed. In the conventional case, 16 initial values T are required as described above. However, in the present invention, this is performed only in the following one method in order to reduce the circuit scale. T = 000
0 (T ₀ ) and 92 words (T and D0 to D90)
Is divided into two, one of which is the modulation memory 2
And the other is input to the DSV code generation circuit 5. FIG. 2 is a detailed block diagram of the DSV code generation circuit 5, and FIG.
Indicates a signal waveform of a specific portion of the circuit. The serial signal of one word (4 bits) is converted into a parallel signal with the timing shown in FIG. 3 by the flip-flops (51, 52, 53, 54) and the clock generation circuit 55. This parallel signal is transmitted to the NRZI modulation circuit 6a.
Have flip-flops (51a, 52a, 53a, 5
The signal is again converted into a serial signal via 4a) and input. However, the NRZI modulation circuit 6b inverts only the fourth bit data of the outputs of the flip-flops (51, 52, 53, 54) by an inverter, and leaves the other flip-flops (51b, 52b, 53b, 5) intact.
4b). Similarly, it data is input to the DSV code generation circuit 5, the bit data is sequentially inverted by the 16 as different data, thereby, for outputting the same data from the T ₀ of the prior art in the case of T ₁₅ Can be. FIG. 4 is a diagram showing a relationship between an input signal and an output signal of the convolution circuit (only six words (D0 to D5) are shown for simplicity). According to this, it is understood that there is a correlation between the case of T = 0000 (T ₀ ) and the other T _{1 to} T ₁₅ .
For example, T = 0000 (T ₀ ) and T = 1111 (T
_In case ₁₅ ), since all four bits are different data, when convolution is performed, C1 to C5
Are different data. Further, when T is T = 1000 (T ₈ ) which is different only in the first bit, the data is different from the data when T = 0000 (T ₀ ) only in the first bit of each word. Similarly, C1 to C5 are data obtained by inverting the data at the bit position different from the case of T = 0000 (T ₀ ), that is, at the position [1] among the 4 bits. After being generated in this manner, the NRZI modulation circuit (6a, 6b, 6c,..., 6p) performs NRZI modulation on a bit-by-bit basis, and a DSV calculation circuit (7a, 7b, 7).
c,..., 7p), DS for each word (4 bits)
V is calculated. FIG. 5 shows an NRZI modulation circuit (6a, 6
, 6p) and the output signals of the DSV calculation circuits (7a, 7b, 7c,..., 7p). Then, the DSV comparators (8a, 8b, 8c,
.., 8p) compares this value with the DSV one word before, and when the value is larger than the DSV one word before, stores the DSV value in the DSV memory + address generation circuit (9a, 9b, 9).
c,..., 9p). As a result, the maximum DSV of each of the 92 words is held in each DSV memory + address generation circuit. Then, 92 words of D
The maximum value of the SV is output to the selector 10. Selector 10
Is a DSV memory + address generation circuit (9a, 9b, 9
c,..., 9p), the initial value T of the system having the smallest DSV is selected, and its address is output to the switch 3 (for example, in the case of the DSV memory + address generation circuit 9a, “ 0000 "). Then, the data delayed by 92 words by the modulation memory 2 is converted into T = 0000 (T
_The waveform of the signal of a bit different from ₀ ) is inverted in the order in which it is performed by the DSV code generation circuit 5. Recorded data is the most DS
The sign becomes the same as that in the case where the initial value T at which V becomes the minimum is added. This is modulated by the NRZI modulation circuit 4 for each bit and output to the recording amplifier 15. In this way, the convolution circuit conventionally provided in 16 parallel systems can be reduced to one system. FIG. 6 shows a frequency spectrum of the modulation circuit of the present invention. The solid line is a characteristic based on simple NRZI modulation, and the dashed line is a characteristic based on NRZI + modulation according to the present invention. According to this, in the frequency spectrum of the modulation circuit of the present invention, a low frequency component having a period of 92 words is suppressed, and the modulation output has a spectrum in which the low frequency component is suppressed as compared with a simple NRZI modulation. As described above, according to the present invention, the NRZ
By utilizing the characteristics of I-modulation, the circuit scale of the conventional modulation circuit can be halved, the power consumption can be greatly reduced, and a low frequency component suppressed DC-free digital modulation circuit can be constructed. Can improve data detection accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a modulation circuit according to the present invention. FIG. 2 is a block diagram of a DSV code generation circuit according to the present invention. FIG. 3 is a waveform diagram of the DSV code generation circuit of the present invention. FIG. 4 is a diagram illustrating a part of input / output signals of a convolution circuit; FIG. 5 is a diagram illustrating a part of input / output signals of the NRZI modulation circuit and DSV values thereof. FIG. 6 is a diagram showing a frequency spectrum of the modulation circuit of the present invention. FIG. 7 is a diagram schematically showing a magneto-optical disk recording / reproducing apparatus using the modulation circuit of the present invention. FIG. 8 is a circuit block diagram of a conventional modulation circuit. FIG. 9 is a diagram illustrating a function of the NRZI modulation circuit. [Description of Signs] 1, 1a to 1p: convolution circuit, 2, 2a to
2p: modulation memory, 3: switch, 4, 6a-6p ... N
RZI modulation circuit, 5... DSV code generation circuit, 7a to 7p
... DSV calculation circuit, 8a-8p ... DSV comparator,
9a to 9p ... DSV memory + address generation circuit, 10 ...
selector.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/14 G11B 20/14 341 H03M 13/23

Claims (1)

(57) [Claims 1] Convolution means for performing convolution by adding a predetermined initial value to each recording data composed of digital data of a fixed length, and output data of the convolution means , A plurality of convolution values, and a plurality of convolution values, a plurality of outputs of the conversion means, NRZI modulation of a plurality of outputs, a plurality of calculation means for calculating a DSV for each predetermined unit, a plurality of calculation means DS by each means
A plurality of maximum value calculating means for obtaining the maximum value of V; a selecting means for selecting a minimum value among the plurality of DSV maximum values; and a selecting means selected from the output data of the convolution means. Inverting the data of the same part as the convolution value obtained by inverting the partial data input to the calculating means that has calculated the minimum DSV,
Means for performing I modulation.