JP2002056628A - Reproducing device and method, clock generating device and computer readable storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly obtain a clock synchronized with input data. SOLUTION: This reproducing device is provided with a reproducing means for reproducing a digital signal, a phase difference detecting means for detecting the phase difference between the digital signal and the clock, a differentiating means for differentiating the output of the phase difference detecting means, a limiting means for limiting the output of the differentiating means, an integrating means for integrating the output of the limiting means, and an oscillating means for generating the clock in accordance with the output of the integrating means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, a reproducing method, a clock generating apparatus, and a computer-readable storage medium, and more particularly to a clock generating operation synchronized with reproduced data and input data.

[0002]

2. Description of the Related Art As this kind of apparatus, a digital VTR for digitizing a video signal supplied from the outside and recording / reproducing it on a magnetic tape, and a magneto-optical disk on which a digital video signal and a digital audio signal are recorded are used. Disc players for reproducing digital signals are known.

In this type of apparatus, in order to detect original digital data from a reproduced signal, it is necessary to obtain a clock phase-synchronized with the reproduced data. A PLL circuit is used as a means for extracting a clock from a reproduced data string.

[0004]

SUMMARY OF THE INVENTION In a digital VTR,
The frequency of the signal recorded on the tape may be unstable depending on the state of the apparatus at the time of recording. In a PLL circuit used for generating a clock, a wider capture range can cope with such a large frequency fluctuation. However, the signal reproduced from the tape is S
If / N is poor and the capture range of the PLL circuit is widened, the stability of the circuit will be poor and the capture range cannot be unnecessarily widened.

Therefore, it has been difficult for the conventional PLL circuit to follow a wide frequency variation while maintaining the stability of the circuit.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to quickly obtain a clock synchronized with input data.

[0008]

In order to solve the above-mentioned problems and achieve the object, the present invention provides a reproducing means for reproducing a digital signal and a phase difference detecting means for detecting a phase difference between the digital signal and a clock. A differentiating means for differentiating an output of the phase difference detecting means; a limiting means for limiting an output of the differentiating means; an integrating means for integrating an output of the limiting means; and the clock according to an output of the integrating means. And an oscillating means for generating

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a digital VTR to which the present invention is applied.
FIG. 3 is a block diagram showing a configuration of a reproduction system of FIG.

In FIG. 1, a recording signal is reproduced from a magnetic tape 101 by a reproducing circuit 103 including a magnetic head, a reproducing amplifier and the like, and is output to an equalizer 105. The equalizer 105 performs integral equalization processing on the reproduced signal,
Output to the D converter 107.

The A / D converter 107 samples the reproduced signal output from the equalizer 105 in accordance with the clock output from the VCO 129, and converts it into a digital signal of one sample and a plurality of bits (5 bits in this embodiment). The reproduced data converted into a digital signal is output to a PR processing circuit 11.
1 and output to the phase difference detection circuit 119.

The PR processing circuit 11 described below
1, data detection circuit 113, error correction circuit 115, decoding circuit 117, phase difference detection circuit 119, integration circuit 12
1. The differentiation processing circuit 123, the adder 127, and the D / A converter 129 are all configured by digital circuits, and are configured as the same integrated circuit 109. Each circuit of these integrated circuits 109 operates according to the clock from the VCO 129.

The PR processing circuit 111 includes an A / D converter 107
This is a circuit for giving the characteristics of the well-known partial response class 4 to the reproduced data from, and comprises a delay circuit for delaying data by two samples and a subtractor. That is, the difference between the input data delayed by two samples and the input data is obtained, and the reproduction data integrated and equalized by the equalizer 105 is PR (1, 0,
-1) Give characteristics. The eye pattern of the reproduced data having the PR (1, 0, -1) characteristic is 3 as shown in FIG.
Value. Next, the PR (1, 0, -1) signal is output to the data detection circuit 113. The data detection circuit 113 detects a digital signal of 1 bit per sample from input data of a plurality of bits per sample using a known Viterbi algorithm.

The combination of the PR (1, 0, -1) method and Viterbi decoding is based on digital VT using high-density magnetic recording.
R, etc., and the poor low-frequency characteristics of the magnetic recording system (S
/ N, waveform distortion, etc.) can be avoided and transmission errors can be kept to a minimum. The reproduced data detected by the data detection circuit 113 is output to the error correction circuit 115. The error correction circuit 115 corrects an error in the reproduced data generated on the transmission path using the parity data added at the time of recording, and outputs the error to the decoding circuit 117. The decoding circuit 117 is the error correction circuit 1
Compression applied to the reproduced data from
Decompression / decoding processing corresponding to the encoding processing is performed and output.

Next, the phase difference detection circuit 119 will be described. FIG. 2 is a diagram showing the configuration of the phase difference detection circuit 119.

In FIG. 2, the digital signal of one sample and a plurality of bits output from the A / D converter 107 is output to the register 205, and the most significant bit is the signal a.
Is output to the decoder 203. The multi-bit output of the register 207 is output to the register 207,
Are sequentially output to the register 209, and the output of the register 209 is sequentially output to the register 211.
The most significant bits of the outputs of 7, 209 and 211 are output to the decoder 203 as signals b, c, d and e, respectively. The decoder 203 outputs these signals a, b, c, d, e
Is subjected to a predetermined logical operation to generate each control signal as described later.

The outputs of the registers 205 and 209 are output to a subtracter 213, and the value of the register 207 is subtracted from the value of the register 205. The result of this subtraction is P
It has R (1, 0, -1) characteristics. The result of the subtraction is output to the terminal 0 of the switch 217 and the sign inversion circuit 21.
5 is output. The sign inversion circuit 215 inverts the sign of the input value and outputs the result to the other terminal 1 of the switch 217. The switch 217 is connected to the decoder 20.
3 is switched by a control signal s. When s = 0, the output of the subtractor 213 is selected. When s = 1, the result of the sign inversion of the output value of the subtractor 213 by the sign inversion circuit 215 is selected. Is done.

The output of the switch 217 is output to the register 221 via one terminal 0 of the switch 219. The output of the register 221 is supplied to the other terminal 1 of the switch 219. The switch 219 is connected to the decoder 203.
From the switch 217 when h = 0, and the register 221 when h = 1.
Select the value of and keep that value. This register 221
Is output to the loop filter 121 and the differentiation processing circuit 123 via the output terminal 223 as a phase detection signal.

FIG. 4 shows a truth table of the operation logic of the decoder 203.

Each of e, d, c, b, and a is a register 2
11, 209, 207, 205 and the most significant bit of the output of the input terminal 201.
17 and 219 are control signals.

Next, how to select the signals s and h will be described. FIG. 3 shows an eye pattern of a PR (1, 0, -1) signal. This eye pattern takes three values at the data detection point. Looking at the zero cross point of this eye pattern, it can be seen that the signal passing through the zero cross point has a slope proportional to the phase difference between the data and the detection point. However, this slope has both positive and negative values. By performing a predetermined logical operation so that the signal s determines whether the slope is positive or negative and the signal h is a zero cross point, the terminal 2
The phase difference detection output from 23 has a value proportional to the phase difference between the data and the detection point.

Next, the operation principle of the circuit of FIG. 2 will be described with reference to FIG. In FIG. 5A, a, b, c, d, e
A vertical line with a mark indicates a sampling point of the A / D converter 107, and a black circle indicates an output value of the A / D converter 107. A solid line indicates an analog waveform input to the input terminal 201. Here, a case where an analog waveform corresponding to 10001 is input as binary data is illustrated. FIG.
(A) shows the case where the phase of the reproduced data is earlier than the phase of the sampling clock of the A / D converter 107.
In the figure, since the sampling result at the sampling point b is larger than the sampling result at the sampling point d,
The output result of the subtractor 213 is a positive number.

According to the truth table shown in FIG. 4, when the pattern of the input data is 10001, s = 0,
Outputs h = 0. As a result, the value of the register 221 is updated, and a positive number corresponding to the phase shift is output to the output terminal 223. Here, a positive sign indicates that the phase of the reproduced data is ahead of the sampling clock.

A case where the phase of the reproduced data is behind the phase of the sampling clock of the A / D converter 107 will be described with reference to FIG. In FIG. 5B, since the sampling result at the sampling point d is larger than the sampling result at the sampling point b, the output of the subtracter 213 is a negative number.

The decoder 203 outputs s = 0 and h = 0 according to the truth table of FIG. 4 as in the case of FIG. 5A. As a result, the value of the register 221 is updated, and a negative number corresponding to the phase shift is output to the output terminal 223. A negative sign indicates that the phase is behind the sampling phase of the A / D converter 503.

As described above, the decoder 203 uses the MSB data of the five points a, b, c, d and e obtained by sampling the analog waveform of the reproduced signal and the difference value between the points b and d. By detecting each pattern shown in FIG. 4 and controlling each of the switches 217 and 219 according to this truth table, it is possible to detect the phase difference between the reproduced data and the clock at the sampling point extremely easily and with high accuracy. it can.

The phase difference signal output from the phase difference detection circuit 119 is output to the loop filter 121 and the differentiation processing circuit 123.

FIG. 6 is a diagram showing the configuration of the loop filter 121.

In FIG. 6, a phase difference signal from a phase difference detection circuit 119 is input to an input terminal 301, and an adder 30
3 and output to the adder 305. The adder 303, the limiter 307, and the register 309 constitute an integrator. That is, the output of the adder 303 is output to the register 309 via the limiter 307. The register 309 latches the output of the limiter 307 and outputs it to the adder 303.

Then, the integration result from the limiter 307 is multiplied by an appropriate coefficient in a coefficient unit 311 and output to an adder 305. The adder 305 adds the integration result from the coefficient unit 311 and the phase difference signal from the input terminal 301, and outputs the result from the output terminal 313. As described above, the loop filter 121 filters the phase difference detection output and outputs the result to the adder 125.

Next, the differential processing circuit 123 will be described.

The differential processing circuit 123 is a phase difference detecting circuit 1
19, a loop filter 121, a D / A converter 127, and a circuit serving to draw in when the PLL comprising the VCO 129 is not phase locked. FIG. 7 is a diagram showing the configuration of the differentiation processing circuit 123.

In FIG. 7, an input terminal 401 receives the phase difference signal from the phase difference detection circuit 119 and
3 and output to the subtractor 405. The register 403 delays the input phase difference signal by four clock periods, and outputs the delayed signal to the subtracter 405. The subtractor 705 uses this register 403
, And a signal from the input terminal 401, and outputs the difference to the limiter 407.

The limiter 407 limits the output data from the subtractor 405 to a predetermined level and outputs the data to the adder 409. The output of the adder 409 is limited by the limiter 411 and output to the register 413. Register 41
Reference numeral 3 latches the output of the limiter 411 in accordance with the input clock, and outputs it to the coefficient unit 415 and the adder 709. The adder 409, the limiter 411, and the register 413 form an integrator. The limiter 411 limits the integration result so as not to exceed a predetermined level. Register 413
The level of the integration result output from the output terminal 419 is adjusted by the coefficient unit 417 and output from the output terminal 419.

The output of the loop filter 121 and the output of the differentiation processing circuit 123 are added by an adder 125, and D / A
Output to converter 127. The D / A converter 127 converts the digital data output from the adder 125 into an analog signal, and outputs the analog signal to the VCO 129. VCO 129 is D
A / D converter 127 generates a clock having a frequency according to the output signal level from A / D converter 107 and circuit 10.
9 is output.

Next, the operation of the differential processing circuit 123 will be described.

FIG. 8A shows the state of the output signal of the phase difference detection circuit 119 when the PLL is off. Since the PLL is off, a beat appears at the frequency component of the difference between the clock frequency of the VCO 129 and the frequency of the reproduction signal, and -1
A saw-tooth signal indicating a phase difference from 80 ° to + 180 ° is output.

This signal is delayed by four clock periods by the register 403, and the difference from the input signal is obtained, thereby detecting the slope of this waveform. The state of the output signal of the subtractor 405 is shown in FIG.

As shown in FIG. 8B, the value is constant at the slope portion of the sawtooth wave, and is a large negative value at the portion where the angle changes from + 180 ° to -180 °.

Next, in the limiter 407, this signal is limited up and down at a predetermined level around 0. Limiter 4
FIG. 8C shows the waveform of the output signal 07. FIG. 8 (c)
In FIG. 8B, a large negative value in FIG. 8B is limited at a predetermined level.

The output of the limiter 407 is added to the adder 4
09, the limiter 411 and the register 413 perform integration. FIG. 8 shows a state of the integration result stored in the register 413.
(D).

As is apparent from the figure, since the output of the subtractor 405 is limited by the limiter 407, the integration result is 0.
Instead of returning to, the value increases in the positive direction. The level of this signal is adjusted by a coefficient unit 415 and the adder 12
By feeding back to VCO 129 via 5
It is possible to guide the output clock frequency of the VCO to a range where the PLL can be pulled in from a state where the PLL is disconnected.

As described above, according to the present embodiment, the phase difference detection signal is differentiated, the output obtained by subjecting this differentiation result to the limiter processing is integrated, and the result is added to the output of the loop filter.
Feedback to O. Therefore, even when the PLL is not in phase lock, the output of the VCO is quickly switched to the PL.
L can be drawn into the lock range.

In this embodiment, the output of the differential processing circuit 123 is output to the adder 125 as it is and fed back to the VCO.
5 to control the output timing to the adder 125 based on the output of the differential processing circuit 123, or to greatly change the output level of the differential processing circuit 123 to the adder 125. It is also possible to output. In this case, since the microcomputer performs other processing, the frequency of processing the output signal of the differential processing circuit 123 is about several times in one track period.

In the above embodiment, the case where the present invention is applied to a digital VTR has been described.
In addition to the above, the present invention is applicable to a device that generates a clock phase-synchronized with a reproduced digital signal, and has the same effect.

In the above embodiment, PR (1,
Although a pattern corresponding to a zero crossing point in a digital signal having 0, -1) characteristics is detected, the present invention is also applied to, for example, a case where a clock is extracted from PR (1) data. It is possible.

In the above-described embodiment, the digital integrated circuit 109 has been described with the hardware configuration. However, each of these circuit configurations can be realized by software processing by a microcomputer.

That is, FIG. 1 or FIGS. 2, 6, and 7
The present invention also includes a computer-readable storage medium storing a program for realizing each function of each circuit shown in FIG.

[0050]

As described above, according to the present invention,
Even when the phase difference between the reproduction signal and the clock is largely different, a clock phase-synchronized with the reproduction signal can be quickly obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a reproduction system of a digital VTR to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a phase difference detection circuit in the device of FIG.

FIG. 3 is a diagram showing an eye pattern of data handled by the apparatus of FIG. 1;

FIG. 4 is a truth table for explaining the operation of the circuit of FIG. 2;

FIG. 5 is a diagram for explaining the operation of the circuit of FIG. 2;

FIG. 6 is a diagram illustrating a configuration of a loop filter of the device of FIG. 1;

FIG. 7 is a diagram illustrating a configuration of a differentiation processing circuit of the device in FIG. 1;

FIG. 8 is a diagram for explaining the operation of the circuit of FIG. 7;

Continued on front page F-term (reference) 5D044 AB05 AB07 BC01 CC03 GM12 GM14 JJ02 5J106 AA04 CC01 CC21 CC41 DD03 DD04 DD13 DD35 DD36 JJ04 KK03

Claims (12)

[Claims] A reproducing means for reproducing a digital signal; a phase difference detecting means for detecting a phase difference between the digital signal and a clock; a differentiating means for differentiating an output of the phase difference detecting means; A reproducing apparatus comprising: limiting means for limiting an output; integrating means for integrating the output of the limiting means; and oscillating means for generating the clock in accordance with the output of the integrating means. 2. The reproducing apparatus according to claim 1, wherein said reproducing means has a converting means for converting an analog signal reproduced from a recording medium into a digital signal according to said clock. 3. The apparatus according to claim 2, wherein the phase difference detecting means includes pattern detecting means for detecting a specific pattern in the reproduced signal, and latch means for latching the reproduced digital signal in accordance with an output of the pattern detecting means. The playback device according to claim 1, wherein 4. The reproduction digital signal is a digital signal of a plurality of bits per sample, and the pattern detection means uses N-bit digital data obtained by performing binary judgment on the digital signal of N consecutive samples. 4. The reproducing apparatus according to claim 3, wherein the specific pattern is detected. 5. The control signal generating means includes a calculating means for extracting a part of the reproduced digital signal and performing a calculating process, and the latch means latches a calculation result of the calculating means. The playback device according to claim 3, wherein 6. The reproduction digital signal according to claim 1, wherein the reproduction digital signal is a digital signal of a plurality of bits per sample, and further comprising data detection means for detecting digital data of 1 bit per sample from the reproduction digital signal. Playback device. 7. A loop filter for filtering an output of the phase difference detecting means, and an adding means for adding an output of the loop filter and an output of the integrating means, wherein the oscillating means outputs the output of the adding means. 2. The reproducing apparatus according to claim 1, wherein a clock having a frequency corresponding to the frequency is generated. 8. A reproducing apparatus according to claim 1, wherein said limit means limits the output of said differentiating means at a predetermined level in positive and negative directions centering on a zero level. 9. A phase detector for detecting a phase difference between a reproduced signal and a clock, a loop filter for filtering an output of the phase detector, and an oscillator for generating a clock having a frequency corresponding to an input control signal. An apparatus configured to differentiate an output of the phase detector by a differentiating circuit, limit the differential result of the differentiating circuit at a predetermined level by a limiter, and integrate an output of the limiter by an integrating circuit. A clock generator, wherein a result is added to an output of the loop filter and input to the oscillator as the control signal. 10. The clock generator according to claim 1, wherein said phase detector, said loop filter, said differentiating circuit, said limiter and said integrating circuit are formed on the same integrated circuit. 11. A method for generating a clock phase-synchronized with a reproduced digital signal, comprising: detecting a phase difference between the reproduced digital signal and the clock; and differentiating a detection output of the phase difference. And a process for limiting the differential output, a process for integrating the output of the limit process, and a process for generating the clock in accordance with the result of the integration process. 12. A computer-readable storage medium storing a program capable of realizing the method according to claim 11.