JP2006165236A - 半導体装置の製造方法及び三次元半導体装置 - Google Patents
半導体装置の製造方法及び三次元半導体装置 Download PDFInfo
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- JP2006165236A JP2006165236A JP2004353873A JP2004353873A JP2006165236A JP 2006165236 A JP2006165236 A JP 2006165236A JP 2004353873 A JP2004353873 A JP 2004353873A JP 2004353873 A JP2004353873 A JP 2004353873A JP 2006165236 A JP2006165236 A JP 2006165236A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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Abstract
【解決手段】 多層プリント配線板10の複数箇所にチップ部品11を接続する工程と、多層プリント配線板10の複数箇所の取り付け部12、13に接続用フィルムを貼り付ける工程と、複数箇所の取り付け部13に第1半導体素子15aを仮置きした状態で、複数箇所にキャビティ部が形成された両面印刷板17を取り付け部12に仮貼り付けする工程と、第1半導体素子15aおよび両面印刷板17を一括して加圧・加熱して多層プリント配線板10に接続する工程と、第1半導体素子15aの上に第2半導体素子15bマウントして接続端子部とワイヤボンディング接続した後に、キャビティ部を樹脂封止する。最後に半導体装置毎に接続用バンプを形成し、個片化して半導体装置を製造する。
【選択図】 図1
Description
11‥チップ部品(受動部品)
13‥半導体素子の取り付け部
14‥両面配線板の取り付け部
15(15a、15b)‥半導体素子
16‥キャビティ部
17‥両面配線板
18‥エポキシ樹脂
19‥接続部
20、50‥はんだバンプ
Claims (4)
- 多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、
前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、
前記多層プリント配線板の前記複数箇所の半導体素子取り付け部および両面印刷板取り付け部に接続用フィルムを貼り付ける工程と、
前記半導体素子取り付け部に第1半導体素子を仮置きし、前記第1半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面印刷板を前記両面印刷板取り付け部に仮貼り付けする工程と、
前記第1半導体素子および前記両面印刷板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、
前記第1半導体素子の上に第2半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、
前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項1の製造方法によって製造された半導体装置が複数積層されて構成される三次元半導体装置。
- 多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、
前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、
前記多層プリント配線板の前記複数箇所内の両面印刷板取り付け部に接続用フィルムを貼り付ける工程と、
前記複数箇所内の半導体素子取り付け部に金属製パンプ付きの第1半導体素子を仮置きし、前記第1半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面印刷板を前記両面印刷板取り付け部に仮貼り付けする工程と、
前記第1半導体素子および前記両面印刷板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、
前記第1半導体素子の上に第2半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、
前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項3の製造方法によって製造された半導体装置が複数積層されて構成される三次元半導体装置。
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JP2004353873A JP4433399B2 (ja) | 2004-12-07 | 2004-12-07 | 半導体装置の製造方法及び三次元半導体装置 |
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JP2004353873A JP4433399B2 (ja) | 2004-12-07 | 2004-12-07 | 半導体装置の製造方法及び三次元半導体装置 |
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JP2006165236A true JP2006165236A (ja) | 2006-06-22 |
JP4433399B2 JP4433399B2 (ja) | 2010-03-17 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009152535A (ja) * | 2007-12-18 | 2009-07-09 | Samsung Electro Mech Co Ltd | 半導体パッケージの製造方法及びそれを用いた半導体プラスチックパッケージ |
JP2010219492A (ja) * | 2009-02-17 | 2010-09-30 | Dainippon Printing Co Ltd | 電子モジュール、電子モジュールの製造方法 |
KR20150112769A (ko) * | 2014-03-27 | 2015-10-07 | 인텔 아이피 코포레이션 | 적층된 전자 컴포넌트를 포함하는 전자 어셈블리 |
-
2004
- 2004-12-07 JP JP2004353873A patent/JP4433399B2/ja not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009152535A (ja) * | 2007-12-18 | 2009-07-09 | Samsung Electro Mech Co Ltd | 半導体パッケージの製造方法及びそれを用いた半導体プラスチックパッケージ |
US8030752B2 (en) | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
US8174128B2 (en) | 2007-12-18 | 2012-05-08 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package having a first board, second boards electrically connected to both sides of the first board, and at least one component connected to the first board by a flip chip method |
JP2010219492A (ja) * | 2009-02-17 | 2010-09-30 | Dainippon Printing Co Ltd | 電子モジュール、電子モジュールの製造方法 |
JP2015026839A (ja) * | 2009-02-17 | 2015-02-05 | 大日本印刷株式会社 | 電子モジュール、電子モジュールの製造方法 |
KR20150112769A (ko) * | 2014-03-27 | 2015-10-07 | 인텔 아이피 코포레이션 | 적층된 전자 컴포넌트를 포함하는 전자 어셈블리 |
JP2015192143A (ja) * | 2014-03-27 | 2015-11-02 | インテル アイピー コーポレイション | スタックされた電子コンポーネントを含む電子アセンブリ |
KR101723003B1 (ko) * | 2014-03-27 | 2017-04-04 | 인텔 아이피 코포레이션 | 적층된 전자 컴포넌트를 포함하는 전자 어셈블리 |
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