JP2006100651A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
【解決手段】 個片モールディングを行い、その後のダイシングによる個片化の際に、樹脂薄膜部2aと給電線5dとをいっしょに切断することにより、樹脂薄膜部2aを形成する封止用樹脂がブレード13に対してドレス作用を引き起し、引きずられて絡みつこうとする銅バリを前記封止用樹脂が切断してブレード13への前記銅バリの付着を抑制することができ、その結果、配線基板の切断面への前記銅バリの発生を防止してBGA(半導体装置)の信頼性の向上を図る。
【選択図】 図17
Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の構造の一例を示す側面図、図3は図1に示す半導体装置の構造の一例を示す断面図、図4は図1に示す半導体装置の構造の一例を示す裏面図、図5は図1に示す半導体装置の組み立ての一例を示す製造プロセスフロー図、図6は図1に示す半導体装置の組み立てに用いられる配線基板の構造の一例を示す平面図、図7は図6に示す配線基板の裏面の構造の一例を示す裏面図、図8は図1に示す半導体装置の組み立ての樹脂封止工程で用いられる樹脂成形金型の上型の構造の一例を示す平面図、図9は図8に示すA−A線に沿って切断した樹脂成形金型の構造の一例を示す断面図、図10は図8に示すB−B線に沿って切断した樹脂成形金型の構造の一例を示す断面図、図11は図1に示す半導体装置の組み立ての樹脂封止工程における金型クランプ前の構造の一例を示す部分断面図、図12は図1に示す半導体装置の組み立ての樹脂封止工程における樹脂充填時の構造の一例を示す部分断面図、図13は図1に示す半導体装置の組み立ての樹脂封止工程における型開き時の構造の一例を示す部分断面図、図14は図1に示す半導体装置の組み立ての樹脂封止後の基板の構造の一例を示す部分平面図、図15は図14に示す基板の構造を示す部分裏面図、図16は図1に示す半導体装置の組み立ての個片化工程におけるダイシング時の構造の一例を示す断面図、図17は図16に示すC部の構造を示す拡大部分断面図、図18は本発明の実施の形態の変形例の半導体装置の組み立ての個片化工程におけるダイシング時の構造を示す拡大部分断面図、図19は本発明の実施の形態の変形例の半導体装置の構造を示す断面図である。
1a 主面
1b 裏面
1c パッド(電極)
2 封止体
2a 樹脂薄膜部(樹脂切断部)
2b 表面
2c 第2樹脂切断部(樹脂切断部)
2d 裏面
3 ワイヤ
4 BGA(半導体装置)
5 パッケージ基板(配線基板)
5a 主面
5b 裏面
5c 主配線(金属配線)
5d 給電線(金属配線)
5e ボンディング電極(電極)
5f インデックス
5g ソルダレジスト
5h ランド
5i ゲート用メタル部
6 ダイボンド剤
7 ヒートスプレッダ
8 接着剤
9 多数個取り基板(配線基板)
9a 主面
9b 裏面
9c デバイス領域(装置形成領域)
9d スリット
9e 基板長手方向
9f 位置決め孔
9g ダイシングライン
9h チップ搭載エリア
10 半田ボール
11 封止用樹脂
12 樹脂成形金型
12a 上型
12b キャビティ
12c ゲート
12d 凹部
12e 下型
12f 金型面
12g キャビティブロック
12h カルブロック
12i カル
12j ランナ
13 ブレード
14 ダイシング用治具
15 押さえゴム
16 QFN(半導体装置)
17 タブ
18 銅リード(導体リード)
Claims (15)
- (a)主面と、前記主面に対向する裏面と、前記主面上に形成された複数の装置形成領域と、複数の配線を有する配線基板を準備する工程と、
(b)主面と、前記主面に対向する裏面と、前記主面上に形成された複数の電極を有する半導体チップを準備する工程と、
(c)前記配線基板の前記複数の装置形成領域上にそれぞれ前記半導体チップを搭載する工程と、
(d)前記複数の配線の一部と前記半導体チップの複数の電極とを電気的に接続する工程と、
(e)前記配線基板の主面および前記半導体チップを樹脂封止する第1封止体と、前記装置形成領域の外側に配置される第2封止体とを一体に形成する工程と、
(f)前記第2封止体と前記複数の配線とをダイシングによって同時に切断して個片化する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記(e)工程では、樹脂成形金型の1つのキャビティで1つの前記装置形成領域を覆った状態で封止することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記第2封止体の厚さは、前記第1封止体の厚さよりも薄いことを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記第2封止体の厚さは、前記第1封止体の厚さと同じであることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(f)工程では、回転するブレードを使用して切断することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記複数の配線は導体リードからなることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記複数の配線は金属配線からなることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記複数の配線は銅配線からなることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記複数の配線の一部には電解メッキを施されていることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(e)工程の後、前記配線基板の裏面に複数の外部端子を形成することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(d)工程では、前記複数の配線の一部と前記半導体チップの複数の電極とをそれぞれ複数のワイヤを介して電気的に接続することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記配線基板の厚さと交差する平面形状は長方形であり、前記複数の装置形成領域は前記配線基板の長手方向に沿って並んで形成されていることを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記配線基板の長手方向に沿って、かつ、前記装置形成領域の両側にスリットが形成されていることを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記第2封止体は前記配線基板の短手方向に沿って、かつ、前記装置形成領域の両側に形成されることを特徴とする半導体装置の製造方法。
- (a)複数の装置形成領域が基板長手方向に沿って並んで形成されており、各装置形成領域それぞれの前記基板長手方向の両側にスリットが形成され、複数の金属配線および電極を有する配線基板を準備する工程と、
(b)前記配線基板と半導体チップとを接続する工程と、
(c)前記配線基板の電極と前記半導体チップの電極とを電気的に接続する工程と、
(d)樹脂成形金型の1つのキャビティで1つの前記装置形成領域を覆った状態で前記半導体チップを封止用樹脂によって封止して、第1封止体とその外側に配置される第2封止体とを形成する工程と、
(e)前記装置形成領域に沿って、かつ前記スリットと直角を成す方向に前記第2封止体と前記金属配線とをダイシングによっていっしょに切断して個片化する工程とを有することを特徴とする半導体装置の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007114338A1 (ja) | 2006-03-31 | 2007-10-11 | Takeda Pharmaceutical Company Limited | 酸分泌抑制薬 |
JP2015026811A (ja) * | 2013-06-21 | 2015-02-05 | 株式会社デンソー | 電子装置およびその製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2007114338A1 (ja) | 2006-03-31 | 2007-10-11 | Takeda Pharmaceutical Company Limited | 酸分泌抑制薬 |
JP2015026811A (ja) * | 2013-06-21 | 2015-02-05 | 株式会社デンソー | 電子装置およびその製造方法 |
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