JP2006080574A - 電子部品収納用パッケージ及びそれを用いた半導体装置 - Google Patents
電子部品収納用パッケージ及びそれを用いた半導体装置 Download PDFInfo
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- JP2006080574A JP2006080574A JP2005350622A JP2005350622A JP2006080574A JP 2006080574 A JP2006080574 A JP 2006080574A JP 2005350622 A JP2005350622 A JP 2005350622A JP 2005350622 A JP2005350622 A JP 2005350622A JP 2006080574 A JP2006080574 A JP 2006080574A
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- wiring layer
- electronic component
- ground wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】信号配線層2とそれを上下から挟む複数のグランド配線層4・5と電子部品6の搭載部とを有する基体1と、電子部品6を内部に収容するための凹部を有する蓋体7とから成る電子部品収納用パッケージであって、複数のグランド配線層4・5は、
電子部品6のグランドが電気的に接続されるとともに信号配線層2を上下から挟む第1のグランド配線層4と、第1のグランド配線層4とは電気的に独立した別個の外部端子を介して接地されるとともに信号配線層2およびその上下に位置する第1のグランド配線層4をさらに上下から挟むように配置された第2のグランド配線層5とから成り、かつ蓋体7の導電性の内壁である金属層8を第2のグランド配線層5に電気的に接続させている。
【選択図】図1
Description
2・・・・・・信号配線層
3・・・・・・電源配線層
4・・・・・・第1のグランド配線層
5・・・・・・第2のグランド配線層
6・・・・・・半導体素子(電子部品)
7・・・・・・蓋体
8・・・・・・金属層(導電性の内壁)
Claims (2)
- 内部に信号配線層および該信号配線層を上下から挟む複数のグランド配線層を有するとともに上面に電子部品を搭載するための搭載部を有する基体と、前記搭載部に搭載される前記電子部品を内部に収容するための凹部を有する蓋体とから成り、前記基体と前記蓋体とを封止材を介して接合することによって内部に前記電子部品を気密に収容するようになした電子部品収納用パッケージであって、
前記複数のグランド配線層は、前記電子部品のグランドが電気的に接続されるとともに前記信号配線層を上下から挟む第1のグランド配線層と、該第1のグランド配線層とは電気的に独立した別個の外部端子を介して接地されるとともに前記信号配線層およびその上下に位置する前記第1のグランド配線層をさらに上下から挟むように配置された第2のグランド配線層とを含み、さらに前記蓋体の内壁を導電性となして前記第2のグランド配線層に電気的に接続させたことを特徴とする電子部品収納用パッケージ。 - 請求項1記載の電子部品収納用パッケージの前記搭載部に、前記電子部品として半導体素子を搭載するとともに、該半導体素子が前記凹部内に収容されるようにして前記蓋体を前記基体に接合してなる半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005350622A JP4164089B2 (ja) | 2005-12-05 | 2005-12-05 | 電子部品収納用パッケージ及びそれを用いた半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005350622A JP4164089B2 (ja) | 2005-12-05 | 2005-12-05 | 電子部品収納用パッケージ及びそれを用いた半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35190698A Division JP3766556B2 (ja) | 1998-12-10 | 1998-12-10 | 電子部品収納用パッケージ及びそれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006080574A true JP2006080574A (ja) | 2006-03-23 |
JP4164089B2 JP4164089B2 (ja) | 2008-10-08 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005350622A Expired - Fee Related JP4164089B2 (ja) | 2005-12-05 | 2005-12-05 | 電子部品収納用パッケージ及びそれを用いた半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4164089B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009010149A (ja) * | 2007-06-28 | 2009-01-15 | Kyocera Corp | 接続端子及びこれを用いたパッケージ並びに電子装置 |
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2005
- 2005-12-05 JP JP2005350622A patent/JP4164089B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009010149A (ja) * | 2007-06-28 | 2009-01-15 | Kyocera Corp | 接続端子及びこれを用いたパッケージ並びに電子装置 |
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JP4164089B2 (ja) | 2008-10-08 |
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