JP2005521288A5 - - Google Patents

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Publication number
JP2005521288A5
JP2005521288A5 JP2003577426A JP2003577426A JP2005521288A5 JP 2005521288 A5 JP2005521288 A5 JP 2005521288A5 JP 2003577426 A JP2003577426 A JP 2003577426A JP 2003577426 A JP2003577426 A JP 2003577426A JP 2005521288 A5 JP2005521288 A5 JP 2005521288A5
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JP
Japan
Prior art keywords
signal
reconfigurable processing
processing device
output
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003577426A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005521288A (ja
JP4260026B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/IB2003/000967 external-priority patent/WO2003079550A2/en
Publication of JP2005521288A publication Critical patent/JP2005521288A/ja
Publication of JP2005521288A5 publication Critical patent/JP2005521288A5/ja
Application granted granted Critical
Publication of JP4260026B2 publication Critical patent/JP4260026B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003577426A 2002-03-18 2003-03-17 リコンフィギャラブル・ロジックにおける大型マルチプレクサの実現 Expired - Fee Related JP4260026B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076049 2002-03-18
PCT/IB2003/000967 WO2003079550A2 (en) 2002-03-18 2003-03-17 Implementation of wide multiplexers in reconfigurable logic

Publications (3)

Publication Number Publication Date
JP2005521288A JP2005521288A (ja) 2005-07-14
JP2005521288A5 true JP2005521288A5 (https=) 2006-05-11
JP4260026B2 JP4260026B2 (ja) 2009-04-30

Family

ID=27838094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003577426A Expired - Fee Related JP4260026B2 (ja) 2002-03-18 2003-03-17 リコンフィギャラブル・ロジックにおける大型マルチプレクサの実現

Country Status (8)

Country Link
US (1) US8082284B2 (https=)
EP (1) EP1488523B1 (https=)
JP (1) JP4260026B2 (https=)
CN (1) CN1295879C (https=)
AT (1) ATE458310T1 (https=)
AU (1) AU2003209576A1 (https=)
DE (1) DE60331296D1 (https=)
WO (1) WO2003079550A2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004045527B4 (de) 2003-10-08 2009-12-03 Siemens Ag Konfigurierbare Logikschaltungsanordnung
CN102147720B (zh) * 2011-03-18 2014-04-09 深圳市国微电子有限公司 用查找表实现多输入逻辑项之间的运算的装置及方法
US9450585B2 (en) * 2011-04-20 2016-09-20 Microchip Technology Incorporated Selecting four signals from sixteen inputs
US9425800B2 (en) * 2013-04-02 2016-08-23 Taiyo Yuden Co., Ltd. Reconfigurable logic device
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
JP6653126B2 (ja) * 2015-04-28 2020-02-26 太陽誘電株式会社 再構成可能な半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
JP3127654B2 (ja) * 1993-03-12 2001-01-29 株式会社デンソー 乗除算器
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5426379A (en) * 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
US5442306A (en) 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
JPH09181598A (ja) 1995-12-18 1997-07-11 At & T Corp フィールドプログラマブルゲートアレイ
US6154049A (en) * 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
DE69834942T2 (de) * 1997-12-17 2007-06-06 Panasonic Europe Ltd., Uxbridge Vorrichtung zum Multiplizieren
GB9727414D0 (en) * 1997-12-29 1998-02-25 Imperial College Logic circuit
JP3123977B2 (ja) * 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
US6118300A (en) 1998-11-24 2000-09-12 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables
JP3269526B2 (ja) 1999-02-09 2002-03-25 日本電気株式会社 プログラマブルロジックｌｓｉ
US6556042B1 (en) * 2002-02-20 2003-04-29 Xilinx, Inc. FPGA with improved structure for implementing large multiplexers
US6816562B2 (en) * 2003-01-07 2004-11-09 Mathstar, Inc. Silicon object array with unidirectional segmented bus architecture

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