JP2005347479A - Laminated electronic component - Google Patents

Laminated electronic component Download PDF

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JP2005347479A
JP2005347479A JP2004164667A JP2004164667A JP2005347479A JP 2005347479 A JP2005347479 A JP 2005347479A JP 2004164667 A JP2004164667 A JP 2004164667A JP 2004164667 A JP2004164667 A JP 2004164667A JP 2005347479 A JP2005347479 A JP 2005347479A
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cavity
chip component
shield electrode
electronic component
chip
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JP4506291B2 (en
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Kazuto Ogawa
和渡 小川
Hiroyuki Kawabata
博之 川端
Mitsuhide Katou
充英 加藤
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated electronic component 10 in which a chip component 20 is mounted on a multilayered substrate 11 wherein, when the chip component 20 is mounted on the bottom 13 of a cavity 12, four corners 22 of the chip component 20 are prevented from being cracked. <P>SOLUTION: The laminated electronic component 10 comprises: a multilayered substrate 11 having the cavity 12 on a main surface thereof; a shield electrode 14 formed so as to cover at least the chip component mounting region of the bottom 13 of the cavity 12; and the chip component 20 which is secured to the bottom 13 of the cavity 12 by using the shield electrode 14 as a die bond surface. A portion relevant to the four corners 22 of the chip component 20 housed in the cavity 12 is configured to be formed with a notch 18 in the shield electrode 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多層基板にチップ部品を搭載した積層型電子部品に関する。   The present invention relates to a multilayer electronic component in which a chip component is mounted on a multilayer substrate.

従来より、内部にコンデンサやコイルを形成した多層基板に、IC等のチップ部品を搭載した積層型電子部品が提案されている(例えば、特許文献1)。   Conventionally, a multilayer electronic component in which a chip component such as an IC is mounted on a multilayer substrate in which capacitors and coils are formed has been proposed (for example, Patent Document 1).

積層型電子部品は、多層基板の一方主面にキャビティを形成し、このキャビティ内にチップ部品を収納して構成されている。キャビティの底面には、シールド用の電極が形成されており、チップ部品はこの電極をダイボンド面としてキャビティ底面に固着されている。   A multilayer electronic component is configured by forming a cavity in one main surface of a multilayer substrate and housing a chip component in the cavity. An electrode for shielding is formed on the bottom surface of the cavity, and the chip component is fixed to the bottom surface of the cavity with this electrode as a die bond surface.

シールド電極は、多層基板内の回路と、チップ部品内の回路との電気的な結合を遮蔽するための電極であり、シールド効果を増すためにグランドに接続されていることが好ましい。   The shield electrode is an electrode for shielding electrical coupling between the circuit in the multilayer substrate and the circuit in the chip component, and is preferably connected to the ground in order to increase the shielding effect.

さらに、キャビティ内に露出した配線パターンと、チップ部品の電極とがワイヤボンディングによって電気的に接続されている。   Furthermore, the wiring pattern exposed in the cavity and the electrode of the chip component are electrically connected by wire bonding.

しかし、上記従来の構成では、キャビティ内に収納したチップ部品の四隅に欠けが生じているのがよく見受けられている。
特開2004−103608号
However, in the above-described conventional configuration, it is often seen that the chip parts housed in the cavity are chipped at the four corners.
JP 2004-103608 A

そこで、本発明においては、キャビティ内に収納するチップ部品の四隅に欠けが生じるのを防止できる積層型電子部品を提供することを解決すべき課題としている。   Therefore, in the present invention, it is an object to be solved to provide a multilayer electronic component that can prevent chipping at four corners of a chip component housed in a cavity.

本発明の積層型電子部品は、主面にキャビティを有した多層基板と、前記キャビティの底面の少なくともチップ部品搭載領域を覆うように形成されたシールド電極と、前記シールド電極をダイボンド面として前記キャビティの底面に固着したチップ部品とを備え、前記キャビティに収納した前記チップ部品の四隅に相当する部分、または外周に相当する部分において、前記シールド電極に切り欠きを形成したものである。   The multilayer electronic component according to the present invention includes a multilayer substrate having a cavity on a main surface, a shield electrode formed so as to cover at least a chip component mounting region on a bottom surface of the cavity, and the cavity using the shield electrode as a die bond surface. The shield electrode is cut out at a portion corresponding to the four corners of the chip component housed in the cavity or a portion corresponding to the outer periphery.

本発明者らが上記チップ部品の四隅の欠けについて鋭意検討したところ、従来の積層型電子部品において、キャビティの底面に形成されたシールド電極は、チップ部品からの輻射を効果的にシールドして十分なシールド性を確保するため、少なくともチップ部品搭載領域を覆って形成されている。   When the present inventors diligently examined the chipping at the four corners of the chip component, in the conventional multilayer electronic component, the shield electrode formed on the bottom surface of the cavity is sufficient to effectively shield the radiation from the chip component. In order to ensure a good shielding property, it is formed so as to cover at least the chip component mounting region.

しかし、シールド電極と多層基板との収縮率が異なる(シールド電極はセラミックに比べて収縮し難い)ため、キャビティの底面に凹凸が生じることがある。特に、キャビティの底面の中央部分が落ち込むように若干反った状態でチップ部品を搭載しようとすると、チップ部品の四隅が凹曲したシールド電極の表面に当接し、その衝撃によってチップ部品の脆い四隅が欠けてしまうことを見出し、これに基づいてさらに鋭意研究を重ねた結果、本発明を完成するに至った。   However, since the shrinkage rate of the shield electrode is different from that of the multilayer substrate (the shield electrode is less likely to shrink than ceramic), unevenness may occur on the bottom surface of the cavity. In particular, when trying to mount a chip component with the center part of the bottom of the cavity slightly bent so that it falls, the four corners of the chip component come into contact with the surface of the shielded shield electrode, and the impact causes the four corners of the chip component to be brittle. As a result of finding out that it is missing and further intensive studies based on this, the present invention has been completed.

本発明の積層型電子部品によると、キャビティに収納したチップ部品の四隅に相当する部分、または外周に相当する部分において、キャビティの底面に形成されたシールド電極に切り欠きを形成したので、シールド電極をダイボンド面としてキャビティの底面にチップ部品を固着した際、チップ部品の四隅がシールド電極の切り欠きに入り込み、シールド電極の表面は当接せず、チップ部品の四隅に欠けが生じるのを防止できる。さらに、チップ部品の外周に相当する部分においてシールド電極に切り欠きを形成した場合、チップ部品の四隅のみならず、外周縁の欠けも防止できる。   According to the multilayer electronic component of the present invention, the notch is formed in the shield electrode formed on the bottom surface of the cavity in the portion corresponding to the four corners of the chip component housed in the cavity or the portion corresponding to the outer periphery. When the chip part is fixed to the bottom surface of the cavity with the die bonding surface as the die bond surface, the four corners of the chip part enter the notch of the shield electrode, the surface of the shield electrode does not contact, and the chip part can be prevented from being chipped. . Furthermore, when the notch is formed in the shield electrode in the portion corresponding to the outer periphery of the chip component, not only the four corners of the chip component but also the outer peripheral chip can be prevented.

本発明の積層型電子部品によると、キャビティの底面にチップ部品を搭載する際に、チップ部品の四隅に欠けが生じるのを防止できる。   According to the multilayer electronic component of the present invention, chipping can be prevented from occurring at the four corners of the chip component when the chip component is mounted on the bottom surface of the cavity.

本発明の最良の実施形態を図1ないし図4に示す。   The best embodiment of the present invention is shown in FIGS.

図1は積層型電子部品の断面図、図2は積層型電子部品の部分拡大断面図、図3は積層型電子部品の部分拡大底面図、図4はチップ部品の実装時の部分拡大断面図である。   1 is a cross-sectional view of a multilayer electronic component, FIG. 2 is a partial enlarged cross-sectional view of the multilayer electronic component, FIG. 3 is a partial enlarged bottom view of the multilayer electronic component, and FIG. 4 is a partial enlarged cross-sectional view when the chip component is mounted. It is.

図1に示すように、積層型電子部品10は、セラミックの多層基板11の主面にキャビティ12を形成し、キャビティ12内にチップ部品20を収納する。キャビティ12の底面13には、ベアチップIC等のチップ部品20の搭載領域を覆うようにキャビティ12の底面13全体に渡ってシールド電極14が形成されており、チップ部品20はシールド電極14をダイボンド面としてキャビティ12の底面13に固着されている。さらに、チップ部品20は、ワイヤボンディングやフリップチップボンディング(バンプ接続)により、多層基板11の導電ランド(図示せず)と電気的に接続されている。また、チップ部品20をキャビティ12内に搭載した後、キャビティ12に電気絶縁性の封止樹脂を充填してもよい。   As shown in FIG. 1, the multilayer electronic component 10 has a cavity 12 formed in the main surface of a ceramic multilayer substrate 11, and a chip component 20 is accommodated in the cavity 12. A shield electrode 14 is formed on the bottom surface 13 of the cavity 12 over the entire bottom surface 13 of the cavity 12 so as to cover a mounting region of the chip component 20 such as a bare chip IC. The chip component 20 attaches the shield electrode 14 to the die bond surface. As fixed to the bottom surface 13 of the cavity 12. Further, the chip component 20 is electrically connected to a conductive land (not shown) of the multilayer substrate 11 by wire bonding or flip chip bonding (bump connection). Further, after the chip component 20 is mounted in the cavity 12, the cavity 12 may be filled with an electrically insulating sealing resin.

積層型電子部品10を実装基板15に実装する際には、キャビティ12が下になるように配置して、外部導体16を介して実装基板15に電気的に接続する。また、キャビティ12と反対側の上面には、コンデンサ,インダクタ,抵抗器,ダイオード,IC,メモリ,SAWフィルタ,水晶振動子等のチップ部品21が外部導体17を介して搭載される。さらに、搭載されたチップ部品21を保護する金属カバー(図示せず)を多層基板11に装着してもよい。   When the multilayer electronic component 10 is mounted on the mounting substrate 15, the multilayer electronic component 10 is disposed so that the cavity 12 faces downward, and is electrically connected to the mounting substrate 15 via the external conductor 16. A chip component 21 such as a capacitor, an inductor, a resistor, a diode, an IC, a memory, a SAW filter, or a crystal resonator is mounted on the upper surface opposite to the cavity 12 via an external conductor 17. Further, a metal cover (not shown) for protecting the mounted chip component 21 may be attached to the multilayer substrate 11.

シールド電極14は、キャビティ12に収納したチップ部品20の四隅22に相当する部分において、計4箇所の矩形状の切り欠き18を有している。これにより、図4に示すように、シールド電極14と多層基板11との収縮率の差によってシールド電極14が凹曲した状態でチップ部品20をキャビティ12に収納しようとした際、チップ部品20の四隅22がシールド電極14の切り欠き18に入り込んでキャビティ12の底面13に固着される。   The shield electrode 14 has a total of four rectangular cutouts 18 at portions corresponding to the four corners 22 of the chip component 20 housed in the cavity 12. Accordingly, as shown in FIG. 4, when the chip component 20 is stored in the cavity 12 in a state where the shield electrode 14 is bent due to a difference in shrinkage between the shield electrode 14 and the multilayer substrate 11, The four corners 22 enter the notch 18 of the shield electrode 14 and are fixed to the bottom surface 13 of the cavity 12.

このように構成された積層型電子部品10によると、キャビティ12に収納したチップ部品20の四隅22に相当する部分において、キャビティ12の底面13に形成されたシールド電極14に切り欠き18を形成したので、シールド電極14をダイボンド面としてキャビティ12の底面13にチップ部品20を固着した際、チップ部品20の四隅22がシールド電極14の切り欠き18に入り込んでシールド電極14の表面に当接せず、チップ部品20の四隅22に欠けが生じるのを防止できる。   According to the multilayer electronic component 10 configured as described above, the notch 18 is formed in the shield electrode 14 formed on the bottom surface 13 of the cavity 12 in the portion corresponding to the four corners 22 of the chip component 20 housed in the cavity 12. Therefore, when the chip component 20 is fixed to the bottom surface 13 of the cavity 12 using the shield electrode 14 as a die bond surface, the four corners 22 of the chip component 20 enter the notch 18 of the shield electrode 14 and do not contact the surface of the shield electrode 14. It is possible to prevent chipping at the four corners 22 of the chip component 20.

なお、チップ部品20の四隅22に相当する部分において、シールド電極14に形成する切り欠きの形状は矩形に限定されるものではない。例えば、図5に示すように、三角形状に切り欠いたり、あるいはシールド電極14の四隅全体を切り欠くのではなく、チップ部品20の四隅22に相当する部分のみに任意形状の開口を形成したものであってもよい。   It should be noted that the shape of the notch formed in the shield electrode 14 in the portion corresponding to the four corners 22 of the chip component 20 is not limited to a rectangle. For example, as shown in FIG. 5, an opening having an arbitrary shape is formed only in a portion corresponding to the four corners 22 of the chip component 20, rather than being cut out in a triangular shape or cutting out all four corners of the shield electrode 14. It may be.

また、上記実施形態の積層型電子部品10は、実装基板15側(下側)にキャビティ12を形成したものであったが、図6に示すように、実装基板15とは反対側(上側)にキャビティ12を形成し、チップ部品20を収納して電気絶縁性の封止樹脂を充填したものであってもよい。積層型電子部品10を実装基板15に実装する際には、キャビティ12が上になるように配置して、外部導体16を介して実装基板15に電気的に接続する。また、キャビティ12側の上面には、チップ部品21が外部導体17を介して搭載される。   In the multilayer electronic component 10 of the above embodiment, the cavity 12 is formed on the mounting substrate 15 side (lower side). However, as shown in FIG. 6, the side opposite to the mounting substrate 15 (upper side). Alternatively, the cavity 12 may be formed, the chip component 20 may be accommodated, and an electrically insulating sealing resin may be filled therein. When the multilayer electronic component 10 is mounted on the mounting substrate 15, the multilayer electronic component 10 is disposed with the cavity 12 facing upward and is electrically connected to the mounting substrate 15 via the external conductor 16. Further, the chip component 21 is mounted on the upper surface on the cavity 12 side via the external conductor 17.

本発明の他の実施形態を図7および図8に示す。   Another embodiment of the present invention is shown in FIGS.

図7は積層型電子部品の部分拡大底面図、図8はチップ部品の実装時の部分拡大断面図である。   FIG. 7 is a partially enlarged bottom view of the multilayer electronic component, and FIG. 8 is a partially enlarged cross-sectional view when the chip component is mounted.

本実施形態は、キャビティ12に収納したチップ部品20の外周に相当する部分において、シールド電極30に額縁状に切り欠き31を形成したことを特徴とするものである。なお、その他の構成は、図1に示した例と同様である。   This embodiment is characterized in that a cutout 31 is formed in a frame shape on the shield electrode 30 in a portion corresponding to the outer periphery of the chip component 20 housed in the cavity 12. Other configurations are the same as the example shown in FIG.

このように、シールド電極30に額縁状に切り欠き31を形成したことにより、図7に示すように、シールド電極30が凹曲した状態でチップ部品20をキャビティ12に収納しようとした際、チップ部品20の外周縁23が切り欠き31に入り込んでシールド電極30の表面に当接することなくキャビティ12の底面13に固着される。よって、チップ部品20の四隅22ならびに外周縁23に欠けが生じるのを防止できる。   Thus, by forming the cutout 31 in a frame shape on the shield electrode 30, as shown in FIG. 7, when the chip component 20 is stored in the cavity 12 with the shield electrode 30 bent, The outer peripheral edge 23 of the component 20 enters the notch 31 and is fixed to the bottom surface 13 of the cavity 12 without contacting the surface of the shield electrode 30. Therefore, chipping can be prevented from occurring at the four corners 22 and the outer peripheral edge 23 of the chip component 20.

さらに、シールド電極30に形成した額縁状の切り欠き31によってシールド電極30と多層基板11との収縮差を吸収でき、シールド電極30の表面に形成される凹凸を緩和できる。   Further, the frame-shaped cutout 31 formed in the shield electrode 30 can absorb the shrinkage difference between the shield electrode 30 and the multilayer substrate 11, and the unevenness formed on the surface of the shield electrode 30 can be alleviated.

本発明は、セラミック多層基板にIC等のチップ部品を搭載した積層型電子部品として有用である。   The present invention is useful as a multilayer electronic component in which a chip component such as an IC is mounted on a ceramic multilayer substrate.

本発明の実施形態における積層型電子部品の断面図Sectional drawing of the multilayer electronic component in embodiment of this invention 本発明の実施形態における積層型電子部品の部分拡大断面図Partial expanded sectional view of the multilayer electronic component in the embodiment of the present invention 本発明の実施形態における積層型電子部品の部分拡大底面図The partial expanded bottom view of the multilayer electronic component in embodiment of this invention 本発明の実施形態におけるチップ部品の実装時の部分拡大断面図Partial expanded sectional view at the time of mounting of chip parts in an embodiment of the present invention 本発明の実施形態における変形例の積層型電子部品の部分拡大底面図The partial expanded bottom view of the multilayer electronic component of the modification in embodiment of this invention 本発明の実施形態における変形例の積層型電子部品の断面図Sectional drawing of the multilayer electronic component of the modification in embodiment of this invention 本発明の他の実施形態における積層型電子部品の部分拡大底面図The partially expanded bottom view of the multilayer electronic component in other embodiment of this invention 本発明の他の実施形態におけるチップ部品の実装時の部分拡大断面図Partial expanded sectional view at the time of mounting of chip parts in other embodiments of the present invention

符号の説明Explanation of symbols

10 積層型電子部品
11 多層基板
12 キャビティ
13 底面
14,30 シールド電極
18,31 切り欠き
20 チップ部品
22 隅
23 外周縁
DESCRIPTION OF SYMBOLS 10 Multilayer type electronic component 11 Multilayer substrate 12 Cavity 13 Bottom surface 14, 30 Shield electrode 18, 31 Notch 20 Chip component 22 Corner 23 Outer periphery

Claims (2)

主面にキャビティを有した多層基板と、前記キャビティの底面の少なくともチップ部品搭載領域を覆うように形成されたシールド電極と、前記シールド電極をダイボンド面として前記キャビティの底面に固着したチップ部品とを備えた積層型電子部品であって、
前記キャビティに収納した前記チップ部品の四隅に相当する部分において、前記シールド電極に切り欠きを形成したことを特徴とする積層型電子部品。
A multilayer substrate having a cavity on a main surface; a shield electrode formed so as to cover at least a chip component mounting region on a bottom surface of the cavity; and a chip component fixed to the bottom surface of the cavity with the shield electrode as a die bond surface. A laminated electronic component comprising:
A multilayer electronic component, wherein notches are formed in the shield electrode at portions corresponding to the four corners of the chip component housed in the cavity.
主面にキャビティを有した多層基板と、前記キャビティの底面の少なくともチップ部品搭載領域を覆うように形成されたシールド電極と、前記シールド電極をダイボンド面として前記キャビティの底面に固着したチップ部品とを備えた積層型電子部品であって、
前記キャビティに収納した前記チップ部品の外周に相当する部分において、前記シールド電極に切り欠きを形成したことを特徴とする積層型電子部品。
A multilayer substrate having a cavity on a main surface; a shield electrode formed so as to cover at least a chip component mounting region on a bottom surface of the cavity; and a chip component fixed to the bottom surface of the cavity with the shield electrode as a die bond surface. A laminated electronic component comprising:
A multilayer electronic component, wherein a cutout is formed in the shield electrode in a portion corresponding to the outer periphery of the chip component housed in the cavity.
JP2004164667A 2004-06-02 2004-06-02 Multilayer electronic components Expired - Fee Related JP4506291B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009066504A1 (en) * 2007-11-20 2009-05-28 Murata Manufacturing Co., Ltd. Module with embedded components
JP2010045271A (en) * 2008-08-18 2010-02-25 Hitachi Metals Ltd Multilayer circuit board
JP2016103520A (en) * 2014-11-27 2016-06-02 京セラ株式会社 Electronic component mounting package and electronic device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120270A (en) * 1992-09-30 1994-04-28 Fuji Xerox Co Ltd Semiconductor apparatus
JP2004103608A (en) * 2002-09-04 2004-04-02 Murata Mfg Co Ltd Laminated electronic part

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120270A (en) * 1992-09-30 1994-04-28 Fuji Xerox Co Ltd Semiconductor apparatus
JP2004103608A (en) * 2002-09-04 2004-04-02 Murata Mfg Co Ltd Laminated electronic part

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009066504A1 (en) * 2007-11-20 2009-05-28 Murata Manufacturing Co., Ltd. Module with embedded components
US8139368B2 (en) 2007-11-20 2012-03-20 Murata Manufacturing Co., Ltd. Component-containing module
JP2010045271A (en) * 2008-08-18 2010-02-25 Hitachi Metals Ltd Multilayer circuit board
JP2016103520A (en) * 2014-11-27 2016-06-02 京セラ株式会社 Electronic component mounting package and electronic device

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