JPH06120270A - Semiconductor apparatus - Google Patents
Semiconductor apparatusInfo
- Publication number
- JPH06120270A JPH06120270A JP4285311A JP28531192A JPH06120270A JP H06120270 A JPH06120270 A JP H06120270A JP 4285311 A JP4285311 A JP 4285311A JP 28531192 A JP28531192 A JP 28531192A JP H06120270 A JPH06120270 A JP H06120270A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- silicon chip
- thermal expansion
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に半導体装置の製造時の半導体素子の封止工程におい
て、切断分離された半導体素子をパッケージ・キャビテ
ィに接着するダイボンディング工程での熱膨張ストレス
を緩和する構造の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thermal expansion in a die bonding process for adhering the cut and separated semiconductor device to a package cavity in a semiconductor device encapsulating process in manufacturing the semiconductor device. It relates to the improvement of the structure for relieving stress.
【０００２】[0002]
【従来の技術】近年、半導体集積回路に対するユーザー
の要求は多岐にわたり、高密度化に伴う集積回路の微細
化と共に、多品種、少量生産の要求も高まりつつある。
このため、半導体装置のパッケージ工程においても従来
の、量産性に優れた樹脂封止型のパッケージだけでな
く、一個当たりのコストは上昇するものの、多品種、少
量生産に適したセラミックパッケージの需要が増加しつ
つある。セラミックパッケージは、図２、図３に示すよ
うに、予めリード（入力／出力ピン）４を備えたキャビ
ティ１を形成しておき、シリコンチップ２をキャビティ
１内へ接着し、その後、シリコンチップ２とリード４を
ワイヤ５によりボンディングして、続いてキャビティ１
へのキャップ３を接着することによって行われている。2. Description of the Related Art In recent years, users' demands for semiconductor integrated circuits have been diversified, and demands for high-mix low-volume production are increasing along with miniaturization of integrated circuits accompanying high density.
Therefore, in the packaging process of semiconductor devices, not only the conventional resin-encapsulated package with excellent mass productivity but also the cost per unit rises, but there is a demand for ceramic packages suitable for high-mix low-volume production. It is increasing. In the ceramic package, as shown in FIGS. 2 and 3, a cavity 1 having leads (input / output pins) 4 is formed in advance, the silicon chip 2 is bonded into the cavity 1, and then the silicon chip 2 is bonded. And the lead 4 are bonded by the wire 5, and then the cavity 1
This is done by adhering the cap 3 to the.
【０００３】ところが、シリコンチップ２のキャビティ
１内への接着はハンダ接着や、銀ペーストによる方法が
一般的であるが、接着工程で１５０〜３００℃の加熱が
必要となる。シリコンチップ２とキャビティ１の熱膨張
率が互いに異なると、両者を接着した後、室温まで冷却
した時にシリコンチップ２とキャビティ１との間の接着
面で収縮量に違いが出るため、歪みが生じて、その機械
的ストレスが半導体素子へダメージを与え、歩留まりの
低下を引き起こす要因となる。However, the silicon chip 2 is generally bonded to the inside of the cavity 1 by solder bonding or silver paste, but heating at 150 to 300 ° C. is required in the bonding process. If the thermal expansion coefficients of the silicon chip 2 and the cavity 1 are different from each other, when the two are bonded and then cooled to room temperature, the amount of shrinkage varies at the bonding surface between the silicon chip 2 and the cavity 1, resulting in distortion. As a result, the mechanical stress damages the semiconductor element and causes a decrease in yield.
【０００４】[0004]
【発明が解決しようとする課題】図４（ａ）はキャビテ
ィ１のシリコンチップ２との接着工程を示す。通常、キ
ャビティ１の接着部分はシリコンチップ２との接着性、
その他パッケージ材としての特性を考慮してアルミナに
金メッキを施したものを使用するが、シリコンチップ２
に比較して熱膨張率が大きい。例えば１ｃｍ□のシリコ
ンチップ２の場合、１５０℃から室温までの冷却により
キャビティ１はシリコンチップ２よりも５μｍ余分に収
縮し、図４（ｂ）に示すようにシリコンチップ２’に圧
縮応力６を与える。FIG. 4A shows a step of bonding the cavity 1 to the silicon chip 2. Normally, the adhesive portion of the cavity 1 has adhesiveness with the silicon chip 2,
Considering the characteristics of other packaging materials, we use alumina plated with gold. Silicon chip 2
The coefficient of thermal expansion is large compared to. For example, in the case of a silicon chip 2 of 1 cm square, the cavity 1 contracts 5 μm more than the silicon chip 2 by cooling from 150 ° C. to room temperature, and a compressive stress 6 is applied to the silicon chip 2 ′ as shown in FIG. 4 (b). give.
【０００５】そこで、本発明者らは鋭意研究を重ねた結
果、シリコンチップ２とキャビティ１との間で熱膨張率
の違いによって生じる歪みを低減させ、シリコンチップ
２へのダメージを減少させるパッケージ方法を見出し、
本発明に到達した。すなわち、本発明の目的は、半導体
素子のキャビティへの接着時に熱膨張率の違いによって
生じる半導体素子の機械的ストレスを低減させ、半導体
素子へのダメージを減少させ、歩留まり低下の少ない半
導体装置の製造方法およびキャビティの構造に特徴を持
つ半導体装置を提供することにある。Therefore, as a result of intensive studies by the present inventors, a packaging method for reducing the strain caused by the difference in the coefficient of thermal expansion between the silicon chip 2 and the cavity 1 and reducing the damage to the silicon chip 2. Heading
The present invention has been reached. That is, the object of the present invention is to reduce the mechanical stress of the semiconductor element caused by the difference in the coefficient of thermal expansion at the time of bonding the semiconductor element to the cavity, reduce the damage to the semiconductor element, and manufacture the semiconductor device with less yield reduction. It is to provide a semiconductor device characterized by a method and a structure of a cavity.
【０００６】[0006]
【課題を解決するための手段】本発明の上記目的は次の
構成によって達成される。すなわち、半導体素子をキャ
ビティに封止して得られる半導体装置において、キャビ
ティと半導体素子との接着面が半導体素子とキャビティ
との熱膨張率の違いによって生じる熱膨張ストレスを緩
和する構造を持つ半導体装置である。前記熱膨張ストレ
スを緩和する構造は、例えばキャビティの半導体素子と
の接着面を複数の断面凸状部とすることである。The above objects of the present invention can be achieved by the following constitutions. That is, in a semiconductor device obtained by sealing a semiconductor element in a cavity, a semiconductor device having a structure in which a bonding surface between the cavity and the semiconductor element relaxes thermal expansion stress caused by a difference in thermal expansion coefficient between the semiconductor element and the cavity. Is. The structure for alleviating the thermal expansion stress is, for example, that the bonding surface of the cavity with the semiconductor element has a plurality of convex portions in cross section.
【０００７】[0007]
【作用】本発明は半導体素子とキャビティとの熱膨張率
の違いによって生じる歪みによる機械的ストレスを緩和
させるため、半導体素子との接着面となるキャビティ底
部を複数の断面凸状部を持つ構造にすることにより、キ
ャビティの熱膨張／収縮をこの断面凸状部の変形により
吸収させ、半導体素子に直接キャビティの熱膨張／収縮
が及ばないようにするものである。According to the present invention, in order to relieve the mechanical stress due to the strain caused by the difference in the coefficient of thermal expansion between the semiconductor element and the cavity, the cavity bottom portion serving as the bonding surface with the semiconductor element has a structure having a plurality of convex portions in cross section. By doing so, the thermal expansion / contraction of the cavity is absorbed by the deformation of the convex portion in cross section so that the thermal expansion / contraction of the cavity does not directly reach the semiconductor element.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図面と共に説明す
る。本実施例の半導体の製造工程の一部を図１に示す。
本実施例においても、前記従来技術で述べたように、図
３に示す場合と同様に、予めリード（入力／出力ピン）
４を備えたキャビティ１を形成しておき、シリコンチッ
プ２をキャビティ１内へ接着し、その後、シリコンチッ
プ２とリード４をボンディングして、続いてキャビティ
１へのキャップ（図示せず）を接着することによってセ
ラミックパッケージを製造する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of the manufacturing process of the semiconductor of this embodiment.
Also in this embodiment, as described in the above-mentioned prior art, similarly to the case shown in FIG. 3, leads (input / output pins) are previously set.
The cavity 1 provided with 4 is formed, the silicon chip 2 is bonded into the cavity 1, the silicon chip 2 and the lead 4 are bonded, and then the cap (not shown) is bonded to the cavity 1. To produce a ceramic package.
【０００９】本実施例では、図１に示すように、キャビ
ティ１のシリコンチップ２との接着面に例えば、幅０．
５ｍｍ、深さ０．５ｍｍ程度のスリット状のを縦横に形
成し、シリコンチップ２との接着される部分のキャビテ
ィ１がシリコンチップ２の熱収縮に合わせて、変形でき
るようにすることによりシリコンチップ２に直接キャビ
ティの熱膨張／収縮が及ばないようにした。In this embodiment, as shown in FIG. 1, the bonding surface of the cavity 1 with the silicon chip 2 has, for example, a width of 0.
A silicon chip is formed by forming slits having a length of 5 mm and a depth of about 0.5 mm vertically and horizontally so that the cavity 1 at the portion bonded to the silicon chip 2 can be deformed in accordance with the thermal contraction of the silicon chip 2. No thermal expansion / contraction of the cavity was directly applied to No.2.
【００１０】以上の実施例では、半導体素子としてシリ
コンチップ２を用いた例を示し、またシリコンチップ２
に接着するキャビティ１に断面凸状部１ａを縦横に形成
する構造を示したが、本発明はこれに限らず、半導体素
子としてシリコンチップ２以外のものにも適用でき、ま
たキャビティ１にストレス緩和のための構造を形成する
全ての方法を含む。In the above embodiments, an example using the silicon chip 2 as a semiconductor element is shown, and the silicon chip 2 is also used.
Although the structure in which the convex portion 1a in cross section is formed in the vertical and horizontal directions is shown in the cavity 1 to be adhered to, the present invention is not limited to this, and can be applied to other than the silicon chip 2 as a semiconductor element, and stress relaxation in the cavity 1 can be applied. Includes all methods of forming structures for.
【００１１】[0011]
【発明の効果】本発明によれば、パッケージ工程で発生
する半導体素子への熱ストレスに起因する歩留まり低下
を防ぎ、半導体装置を高い信頼性で歩留まり良く製造す
ることができる。According to the present invention, it is possible to prevent a decrease in yield due to thermal stress on a semiconductor element generated in a packaging process, and to manufacture a semiconductor device with high reliability and high yield.
【図１】 本発明の一実施例の作用によって、半導体製
造時の冷却後のチップへのストレスが緩和された状態を
示した断面図である。FIG. 1 is a cross-sectional view showing a state where stress on a chip after cooling during semiconductor manufacturing is relieved by the action of one embodiment of the present invention.
【図２】 従来法による半導体製造時のパッケージ工程
を説明するための斜め透視図である。FIG. 2 is an oblique perspective view for explaining a packaging process at the time of manufacturing a semiconductor by a conventional method.
【図３】 従来法による半導体製造時のパッケージ工程
を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a packaging process at the time of manufacturing a semiconductor by a conventional method.
【図４】 図４（ａ）は本発明の一実施例の半導体製造
時のキャビティへのチップ接着直後のまだ加熱下にある
状態（冷却前）を示した断面図、図４（ｂ）は冷却後の
チップにストレスのかかった状態を示した断面図であ
る。FIG. 4 (a) is a cross-sectional view showing a state (before cooling) immediately after chip bonding to a cavity during semiconductor manufacturing of one embodiment of the present invention (before cooling), and FIG. FIG. 6 is a cross-sectional view showing a state where stress is applied to the chip after cooling.
１…キャビティ、１ａ…断面凸状部、２…シリコンチッ
プ、３…キャップ、４…入／出力ピン、５…ボンディグ
ワイヤ、６…圧縮応力DESCRIPTION OF SYMBOLS 1 ... Cavity, 1a ... Convex section, 2 ... Silicon chip, 3 ... Cap, 4 ... Input / output pin, 5 ... Bonding wire, 6 ... Compressive stress
Claims (1)
れる半導体装置において、キャビティと半導体素子との
接着面が半導体素子とキャビティとの熱膨張率の違いに
よって生じる熱膨張ストレスを緩和する構造を持つこと
を特徴とする半導体装置。1. A semiconductor device obtained by encapsulating a semiconductor element in a cavity, wherein a bonding surface between the cavity and the semiconductor element reduces a thermal expansion stress caused by a difference in thermal expansion coefficient between the semiconductor element and the cavity. A semiconductor device characterized by having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285311A JPH06120270A (en) | 1992-09-30 | 1992-09-30 | Semiconductor apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285311A JPH06120270A (en) | 1992-09-30 | 1992-09-30 | Semiconductor apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06120270A true JPH06120270A (en) | 1994-04-28 |
Family
ID=17689889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4285311A Pending JPH06120270A (en) | 1992-09-30 | 1992-09-30 | Semiconductor apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06120270A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347479A (en) * | 2004-06-02 | 2005-12-15 | Murata Mfg Co Ltd | Laminated electronic component |
| JP2012160639A (en) * | 2011-02-02 | 2012-08-23 | Meidensha Corp | Semiconductor module and stress buffer member |
| CN107367288A (en) * | 2017-07-27 | 2017-11-21 | 宁波中车时代传感技术有限公司 | A kind of micro fluxgate sensor preparation method |
-
1992
- 1992-09-30 JP JP4285311A patent/JPH06120270A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347479A (en) * | 2004-06-02 | 2005-12-15 | Murata Mfg Co Ltd | Laminated electronic component |
| JP4506291B2 (en) * | 2004-06-02 | 2010-07-21 | 株式会社村田製作所 | Multilayer electronic components |
| JP2012160639A (en) * | 2011-02-02 | 2012-08-23 | Meidensha Corp | Semiconductor module and stress buffer member |
| CN107367288A (en) * | 2017-07-27 | 2017-11-21 | 宁波中车时代传感技术有限公司 | A kind of micro fluxgate sensor preparation method |
| CN107367288B (en) * | 2017-07-27 | 2023-11-21 | 宁波中车时代传感技术有限公司 | Preparation method of miniature fluxgate sensor |
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