JP2010045271A - Multilayer circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable multilayer circuit board, in the multilayer circuit board for forming the same electric potential such as a grounding conductor inside and outside a cavity bottom part. <P>SOLUTION: The multilayer circuit board includes: a line conductor 6 formed on a surface of the multilayer circuit board; a first plane conductor 4 oppositely formed in the line conductor 6 inside the multilayer circuit board; and a cavity 3 for mounting a chip element. A bottom part of the cavity 3 and the first plane conductor 4 are positioned on a main surface of a common dielectric layer 2, and a second plane conductor 5 of the same electric potential as the first plane conductor is formed in the bottom part of the cavity, and an area 7 unformed with the first plane conductor is arranged in at least a part of a peripheral edge part of the bottom part positioned inside the multilayer circuit board on the main surface of the common dielectric layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multilayer circuit board that handles high-frequency signals such as a microwave band, a quasi-millimeter wave band, and a millimeter wave band, and has a cavity.

  Conventionally, microstrip lines, coplanar lines, and the like have been used as transmission lines used for circuit components that handle high-frequency signals in the quasi-millimeter wave band (10 GHz to 30 GHz) and the millimeter wave band (30 GHz to 300 GHz). In the microstrip line, the line conductor is opposed to the ground conductor via the dielectric layer. Such a structure is obtained by forming a signal line on one main surface of a substrate made of ceramics, resin or the like and a ground conductor on the other main surface. For example, FIG. 3 of Patent Document 1 that improves the characteristics of a multilayer high-frequency circuit board in the microwave band and the millimeter wave band discloses a configuration in which an MMIC is mounted in a cavity having a ground conductor exposed on the bottom surface. The MMIC (high frequency circuit element 9) is connected to the microstrip line patterns 3a, 3b and the like on the upper surface of the dielectric substrate 2a by connecting wires 10.

JP-A-11-103176

  When the structure having such a cavity is to be realized by a multilayer ceramic substrate manufacturing technique described in Patent Document 1, which is simultaneously fired after patterning a conductor green pattern on a ceramic green sheet, Such a problem may occur.

  A cavity peripheral structure similar to that of Patent Document 1 is shown in FIG. 6A is a cross-sectional view of the structure around the cavity, viewed from the side of the multilayer circuit board, and FIG. 6B is an enlarged view of the peripheral portion. A cavity 18 is formed by laminating a dielectric layer 17 having an opening on a dielectric layer 16 having a ground conductor 19 formed on the main surface. A line conductor 20 is formed on the main surface of the dielectric layer 17 to form a microstrip line structure. On the other hand, the ground conductor 19 is exposed on the bottom surface of the cavity 18 so that a chip element such as MMIC can be mounted. However, the adhesiveness between the conductor component and the ceramic component that originally constitute the ground conductor is low, and pressure at the time of stacking and integration in the cavity peripheral portion escapes in the cavity direction. As a result, in the configuration shown in FIG. 6A, as shown in FIG. 6B, a gap 21 is likely to occur between the ground conductor 19 and the dielectric layer 17 in the peripheral portion of the cavity. When such a gap is generated, the inside of the multilayer circuit board enters a plating solution, moisture, or the like from a post-process or an external environment, and reliability is lowered. In addition, when a load is applied to the position of the arrow in FIG. 6B for wire bonding, there is a problem that the substrate is damaged, such as a crack.

  In view of the above-mentioned problems, the present invention suppresses the generation of gaps around the cavity bottom and causes defects such as cracks in a multilayer circuit board in which conductors of the same potential such as ground conductors are formed inside and outside the cavity bottom. It is an object to provide a multilayer circuit board that is difficult and reliable.

  The multilayer circuit board of the present invention is a multilayer circuit board configured by using a plurality of laminated dielectric layers, the line conductor formed on the surface of the multilayer circuit board, and the multilayer circuit board inside the multilayer circuit board. A first planar conductor formed so as to face the line conductor, and a cavity for mounting the chip element, wherein the bottom of the cavity and the first planar conductor are a common dielectric layer main The second planar conductor having the same potential as the first planar conductor is formed at the bottom of the cavity, and is located on the common dielectric layer main surface and inside the multilayer circuit board. A region where the first planar conductor is not formed is provided on at least a part of the peripheral edge of the bottom. By providing a region inside the multilayer circuit board where no conductor is formed at the peripheral edge of the cavity bottom, contact between dielectric layers in this region is improved, and adhesion strength is improved and gaps are generated. Is suppressed.

  Further, in the multilayer circuit board, the line conductor is extended so that one end thereof is directed to the cavity, and the region is formed so as to sandwich the one end when viewed from the stacking direction of the dielectric layer. Preferably it is. According to such a configuration, by increasing the adhesion strength around the line conductor to which an external force is applied, the generation of a gap in the portion is suppressed. In addition, since the opposing relationship between the line conductor and the first planar conductor is also maintained, fluctuations in impedance can be suppressed.

  Furthermore, in the multilayer circuit board, it is preferable that the first planar conductor and the second planar conductor are connected on the common dielectric layer main surface. According to such a configuration, the first planar conductor and the second planar conductor can be integrally configured, so that the connection reliability is improved and the impedance is stabilized.

  In the multilayer circuit board, the line conductor is extended so that one end thereof faces the cavity, and the width of the region is the width of the cavity in a direction perpendicular to the extending direction of the line conductor. It is also preferable that the region is formed so as to overlap the one end as viewed from the stacking direction of the dielectric layers or on a virtual extension portion of the line conductor. According to this configuration, it is possible to ensure the adhesion between the dielectric layers on the virtual extension portion of the line conductor. Moreover, since the area | region which does not form a conductor is not enlarged more than necessary, it contributes also to stability of an impedance. Note that the region is formed on the virtual extension portion of the line conductor. If one end of the line conductor is extended as it is, the region, the line conductor, and the region are viewed from the stacking direction of the dielectric layers. Means overlapping.

  Furthermore, in the multilayer circuit board, it is preferable that the first planar conductor and the second planar conductor are connected on the common dielectric layer main surface. According to such a configuration, the first planar conductor and the second planar conductor can be integrally configured, so that the connection reliability is improved and the impedance is stabilized.

  In the multilayer circuit board, it is also preferable that the region is formed on the entire periphery of the bottom so as to surround the bottom. According to such a configuration, the generation of a gap is suppressed in the entire peripheral edge of the cavity bottom. Therefore, the reliability related to the peripheral portion of the cavity bottom can be greatly improved.

  Further, in the multilayer circuit board, the line conductor is extended so that one end thereof is directed to the cavity, and the one end and the region overlap each other when viewed from the stacking direction of the dielectric layer. Preferably it is. According to such a configuration, the adhesion strength below the line conductor to which an external force is applied is increased and the generation of a gap in the portion is more reliably suppressed, so that the reliability of the multilayer circuit board can be improved.

  The multilayer circuit board further includes a chip element mounted in the cavity, and a bonding wire that connects the chip element and the line conductor, and the bonding wire and the line conductor are viewed from the stacking direction. It is preferable that they are connected at a portion overlapping the region. In such a configuration, since wire bonding is performed in a region where the adhesion strength is increased and the generation of gaps is suppressed, the occurrence of cracks can be prevented and a highly reliable multilayer circuit board can be provided.

  Further, in the multilayer circuit board, the line conductor is preferably used as a signal line conductor for a quasi-millimeter wave band or a millimeter wave band. A microstrip line structure is used for signal transmission in the quasi-millimeter wave band or the millimeter wave band, but in such a high frequency band, a slight deviation of the line conductor greatly affects the characteristics. Therefore, the configuration that contributes to the suppression of the occurrence of gaps is suitable for a microstrip line structure for a quasi-millimeter wave band or a millimeter wave band.

  According to the present invention, in a multilayer circuit board in which conductors of the same potential such as ground conductors are formed inside and outside the cavity bottom, the generation of gaps around the cavity bottom is suppressed, and defects such as cracks are less likely to occur. It is possible to provide a multi-layer circuit board having a high height.

  Embodiments of the present invention will be described below with reference to the drawings. A multilayer circuit board according to the present invention is configured using a plurality of laminated dielectric layers, and is formed so as to face a line conductor formed on the surface of the multilayer circuit board and the line conductor inside the multilayer board. And a first planar conductor and a cavity for mounting the chip element. The multilayer circuit board may be manufactured, for example, according to a manufacturing process of low temperature co-fired ceramics (LTCC). A dielectric sheet on which a conductive pattern such as Ag is formed is integrated and fired to obtain a multilayer circuit board. FIG. 1 shows a first embodiment of a multilayer circuit board according to the present invention. FIG. 1 shows a part of the multilayer circuit board in order to show the structure around the cavity. FIG. 1A shows a part of the main surface of the first dielectric layer (surface layer) constituting the multilayer circuit board, and FIG. 1B shows the main surface of the second dielectric layer (inner layer) of the multilayer circuit board. A part of FIG. 1C is a plan view of the multilayer circuit board viewed from the stacking direction after the first dielectric layer and the second dielectric layer are stacked and integrated, and FIG. It is sectional drawing in the AA 'line in. The first dielectric layer 1 serving as the surface of the multilayer substrate is provided with a rectangular opening 3 for forming a cavity, and two linear lines having the same longitudinal direction so as to sandwich the opening. A conductor 6 is formed. A first planar conductor 4 is formed on the second dielectric layer 2 so as to face the line conductor 6 when a multilayer circuit board is formed. In FIG. 1B, the position of the edge of the opening in FIG. 1A, that is, the edge of the bottom of the cavity and the projected position of the line conductor 6 are indicated by dotted lines. On the main surface of the second dielectric layer, there is a strip-like (annular) conductor non-forming portion 7 along the portion corresponding to the edge of the bottom of the cavity so as to include the portion corresponding to the edge in the center in the width direction. Is provided. A rectangular second planar conductor 5 is formed inside the conductor non-forming portion 7.

The first dielectric layer shown in FIG. 1A and the second dielectric layer shown in FIG. 1B are stacked to form a multilayer circuit board having a cavity shown in FIGS. 1C and 1D. . In FIG. 1C, the boundary between the first planar conductor 4 and the conductor non-forming portion 7 is indicated by a two-dot chain line. In the case of the embodiment shown in FIG. 1, the first planar conductor 4 opposed to the strip-shaped line conductor 6 via the first dielectric layer 1 is a ground electrode, and in this embodiment, a microstrip line structure is formed. ing. When viewed from the stacking direction of the dielectric layers, the first planar conductor 4 is continuously formed around the cavity bottom so as to surround the cavity. The bottom of the cavity 3 and the first planar conductor 4 are located on the main surface of the common dielectric layer (second dielectric layer 2), and the first planar conductor 4 is disposed on the bottom of the cavity 3. A second planar conductor 5 having the same potential as that of the second planar conductor 5 is formed. The first planar conductor 4 and the second planar conductor 5 are grounded using a via electrode or the like (not shown) formed in the dielectric layer. In FIGS. 1C and 1D, the first planar conductor 4 is formed on the main surface of the second dielectric layer 2 and on the entire peripheral edge of the bottom of the cavity 3 located inside the multilayer circuit board. A region that is not formed (a region between the two-dot chain line in FIG. 1C and the edge of the cavity bottom represented by a solid line) is provided so as to surround the bottom. In the configuration shown in FIG. 1, the second planar conductor 5 is also provided away from the edge of the bottom of the cavity 3, so that the conductor is also surrounded at the bottom of the cavity 3 so as to surround the second planar conductor 5. A region that is not formed is provided. The second planar conductor 5 has a rectangular shape and is used for mounting a chip element. In the above-described region where the first planar conductor 4 is not formed, the first dielectric layer and the second dielectric layer, which are ceramics, are in close contact with each other without a conductor interposed therebetween, so that the bonding strength is increased. Can do. Therefore, generation | occurrence | production of the clearance gap in a cavity bottom part peripheral edge can be suppressed. In the embodiment shown in FIG. 1, the entire peripheral edge portion of the cavity bottom portion is a non-formation region of the first planar conductor 4, so that the reliability is particularly high. With respect to the size of the region where the conductor is not formed at the bottom of the cavity 3, a dimension that takes into account the cavity formation variation and the stacking variation is desirable, and it is desirable to set the direct sum thereof to the maximum allowable value. However, the removal of the conductor at the bottom of the cavity 3 is not a direct effect on the close contact of the substrate, but is intended to ensure the close contact strength at the time of variation, and thus is not necessarily required. On the other hand, the same dimension is required on the inner side of the multilayer circuit board for the same reason, and the strength increases as the conductor removal area increases. However, since a gap is generated at the cavity boundary, it is better to make the area near the boundary larger than the area where the conductor is not formed in the direction perpendicular to the boundary. large. In order to ensure the flatness of the bottom surface of the cavity and stably mount the components to be mounted in the cavity, the area of the cavity is desirably 9 mm ² or less. Further, from the viewpoint of obtaining higher reliability, it is more preferable that the width of the non-formation region of the first planar conductor 4 and the width of the region where the conductor is not formed at the bottom of the cavity 3 be 50 μm or more. On the other hand, the width of the non-formation region of the first planar conductor 4 is more preferably 200 μm or less, and even more preferably 100 μm or less from the viewpoint of suppressing impedance variation.

  Further, the line conductor 6 is extended so that one end thereof faces the cavity 3, and the end of the region where the one end and the first planar conductor 4 are not formed is seen from the stacking direction of the dielectric layers. Match and are arranged so that they do not overlap. In this case, since the first planar conductor 4 exists below the line conductor 6, even if the connection position of the line conductor 6 and the bonding wire changes, the impedance change can be suppressed. On the other hand, the one end and the region may overlap each other. This is because, when priority is given to connection reliability, it is preferable to perform connection such as wire bonding using such a portion. FIG. 5 shows a cross-sectional view of an embodiment in which a chip element such as an MMIC is mounted on the configuration shown in FIG. The chip element 13 mounted in the cavity and the bonding wire 14 for connecting the terminal 15 of the chip element 13 and the line conductor 6 are provided. The bonding wire 14 and the line conductor 6 are the first plane as viewed from the stacking direction. The conductor 4 is connected at a portion overlapping the region where the conductor 4 is not formed. In this case, since the load at the time of wire bonding becomes a joint part between ceramics having high adhesion, generation of defects such as cracks can be suppressed.

  In the embodiment shown in FIG. 1, the first planar conductor 4 which is the ground electrode in the drawing is formed over the entire dielectric layer, but other parts of the multilayer circuit board other than the cavity peripheral part and the surface layer line The first planar conductor 4 may not be provided in a portion where no conductor is disposed. In addition, the region where the first planar conductor is not formed is at least the peripheral surface of the bottom of the cavity located on the main surface of the second dielectric layer 2 that is a common dielectric layer and inside the multilayer circuit board. If it is provided in a part, the adhesion between the dielectric layers in that part is improved, and the reliability is also improved. For example, the configuration shown in FIG. 4 can be employed. In the embodiment shown in FIG. 4, the configuration related to the first planar conductor 12 formed in the second dielectric layer is different from the embodiment shown in FIG. 1. Other configurations are the same as those of the embodiment shown in FIG. As shown in FIG. 4B, the first planar conductor 12 is not formed on the pair of sides of the rectangular cavity 3 facing each other where the line conductor is not disposed. Since the 1st plane conductor 12 should just be arrange | positioned so as to oppose the line conductor 6, the effect which concerns on this invention can be exhibited also in this case.

  Another embodiment in which the region where the first planar conductor is not formed is provided on at least a part of the peripheral edge of the cavity bottom portion, which is located on the common dielectric layer main surface and inside the multilayer circuit board. It is shown in 2. 2A shows a part of the main surface of the first dielectric layer (surface layer) constituting the multilayer circuit board, and FIG. 2B shows the main surface of the second dielectric layer (inner layer) of the multilayer circuit board. A part of FIG. 2C is a plan view of the multilayer circuit board viewed from the stacking direction after the first dielectric layer and the second dielectric layer are stacked and integrated, and FIG. It is sectional drawing in the BB 'line | wire in. The configuration shown in FIG. 2 is different from the embodiment shown in FIG. 1 in the configuration of the planar conductor 8 formed in the second dielectric layer shown in FIG. The other configuration is the same as the configuration shown in FIG.

A first planar conductor 8 is formed on the second dielectric layer 2 so as to face the line conductor 6 when a multilayer circuit board is formed. As viewed from the stacking direction of the dielectric layers, the first planar conductor 8 is continuously formed around the cavity bottom so as to surround the cavity. In FIG. 2B, the position of the opening edge of FIG. 2A, that is, the position of the bottom edge of the cavity and the projection position of the line conductor 6 are indicated by dotted lines. Further, the line conductor 6 extends so that one end thereof is directed to the cavity 3. Further, a conductor non-forming portion 9 is provided so as to overlap one end of the line conductor 6 when viewed from the stacking direction of the dielectric layers. In FIG.2 (c), the projection position of the conductor non-formation part 9 is shown with the dashed-two dotted line. The width of the conductor non-forming portion 9 is smaller than the width of the cavity 3 in the direction perpendicular to the extending direction of the line conductor 6 (the vertical direction in the figure). The conductor non-forming portion 9 is disposed only on the two sides where the line conductor 6 is close to the cavity 3. That is, in the embodiment shown in FIG. 2, the region where the first planar conductor 8 is not formed is formed so that a part including the portion overlapping the end of the line conductor 6 is cut out from the first planar conductor 8. Has been. Since the conductor non-forming portion 9 is formed across the edge of the bottom of the cavity 3, at least one of the peripheral portions of the bottom of the cavity located on the main surface of the second dielectric layer 2 and inside the multilayer circuit board. A configuration in which a region where the first planar conductor is not formed is provided in the part is realized. In the above-described region where the first planar conductor 4 is not formed, the first dielectric layer and the second dielectric layer, which are ceramics, are in close contact with each other without a conductor interposed therebetween, so that the bonding strength is increased. Can do. Therefore, generation | occurrence | production of the clearance gap in a cavity bottom part peripheral edge can be suppressed. Further, the region is composed of a very small part overlapping the end of the line conductor 6. Therefore, since the portion where the first planar conductor 4 is not formed can be minimized, the impedance stability is excellent. From the viewpoint of impedance stability, the region may be formed on a virtual extension portion of the line conductor 6 when viewed from the stacking direction of the dielectric layers. If the line conductor 6 is virtually extended, the line conductor 6 reaches a portion corresponding to the edge of the cavity. What is necessary is just to make it the said area | region and the said line conductor overlap in the part extended virtually. In any configuration, by increasing the adhesion under the line conductor to which an external force is applied, the generation of a gap in the portion is reliably suppressed. In the embodiment shown in FIG. 2, the conductor non-forming portion 9 is arranged at the bottom of the cavity continuously from the region. Although the conductor non-formation part is not necessarily required on the cavity bottom side, the conductor may straddle the edge of the cavity bottom due to manufacturing variations in the part where the region is to be formed. More preferably, a conductor non-formation part is also provided at the bottom of the cavity continuously from the region. Further, from the viewpoint of obtaining higher reliability, of the conductor non-forming portion 9, the width inside the multilayer circuit board (the width in the direction perpendicular to the side of the bottom of the cavity across which the conductor non-forming portion 9 strides) and the bottom of the cavity 3 More preferably, the width of is secured to 50 μm or more. On the other hand, from the viewpoint of suppressing fluctuations in impedance, the width inside the multilayer circuit board is more preferably 200 μm or less, and even more preferably 100 μm or less. Further, it is more preferable that the width in the direction parallel to the side of the cavity bottom portion over which the conductor non-forming portion 9 is straddled is larger than the width of the line conductor 6 and not more than 5 times the width of the line conductor 6. Furthermore, the area of the conductor non-forming portion 9 is more preferably 1 mm ² or less.

  In the embodiment shown in FIG. 2, the first planar conductor 8 is formed on the entirety of the second dielectric layer other than the conductor non-forming portion 9. The first planar conductor and the second planar conductor formed at the bottom of the cavity 3 are integrally formed, and the first planar conductor and the second planar conductor are a common dielectric layer (second dielectric layer). The dielectric layer is directly connected on the main surface. With this configuration, connection reliability is improved and impedance is stabilized.

  If the region where the first planar conductor 8 is not formed is formed on a virtual extension portion of the line conductor 6 when viewed from the stacking direction of the dielectric layers, Since one planar conductor 8 exists, even if the connection position of the line conductor 6 and the bonding wire changes, the impedance change can be suppressed. On the other hand, in the configuration of FIG. 2, the line conductor 6 is extended so that one end thereof is directed to the cavity 3, and the one end and the first planar conductor 4 are formed when viewed from the stacking direction of the dielectric layers. It is arranged so that the areas that do not overlap. When priority is given to connection reliability, it is preferable to perform connection, such as wire bonding, using this part like the embodiment shown in FIG.

  Next, another implementation in which a region where the first planar conductor is not formed is provided on at least a part of the peripheral portion of the cavity bottom portion located on the common dielectric layer main surface and inside the multilayer circuit board. The form is shown in FIG. 3A shows a part of the main surface of the first dielectric layer (surface layer) constituting the multilayer circuit board, and FIG. 3B shows the main surface of the second dielectric layer (inner layer) of the multilayer circuit board. A part of FIG. 3C is a plan view of the multilayer circuit board viewed from the stacking direction after the first dielectric layer and the second dielectric layer are stacked and integrated, and FIG. It is sectional drawing in CC 'line in. The configuration shown in FIG. 3 is different from the embodiment shown in FIG. 1 or FIG. 2 in the configuration of the planar conductor formed in the second dielectric layer shown in FIG. The other configuration is the same as the configuration shown in FIG. 1 or FIG.

  A first planar conductor 10 is formed on the second dielectric layer 2 so as to face the line conductor 6 when a multilayer circuit board is formed. As viewed from the stacking direction of the dielectric layers, the first planar conductor 10 is continuously formed around the cavity bottom so as to surround the cavity. FIG. 3B shows the position of the edge of the opening of FIG. 3A, that is, the edge of the bottom of the cavity and the projection position of the line conductor 6 by dotted lines. Further, the line conductor 6 extends so that one end thereof is directed to the cavity 3. Furthermore, the conductor non-formation part 11 is provided so that the end of the line conductor 6 may be pinched | interposed into the both sides on the extension line of the line conductor 6 seeing from the lamination direction of a dielectric material layer. In FIG.3 (c), the projection position of the conductor non-formation part 11 is shown with the dashed-two dotted line. The conductor non-forming portion 11 is disposed only on the two sides where the line conductor 6 is close to the cavity 3. That is, in the embodiment shown in FIG. 3, the region where the first planar conductor 10 is not formed is formed so as to be partially cut out from both sides of the line conductor 6 from the first planar conductor 10. The embodiment shown in FIG. 3 is shown in FIG. 1 or FIG. 2 in that the conductor non-forming part 11 is not provided on the extension line of the line conductor 6 and the end of the line conductor 6 does not overlap the conductor non-forming part 11. Different from the embodiment. Since the conductor non-forming portion 11 is formed across the edge of the bottom of the cavity 3, at least one of the peripheral portions of the bottom of the cavity located on the main surface of the second dielectric layer 2 and inside the multilayer circuit board. A configuration in which a region where the first planar conductor is not formed is provided in the part is realized. A part of the first planar conductor 10 is present on the extended line of the line conductor 6 in the peripheral part of the bottom of the cavity, but regions where the first planar conductor 10 is not formed are provided on both sides thereof. Therefore, sufficient adhesion can be ensured at such a portion. In addition, in the embodiment shown in FIG. 3 in which the conductor non-forming portion 11 is not disposed below the line conductor 6 and the entire line conductor faces the first planar conductor 10, the variation in impedance is suppressed. This is a particularly preferable configuration.

In the embodiment shown in FIG. 3, similarly to the embodiment shown in FIG. 2, the conductor non-formation part 11 is arranged at the cavity bottom continuously from the region. Although the conductor non-formation part is not necessarily required on the cavity bottom side, the conductor may straddle the edge of the cavity bottom due to manufacturing variations in the part where the region is to be formed. More preferably, a conductor non-formation part is also provided at the bottom of the cavity continuously from the region. Further, from the viewpoint of obtaining higher reliability, among the conductor non-forming portions 11, the width inside the multilayer circuit board (the width in the direction perpendicular to the side of the cavity bottom across the conductor non-forming portions 11) and the bottom of the cavity 3. More preferably, the width of is secured to 50 μm or more. On the other hand, from the viewpoint of suppressing fluctuations in impedance, the width inside the multilayer circuit board is more preferably 200 μm or less, and even more preferably 100 μm or less. In addition, the width in the direction parallel to the side of the cavity bottom portion over which the conductor non-forming portion 9 straddles is more preferably 5 times or less the width of the line conductor 6. Furthermore, the area of the conductor non-forming portion 9 is more preferably 1 mm ² or less.

  In the embodiment shown in FIG. 3, as in the embodiment shown in FIG. 2, the first planar conductor 10 is formed on the entirety of the second dielectric layer other than the conductor non-forming portion 11. The first planar conductor and the second planar conductor formed at the bottom of the cavity 3 are integrally formed, and the first planar conductor and the second planar conductor are a common dielectric layer (second dielectric layer). The dielectric layer is directly connected on the main surface. With this configuration, connection reliability is improved and impedance is stabilized.

  Since the multilayer circuit board according to the above embodiment forms a microstrip line structure using the first planar conductor as a ground electrode, the line conductor 6 is used as a signal line conductor for a quasi-millimeter wave band or a millimeter wave band signal. It is suitable when used as.

  Moreover, although the said embodiment is an example which laminated | stacked the 1st dielectric material layer and the 2nd dielectric material layer adjacent, you may arrange | position another dielectric material layer between these. Of the other dielectric layers, conductors can be appropriately formed in portions other than the periphery of the cavity as shown in FIGS. Further, a dielectric layer may be further disposed below the second dielectric layer. On the other hand, the cavity side on which the chip element is mounted may be resin-sealed. The first planar conductor and the second planar conductor have the same potential. In this case, the same potential is intended to allow variation in potential due to simple connection wiring. The above embodiment has a configuration related to the microstrip line structure in which the first planar conductor is the ground electrode. However, the configuration of the above embodiment is when the first planar conductor and the second planar conductor are other than the ground potential. Can also be used. Moreover, the cavity should just be formed in at least one of the two main surfaces of a multilayer circuit board, and may be formed in both main surfaces. Furthermore, a multistage cavity may be formed on at least one of the two main surfaces. When a plurality of cavities are formed, it is sufficient that at least one of them has the configuration according to the above embodiment, but it is more preferable that all the cavity portions have the configuration according to the above embodiment. Further, flip chip mounting may be used instead of wire bonding for mounting the chip element.

The multilayer circuit board according to the present invention uses, for example, a ceramic dielectric material LTCC (Low Temperature Co-fired Ceramics) that can be sintered at a low temperature of 1000 ° C. or less to a green sheet having a thickness of 10 μm to 200 μm and a low resistance. It can be manufactured by printing a conductive paste such as Ag or Cu at a predetermined rate to form a predetermined electrode pattern, laminating a plurality of green sheets as appropriate, and sintering. A semiconductor having a green sheet having an opening (through hole) and no opening (through hole) at a position corresponding to the opening (through hole), that is, a uniform green sheet is stacked and pressure-bonded. A cavity for mounting a chip element such as an element is formed. In that case, the above-mentioned conductor non-formation part is provided in the predetermined part of the green sheet which does not have an opening. Here, the number of laminated green sheets is not particularly limited, but a conductor pattern constituting a ground electrode, a desired circuit, or the like is printed and formed between the layers of the green sheet. A via hole electrode for connecting the pattern is provided. A dummy conductor or a partial dielectric layer may be provided on the surface dielectric layer so as to overlap with the region where the first planar conductor is not formed, which is formed at the peripheral edge of the cavity bottom. Due to their thickness, pressure is easily applied to the region during pressure bonding, and adhesion is further improved. As the dielectric material, for example, Al, Si, Sr as a main component, Ti, Bi, Cu, Mn, Na, K as a subcomponent, Al, Si, Sr as a main component, Ca, Pb, A material containing Na and K as a multicomponent, a material containing Al, Mg, Si, and Gd, and a material containing Al, Si, Zr, and Mg are used, and a material having a dielectric constant of, for example, about 3 to 15 is used. The ceramic substrate is made of HTCC (high temperature co-fired ceramic) technology, the dielectric material is mainly Al ₂ O ₃ and the transmission line is made of a metal conductor that can be sintered at a high temperature such as tungsten or molybdenum. You may do it. Moreover, the resin sealing method in the case of resin sealing does not specifically limit this, The conventional methods, such as printing and a mold, are employable.

  The multilayer circuit board according to the present invention can be suitably used for applications such as communication module boards, antenna boards, and various sensor boards that handle quasi-millimeter wave band or millimeter wave band signals. However, the application is not limited to these, and the present invention can be widely applied to a multilayer circuit board in which a circuit is formed on a dielectric substrate.

It is a figure which shows one Embodiment of the multilayer circuit board based on this invention. It is a figure which shows other embodiment of the multilayer circuit board based on this invention. It is a figure which shows other embodiment of the multilayer circuit board based on this invention. It is a figure which shows other embodiment of the multilayer circuit board based on this invention. It is a figure which shows other embodiment of the multilayer circuit board based on this invention. It is a figure which shows the conventional multilayer circuit board.

Explanation of symbols

1: first dielectric layer 2: second dielectric layer 3, 18: cavity 4, 8, 10, 12: first planar conductor 5: second planar conductor 6, 20: line conductor 7, 9 11: Conductor non-formation part 13: Chip element 14: Bonding wire 15: Terminal 16, 17: Dielectric layer 19: Ground conductor 21: Gap

Claims (9)

A multilayer circuit board configured by using a plurality of laminated dielectric layers,
A line conductor formed on the surface of the multilayer circuit board;
A first planar conductor formed to face the line conductor inside the multilayer circuit board;
A cavity for mounting the chip element,
The bottom of the cavity and the first planar conductor are located on a common dielectric layer principal surface;
A second planar conductor having the same potential as the first planar conductor is formed at the bottom of the cavity,
A region where the first planar conductor is not formed is provided in at least a part of the peripheral edge portion of the bottom portion located on the common dielectric layer main surface and inside the multilayer circuit board. A featured multilayer circuit board. The line conductor is extended so that one end thereof faces the cavity,
2. The multilayer circuit board according to claim 1, wherein the region is formed so as to sandwich the one end when viewed from the stacking direction of the dielectric layers.   The multilayer circuit board according to claim 2, wherein the first planar conductor and the second planar conductor are connected on the common dielectric layer main surface. The line conductor is extended so that one end thereof faces the cavity,
In a direction perpendicular to the extending direction of the line conductor, the width of the region is smaller than the width of the cavity,
2. The multilayer circuit board according to claim 1, wherein the region is formed so as to overlap with the one end as viewed from the stacking direction of the dielectric layer or on a virtual extension portion of the line conductor.   The multilayer circuit board according to claim 4, wherein the first planar conductor and the second planar conductor are connected on the main surface of the common dielectric layer.   The multilayer circuit board according to claim 1, wherein the region is formed on the entire peripheral edge of the bottom so as to surround the bottom. The line conductor is extended so that one end thereof faces the cavity,
The multilayer circuit board according to claim 6, wherein the one end and the region overlap each other when viewed from the stacking direction of the dielectric layers. A chip element mounted in the cavity, and a bonding wire that connects the chip element and the line conductor;
8. The multilayer circuit board according to claim 4, wherein the bonding wire and the line conductor are connected at a portion overlapping with the region when viewed from the stacking direction.   The multilayer circuit board according to any one of claims 1 to 8, wherein the line conductor is used as a line conductor for a quasi-millimeter wave band or a millimeter wave band signal.

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