JP2005332497A5 - - Google Patents

Download PDF

Info

Publication number
JP2005332497A5
JP2005332497A5 JP2004150614A JP2004150614A JP2005332497A5 JP 2005332497 A5 JP2005332497 A5 JP 2005332497A5 JP 2004150614 A JP2004150614 A JP 2004150614A JP 2004150614 A JP2004150614 A JP 2004150614A JP 2005332497 A5 JP2005332497 A5 JP 2005332497A5
Authority
JP
Japan
Prior art keywords
counter
moriseru
refresh
cell array
count value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004150614A
Other languages
English (en)
Japanese (ja)
Other versions
JP4664622B2 (ja
JP2005332497A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2004150614A priority Critical patent/JP4664622B2/ja
Priority claimed from JP2004150614A external-priority patent/JP4664622B2/ja
Publication of JP2005332497A publication Critical patent/JP2005332497A/ja
Publication of JP2005332497A5 publication Critical patent/JP2005332497A5/ja
Application granted granted Critical
Publication of JP4664622B2 publication Critical patent/JP4664622B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2004150614A 2004-05-20 2004-05-20 半導体集積回路装置 Expired - Fee Related JP4664622B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004150614A JP4664622B2 (ja) 2004-05-20 2004-05-20 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004150614A JP4664622B2 (ja) 2004-05-20 2004-05-20 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2005332497A JP2005332497A (ja) 2005-12-02
JP2005332497A5 true JP2005332497A5 (enExample) 2007-04-19
JP4664622B2 JP4664622B2 (ja) 2011-04-06

Family

ID=35487036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004150614A Expired - Fee Related JP4664622B2 (ja) 2004-05-20 2004-05-20 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP4664622B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US9257169B2 (en) 2012-05-14 2016-02-09 Samsung Electronics Co., Ltd. Memory device, memory system, and operating methods thereof
US9245604B2 (en) 2013-05-08 2016-01-26 International Business Machines Corporation Prioritizing refreshes in a memory device
US9224450B2 (en) 2013-05-08 2015-12-29 International Business Machines Corporation Reference voltage modification in a memory device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950014089B1 (ko) * 1993-11-08 1995-11-21 현대전자산업주식회사 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치
JP4704691B2 (ja) * 2004-02-16 2011-06-15 シャープ株式会社 半導体記憶装置

Similar Documents

Publication Publication Date Title
TW557570B (en) Semiconductor memory device
CN101740118B (zh) 相变和阻变随机存取存储器及其执行突发模式操作的方法
TWI746988B (zh) 順序讀取模式靜態隨機存取記憶體（ｓｒａｍ）
JP2009545095A5 (enExample)
Wuu et al. The asynchronous 24mb on-chip level-3 cache for a dual-core itanium/sup/spl reg//-family processor
US10867669B2 (en) Serialized SRAM access to reduce congestion
CN102655023A (zh) 用于半导体存储器件的刷新控制电路及方法
TWI762827B (zh) 記憶體裝置以及用於操作記憶體裝置的方法
JP2003308224A (ja) マルチポートスキャンチェーンレジスタ装置及び方法
CN109584944A (zh) 支持多输入移位寄存器功能的输入输出电路及存储器件
JP2003204001A5 (enExample)
US7548485B2 (en) Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof
JP2006155710A5 (enExample)
JP2005332497A5 (enExample)
Ishii et al. A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs
US9218262B2 (en) Dynamic memory cell replacement using column redundancy
JP2010186525A5 (enExample)
US20240006012A1 (en) Virtualized scan chain testing in a random access memory (ram) array
US20070011511A1 (en) Built-in self-test method and system
JP2002093175A5 (enExample)
JP2004362756A5 (enExample)
US10496569B2 (en) Semiconductor integrated circuit
JP2022533622A (ja) シフト可能メモリ、およびシフト可能メモリを動作させる方法
JPS63293787A (ja) 半導体集積回路装置
WO2024159565A1 (zh) 地址选择电路、地址选择方法、刷新控制电路和存储系统