JP2005311307A - 基板上に半導体材料を備えた構造体の製造 - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
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Abstract
【解決手段】ドナー基板とレシーバ基板とが設けられ、レシーバ基板はその表面上にレリーフによる一つ又はそれ以上のモチーフを備え、ドナー基板がモチーフにおいてレシーバ基板と結合される。脆弱領域がドナー基板の所定深さに在り、脆弱領域と結合界面との間に薄い層が設けられる。この方法は、モチーフとドナー基板との間の結合を保持し、脆弱領域内と薄い層の厚み内とにおいて破断を起こさせて各モチーフに位置する薄い層の部分をドナー基板から剥離させ、この剥離された部分を構造体とするために、エネルギを与えることを特徴とする。
【選択図】 図8
Description
b)レシーバ基板の表面にモチーフを形成し、
c)モチーフを介してドナー基板にレシーバ基板を結合し、
d)脆弱領域の近傍のレシーバ基板に結合されたドナー基板のある部分を剥離する。
第一の基板41の表面を祖面化し、そして、任意であるが、第二の基板42を祖面化し、
第一の基板41と第二の基板42とを結合し、
第二の基板42を低減することを含む。
モチーフを分離する窪み部分(ウエハ30内に空洞を形成する)に関わる脆弱な結合
モチーフ22(実線部分)のようなモチーフにおいては脆弱領域15に沿って破断が起きやすい。
脆弱領域15に沿って、又は、
厚み“e”の材料層の凝固効果に打ち勝って内部空洞21に沿って
剥離が起きやすい。
下部19は、下部バッファ層との界面にAsGaを備える支持基板と、薄い層18との界面にInGaAsを備える変成バッファ層とから成る。
下部19は、サファイヤ、SiC又はSiから作られる支持基板と、xがサファイヤとの界面から0から1の範囲で厚みが変化するAlxGa1−xNと、転位型結晶欠陥を含むためのGaNの追加層とを備える。
基板1は、サファイヤ、SiC又はSiから作られる支持基板と、中間GaN層と、SiO2マスクと、GaNバッファ層とから成る。
Claims (18)
- 複数の半導体材料から選択された材料により成る構造体を基板上に形成する方法であって、該方法はドナー基板とレシーバ基板とから行われ、該レシーバ基板はその表面上にレリーフによる一つ又はそれ以上のモチーフを備え、前記ドナー基板が前記モチーフにおいて前記レシーバ基板と結合され、脆弱領域が前記ドナー基板の所定深さに在り、前記脆弱領域と前記結合界面との間に薄い層が設けられ、
前記モチーフと前記ドナー基板との間の結合を保持し、
前記脆弱領域内と前記薄い層の厚み内とにおいて破断を起こさせて各モチーフに位置する前記薄い層の部分を前記ドナー基板から剥離させ、該剥離された部分を前記構造体とするために、エネルギを与えることを特徴とする方法。 - 前記薄い層の厚み内における破断は一つ又はそれ以上のスリップ面に沿った劈開であることを特徴とする請求項1に記載の方法。
- 前記エネルギを与えるのは局部的なエネルギを与えることであることを特徴とする請求項2に記載の方法。
- 前記エネルギを与えるのは前記脆弱領域に局部的なエネルギを与えることであることを特徴とする請求項1又は2に記載の方法。
- 前記脆弱領域における結合力は前記モチーフと前記レシーバ基板との間の接着力より実質的に小さいことを特徴とする請求項4に記載の方法。
- 前記エネルギを与えるのは前記互いに結合されたドナー基板とレシーバ基板とにより成るウエハ全体でほぼ均等にエネルギを与えることを特徴とする請求項5に記載の方法。
- エネルギを与える前に前記ドナー基板を脆弱化させて前記脆弱領域を形成する工程を備えたことを特徴とする請求項1乃至6いずれかに記載の方法。
- 前記脆弱化工程は、前記脆弱領域の深さに近い深さにおいて前記ドナー基板内に原子種を注入し、前記注入領域を過脆弱化させて前記脆弱領域を形成することを特徴とする請求項7に記載の方法。
- 前記脆弱化工程は、支持ウエハの表面に多孔層を形成し、その後、該多孔層上に上部層を結晶成長させ、前記支持ウエハと前記多孔層と前記上部層とにより前記ドナー基板を形成し、前記多孔層が前記脆弱領域を形成することを特徴とする請求項7に記載の方法。
- 前記脆弱化工程は、二つのウエハの内の少なくとも一つが祖面化された前記二つのウエハを互いに結合し、その後、前記祖面化領域上に結合された上部層を残すように前記二つのウエハの内の一つを低減し、残部ウエハと前記上部層とにより前記ドナー基板を形成し、前記祖面化領域が前記脆弱領域を形成することを特徴とする請求項7に記載の方法。
- エネルギを与える前に前記レシーバ基板の表面上に前記複数モチーフを所定形状に形成することを特徴とする請求項1乃至10いずれかに記載の方法。
- エネルギを与えた後に前記レシーバ基板の表面上において一つ又はそれ以上のモチーフを分割することを特徴とする請求項1乃至11いずれかに記載の方法。
- エネルギを与えた後に構造体間を光接続させることを特徴とする請求項1乃至12いずれかに記載の方法。
- 少なくとも一つの形成された構造体はIII−V属合金を含むことを特徴とする請求項1乃至13いずれかに記載の方法。
- 少なくとも一つのモチーフはIII−V属合金を含むことを特徴とする請求項1乃至14いずれかに記載の方法。
- 請求項1乃至15いずれかに記載の方法の実施の間に得られたウエハであって、互いに結合された二つの基板から成り、該二つの基板の一つは、
他の基板に結合され、表面が突出した複数のモチーフと、
前記複数突出モチーフの下部に機械的に脆弱な領域を備えていることを特徴とするウエハ。 - 請求項1乃至15いずれかに記載の方法の使用であって、電子工学、光学又は光電子工学用に基板上に複数チップを形成し、あるチップはモチーフと下部の剥離された構造体とから成り、前記基板は前記レシーバ基板であることを特徴とする使用。
- 特に、LED又はLDのような半導体レーザ、又は、光受信機のために複数チップを形成することを特徴とする請求項17に記載の使用。
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Application Number | Priority Date | Filing Date | Title |
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FR0402080A FR2866983B1 (fr) | 2004-03-01 | 2004-03-01 | Realisation d'une entite en materiau semiconducteur sur substrat |
FR0402080 | 2004-03-01 | ||
US863193 | 2004-06-07 | ||
US10/863,193 US7176554B2 (en) | 2004-03-01 | 2004-06-07 | Methods for producing a semiconductor entity |
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JP2005311307A true JP2005311307A (ja) | 2005-11-04 |
JP4818618B2 JP4818618B2 (ja) | 2011-11-16 |
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US (1) | US7439160B2 (ja) |
EP (1) | EP1571705A3 (ja) |
JP (1) | JP4818618B2 (ja) |
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US11088016B2 (en) | 2013-07-15 | 2021-08-10 | Soitec | Method for locating devices |
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JP2008091862A (ja) * | 2006-09-08 | 2008-04-17 | Sharp Corp | 窒化物半導体発光素子および窒化物半導体発光素子の製造方法 |
JP2008117824A (ja) * | 2006-11-01 | 2008-05-22 | Sharp Corp | 窒化物系半導体素子の製造方法 |
FR2911430B1 (fr) * | 2007-01-15 | 2009-04-17 | Soitec Silicon On Insulator | "procede de fabrication d'un substrat hybride" |
US20100054289A1 (en) | 2008-08-29 | 2010-03-04 | Cobolt Ab | Solid-state laser |
US8888944B2 (en) | 2012-09-07 | 2014-11-18 | Erik G. de Jong | Affinity bond layer |
US20140264456A1 (en) * | 2013-03-15 | 2014-09-18 | Semiconductor Components Industries, Llc | Method of forming a high electron mobility semiconductor device |
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JP2004533717A (ja) * | 2001-04-13 | 2004-11-04 | コミサリヤ・ア・レネルジ・アトミク | 制御された機械的保持力を有する剥離可能な基板、およびその製造方法 |
WO2003010825A1 (en) * | 2001-07-24 | 2003-02-06 | Seiko Epson Corporation | Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipmen |
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US11088016B2 (en) | 2013-07-15 | 2021-08-10 | Soitec | Method for locating devices |
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EP1571705A2 (fr) | 2005-09-07 |
US7439160B2 (en) | 2008-10-21 |
US20070104240A1 (en) | 2007-05-10 |
JP4818618B2 (ja) | 2011-11-16 |
EP1571705A3 (fr) | 2006-01-04 |
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