JP2005203557A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005203557A
JP2005203557A JP2004008223A JP2004008223A JP2005203557A JP 2005203557 A JP2005203557 A JP 2005203557A JP 2004008223 A JP2004008223 A JP 2004008223A JP 2004008223 A JP2004008223 A JP 2004008223A JP 2005203557 A JP2005203557 A JP 2005203557A
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adhesive
semiconductor chip
electrode
electrode plate
lead frame
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Hiroyuki Nakamura
弘幸 中村
Hirotake Oka
浩偉 岡
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Renesas Technology Corp
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Renesas Technology Corp
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method which prevents voids from being generated in an adhesive connecting a semiconductor chip and an electrode plate. <P>SOLUTION: The manufacturing method of the semiconductor device has a process for applying an adhesive (Ag paste) in multipoint to either one surface of the quadrangular semiconductor chip or a quadrangular first electrode plate; and a process for connecting the semiconductor chip and the first electrode plate by putting the semiconductor chip or the first electrode plate on the surface whereto the adhesive is applied with a prescribed load applied, and performing hardening treatment for the adhesive. In applying the adhesive, a first adhesive is applied to the center of the quadrangle, a plurality of second adhesives are applied to a periphery of the first adhesive, and the diameter of the first adhesive is made larger than that of the second adhesive. A plurality of second adhesives are arranged symmetrically about a point to the first adhesive. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は高出力半導体装置に係わり、特に、半導体チップの１面を導電性接着剤を介して電極板に固定する構成の半導体装置に適用して有効な技術に関する。   The present invention relates to a high-power semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a configuration in which one surface of a semiconductor chip is fixed to an electrode plate via a conductive adhesive.

高出力半導体装置の一つとして、電源用トランジスタを形成した半導体チップを封止体内に組み込んだ半導体装置（パワートランジスタ）が知られている。電源用トランジスタとしては、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor），ＩＧＢＴ（Insulated Gate Bipolar Transistor），バイポーラパワートランジスタ等がある。   As one of high-power semiconductor devices, a semiconductor device (power transistor) in which a semiconductor chip on which a power transistor is formed is incorporated in a sealed body is known. Examples of the power transistor include a power MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a bipolar power transistor.

パワーＭＯＳＦＥＴ装置は、封止体内にパワーＭＯＳＦＥＴチップを組み込んだ構造になっている。パワーＭＯＳＦＥＴ装置として、絶縁性樹脂からなる封止体の底面にドレイン端子となる金属部材からなる電極板を露出させ，封止体の一側にソース用リード端子及びゲート用リード端子を配置したＬＦＰＡＫ（Loss Free Package）が知られている。ソース用リード端子及びゲート用リード端子の内端はバンプ電極を介してソース電極及びゲート電極に接続されている。また、ソース用リード端子及びゲート用リード端子は一部で屈曲し、その先端は封止体の下面と同じ高さに位置し、表面実装が可能な構造になっている（例えば、特許文献１）。   The power MOSFET device has a structure in which a power MOSFET chip is incorporated in a sealed body. As a power MOSFET device, an LFPAK in which an electrode plate made of a metal member serving as a drain terminal is exposed on the bottom surface of a sealing body made of insulating resin, and a source lead terminal and a gate lead terminal are arranged on one side of the sealing body (Loss Free Package) is known. The inner ends of the source lead terminal and the gate lead terminal are connected to the source electrode and the gate electrode through bump electrodes. Further, the source lead terminal and the gate lead terminal are partially bent, and their tips are located at the same height as the lower surface of the sealing body, so that surface mounting is possible (for example, Patent Document 1). ).

特開２００３−８６７８７号公報JP 2003-86787 A

パワーＭＯＳＦＥＴ装置における半導体チップの裏面電極（ドレイン電極）と金属板とは導電性接着剤（例えば、Ａｇペースト）によって接続（固定）されている。この固定は、例えば、図２０（ａ）〜（ｃ）に示すような段階を経て行われる。図２０（ａ）〜（ｃ）において、左側の図は半導体チップ９０と電極板９１を接着剤９２によって接続する状態を示し、右側の図は２列に塗布された接着剤９２の広がり状態を示す図である。   In the power MOSFET device, the back electrode (drain electrode) of the semiconductor chip and the metal plate are connected (fixed) with a conductive adhesive (for example, Ag paste). This fixing is performed through steps as shown in FIGS. 20 (a) to 20 (c), for example. 20A to 20C, the left diagram shows a state where the semiconductor chip 90 and the electrode plate 91 are connected by the adhesive 92, and the right diagram shows the spread state of the adhesive 92 applied in two rows. FIG.

図２０（ａ）に示すように、長方形の半導体チップ９０の１面（第２の面）に接着剤９２を２列に小分けして塗布する。この接着剤９２の塗布は、図２１（ａ），（ｂ）に示すように、シリンジ９３の先端に２列に亘って複数のニードル９４を有するディスペンサーによって行う。図では２列４行に配置された合計８本のニードル９４によって接着剤９２の塗布を行う。図２０（ａ）は、前記ディスペンサーによって半導体チップの第２の面に接着剤９２が塗布された状態を示す。点状に塗布された接着剤９２の間隔は、列間では広く、行間では狭くなっている。   As shown in FIG. 20A, the adhesive 92 is applied to one surface (second surface) of a rectangular semiconductor chip 90 in two rows. The application of the adhesive 92 is performed by a dispenser having a plurality of needles 94 over two rows at the tip of the syringe 93, as shown in FIGS. In the figure, the adhesive 92 is applied by a total of eight needles 94 arranged in two columns and four rows. FIG. 20A shows a state in which the adhesive 92 is applied to the second surface of the semiconductor chip by the dispenser. The interval between the adhesives 92 applied in the form of dots is wide between columns and narrow between rows.

図２０（ｂ）に示すように、半導体チップ９０の第２の面上に電極板９１を位置決めして重ね、ついで図２０（ｃ）に示すように電極板９１を半導体チップ９０に押し付け、さらに接着剤の硬化処理（ベーク処理）を行って半導体チップ９０と電極板９１を固定する。図２０（ｂ）に示すように、半導体チップ９０上に電極板９１を重ねた状態では、２列４行の配置の接着剤９２の各間隔はそれほど変化しないが、図２０（ｃ）に示すように電極板９１を半導体チップ９０に押し付けることによって、半球状に盛り上がっていた接着剤９２は押し潰されて広がり、隣接する接着剤９２と一体化していく。   As shown in FIG. 20B, the electrode plate 91 is positioned and stacked on the second surface of the semiconductor chip 90, and then the electrode plate 91 is pressed against the semiconductor chip 90 as shown in FIG. The adhesive chip is cured (baked) to fix the semiconductor chip 90 and the electrode plate 91. As shown in FIG. 20B, in the state where the electrode plate 91 is stacked on the semiconductor chip 90, the intervals between the adhesives 92 arranged in 2 columns and 4 rows do not change so much, but shown in FIG. By pressing the electrode plate 91 against the semiconductor chip 90 in this manner, the hemispherical adhesive 92 is crushed and spread and integrated with the adjacent adhesive 92.

しかし、接着剤（Ａｇペースト）の濡れ性（広がり性）が悪く、接合部分にボイド（気泡）が発生し、半導体装置の特性・信頼性劣化を引き起こすことが判明した。このボイドの発生について検討した。   However, it has been found that the wettability (spreading property) of the adhesive (Ag paste) is poor, and voids (bubbles) are generated in the joint portion, causing deterioration of characteristics and reliability of the semiconductor device. The occurrence of this void was examined.

電極板９１を半導体チップ９０に押し付けた場合、図２０（ｃ）の右側の図に示すように、一列目と２列目の間に空気が閉じ込められてしまう。例えば、１列目（図で上列）の左側の１番目及び２番目の接着剤９２と、２列目（図で下列）の左側の１番目及び２番目の接着剤９２は、四角形の各頂点にそれぞれ接着剤９２が配置された格好である。このため、各頂点位置の接着剤９２が潰されて周辺に広がると、列列間、行行間で隣接する接着剤の一体化が進み、四角形の中心部分の空気が外に逃げることができなくなり、四角形の中心部分に空気が閉じ込められてボイド９５が発生してしまう。   When the electrode plate 91 is pressed against the semiconductor chip 90, air is trapped between the first row and the second row as shown in the diagram on the right side of FIG. For example, the first and second adhesives 92 on the left side of the first row (upper row in the figure) and the first and second adhesives 92 on the left side of the second row (lower row in the figure) The adhesive 92 is arranged at each apex. For this reason, when the adhesive 92 at each vertex position is crushed and spread to the periphery, the integration of adjacent adhesives between columns and rows proceeds, and the air in the central part of the rectangle cannot escape to the outside. The air is trapped in the central portion of the quadrangle, and the void 95 is generated.

本発明の一つの目的は、半導体チップと電極板との接着剤による接続の信頼性が高い半導体装置を提供することにある。   One object of the present invention is to provide a semiconductor device having a high connection reliability between a semiconductor chip and an electrode plate using an adhesive.

本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面からあきらかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

（１）本発明の半導体装置の製造方法は、
表裏面である上面と下面を有し、前記上面と前記下面を繋ぐ側面を有する絶縁性樹脂からなる封止体と、
前記封止体内に位置し、第１の面に第１電極及び制御電極を有し、前記第１の面の裏面になる第２の面に第２電極を有する半導体チップと、
表裏面である上面と下面を有し、下面は前記封止体の下面に露出し、前記封止体内に位置する上面は接着剤（例えば、Ａｇペースト）を介して前記半導体チップの第２電極に接続される第１の電極板と、
表裏面である上面と下面を有し、前記封止体の内外に亘って延在し、前記封止体内の前記半導体チップの第１電極に接続される第２の電極板と、
表裏面である上面と下面を有し、前記封止体の内外に亘って延在し、前記封止体内の前記半導体チップの制御電極に接続される第３の電極板とを有する半導体装置の製造方法であって、
前記第１の電極板を有する第１のリードフレーム、前記第２及び前記第３の電極板を有する第２のリードフレームを用意する工程と、
前記第２のリードフレームの前記第２及び前記第３の電極板に前記半導体チップの前記第１電極及び制御電極を電気的に接続する工程と、
前記半導体チップの前記第２電極上に接着剤を多点状に塗布した後、前記第１のリードフレームの前記第１の電極板を所定の荷重を掛けて重ね合わせ、かつ前記接着剤を硬化処理して前記第２電極を前記第１の電極板に電気的に接続する工程と、
前記半導体チップ、第１及び第２のリードフレームの所定部を絶縁性の樹脂で封止する工程と、
前記第１及び第２のリードフレームの不要部分を切断除去する工程とを有し、
前記接着剤の塗布において、前記四角形体の中心に第１の接着剤を塗布し、前記第１の接着剤の周囲であり、かつ前記四角形体の各角に対応して配置される第２の接着剤を塗布し、
前記第１の接着剤の直径は前記第２の接着剤よりも、例えば、１．２〜１．５倍程度と大きくすることを特徴とする。 (1) A manufacturing method of a semiconductor device of the present invention includes:
A sealing body made of an insulating resin having an upper surface and a lower surface, which are front and back surfaces, and a side surface connecting the upper surface and the lower surface;
A semiconductor chip located in the encapsulant, having a first electrode and a control electrode on a first surface, and having a second electrode on a second surface which is the back surface of the first surface;
It has an upper surface and a lower surface, which are front and back surfaces, the lower surface is exposed on the lower surface of the sealing body, and the upper surface located in the sealing body is a second electrode of the semiconductor chip via an adhesive (for example, Ag paste) A first electrode plate connected to
A second electrode plate having an upper surface and a lower surface that are front and back surfaces, extending over the inside and outside of the sealing body, and connected to the first electrode of the semiconductor chip in the sealing body;
A semiconductor device having an upper surface and a lower surface that are front and back surfaces, a third electrode plate extending over the inside and outside of the sealing body and connected to a control electrode of the semiconductor chip in the sealing body A manufacturing method comprising:
Preparing a first lead frame having the first electrode plate and a second lead frame having the second and third electrode plates;
Electrically connecting the first electrode and the control electrode of the semiconductor chip to the second and third electrode plates of the second lead frame;
After applying an adhesive on the second electrode of the semiconductor chip in a multipoint manner, the first electrode plate of the first lead frame is overlaid with a predetermined load, and the adhesive is cured. Processing to electrically connect the second electrode to the first electrode plate;
Sealing predetermined portions of the semiconductor chip and the first and second lead frames with an insulating resin;
Cutting and removing unnecessary portions of the first and second lead frames,
In the application of the adhesive, a first adhesive is applied to the center of the rectangular body, and the second adhesive is disposed around the first adhesive and corresponding to each corner of the rectangular body. Apply glue,
The diameter of the first adhesive is, for example, about 1.2 to 1.5 times larger than that of the second adhesive.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

前記（１）の手段によれば、四角形体の半導体チップの第２の面に接着剤を多点状に塗布する際、前記四角形体の中心に第１の接着剤を塗布し、前記第１の接着剤の周囲に複数の第２の接着剤を塗布し、かつ前記第１の接着剤の直径は前記第２の接着剤よりも大きくしてある。従って、第１のリードフレームの第１の電極板を半導体チップに押し付けた際広がる多点状に配置される接着剤は、四角形体の中心から周囲に広がり、四角形体の中心の空気を外部に押し出すように作用する。また、前記第２の接着剤は前記四角形体の各角に対応して配置されている。従って、第１の接着剤の半径方向の広がりと相俟って第２の接着剤は各領域で円周方向に広がり、四角形体の中心から押し出される空気を各領域で３方向から押し出して空気を半径方向に押し出すことになり、接着剤内にボイドが発生し難くなる。この結果、半導体チップと第１の電極板を接続する接着剤は均一な厚さになるとともにボイドを含まないようになることから、伝熱特性も良好になり、放熱性が向上し、電気特性が安定した信頼性の高い半導体装置とすることができる。   According to the means (1), when the adhesive is applied to the second surface of the rectangular semiconductor chip in a multipoint manner, the first adhesive is applied to the center of the rectangular body, and the first A plurality of second adhesives are applied around the adhesive, and the diameter of the first adhesive is larger than that of the second adhesive. Therefore, the adhesive arranged in a multi-point shape that spreads when the first electrode plate of the first lead frame is pressed against the semiconductor chip spreads from the center of the rectangular body to the periphery, and the air at the center of the rectangular body is exposed to the outside. Acts to extrude. The second adhesive is disposed corresponding to each corner of the rectangular body. Accordingly, the second adhesive spreads in the circumferential direction in each region in combination with the radial spread of the first adhesive, and the air pushed out from the center of the quadrilateral is pushed out from the three directions in each region. Will be pushed out in the radial direction, and voids are less likely to occur in the adhesive. As a result, since the adhesive connecting the semiconductor chip and the first electrode plate has a uniform thickness and does not contain voids, heat transfer characteristics are improved, heat dissipation is improved, and electric characteristics are improved. However, a stable and highly reliable semiconductor device can be obtained.

以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

図１乃至図１９は本発明の実施例１である半導体装置の製造方法に係わる図である。本実施例１では、本発明をＬＦＰＡＫ型のパワーＭＯＳＦＥＴ装置（半導体装置）の製造に適用した例について説明する。本発明の製法によって製造されたパワーＭＯＳＦＥＴ装置は、封止体内に縦型のパワーＭＯＳＦＥＴを形成した半導体チップが組み込まれている。半導体チップの第１の面（主面）には、第１電極であるソース（Ｓ）電極と、制御電極であるゲート（Ｇ）電極が設けられ、前記第１の面の反対面となる第２の面（主面）には第２電極となるドレイン（Ｄ）電極が設けられる構造になっている。   1 to 19 are diagrams relating to a method of manufacturing a semiconductor device which is Embodiment 1 of the present invention. In the first embodiment, an example in which the present invention is applied to the manufacture of an LFPAK type power MOSFET device (semiconductor device) will be described. The power MOSFET device manufactured by the manufacturing method of the present invention incorporates a semiconductor chip in which a vertical power MOSFET is formed in a sealed body. A first surface (main surface) of the semiconductor chip is provided with a source (S) electrode which is a first electrode and a gate (G) electrode which is a control electrode, and is a first surface opposite to the first surface. A drain (D) electrode serving as a second electrode is provided on the second surface (main surface).

パワーＭＯＳＦＥＴ装置（半導体装置）１は、図１８及び図１９に示すような構造になっている。図１８は平面図であり、図１９は断面図である。これらの図に示すように、偏平四角形状の絶縁性樹脂からなる封止体（パッケージ）２の右端からドレイン電極板３を突出させ、左端から３本のソースリード４と１本のゲートリード５を突出させている。ドレイン電極板３は第１の電極板で形成されている。３本のソースリード４は封止体２内で一体となり、第２の電極板で形成されている。１本のゲートリード５は第３の電極板で形成される。   The power MOSFET device (semiconductor device) 1 has a structure as shown in FIGS. 18 is a plan view, and FIG. 19 is a cross-sectional view. As shown in these drawings, a drain electrode plate 3 is projected from the right end of a sealing body (package) 2 made of a flat rectangular insulating resin, and three source leads 4 and one gate lead 5 are projected from the left end. Is protruding. The drain electrode plate 3 is formed of a first electrode plate. The three source leads 4 are integrated in the sealing body 2 and are formed of the second electrode plate. One gate lead 5 is formed of a third electrode plate.

ドレイン電極板３は、その一部（左側）が封止体２に埋め込まれ、下面は封止体２の下面に露出し、右端部は封止体２の側面から突出する幅広の平板からなっている。ドレイン電極板３は封止体２内において半導体チップ８を搭載するに十分な面積のチップ固定部分を有している。突出側のドレイン電極板部分には、封止体２の縁に沿ってスリット６が設けられている。このスリット６内には封止体２を形成する樹脂が充填されている。このスリット６によって、封止体２がドレイン電極板３から剥離し難くなる。封止体２とドレイン電極板３との接着強度を高めるため、図１９に示すように、ドレイン電極板３の封止体２内に埋没する上面側の周面やスリット６部分には鍔部３ａが設けられている。ドレイン電極板３は半導体チップ８で発生した熱を外部に放散させるヒートスプレッダとなる。   A part (left side) of the drain electrode plate 3 is embedded in the sealing body 2, the lower surface is exposed on the lower surface of the sealing body 2, and the right end portion is a wide flat plate protruding from the side surface of the sealing body 2. ing. The drain electrode plate 3 has a chip fixing portion having an area sufficient for mounting the semiconductor chip 8 in the sealing body 2. A slit 6 is provided along the edge of the sealing body 2 in the drain electrode plate portion on the protruding side. The slit 6 is filled with a resin that forms the sealing body 2. The slit 6 makes it difficult for the sealing body 2 to peel from the drain electrode plate 3. In order to increase the adhesive strength between the sealing body 2 and the drain electrode plate 3, as shown in FIG. 19, the peripheral surface on the upper surface side embedded in the sealing body 2 of the drain electrode plate 3 and the slit 6 portion are the flanges. 3a is provided. The drain electrode plate 3 serves as a heat spreader that dissipates heat generated in the semiconductor chip 8 to the outside.

ソースリード４及びゲートリード５は共に平行に延在して封止体２の側面から突出している。これらのリードは途中で一段屈曲して先端をドレイン電極板３と同じ高さに位置させている。これにより、パワーＭＯＳＦＥＴ装置１は表面実装型となる。   The source lead 4 and the gate lead 5 both extend in parallel and protrude from the side surface of the sealing body 2. These leads are bent one step in the middle and have their tips positioned at the same height as the drain electrode plate 3. Thereby, the power MOSFET device 1 becomes a surface mount type.

ソースリード４及びゲートリード５は、封止体２内において半導体チップ８のソース電極及びゲート電極に金バンプ電極９を介して電気的に接続されている。図１９はソースリード４が金バンプ電極９を介して半導体チップ８の図示しないソース電極に接続される状態を示す図である。ゲートリード５は１本であり、第３の電極板で形成される。また、３本のソースリード４は封止体２内において連結される構造になっている（図７参照）。   The source lead 4 and the gate lead 5 are electrically connected to the source electrode and the gate electrode of the semiconductor chip 8 through the gold bump electrode 9 in the sealing body 2. FIG. 19 is a diagram showing a state in which the source lead 4 is connected to a source electrode (not shown) of the semiconductor chip 8 through the gold bump electrode 9. One gate lead 5 is formed by a third electrode plate. The three source leads 4 are connected in the sealing body 2 (see FIG. 7).

なお、封止体２の表面には、図１８に示すように、方向識別のために円形窪みからなるインデックス１０が設けられている。   As shown in FIG. 18, an index 10 made of a circular depression is provided on the surface of the sealing body 2 for direction identification.

つぎに、本実施例のパワーＭＯＳＦＥＴ装置１の製造方法について説明する。パワーＭＯＳＦＥＴ装置１は、図２のフローチャートで示すように、第１及び第２のリードフレーム準備（Ｓ０１）、チップボンディング（Ｓ０２）、接着剤塗布（Ｓ０３）、ヒートスプレッダ固定（Ｓ０４）、封止体形成（Ｓ０５）、切断・成形（Ｓ０６）の各工程を経て製造される。以下順次説明する。   Next, a method for manufacturing the power MOSFET device 1 of this embodiment will be described. As shown in the flowchart of FIG. 2, the power MOSFET device 1 includes first and second lead frame preparations (S01), chip bonding (S02), adhesive application (S03), heat spreader fixing (S04), and a sealing body. It is manufactured through each step of forming (S05) and cutting / molding (S06). This will be sequentially described below.

パワーＭＯＳＦＥＴ装置１の製造においては、図５に示す第１のリードフレーム２０と、図３に示す第２のリードフレーム４０が準備される。第１のリードフレーム２０は、長手方向に沿って２０個、幅方向に２個、合計４０個のリードパターンが配列され、４０個のパワーＭＯＳＦＥＴ装置１を製造できる部品になっている。図６は第１のリードフレーム２０の長手方向２個、幅方向２個、合計４個のリードパターンを示す拡大図である。   In manufacturing the power MOSFET device 1, the first lead frame 20 shown in FIG. 5 and the second lead frame 40 shown in FIG. 3 are prepared. The first lead frame 20 has 20 lead patterns in the longitudinal direction and 2 in the width direction, for a total of 40 lead patterns, and is a component capable of manufacturing 40 power MOSFET devices 1. FIG. 6 is an enlarged view showing a total of four lead patterns, two in the longitudinal direction and two in the width direction of the first lead frame 20.

第２のリードフレーム４０は、図３に示すように、長手方向に沿って２０個、幅方向に４個、合計８０個のリードパターンが配列され、８０個のパワーＭＯＳＦＥＴ装置１を製造できる部品になっている。図４は第２のリードフレーム４０の単一のリードパターンを示す拡大図である。   As shown in FIG. 3, the second lead frame 40 has 20 lead patterns along the longitudinal direction and 4 in the width direction, and a total of 80 lead patterns are arranged, so that 80 power MOSFET devices 1 can be manufactured. It has become. FIG. 4 is an enlarged view showing a single lead pattern of the second lead frame 40.

第１のリードフレーム２０は、長手方向に沿って平行に延在する２本の外枠２１と、これら２本の外枠２１を所定間隔で連結する２本の横枠２２とからなる枠体からなっている。この横枠２２はリードフレームの両端では１本になっている。図６は第１のリードフレーム２０の一部の拡大平面図であり、隣接する横枠２２間に配置される４個のリードパターンを示す。隣接する横枠２２の中間には、横枠２２に平行に細い支持片２３が設けられている。この支持片２３はそれぞれ外枠２１から延在している。また、支持片２３の中央に沿ってスリット２４が２本直列に設けられている。   The first lead frame 20 includes a frame body including two outer frames 21 extending in parallel along the longitudinal direction and two horizontal frames 22 connecting the two outer frames 21 at a predetermined interval. It is made up of. The horizontal frame 22 is single at both ends of the lead frame. FIG. 6 is an enlarged plan view of a part of the first lead frame 20 and shows four lead patterns arranged between adjacent horizontal frames 22. In the middle of the adjacent horizontal frames 22, a thin support piece 23 is provided in parallel to the horizontal frame 22. Each of the support pieces 23 extends from the outer frame 21. Two slits 24 are provided in series along the center of the support piece 23.

また、スリット２４に沿う両側の支持片部分から四角形状の第１の電極板２５が突出している。この第１の電極板２５の付け根はその幅がわずかに狭くなっている。またこの狭くなった第１の電極板２５の部分には前述のスリット６が形成されている。第１の電極板２５及びスリット６の縁は段付き形状にされて前述のように鍔部３ａが設けられている。従って、図６では裏面側に半導体チップ８が固定されることになる。また、スリット２４の両端部分は円形となっている。これは、パワーＭＯＳＦＥＴ装置１の製造の最終に近い段階で支持片２３を切断するため、切断長さを短くするためである。支持片２３を所定箇所で切断することにより、第１の電極板２５及び支持片２３部分によって、前記ドレイン電極板３が形成されることになる。第１の電極板２５は前述のようにヒートスプレッダの一部を構成する。なお、外枠２１にはリードフレームを移送したり、位置決めする際使用されるガイド孔２７が設けられている。第１のリードフレーム２０は厚さ０．２ｍｍ程度の銅合金板で形成されている。   Further, a rectangular first electrode plate 25 protrudes from the support piece portions on both sides along the slit 24. The width of the base of the first electrode plate 25 is slightly narrowed. Further, the slit 6 is formed in the narrowed portion of the first electrode plate 25. The edges of the first electrode plate 25 and the slit 6 are stepped and provided with the flange 3a as described above. Therefore, in FIG. 6, the semiconductor chip 8 is fixed to the back side. Further, both end portions of the slit 24 are circular. This is for shortening the cutting length because the support piece 23 is cut at a stage close to the end of the manufacture of the power MOSFET device 1. By cutting the support piece 23 at a predetermined location, the drain electrode plate 3 is formed by the first electrode plate 25 and the support piece 23 portion. The first electrode plate 25 constitutes a part of the heat spreader as described above. The outer frame 21 is provided with a guide hole 27 used when the lead frame is transferred or positioned. The first lead frame 20 is formed of a copper alloy plate having a thickness of about 0.2 mm.

第２のリードフレーム４０は、長手方向に沿って平行に延在する２本の外枠４１と、これら２本の外枠４１を所定間隔で連結する横枠４２とからなる枠体からなっている。そして、一対の外枠４１間には４個のリードパターンが配置されている。図３はリードフレーム全体を示すことから図が微細となるため、単位リードパターン部分を図４にて説明する。図３に示すように、一対の外枠４１間には細いダム片４３が延在している。このダム片４３は横枠４２に平行に延在している。ダム片４３には交差するように４本のリード４ａ，５ａが連なっている。これらリード４ａ，５ａは平行に延在し、両側のリード４ａ，５ａの端末が直接横枠４２に連なっている。中央の２本のリード４ａの端末は、両側のリード４ａ，５ａ間に設けられた補助支持片に連なっている（図３参照）。   The second lead frame 40 includes a frame body including two outer frames 41 extending in parallel along the longitudinal direction and a horizontal frame 42 connecting the two outer frames 41 at a predetermined interval. Yes. Four lead patterns are arranged between the pair of outer frames 41. Since FIG. 3 shows the entire lead frame and the figure becomes fine, the unit lead pattern portion will be described with reference to FIG. As shown in FIG. 3, a thin dam piece 43 extends between the pair of outer frames 41. The dam piece 43 extends in parallel to the horizontal frame 42. Four leads 4a and 5a are connected to the dam piece 43 so as to intersect with each other. These leads 4 a and 5 a extend in parallel, and the ends of the leads 4 a and 5 a on both sides are directly connected to the horizontal frame 42. The ends of the central two leads 4a are connected to auxiliary support pieces provided between the leads 4a and 5a on both sides (see FIG. 3).

３本のリード４ａの先端側は幅広の接続部４４に連なっている。この接続部４４は半導体チップ８のゲート電極に接続される部分である。接続部４４は細い支持片４５を介して隣接する接続部４４または外枠４１に接続されている。また、接続部４４にはスリット４６が２本設けられている。このスリット４６は、封止体２を形成する際、封止体２を形成する樹脂がこのスリット４６を通過して半導体チップ８の表面に充填されるべく設けられている。   The leading ends of the three leads 4a are connected to a wide connecting portion 44. The connection portion 44 is a portion connected to the gate electrode of the semiconductor chip 8. The connection portion 44 is connected to the adjacent connection portion 44 or the outer frame 41 through a thin support piece 45. The connecting portion 44 is provided with two slits 46. The slit 46 is provided so that the resin forming the sealing body 2 passes through the slit 46 and fills the surface of the semiconductor chip 8 when the sealing body 2 is formed.

リード５ａは１本で形成され、その先端部分は半導体チップ８のゲート電極に接続される接続部５０となっている。接続部５０は接続部４４に隣接している。パワーＭＯＳＦＥＴ装置１の製造の最終段階に近い段階で行われる切断時には、ダム片４３は切断除去され、支持片４５及びリード４ａ，５ａは所定箇所で切断される。リード４ａ，５ａ及び接続部４４は、封止体２で覆われる部分は、封止体２を形成する樹脂との噛み合いを多くして抜けないようにするため、あるいは樹脂との接着強度を向上させるために所定縁部分を突出あるいは窪ませてある。また、熱の影響でリードフレームが変形しないように、例えば、支持片４５は屈曲させてある。また、外枠４１にはリードフレームを移送したり、位置決めする際使用されるガイド孔５５が設けられている。第２のリードフレーム４０は厚さ０．２５ｍｍ程度の銅合金板で形成されている。   One lead 5 a is formed, and the tip portion thereof is a connection portion 50 connected to the gate electrode of the semiconductor chip 8. The connection part 50 is adjacent to the connection part 44. At the time of cutting performed at a stage close to the final stage of manufacturing the power MOSFET device 1, the dam piece 43 is cut and removed, and the support piece 45 and the leads 4a and 5a are cut at predetermined positions. The lead 4a, 5a and the connecting part 44 are not covered with the resin forming the sealing body 2 in the portion covered with the sealing body 2, or the adhesion strength with the resin is improved. For this purpose, a predetermined edge portion is protruded or recessed. Further, for example, the support piece 45 is bent so that the lead frame is not deformed by the influence of heat. The outer frame 41 is provided with a guide hole 55 that is used when the lead frame is transferred or positioned. The second lead frame 40 is formed of a copper alloy plate having a thickness of about 0.25 mm.

第２のリードフレーム４０において、３本のリード４ａや接続部４４は第２の電極板を構成し、切断後はソースリード４を形成する。また、リードフレーム状態において、１本のリード５ａ及びその先端の接続部５０は第３の電極板を構成し、切断後はゲートリード５を形成する。   In the second lead frame 40, the three leads 4a and the connecting portion 44 constitute a second electrode plate, and the source lead 4 is formed after cutting. In the lead frame state, one lead 5a and the connecting portion 50 at the tip thereof constitute a third electrode plate, and the gate lead 5 is formed after cutting.

上記の第１のリードフレーム２０及び第２のリードフレーム４０を準備した（Ｓ０１）後、図７に示すように、第２のリードフレーム４０上に半導体チップ８を固定する（チップボンディング：Ｓ０２）。図７では、半導体チップ８は透過状態で模式的に示してある。また、図８には第２のリードフレーム４０に固定された半導体チップ８を示してある。半導体チップ８は、例えば、主面にｎ−型のエピタキシャル層を有するｎ＋型のシリコン半導体基板を基に形成され、平面的に多数のセル（トランジスタ）を整列配置した構造になっている。そして、半導体チップ８の第１の主面に各セルに繋がるソース電極及びゲート電極を有し、裏面にドレイン電極を有する構造になっている。 After the first lead frame 20 and the second lead frame 40 are prepared (S01), the semiconductor chip 8 is fixed on the second lead frame 40 as shown in FIG. 7 (chip bonding: S02). . In FIG. 7, the semiconductor chip 8 is schematically shown in a transmissive state. FIG. 8 shows the semiconductor chip 8 fixed to the second lead frame 40. The semiconductor chip 8 is formed based on, for example, an n + type silicon semiconductor substrate having an n − type epitaxial layer on the main surface, and has a structure in which a large number of cells (transistors) are arranged in a plane. The first main surface of the semiconductor chip 8 has a source electrode and a gate electrode connected to each cell, and has a drain electrode on the back surface.

そこで、図７に示すように、リード５ａの接続部５０は金バンプ電極９を介して半導体チップ８のゲート電極が接続される。また、リード４ａに連なる接続部４４は金バンプ電極９を介して半導体チップ８のソース電極に接続される。   Therefore, as shown in FIG. 7, the connection portion 50 of the lead 5 a is connected to the gate electrode of the semiconductor chip 8 through the gold bump electrode 9. Further, the connecting portion 44 connected to the lead 4 a is connected to the source electrode of the semiconductor chip 8 through the gold bump electrode 9.

つぎに、図８及び図９に示すように、第２のリードフレーム４０に固定された半導体チップ８の第２の面（主面）に接着剤を多点状に塗布する（Ｓ０３）。接着剤は、例えばＡｇペーストである。半導体チップ８は四角形体、即ち、長方形となっている。そこで、図８及び図９に示すように、長方形である半導体チップ８の中心上に第１の接着剤６０を塗布するとともに、この第１の接着剤６０の周囲に第２の接着剤６１を４個塗布する。第１の接着剤６０は第２の接着剤６１に比較して直径が大きい。従って、半導体チップ８の第２の面に半球状に塗布される第１の接着剤６０の量も第２の接着剤６１よりも多いことになる。例えば、第１の接着剤６０の直径は第２の接着剤６１の直径の１．２〜１．５倍程度の大きさになっている。   Next, as shown in FIGS. 8 and 9, an adhesive is applied to the second surface (main surface) of the semiconductor chip 8 fixed to the second lead frame 40 in a multipoint manner (S03). The adhesive is, for example, an Ag paste. The semiconductor chip 8 is a rectangular body, that is, a rectangle. Therefore, as shown in FIGS. 8 and 9, the first adhesive 60 is applied on the center of the rectangular semiconductor chip 8, and the second adhesive 61 is applied around the first adhesive 60. Apply 4 pieces. The first adhesive 60 has a larger diameter than the second adhesive 61. Therefore, the amount of the first adhesive 60 applied in a hemispherical shape to the second surface of the semiconductor chip 8 is also larger than that of the second adhesive 61. For example, the diameter of the first adhesive 60 is about 1.2 to 1.5 times the diameter of the second adhesive 61.

また、半導体チップ８が長方形であることから、第２の接着剤６１は長辺に沿って配置され、かつ四角形体の各辺に対応している。また、第２の接着剤６１は第１の接着剤６０に対して点対称に配置されている。一例を挙げるならば、長さ３．９ｍｍ、幅２．８ｍｍの半導体チップ８の場合、第１の接着剤６０は直径０．４９ｍｍであり、第２の接着剤６１の直径は０．３９ｍｍである。また、第１の接着剤６０と第２の接着剤６１との間隔は１．３２ｍｍであり、隣接する第２の接着剤６１同士の間隔は２．４ｍm及び１．１ｍｍである。   In addition, since the semiconductor chip 8 is rectangular, the second adhesive 61 is disposed along the long side and corresponds to each side of the quadrilateral. Further, the second adhesive 61 is arranged point-symmetrically with respect to the first adhesive 60. For example, in the case of the semiconductor chip 8 having a length of 3.9 mm and a width of 2.8 mm, the first adhesive 60 has a diameter of 0.49 mm, and the second adhesive 61 has a diameter of 0.39 mm. is there. Moreover, the space | interval of the 1st adhesive agent 60 and the 2nd adhesive agent 61 is 1.32 mm, and the space | interval of adjacent 2nd adhesive agents 61 is 2.4 mm and 1.1 mm.

接着剤の多点状塗布は、例えば、図１０に示すディスペンサー６５を用いて行う。ディスペンサー６５のコントロールボックス６６から延在するチューブ６７にはシリンジ６８が接続されている。シリンジ６８の先端のニードル６９に本発明による補助のシリンジ７０を取り付ける。この補助のシリンジ７０の底の中心には第１のニードル７１が設けられている。また、この第１のニードル７１の周囲には第２のニードル７２が設けられている。第１のニードル７１と第２のニードル７２の配置関係は、図８に示す半導体チップ８に塗布された第１の接着剤６０及び第２の接着剤６１の関係に対応している。即ち、図１１は補助のシリンジ７０の底部を示す模式図であり、中心には太い第１のニードル７１が位置し、その周囲に４本の第２のニードル７２が配置されている。従って、この補助のシリンジ７０を使用して、Ａｇペーストを塗布することによって、図８に示すような第１の接着剤６０及び第２の接着剤６１の塗布が可能になる。図１２（ａ）は多点状塗布の状態を示す模式図である。   The multipoint application of the adhesive is performed using, for example, a dispenser 65 shown in FIG. A syringe 68 is connected to a tube 67 extending from the control box 66 of the dispenser 65. An auxiliary syringe 70 according to the present invention is attached to the needle 69 at the tip of the syringe 68. A first needle 71 is provided at the center of the bottom of the auxiliary syringe 70. A second needle 72 is provided around the first needle 71. The arrangement relationship between the first needle 71 and the second needle 72 corresponds to the relationship between the first adhesive 60 and the second adhesive 61 applied to the semiconductor chip 8 shown in FIG. That is, FIG. 11 is a schematic diagram showing the bottom of the auxiliary syringe 70, in which a thick first needle 71 is located at the center, and four second needles 72 are arranged around it. Therefore, by applying the Ag paste using the auxiliary syringe 70, the first adhesive 60 and the second adhesive 61 as shown in FIG. 8 can be applied. Fig.12 (a) is a schematic diagram which shows the state of multipoint application | coating.

つぎに、図１、図１２（ｂ）及び図１３（ａ）〜（ｄ）に示すように、半導体チップ８の第２の面に第１のリードフレーム２０のヒートスプレッダの一部を構成する第１の電極板２５を接着剤によって固定する。図１は半導体チップ８の第２の面に第１のリードフレーム２０の第１の電極板２５を矢印に示すように移動して位置決めして重ねることを示す模式図である。これ以降、第１のリードフレーム２０は模式図で示す。図１２（ｂ）は、ヒートスプレッダを構成する第１の電極板２５を半導体チップ８の第２の面にヒートスプレッダ押さえ用コレット７５で押さえた状態を示す。そして、この状態で半導体チップ８と第１の電極板２５との間に均一に広がった接着剤７を硬化処理（ベーク処理）して接着剤７を硬化させる。これにより、ヒートスプレッダが半導体チップ８に固定される（Ｓ０４）。   Next, as shown in FIG. 1, FIG. 12B and FIGS. 13A to 13D, a second part of the heat spreader of the first lead frame 20 is formed on the second surface of the semiconductor chip 8. One electrode plate 25 is fixed with an adhesive. FIG. 1 is a schematic diagram showing that the first electrode plate 25 of the first lead frame 20 is moved, positioned, and overlapped on the second surface of the semiconductor chip 8 as indicated by arrows. Thereafter, the first lead frame 20 is schematically shown. FIG. 12B shows a state where the first electrode plate 25 constituting the heat spreader is pressed against the second surface of the semiconductor chip 8 by the heat spreader pressing collet 75. In this state, the adhesive 7 spread evenly between the semiconductor chip 8 and the first electrode plate 25 is cured (baked) to cure the adhesive 7. Thereby, the heat spreader is fixed to the semiconductor chip 8 (S04).

図１３（ａ）〜（ｄ）は半導体チップ８の第２の面に多点状に接着剤を塗布した後、ヒートスプレッダとなる第１の電極板２５を半導体チップ８に接着剤７によって固定する状態を示す模式図である。図１３（ａ）〜（ｄ）において、左側の図は半導体チップ８と第１の電極板２５を接着剤７（第１・第２の接着剤６０，６１）によって接続する状態を示し、右側の図は多点状塗布された第１・第２の接着剤６０，６１の広がり状態を示す図である。   13A to 13D, after applying adhesive on the second surface of the semiconductor chip 8 in a multipoint manner, the first electrode plate 25 serving as a heat spreader is fixed to the semiconductor chip 8 with the adhesive 7. It is a schematic diagram which shows a state. 13A to 13D, the left diagram shows a state in which the semiconductor chip 8 and the first electrode plate 25 are connected by the adhesive 7 (first and second adhesives 60 and 61). This figure is a view showing the spread state of the first and second adhesives 60 and 61 applied in a multipoint manner.

図１３（ａ）に示すように、長方形の半導体チップ８第２の面に第１・第２の接着剤６０，６１を小分けして塗布する。   As shown in FIG. 13A, the first and second adhesives 60 and 61 are applied in small portions to the second surface of the rectangular semiconductor chip 8.

つぎに、図１３（ｂ）に示すように、半導体チップ８の第２の面上に第１の電極板２５を位置決めして重ね、ついで図１３（ｃ）に示すように第１の電極板２５を半導体チップ８に押し付けて、図１３（ｄ）に示すように第１・第２の接着剤６０，６１を一体化して接着剤７とさせ、さらに接着剤の硬化処理（ベーク処理）を行って半導体チップ８と第１の電極板２５を固定する。これにより、図１４及び図１５に示すように、半導体チップ８に接着剤７を介して第１の電極板２５を固定することができる。図１４及び図１５は半導体チップ８に接着剤７を介して第１の電極板２５が固定された状態の模式的平面図及び模式的断面図である。   Next, as shown in FIG. 13 (b), the first electrode plate 25 is positioned and overlapped on the second surface of the semiconductor chip 8, and then the first electrode plate as shown in FIG. 13 (c). 25 is pressed against the semiconductor chip 8 so that the first and second adhesives 60 and 61 are integrated into the adhesive 7 as shown in FIG. 13 (d), and the adhesive is cured (baked). Then, the semiconductor chip 8 and the first electrode plate 25 are fixed. Thereby, as shown in FIGS. 14 and 15, the first electrode plate 25 can be fixed to the semiconductor chip 8 via the adhesive 7. 14 and 15 are a schematic plan view and a schematic cross-sectional view showing a state in which the first electrode plate 25 is fixed to the semiconductor chip 8 with the adhesive 7 interposed therebetween.

この間の多点状塗布による接着剤（Ａｇペースト）は、図１３（ａ）〜（ｄ）と進むにつれて順次押し潰されて広がり、半導体チップ８と第１の電極板２５の間で一体化する。この一体化の段階において、従来のように空気を巻き込むことがなく、接着剤７内には気泡（ボイド）が発生しなくなる。   The adhesive (Ag paste) by the multi-point application during this time is sequentially crushed and spread as it proceeds to FIGS. 13A to 13D, and is integrated between the semiconductor chip 8 and the first electrode plate 25. . At this stage of integration, air is not engulfed as in the prior art, and bubbles (voids) are not generated in the adhesive 7.

即ち、本実施例によれば、四角形体の半導体チップ８の第２の面に接着剤を多点状に塗布する際、前記四角形体の中心に第１の接着剤６０を塗布し、前記第１の接着剤６０の周囲に複数の第２の接着剤６１を塗布し、かつ第１の接着剤６０の直径は第２の接着剤６１よりも大きくしてある。従って、第１のリードフレーム２０の第１の電極板２５を半導体チップ８に押し付けた際広がる多点状に配置される接着剤（第１・第２の接着剤６０，６１）は、四角形体の中心から周囲に広がり、四角形体の中心の空気を外部に押し出すように作用する。また、第２の接着剤６１は半導体チップ８の四角形体の各角に対応して配置されている。従って、第１の接着剤６０の半径方向の広がりと相俟って第２の接着剤６１は各領域で円周方向に広がり、四角形体の中心から押し出される空気を各領域で３方向から押し出して空気を半径方向に押し出すことになり、接着剤７内にボイドが発生し難くなる。この結果、半導体チップ８と第１の電極板２５を接続する接着剤７は均一な厚さになるとともにボイドを含まないようになる。   That is, according to this embodiment, when the adhesive is applied to the second surface of the rectangular semiconductor chip 8 in a multipoint manner, the first adhesive 60 is applied to the center of the rectangular body, and the first A plurality of second adhesives 61 are applied around one adhesive 60, and the diameter of the first adhesive 60 is larger than that of the second adhesive 61. Therefore, the adhesives (first and second adhesives 60 and 61) arranged in a multipoint shape that spread when the first electrode plate 25 of the first lead frame 20 is pressed against the semiconductor chip 8 are rectangular bodies. It spreads from the center of the center to the periphery and acts to push out the air at the center of the rectangular body to the outside. Further, the second adhesive 61 is disposed corresponding to each corner of the rectangular body of the semiconductor chip 8. Accordingly, in combination with the radial spread of the first adhesive 60, the second adhesive 61 spreads in the circumferential direction in each region, and the air pushed out from the center of the rectangular body is pushed out from the three directions in each region. As a result, air is pushed out in the radial direction, and voids are hardly generated in the adhesive 7. As a result, the adhesive 7 connecting the semiconductor chip 8 and the first electrode plate 25 has a uniform thickness and does not include voids.

つぎに、図１６及び図１７に示すように、半導体チップ８等を含む部分を覆うように封止体２を形成する（Ｓ０５）。封止体２の形成は、例えば、トランスファモールディング装置によって形成する。図１６は封止体２を含む部分の模式的平面図であり、図１７は裏返し状態の模式的断面図である。封止体２は第２のリードフレーム４０のダム片４３よりも先端側に設けられる。また、封止体２の縁は第１のリードフレーム２０のスリット６に沿って延在するように形成される。封止体２の表面には、図１６に示すように、方向識別用の円形窪みからなるインデックス１０が設けられる。   Next, as shown in FIGS. 16 and 17, the sealing body 2 is formed so as to cover the portion including the semiconductor chip 8 and the like (S05). For example, the sealing body 2 is formed by a transfer molding apparatus. 16 is a schematic plan view of a portion including the sealing body 2, and FIG. 17 is a schematic cross-sectional view in an inverted state. The sealing body 2 is provided on the tip side of the dam piece 43 of the second lead frame 40. Further, the edge of the sealing body 2 is formed so as to extend along the slit 6 of the first lead frame 20. As shown in FIG. 16, the surface of the sealing body 2 is provided with an index 10 composed of a circular depression for direction identification.

つぎに、第１のリードフレーム２０及び第２のリードフレーム４０の不要部分を切断除去するとともに、所定のリードの成形を行って図１８及び図１９に示すようなパワーＭＯＳＦＥＴ装置１を製造する（Ｓ０６）。即ち、第１のリードフレーム２０においては支持片２３を所定箇所で切断し、第２のリードフレーム４０においてはダム片４３を切断除去するとともに支持片４５及びリード４ａ，５ａを所定箇所で切断する。また成形においてはリード４ａ，５ａを階段状に折り曲げ加工して表面実装型の半導体装置に形成する。   Next, unnecessary portions of the first lead frame 20 and the second lead frame 40 are cut and removed, and predetermined leads are formed to manufacture the power MOSFET device 1 as shown in FIGS. S06). That is, in the first lead frame 20, the support piece 23 is cut at a predetermined location, and in the second lead frame 40, the dam piece 43 is cut and removed, and the support piece 45 and the leads 4a and 5a are cut at a predetermined location. . In molding, the leads 4a and 5a are bent in a step shape to form a surface mount type semiconductor device.

本実施例１の半導体装置の製造方法によれば、四角形体の半導体チップ８の第２の面に接着剤を多点状に塗布する際、前記四角形体の中心に第１の接着剤６０を塗布し、前記第１の接着剤６０の周囲に複数の第２の接着剤６１を塗布し、かつ第１の接着剤６０の直径は第２の接着剤６１よりも大きくしてある。従って、第１のリードフレーム２０の第１の電極板２５を半導体チップ８に押し付けた際広がる多点状に配置される接着剤（第１・第２の接着剤６０，６１）は、四角形体の中心から周囲に広がり、四角形体の中心の空気を外部に押し出すように作用する。また、第２の接着剤６１は半導体チップ８の四角形体の各角に対応して配置されている。従って、第１の接着剤６０の半径方向の広がりと相俟って第２の接着剤６１は各領域で円周方向に広がり、四角形体の中心から押し出される空気を各領域で３方向から押し出して空気を半径方向に押し出すことになり、接着剤７内にボイドが発生し難くなる。この結果、半導体チップ８と第１の電極板２５を接続する接着剤７は均一な厚さになるとともにボイドを含まないようになることから、伝熱特性も良好になり、放熱性が向上し、電気特性が安定した信頼性の高い半導体装置１とすることができる。   According to the manufacturing method of the semiconductor device of the first embodiment, when the adhesive is applied to the second surface of the rectangular semiconductor chip 8 in a multipoint manner, the first adhesive 60 is applied to the center of the rectangular body. The plurality of second adhesives 61 are applied around the first adhesive 60, and the diameter of the first adhesive 60 is larger than that of the second adhesive 61. Therefore, the adhesives (first and second adhesives 60 and 61) arranged in a multipoint shape that spread when the first electrode plate 25 of the first lead frame 20 is pressed against the semiconductor chip 8 are rectangular bodies. It spreads from the center of the center to the periphery and acts to push out the air at the center of the rectangular body to the outside. Further, the second adhesive 61 is disposed corresponding to each corner of the rectangular body of the semiconductor chip 8. Accordingly, in combination with the radial spread of the first adhesive 60, the second adhesive 61 spreads in the circumferential direction in each region, and the air pushed out from the center of the rectangular body is pushed out from the three directions in each region. As a result, air is pushed out in the radial direction, and voids are hardly generated in the adhesive 7. As a result, the adhesive 7 connecting the semiconductor chip 8 and the first electrode plate 25 has a uniform thickness and does not include voids, so that heat transfer characteristics are improved and heat dissipation is improved. Thus, a highly reliable semiconductor device 1 with stable electrical characteristics can be obtained.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。実施例では、パワーＭＯＳＦＥＴを半導体チップに組み込んだ例を示したが、組み込む素子としてはＭＩＳＦＥＴ，パワーバイポーラトランジスタ，ＩＧＢＴ等のトランジスタ、あるいはトランジスタを含むＩＣでもよい。   The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. In the embodiment, an example in which a power MOSFET is incorporated in a semiconductor chip is shown. However, as an element to be incorporated, a transistor such as a MISFET, a power bipolar transistor, or an IGBT, or an IC including a transistor may be used.

本発明の実施例１である半導体装置の製造方法の一部を示す模式的平面図である。It is a schematic plan view which shows a part of manufacturing method of the semiconductor device which is Example 1 of this invention. 実施例１の半導体装置の製造方法を示すフローチャートである。3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. 実施例１の半導体装置の製造に用いる第２のリードフレームの平面図である。4 is a plan view of a second lead frame used for manufacturing the semiconductor device of Example 1. FIG. 前記第２のリードフレームの一部を示す拡大平面図である。FIG. 6 is an enlarged plan view showing a part of the second lead frame. 実施例１の半導体装置の製造に用いる第１のリードフレームの平面図である。3 is a plan view of a first lead frame used for manufacturing the semiconductor device of Example 1. FIG. 前記第１のリードフレームの一部を示す拡大平面図である。FIG. 3 is an enlarged plan view showing a part of the first lead frame. 前記第２のリードフレームに第１の面を介して半導体チップを固定する状態を示す模式的拡大平面図である。FIG. 6 is a schematic enlarged plan view showing a state in which a semiconductor chip is fixed to the second lead frame via a first surface. 前記第２のリードフレームに固定された半導体チップの第２の面に接着剤を塗布した状態を示す模式的拡大平面図である。FIG. 6 is a schematic enlarged plan view showing a state in which an adhesive is applied to a second surface of a semiconductor chip fixed to the second lead frame. 前記第２のリードフレームに固定された半導体チップの第２の面に接着剤を塗布した状態を示す模式的拡大断面図である。FIG. 6 is a schematic enlarged cross-sectional view showing a state where an adhesive is applied to a second surface of a semiconductor chip fixed to the second lead frame. 前記接着剤の塗布を行うディスペンサーを示す模式的斜視図である。It is a typical perspective view which shows the dispenser which apply | coats the said adhesive agent. 前記ディスペンサーのノズル端を示す模式的平面図である。It is a typical top view which shows the nozzle end of the said dispenser. 前記ディスペンサーによる半導体チップへの接着剤の塗布作業状態と、半導体チップの第２の面に第２のリードフレームを固定する作業状態を示す模式図である。It is a schematic diagram which shows the application | coating operation state of the adhesive agent to a semiconductor chip by the said dispenser, and the operation | work state which fixes a 2nd lead frame to the 2nd surface of a semiconductor chip. 前記半導体チップへの接着剤の塗布から、半導体チップに第２のリードフレームを固定するまでの間における接着剤の広がり変化を示す模式図である。It is a schematic diagram showing a change in the spread of the adhesive from the application of the adhesive to the semiconductor chip until the second lead frame is fixed to the semiconductor chip. 前記半導体チップに第２のリードフレームが固定された状態を示す一部の模式的拡大平面図である。FIG. 4 is a partial schematic plan view showing a state in which a second lead frame is fixed to the semiconductor chip. 前記半導体チップに第２のリードフレームが固定された状態を示す一部の模式的拡大断面図である。FIG. 6 is a partial schematic enlarged cross-sectional view showing a state in which a second lead frame is fixed to the semiconductor chip. 前記半導体チップや前記リードフレームの一部等を封止体で封止した状態を示す一部の模式的拡大平面図である。It is a partial schematic plan view showing a state in which a part of the semiconductor chip, the lead frame, and the like are sealed with a sealing body. 図１６の裏返し状態の模式的拡大断面図である。It is a typical expanded sectional view of the reverse state of FIG. 前記リードフレームの不要部分の切断除去と、リードの成形を行って実施例１の半導体装置を製造した状態を示す模式的拡大平面図である。FIG. 6 is a schematic enlarged plan view showing a state where the semiconductor device of Example 1 is manufactured by cutting and removing unnecessary portions of the lead frame and forming the leads. 前記リードフレームの不要部分の切断除去と、リードの成形を行って実施例１の半導体装置を製造した状態を示す模式的拡大断面図である。FIG. 5 is a schematic enlarged cross-sectional view showing a state where the semiconductor device of Example 1 is manufactured by cutting and removing unnecessary portions of the lead frame and forming the leads. 本発明に先立って検討した半導体装置の製造における半導体チップの第２の面への接着剤による第２のリードフレームの固定方法と、前記固定時の接着剤の広がり変化を示す模式図である。It is a schematic diagram showing a method for fixing the second lead frame to the second surface of the semiconductor chip in the manufacture of the semiconductor device examined prior to the present invention, and a change in the spread of the adhesive during the fixing. 前記接着剤の塗布を行うディスペンサーのノズル端部分と、ノズル端面を示す模式図である。It is a schematic diagram which shows the nozzle end part and nozzle end surface of a dispenser which apply | coat the said adhesive agent.

符号の説明Explanation of symbols

１…半導体装置（パワーＭＯＳＦＥＴ装置）、２…封止体（パッケージ）、３…ドレイン電極板、３ａ…鍔部、３ｂ…第１の電極板、４…ソースリード、４ａ…リード、５…ゲートリード、５ａ…リード、６…スリット、７…接着剤、８…半導体チップ、９…金バンプ電極、１０…インデックス、２０…第１のリードフレーム、２１…外枠、２２…横枠、２３…支持片、２４…スリット、２５…電極版、２７…ガイド孔、４０…第２のリードフレーム、４１…外枠、４２…横枠、４３…ダム片、４４…接続部、４５…支持片、４６…スリット、５０…接続部、５５…ガイド孔、６０…第１の接着剤、６１…第２の接着剤、６５…ディスペンサー、６６…コントロールボックス、６７…チューブ、６８…シリンジ、６９…ニードル、７０…補助のシリンジ、７１…第１のニードル、７２…第２のニードル、７５…ヒートスプレッダ押さえ用コレット、９０…半導体チップ、９１…電極板、９２…接着剤、９３…シリンジ、９４…ニードル、９５…ボイド   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device (power MOSFET device), 2 ... Sealing body (package), 3 ... Drain electrode plate, 3a ... Gutter part, 3b ... 1st electrode plate, 4 ... Source lead, 4a ... Lead, 5 ... Gate Lead, 5a ... Lead, 6 ... Slit, 7 ... Adhesive, 8 ... Semiconductor chip, 9 ... Gold bump electrode, 10 ... Index, 20 ... First lead frame, 21 ... Outer frame, 22 ... Horizontal frame, 23 ... Support piece, 24 ... slit, 25 ... electrode plate, 27 ... guide hole, 40 ... second lead frame, 41 ... outer frame, 42 ... horizontal frame, 43 ... dam piece, 44 ... connection part, 45 ... support piece, 46 ... slit, 50 ... connecting portion, 55 ... guide hole, 60 ... first adhesive, 61 ... second adhesive, 65 ... dispenser, 66 ... control box, 67 ... tube, 68 ... syringe, 69 ... needle , 70 ... Auxiliary Syringe, 71 ... first needle, 72 ... second needle, 75 ... heat spreader retainer collet, 90 ... semiconductor chip, 91 ... electrode plate, 92 ... adhesive, 93 ... syringe, 94 ... needle, 95 ... void

Claims (5)

いずれも四角形体となる半導体チップまたは第１の電極板のいずれか一方の面に多点状に接着剤を塗布する工程と、
前記接着剤を塗布した面に前記半導体チップまたは前記第１の電極板を所定の荷重を掛けて重ねかつ前記接着剤を硬化処理して前記半導体チップと前記第１の電極板を接続する工程とを有する半導体装置の製造方法であって、
前記接着剤の塗布において、前記四角形体の中心に第１の接着剤を塗布し、前記第１の接着剤の周囲に複数の第２の接着剤を塗布し、
前記第１の接着剤の直径は前記第２の接着剤よりも大きくすることを特徴とする半導体装置の製造方法。 A step of applying an adhesive in a multipoint manner to either one of the surface of the semiconductor chip or the first electrode plate, both of which are rectangular bodies;
A step of stacking the semiconductor chip or the first electrode plate on a surface to which the adhesive has been applied by applying a predetermined load and curing the adhesive to connect the semiconductor chip and the first electrode plate; A method of manufacturing a semiconductor device having
In the application of the adhesive, a first adhesive is applied to the center of the rectangular body, a plurality of second adhesives are applied around the first adhesive,
A method of manufacturing a semiconductor device, wherein the diameter of the first adhesive is larger than that of the second adhesive. 前記第２の接着剤は前記四角形体の各角に対応して配置されていることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second adhesive is arranged corresponding to each corner of the rectangular body. 前記複数の第２の接着剤は前記第１の接着剤に対して点対称に配置されていることを特徴とする半導体装置の製造方法。   The method of manufacturing a semiconductor device, wherein the plurality of second adhesives are arranged point-symmetrically with respect to the first adhesive. 前記接着剤としてＡｇペーストを用いることを特徴とする半導体装置の製造方法。   A method of manufacturing a semiconductor device, wherein an Ag paste is used as the adhesive. 表裏面である上面と下面を有し、前記上面と前記下面を繋ぐ側面を有する絶縁性樹脂からなる封止体と、
前記封止体内に位置し、第１の面に第１電極及び制御電極を有し、前記第１の面の裏面になる第２の面に第２電極を有する半導体チップと、
表裏面である上面と下面を有し、下面は前記封止体の下面に露出し、前記封止体内に位置する上面は接着剤を介して前記半導体チップの第２電極に接続される第１の電極板と、 表裏面である上面と下面を有し、前記封止体の内外に亘って延在し、前記封止体内の前記半導体チップの第１電極に接続される第２の電極板と、
表裏面である上面と下面を有し、前記封止体の内外に亘って延在し、前記封止体内の前記半導体チップの制御電極に接続される第３の電極板とを有する半導体装置の製造方法であって、
前記第１の電極板を有する第１のリードフレーム、前記第２及び前記第３の電極板を有する第２のリードフレームを用意する工程と、
前記第２のリードフレームの前記第２及び前記第３の電極板に前記半導体チップの前記第１電極及び制御電極を電気的に接続する工程と、
前記半導体チップの前記第２電極上に接着剤を多点状に塗布した後、前記第１のリードフレームの前記第１の電極板を所定の荷重を掛けて重ね合わせ、かつ前記接着剤を硬化処理して前記第２電極を前記第１の電極板に電気的に接続する工程と、
前記半導体チップ、第１及び第２のリードフレームの所定部を絶縁性の樹脂で封止する工程と、
前記第１及び第２のリードフレームの不要部分を切断除去する工程とを有し、
前記接着剤の塗布において、前記四角形体の中心に第１の接着剤を塗布し、前記第１の接着剤の周囲に複数の第２の接着剤を塗布し、
前記第１の接着剤の直径は前記第２の接着剤よりも大きくすることを特徴とする半導体装置の製造方法。 A sealing body made of an insulating resin having an upper surface and a lower surface, which are front and back surfaces, and a side surface connecting the upper surface and the lower surface;
A semiconductor chip located in the encapsulant, having a first electrode and a control electrode on a first surface, and having a second electrode on a second surface which is the back surface of the first surface;
The upper surface and the lower surface are front and back surfaces, the lower surface is exposed on the lower surface of the sealing body, and the upper surface located in the sealing body is connected to the second electrode of the semiconductor chip via an adhesive. A second electrode plate having an upper surface and a lower surface that are front and back surfaces, extending over the inside and outside of the sealing body, and connected to the first electrode of the semiconductor chip in the sealing body When,
A semiconductor device having an upper surface and a lower surface that are front and back surfaces, a third electrode plate extending over the inside and outside of the sealing body and connected to a control electrode of the semiconductor chip in the sealing body A manufacturing method comprising:
Preparing a first lead frame having the first electrode plate and a second lead frame having the second and third electrode plates;
Electrically connecting the first electrode and the control electrode of the semiconductor chip to the second and third electrode plates of the second lead frame;
After applying an adhesive on the second electrode of the semiconductor chip in a multipoint manner, the first electrode plate of the first lead frame is overlaid with a predetermined load, and the adhesive is cured. Processing to electrically connect the second electrode to the first electrode plate;
Sealing predetermined portions of the semiconductor chip and the first and second lead frames with an insulating resin;
Cutting and removing unnecessary portions of the first and second lead frames,
In the application of the adhesive, a first adhesive is applied to the center of the rectangular body, a plurality of second adhesives are applied around the first adhesive,
A method of manufacturing a semiconductor device, wherein the diameter of the first adhesive is larger than that of the second adhesive.
JP2004008223A 2004-01-15 2004-01-15 Semiconductor device Pending JP2005203557A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009048214A (en) * 2005-11-29 2009-03-05 Seiko Instruments Inc Method for producing display arrangement, and lamination method
JP2012234910A (en) * 2011-04-28 2012-11-29 Toshiba Corp Semiconductor device and manufacturing method of the same
EP3703109A4 (en) * 2017-10-23 2022-02-16 Hitachi Chemical Company, Ltd. Member connection method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009048214A (en) * 2005-11-29 2009-03-05 Seiko Instruments Inc Method for producing display arrangement, and lamination method
JP2012234910A (en) * 2011-04-28 2012-11-29 Toshiba Corp Semiconductor device and manufacturing method of the same
EP3703109A4 (en) * 2017-10-23 2022-02-16 Hitachi Chemical Company, Ltd. Member connection method
US11887960B2 (en) 2017-10-23 2024-01-30 Resonac Corporation Member connection method

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