JP4453009B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a product structure for reducing the size of a semiconductor device, a semiconductor device whose package matches or approximates the size of a semiconductor chip, a so-called chip size package (hereinafter referred to as CSP) is known (for example, Patent Documents 1 and 2). .

  In Patent Document 1, a silicon wafer and a multilayer wiring board are bonded by a bump bonding method, and an epoxy resin is injected into a gap between the wafer and the multilayer wiring board from a through-hole of the multilayer wiring board by a nozzle, and then heated and cured. A method of manufacturing a CSP type semiconductor device by cutting a wafer and a multilayer wiring board into individual chips by dicing is described.

  In Patent Document 2, an interposer equivalent to or smaller than a chip is stacked only on a non-defective semiconductor chip of a semiconductor wafer, an inner bump of the interposer and an electrode of the non-defective semiconductor chip are joined, and the semiconductor wafer is separated to obtain an LGA (Land Grid Array). A method of manufacturing a type semiconductor device is described. This document also describes that a BGA (Ball Grid Array) type semiconductor device can be manufactured by a similar manufacturing method.

JP 2000-150549 A JP 2002-110856 A

  In the present applicant, the semiconductor device having the CSP structure, the LGA structure, and the BGA structure is further reduced in thickness and size. In a structure in which a semiconductor chip or a semiconductor wafer and a wiring board or interposer (wiring board structure) are stacked as in the conventional structure, it is difficult to reduce the thickness because the wiring board or interposer is thick. In addition, since the cost of the wiring board is high, a semiconductor device using the wiring board has a high product cost.

An object of the present invention is to provide a thin semiconductor device and a manufacturing method thereof.
An object of the present invention is to provide a semiconductor device capable of reducing the manufacturing cost and a manufacturing method thereof.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) The semiconductor device
A semiconductor chip having a first surface having an electrode, a second surface opposite to the first surface, and a plurality of side surfaces connecting these surfaces;
A first surface is connected to the first surface of the semiconductor chip via an insulating adhesive, and a second surface opposite to the first surface is partially removed by a predetermined thickness. A plurality of electrode plates having a first part that is thinner and a second part that is thicker than the first part;
A conductive wire connecting the second surface of the first part and the electrode of the semiconductor chip;
A first body of the semiconductor chip, a first body of the electrode plate and a sealing body made of an insulating resin covering the wire,
The second surface of the second part of the electrode plate is exposed from the sealing body.

  A conductive film is formed on the second surface of the second part of the electrode plate. The surface of the sealing body located between the electrode plates has a structure that does not protrude from the second surface of the second part of the electrode plate or the surface of the coating provided on the second surface. Yes. The electrode plate is made of, for example, 42 alloy material having a thickness of 0.125 mm.

Such a semiconductor device is
Preparing a semiconductor wafer having circuit elements arranged in vertical and horizontal directions and having electrodes of the circuit elements on a first surface;
A lead plate comprising a metal plate having a first surface and a second surface opposite to the first surface, the lead pattern comprising a plurality of leads provided corresponding to the circuit elements; The first surface of the semiconductor wafer is a flat surface bonded to the first surface of the semiconductor wafer, and the lead is partially thinned by removing the predetermined thickness of the second surface from the first portion and the first portion. Preparing a lead frame to be a thick second part;
Positioning the lead frame on the first surface side of the semiconductor wafer, and connecting the first surface of the lead frame to the semiconductor wafer with an insulating adhesive;
Connecting the electrode of the circuit element and the second surface of the first part of the lead with a conductive wire;
A second surface of the second part of the lead is exposed, and a resin layer is formed by covering the electrode, the wire, the first part of the lead, and the exposed first surface of the semiconductor wafer with an insulating resin. Process,
Applying a tape to the entire exposed surface of the semiconductor wafer or the lead frame;
Grooves that reach the surface of the tape are formed vertically and horizontally in the lead frame and the semiconductor wafer so as to divide the circuit elements, and each lead is formed on an independent electrode plate connected to the electrodes by this groove formation. Process,
And the step of removing the tape.

  In the step of preparing the lead frame, a lead frame in which a conductive film is formed on the second surface of the second part of the lead is prepared. In the wire connecting step, the height of the wire is formed lower than the second surface of the second part of the lead, and in the step of forming the resin layer, the height of the resin layer is set to the height of the resin layer. The lead is formed lower than the second surface of the second part. The lead frame is made of 42 alloy material having a thickness of 0.125 mm, for example.

(2) The semiconductor device
A semiconductor chip having a first surface having an electrode, a second surface opposite to the first surface, and a plurality of side surfaces connecting these surfaces;
A first surface is disposed on the first surface of the semiconductor chip with a predetermined gap therebetween, and a protruding portion protruding from the first surface is connected to the electrode of the semiconductor chip, and the first surface A plurality of electrode plates having a first portion that is thinned by removing a predetermined thickness of a second surface that is the opposite surface, and a second portion that is thicker than the first portion;
A sealing body made of an insulating resin that covers the first surface of the semiconductor chip and the electrode plate and embeds the gap between the semiconductor chip and the electrode plate;
The second surface of the second part of the electrode plate is exposed from the sealing body.

  In addition, a conductive film is formed on the second surface of the second part of the electrode plate. The surface of the sealing body located between the electrode plates has a structure that does not protrude from the second surface of the second part of the electrode plate or the surface of the coating provided on the second surface. Yes. The electrode plate is made of, for example, 42 alloy material having a thickness of 0.125 mm. Moreover, the clearance gap between a semiconductor chip and an electrode plate can be 0.05 mm, for example.

Such a semiconductor device is
Preparing a semiconductor wafer having circuit elements arranged in vertical and horizontal directions and having electrodes of the circuit elements on a first surface;
A lead plate comprising a metal plate having a first surface and a second surface opposite to the first surface, the lead pattern comprising a plurality of leads provided corresponding to the circuit elements; The first surface of the lead is a flat surface, and the lead is a first portion where the second surface is partially removed by a predetermined thickness to become thin, and a second portion which is thicker than the first portion. Part of preparing a lead frame corresponding to the electrode;
The lead frame is positioned so as to have a predetermined gap on the first surface side of the semiconductor wafer, and the first portion corresponding to the electrode of the lead of the lead frame is melted by laser light irradiation to project the protruding portion. And connecting the protrusion to the electrode;
Exposing a second surface of the second portion of the lead, covering the electrode, the first portion of the lead, and the exposed first surface of the semiconductor wafer with an insulating resin, and forming a resin layer;
Applying a tape to the entire exposed surface of the semiconductor wafer or the lead frame;
Grooves that reach the surface of the tape are formed vertically and horizontally in the lead frame and the semiconductor wafer so as to divide the circuit elements, and each lead is formed on an independent electrode plate connected to the electrodes by this groove formation. Process,
A plurality of semiconductor devices are manufactured by the step of removing the tape. In the step of preparing the lead frame, a lead frame is prepared in which a conductive film is formed on the second surface of the second part of the lead. In the wire connecting step, the height of the wire is formed lower than the second surface of the second part of the lead, and in the step of forming the resin layer, the height of the resin layer is set to the height of the resin layer. The lead is formed lower than the second surface of the second part. The lead frame is made of 42 alloy material having a thickness of 0.125 mm, for example. Further, the gap between the semiconductor chip and the electrode plate is as thin as 0.05 mm, for example.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means (1), (a) an electrode plate made of a metal plate is bonded to a semiconductor chip via an adhesive, and the sum of the thicknesses of the electrode plate, the adhesive and the semiconductor chip is the height of the semiconductor device. Therefore, the semiconductor device can be thinned. That is, the metal plate is 0.125 mm, and can be made thinner than a thick wiring board that is generally at least 0.2 mm.

  (B) Since the planar size of the semiconductor device is the size of the semiconductor chip itself, it becomes a CSP structure and the semiconductor device can be miniaturized.

(C) In the semiconductor device, the lead frame and the semiconductor wafer are bonded together, the thin first part of the lead constituting the lead pattern of the lead frame is connected to the electrode of the semiconductor wafer with a wire, and the first surface side of the semiconductor wafer is Cover each lead and the second surface side of the first part with an insulating resin layer, then cut the semiconductor wafer and the lead frame supported by the tape so that they reach the surface on the tape bonding side. Is a method of manufacturing a plurality of semiconductor devices by making the electrode plates electrically independent of each other and then peeling off the tape, so that the manufacturing cost of the semiconductor device can be reduced by simplifying the manufacturing process.
According to the means of (2), (a) the electrode of the semiconductor chip is connected via a protruding portion formed by laser beam irradiation of an electrode plate made of a metal plate, and the thickness of the electrode plate and the semiconductor chip is Since the thickness of the semiconductor device is the sum of the sum and the thickness of the resin embedded in the gap between the electrode plate and the semiconductor chip, the thickness of the semiconductor device can be achieved. That is, the metal plate is 0.125 mm, which can be made thinner than a thick wiring board, which is generally at least 0.2 mm, and the semiconductor device can be made thinner. Further, since the gap for obtaining electrical insulation by resin filling is as narrow as 0.05 mm, the semiconductor device can be thinned.

  (B) Since the planar size of the semiconductor device is the size of the semiconductor chip itself, it becomes a CSP structure and the semiconductor device can be miniaturized.

  (C) The semiconductor device is integrated by connecting the thin first part of the lead of the lead frame to the electrode of the semiconductor wafer by laser light irradiation, and between the leads on the first surface side of the semiconductor wafer, the first part of the lead The second surface side and the gap between the semiconductor wafer and the lead frame are covered (embedded) with an insulating resin layer, and then the semiconductor wafer and the lead frame supported by the tape reach the surface on the tape bonding side. It is a method of manufacturing a plurality of semiconductor devices by cutting and forming each lead in an electrically independent state to form an electrode plate, and then peeling off the tape. Reduction can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

  1 to 14 are diagrams related to the semiconductor device according to the first embodiment of the present invention. 1 to 5 are diagrams related to the structure of the semiconductor device, FIG. 6 is a cross-sectional view showing a mounting state of the semiconductor device, and FIGS. 7 to 14 are diagrams related to a method for manufacturing the semiconductor device.

The semiconductor device 1 according to the first embodiment has a structure as shown in FIGS. 1 is a perspective view of the semiconductor device, FIG. 2 is a plan view of the semiconductor device, and FIG. 3 is a cross-sectional view taken along line AA of FIG.
As shown in the perspective view of FIG. 1, the semiconductor device 1 according to the first embodiment is externally a flat hexahedron (cuboid), the upper portion is formed of the semiconductor chip 2, and the lower portion is made of an insulating resin. A stationary body 3 and a plurality of electrode plates 4 are formed. The electrode plate 4 has a structure in which side surfaces are exposed at a predetermined pitch on both side surfaces of the sealing body 3. This is because, in the manufacture of the semiconductor device 1, the semiconductor wafer is cut into the semiconductor chip 2, the lead of the lead frame is cut into the electrode plate 4, and the resin layer is cut into the sealing body 3. In Example 1, four electrode plates 4 are arranged on each side of the sealing body 3. A pair of end faces of the semiconductor device 1 are formed by a semiconductor chip 2 and a sealing body 3 as shown in FIG.

  The lower surface of the electrode plate 4 is exposed on the lower surface of the sealing body 3 as shown in FIGS. 3 and 4. Each electrode plate 4 is formed from leads of a lead frame made of a single flat metal plate. In the formed state, as shown in FIG. 3, the thick part (second part) is thick. 6 and a thin-walled portion (first portion) 5 that is continuous with the thick-walled portion 6 and has a small plate thickness. Cutting is performed at the thick portion 6. The first surface 4a of the electrode plate 4 (the surface that becomes the upper surface in FIG. 3) is a flat surface, and is adhered to the first surface 2a of the semiconductor chip 2 (the surface that becomes the lower surface in FIG. 3) by the insulating adhesive 7. Has been.

  The second surface 4b (the surface that is the lower surface in FIG. 3) that is the opposite surface of the first surface 4a of the electrode plate 4 is because the electrode plate 4 becomes a thick portion 6 and a thin portion 5 that is continuous with the thick portion 6. There are two steps with steps. The second surface 4b of the thin portion 5 is a recessed surface with respect to the second surface 4b of the thick portion 6, and is buried in the resin forming the sealing body 3. That is, each electrode plate 4 has a structure in which the thin portion 5 is buried in the sealing body 3. Therefore, as shown in FIG. 4, the thick portion 6 is exposed on the lower surface of the semiconductor device 1 and constitutes the external electrode terminal 11. The external electrode terminals 11 are arranged at a predetermined pitch along both sides of the rectangular sealing body 3.

  On the other hand, the second surface 4 b of the buried thin part 5 and the electrode 8 provided on the first surface 2 a of the semiconductor chip 2 are electrically connected by a conductive wire 9. In the first embodiment, the semiconductor chip 2 has a center pad structure in which two rows of electrodes are arranged on the center side of the chip. Therefore, most of the electrode plates 4 are bent as shown in FIGS. 2 and 5 so that the tip portions of the thin portions 5 of the electrode plates 4 buried in the sealing body 3 face the electrodes 8 respectively. Yes. FIG. 5 is a view in which the sealing body 3 is partially removed to make it easy to understand the shape of the electrode plate 4 and the connection state of the wires 9. In this figure, the hatched part is the thick part 6, which is the part that forms the external electrode terminal. As shown only in FIG. 3, when it is difficult to directly connect an Au wire or the like to the electrode plate 4, the plating film 12 is formed in order to improve the wire connectivity. In the first embodiment, for example, the electrode plate 4 uses 42 alloy. In this case, an Ag plating film 12 having a thickness of 2 to 3 μm is formed on the second surface 4 b of the thin portion 5 of the electrode plate 4 in order to improve the wire connectivity.

  The wire 9 is buried in the sealing body 3. For this reason, the wire 9 is also bonded in a low loop shape. The thickness of the thick part 6 is, for example, 125 μm, and the thickness of the thin part 5 is, for example, 60 μm. A coating 10 made of a metal having good wettability with a bonding material used during mounting is formed on the second surface 4b of the thick portion 6 exposed on the surface (lower surface) of the sealing body 3. . The film 10 is formed of, for example, an Au plating film having a thickness of 0.03 to 0.7 μm.

  On the other hand, the semiconductor chip 2 forming the upper part of the semiconductor device 1 is made of, for example, a silicon substrate. Therefore, the upper surface of the semiconductor device 1 is formed by the second surface 2b which is the opposite surface of the first surface 2a of the semiconductor chip 2, and is constituted by a flat silicon substrate surface. Further, the surface 3a (lower surface in FIG. 3) 3a of the sealing body 3 forming the lower surface side of the semiconductor device 1 is the same as or retracted from the second surface 4b of the thick portion 6 of the electrode plate 4. The surface 3a is formed from the second surface 4b of the thick wall portion 6 by performing sheet molding for arranging a sheet on the second surface 4b side of the electrode plate 4 when the sealing body 3 is formed by the transfer molding method. Can also be a recessed surface.

  The height (thickness) of the semiconductor device 1 is the sum of the thickness of the semiconductor chip 2, the thickness of the electrode plate 4, the thickness of the adhesive 7 connecting the semiconductor chip 2 and the electrode plate 4, and the thickness of the coating 10. Thus, the semiconductor device 1 can be thinned. For example, the thickness of the semiconductor chip 2 is about 50 to 200 μm, the thickness of the electrode plate 4 is 125 μm, the adhesive 7 is 50 μm, and the coating 10 is 0.03 to 0.7 μm. Therefore, the semiconductor device 1 has a thickness of 0.225 mm to 0.376 mm, and is thin. Since the generally used wiring board is 0.2 mm even if it is thin, the semiconductor device 1 according to the first embodiment using the electrode plate 4 having a thickness of 125 μm can be thinned. By further reducing the thickness of the electrode plate 4, the semiconductor device 1 can be further reduced in thickness.

  Further, the size of the semiconductor device 1 in the planar direction is the size of the semiconductor chip 2, a CSP structure, and a small size. As shown in FIG. 3, the semiconductor device 1 has an LGA (Land Grid Array) structure in which the lower surface of the electrode plate 4 is exposed on the lower surface of the sealing body 3.

  FIG. 6 shows a state in which the semiconductor device 1 is mounted on the mounting substrate 15. A plurality of lands 16 are provided on the upper surface of the mounting substrate 15. The lands 16 are arranged corresponding to the external electrode terminals 11 formed by the exposed electrode plate portion of the semiconductor device 1. In mounting the semiconductor device 1, a bonding material 17 such as solder is provided in advance on the land 16 of the mounting substrate 15 by a method such as printing. Thereafter, the semiconductor device 1 is placed on the mounting substrate 15 by positioning so that the external electrode terminal 11 is placed on the land 16. Next, the bonding material 17 is melted by temporary heating (reflow), and the land 16 and the external electrode terminal 11 are connected by the bonding material 17. As a result, the semiconductor device 1 is mounted on the mounting substrate 15.

  In the mounting substrate 15, since the semiconductor device 1 has a CSP structure and is small, a mounting area is reduced. As a result, the mounting substrate can be reduced in size, and the electronic device in which the mounting substrate is incorporated can be reduced in size. Further, in the case of an electronic device in which a large number of semiconductor devices 1 are mounted, the area of a vacant area that is not used increases due to a reduction in the mounting area of the semiconductor device 1. Therefore, it is possible to mount the semiconductor device 1 and other electronic components in the empty area. As a result, it is possible to achieve further multi-functionality and performance improvement of the electronic device.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. In the manufacture of the semiconductor device 1, as shown in FIGS. 7A, 7B and 8, the semiconductor wafer 20 and the lead frame 21 are prepared, and the first surface 20a of the semiconductor wafer 20 is insulatively bonded. The first surface 21a of the lead frame 21 is pasted with the agent 7 (adhesion).

  The semiconductor wafer 20 is made of, for example, a silicon substrate, and circuit elements are already formed. Here, the circuit element is a circuit in which one or a plurality of active elements such as transistors are formed, and is an entire circuit formed on a semiconductor chip. In the figure, circuit elements are not shown and omitted, but FIG. 10 shows the electrodes 8 of the circuit elements. The electrode 8 has a center pad structure in which four electrodes are arranged in two rows on the center side of the circuit element. As shown in FIG. 8, the semiconductor wafer 20 has an orientation flat 20c in which one edge is cut out in a straight line, and a plurality of circuit elements are arranged vertically and horizontally with reference to the orientation flat 20c.

  The lead frame 21 has a structure in which a thin rectangular metal plate is patterned by precision pressing or etching, and lead patterns 21c are arranged in a vertical and horizontal manner. That is, as shown in FIG. 8, the lead frame 21 has a matrix lead frame structure in which lead patterns 21c are arranged corresponding to the circuit elements that can be manufactured by the semiconductor wafer 20. Since the lead pattern 21 c is arranged corresponding to the circuit element capable of manufacturing the semiconductor wafer 20, one side of the lead frame 21 is a square plate that substantially matches the diameter of the semiconductor wafer 20.

  As shown in FIG. 8, the lead frame 21 has a structure in which a horizontal frame 21d extending in parallel to the orientation flat 20c is provided at a predetermined interval, and a vertical frame 21e orthogonal to the horizontal frame 21d is provided at a predetermined interval. It has become. Then, a rectangular frame 21f formed by a pair of adjacent horizontal frames 21d, a pair of adjacent vertical frames 21e orthogonal to these horizontal frames 21d, and a rectangular frame from the edges of the pair of vertical frames 21e constituting the rectangular frame 21f A lead pattern 21c is formed by four leads 21h extending inward of 21f. FIG. 9 shows an enlarged unit lead pattern 21c. The horizontal frame 21d and the vertical frame 21e constitute a rectangular frame 21f of another adjacent lead pattern 21c.

  In the latter half of the manufacturing process of the semiconductor device 1, the lead 21 h is cut to form the electrode plate 4 having the thin portion 5 and the thick portion 6. Therefore, at the stage of the lead frame 21, the lead 21 h has a structure including the thick portion 6 and the thin portion 5 connected to the thick portion 6.

  The lead 21h extends from the inner edge of the vertical frame 21e along the horizontal frame 21d, and, as shown in FIG. 10, the tip is bent as necessary to face a predetermined electrode 8 of the circuit element. Is formed. The lead frame 21 is formed of, for example, a 42 alloy plate having a thickness of 125 μm, and the horizontal frame 21d, the vertical frame 21e, and the leads 21h have a width of 70 to 150 μm. Further, as shown in FIGS. 9 and 7B, the tip portion of each lead 21h is the thin portion 5 as described above. In the middle part of each lead 21h, the tip side becomes the thin portion 5 with respect to the line parallel to the vertical frame 21e.

  In the lead frame 21, the coating 10 is formed on the second surface 21 b corresponding to the thick portion 6. Further, although not shown, an Ag plating film is formed on the second surface 21b of the thin portion 5 to a thickness of 2 to 3 μm in order to improve wire connectivity. In addition, the lead frame 21 has an opening where the semiconductor wafer 20 can be seen without arranging the lead 21h in the rectangular frame 21f at a location where the semiconductor device cannot be manufactured. Further, a guide hole 21j used for transferring or positioning the lead frame 21 is provided in the peripheral portion of the lead frame 21.

  In the lead frame 21 having such a structure, as shown in FIG. 7B, the first surface 21a which is a flat surface is bonded to the first surface 20a of the semiconductor wafer 20, and each lead pattern 21c has each lead. 21h, the tip (inner end) comes close to the electrode 8, as shown in FIG. In FIG. 10, a rectangular area that is within a predetermined distance from the rectangular frame 21 f is an area in which circuit elements are formed.

  Next, as shown in FIG. 7C and FIG. 10, in each lead pattern 21c, the electrode 8 (see FIG. 10) provided on the first surface 20a of the semiconductor wafer 20 and the thin wall at the tip of the lead 21h. The parts 5 are connected by a conductive wire 9. The loop height of the wire 9 is made low, for example, lower than the second surface 21b of the thick portion 6 of the lead frame 21. In FIG. 7, the electrode 8 is omitted.

  Next, as shown in FIG. 7D, in each lead pattern 21c, insulation is performed on the exposed first surface 20a side of the semiconductor wafer 20 and the space portion on the second surface 21b side of the thin portion 5 of the lead 21h. A resin layer 22 is formed by embedding a conductive resin. The resin layer 22 covers the electrode 8 and the wire 9. The resin layer 22 is formed by, for example, a potting method or a transfer molding method in which resin is dropped.

  In the first embodiment, a case of transfer molding will be described. FIG. 11 is a plan view showing an overlapping state of a transfer molding die, a part of the semiconductor wafer 20 and the lead frame 21. FIG. 12 is a cross-sectional view. In FIG. 11, the resin flow path formed by the mold 23 will be described. It consists of three circular culls 24 for extruding the melted resin, a runner 25 that guides the resin connected to the cull 24, and a gate 26 and a cavity 27 that follow the runner 25. An air vent 28 that guides air to the outside is disposed on the periphery of the cavity 27. In addition, as shown in FIG. 12, when transfer molding is performed using a mold 23 including a lower mold 23a and an upper mold 23b, resin molding is performed with a resin sheet 29 interposed on the lead frame 21. Since the sheet 29 bites into the cavity 27 side at a portion away from the thick portion 6, the surface 3 a of the resin layer 22 becomes a surface recessed from the thick portion 6 as shown in FIG. This is preferable as the semiconductor device 1 having the LGA structure. For example, an epoxy resin is used as the resin for forming the resin layer 22. After filling the resin, the resin layer 22 is formed by curing at a predetermined temperature to cure the resin.

  By such a transfer molding method, a resin layer 22 is formed on each lead pattern 21c of the lead frame 21 as shown in FIG. In FIG. 13, the resin cured by the runner 25, the gate 26 and the air vent 28 is removed. FIG. 14 shows the lead pattern 21c. As shown in FIGS. 13 and 14, the thick portion 6 of the lead 21 h is exposed on the surface 3 a of the resin layer 22. The thin portion 5 of the lead 21 h is buried in the resin layer 22.

  Next, as illustrated in FIG. 7E, a tape 35 serving as a support member is attached to the second surface 20 b side that is the exposed surface of the semiconductor wafer 20. Thereafter, separation grooves 36 are formed vertically and horizontally so as to reach the surface of the tape 35 from the upper surface of the lead frame 21. The groove 36 is formed by cutting with a dicing blade 37. In cutting with the dicing blade 37, the lead frame 21, the semiconductor wafer 20 and the resin layer 22 are completely divided, but the tape 35 is not divided, and the tip of the dicing blade is controlled to reach the surface of the tape or halfway. .

Further, as shown in FIG. 14, the dicing blade 37 performs cutting with a cutting width of a. That is, the cutting width a is wider than the horizontal frame 21d and the vertical frame 21e, and the horizontal frame 21d and the vertical frame 21e completely disappear. Further, the lead 21 h is cut at the thick portion 6. As a result, the cut surface of the thick portion 6 is exposed on the cut surface. By cutting the dicing blade 37, each lead 21h of the lead frame 21 becomes the electrode plate 4 having the thick portion 6 and the thin portion 5 as shown in FIGS. 1 to 5, and the resin layer 22 is sealed. As a result, the semiconductor wafer 20 becomes the semiconductor chip 2 and a plurality of semiconductor devices 1 attached to the tape 35 are formed. The tape 35 may be attached to the lead frame 21 side, and then the semiconductor wafer 20 and the lead frame 21 may be cut from the semiconductor wafer 20 side.
Next, by removing the tape 35, a plurality of semiconductor devices 1 having the structure shown in FIG. 1 are manufactured.

  FIG. 15 is a schematic plan view showing a unit lead pattern 21c portion of a lead frame which is a modification of the first embodiment. In this figure, the electrode 8 and the wire 9 are also shown. In the first embodiment, the number of lead patterns is reduced for easy explanation, but FIG. 15 shows a pattern applicable to an actual product. Also in this example, the arrangement of the electrodes 8 has a center pad structure. By applying the present invention to a center pad structure, for example, a CSP structure of a DRAM memory chip can be achieved.

The first embodiment has the following effects.
(1) An electrode plate 4 made of a metal plate is bonded to the semiconductor chip 2 via an adhesive 7, and the sum of the thicknesses of the electrode plate 4, the adhesive 7 and the semiconductor chip 2 becomes the height of the semiconductor device 1. Therefore, the semiconductor device 1 can be made thinner than the conventional structure using a thick wiring board. That is, the metal plate 9 has a thickness of 0.125 mm, and can be made thinner than a thick wiring board that is generally at least 0.2 mm.

  (2) Since the planar size of the semiconductor device 1 is the size of the semiconductor chip 2 itself, a CSP structure is formed, and the semiconductor device 1 can be reduced in size.

  (3) The semiconductor device 1 bonds the lead frame 21 and the semiconductor wafer 20, and connects the thin thin portion 5 of the lead 21h constituting the lead pattern 21c of the lead frame 21 and the electrode 8 of the semiconductor wafer 20 with the wire 9, Between the leads on the first surface 20a side of the semiconductor wafer 20 and the second surface 21b side of the thin portion 5 are covered with an insulating resin layer 22, and then the semiconductor wafer 20 and the lead frame 21 supported by the tape 35 are attached to the tape 35. A plurality of semiconductor devices 1 are manufactured by cutting each lead 21h into an electrically independent electrode plate 4 and then peeling off the tape 35. Thus, the manufacturing cost of the semiconductor device 1 can be reduced by simplifying the manufacturing process.

  16 to 18 are diagrams relating to a semiconductor device which is Embodiment 2 of the present invention. 16 is a bottom view of the semiconductor device with the sealing body removed, and FIG. 17 is a bottom view of the semiconductor device. 18A is a cross-sectional view taken along line AA in FIG. 17, and FIG. 18B is a cross-sectional view taken along line BB in FIG.

  The semiconductor device 1 according to the second embodiment is the same as the semiconductor device 1 according to the first embodiment except that the semiconductor chip 2 is a square (rectangular body), and the electrode plate 4 connected to the first surface 2a of the semiconductor chip 2 is a short electrode. The structure is a mixed structure of the plate 4e and the long electrode plate 4f, and the external electrode terminals 11 are arranged in a plurality of rows.

  As shown in FIG. 16, a short electrode plate 4e and a long electrode plate 4f are alternately bonded along each side of the semiconductor chip 2. The short electrode plate 4 e and the long electrode plate 4 f extend perpendicular to the side of the semiconductor chip 2. And in the middle part, it has the wide part 4h wider than other parts. The wide portion 4h has a substantially rectangular shape and is a thick portion (second portion) 6 as in the first embodiment. The portion other than the wide portion 4h is a thin portion (first portion) 5 as in the first embodiment. The wide portions 4h are arranged in two rows in a staggered pattern along each side of the semiconductor chip 2.

  As a result, the wide portion 4h is exposed on the surface 3a of the sealing body 3 formed on the first surface 2a side of the semiconductor chip 2 as shown in FIGS. 17 and 18A, 18B. The external electrode terminal 11 is formed by the exposed wide portion 4h. The external electrode terminals 11 are arranged in two rows in a staggered pattern along each side of the rectangular sealing body 3. A protruding electrode 50 is fixed to the external electrode terminal 11. The protruding electrode 50 is formed by, for example, a solder ball. As a result, the semiconductor device 1 has a BGA structure.

  Bonding pads 4j for connecting wires 9 are provided on the short electrode plate 4e and the long electrode plate 4f. In the embodiment, as shown in FIG. 16, the bonding pad 4j is provided in the middle in the case of the short electrode plate 4e and in two or three places in the case of the long electrode plate 4f. The short electrode plate 4e and the long electrode plate 4f at the end of the arrangement row are provided with branch pieces 4n. A wire 9 is also connected to the branch piece 4n as necessary.

  In the present embodiment, a plurality of electrodes 8 provided on the first surface 2a of the semiconductor chip 2 are arranged along each side of the semiconductor chip 2, and several electrodes 8 are arranged near the center of the chip. It has become.

  The lead frame lead pattern used in the second embodiment is not particularly shown, but the short electrode plate 4e and the long electrode plate 4f shown in FIG. 16 extend outward, and the extended portion is connected to the rectangular frame. Pattern. In the manufacture of the semiconductor device 1 according to the first embodiment, the lead 21h is cut at the thick portion 6, but in the second embodiment, the lead 21h is cut at the thin portion 5. As a result, as shown in FIG. 17, the external electrode terminal 11 is positioned on the inner side from the edge of the rectangular sealing body 3.

  That is, as shown in FIGS. 18A and 18B, the long electrode plate 4f has a longer distance from the side of the semiconductor device 1 than the short electrode plate 4e. In other words, the short electrode plate 4e (electrode plate 4) and the long electrode plate 4f (electrode plate 4) are alternately arranged along the side of the semiconductor chip 2 and the thickness of the electrode plate 4 arranged along this side. The meat part 6 (branch piece 4n: second part) has a structure in which the distance from the side is different between adjacent electrode plates. In this embodiment, the external electrode terminals 11 are arranged in two rows, but the number can be increased.

As shown in FIG. 16, since many bonding pads 4j and branch pieces 4n are provided on the electrode plate 4, the lead pattern shown in FIG. 16 is used as a standard lead frame lead pattern. It can also be used for different semiconductor chips.
According to the second embodiment, in addition to the effects of the first embodiment, the number of external electrode terminals 11 can be further increased, so that the semiconductor device 1 can have higher functions and higher integration.

FIG. 19 is a cross-sectional view of a BGA type semiconductor device that is Embodiment 3 of the present invention. In the semiconductor device 1 of the third embodiment, as shown in FIG. 19, protruding electrodes (bump electrodes) 55 are formed on the thick portion 6 of the electrode plate 4 of the semiconductor device 1 of the first embodiment, and the external electrode terminals 11 are formed. A protruding electrode structure is used.
In the semiconductor device 1 according to the third embodiment, after the resin layer 22 is formed (see FIG. 7D) in the manufacturing process of the semiconductor device 1 according to the first embodiment, the semiconductor wafer 20, the lead frame 21, and the resin layer 22 are formed. Prior to separation (see FIG. 7E), a bump electrode 55 made of a solder ball or the like can be formed on the coating film 10 to be the external electrode terminal 11.
According to the third embodiment, in addition to the effects of the first embodiment, there is an effect of improving the mountability of the CSP.

20 and 21 are diagrams relating to a semiconductor device which is Embodiment 4 of the present invention. FIG. 20 is a cross-sectional view of the semiconductor device, and FIGS. 21A to 21D are process cross-sectional views illustrating a method for manufacturing the semiconductor device.
21A to 21D correspond to FIGS. 7A to 7E showing the method for manufacturing the semiconductor device 1 of the first embodiment. FIG. 21A corresponds to FIG. 7A in the process of preparing the semiconductor chip 2, and FIG. 21C corresponds to FIG. 7D in the process of forming the resin layer. Is a step of cutting by the dicing blade 37 and corresponds to FIG. The semiconductor wafer 20 is the same as that in the first embodiment. The lead frame 21 is the same as the lead frame 21 of the first embodiment except that the lead 21h is longer than that of the first embodiment and the thin portion 5 at the tip (inner end) overlaps the electrode 8 of the semiconductor wafer 20. .

  In the method of manufacturing the semiconductor device 1 according to the fourth embodiment, as shown in FIG. 21B, the first surface 20a having the electrode 8 (not shown) is the upper surface, and the first surface that is a flat surface upward is formed. The lead frame 21 with the surface 21a on the lower surface is positioned and overlapped with a predetermined gap 60 therebetween. Thereafter, the thin portion 5 of the lead 21h is sequentially irradiated with laser light 61 in a spot manner and melted. The melted part hangs down by its own weight and is connected to the electrode 8 of the semiconductor wafer 20 (see FIG. 22). Thereby, the tip portion of each lead 21 h in each lead pattern 21 c is connected to the electrode 8 of each circuit element of the semiconductor wafer 20. In the state after the connection, a gap 60 is maintained between the semiconductor wafer 20 and the lead frame 21 by the connection by the laser light irradiation.

Next, as shown in FIG. 21C, a resin layer 22 is formed by the same method as in the first embodiment. At this time, the gap 60 is filled with an insulating resin that forms the resin layer 22, and electrical insulation is maintained by the insulating resin except for the connection portion between the lead 21 h and the electrode 8.
Next, as shown in FIG. 21 (d), the tape 35 is attached to the semiconductor wafer 20 to support the semiconductor wafer 20 and the lead frame 21 as in the manufacturing method of the first embodiment. Thereafter, grooves 36 for cutting the lead frame 21, the semiconductor wafer 20, and the resin layer 22 are formed vertically and horizontally by a dicing blade 37 to form the semiconductor device 1 adhered to the tape 35.
Next, the tape 35 is peeled off, and a plurality of semiconductor devices 1 are manufactured.
According to the semiconductor device manufacturing technology according to the fourth embodiment, in addition to the effects of the first embodiment, there is a further cost reduction effect by eliminating the adhesive and the wires.

FIG. 22 is a diagram related to a semiconductor device which is Embodiment 5 of the present invention. As shown in FIG. 22, the semiconductor device 1 according to the fifth embodiment has a protruding electrode (bump electrode) 55 formed on the thick portion 6 of the electrode plate 4 of the semiconductor device 1 according to the fourth embodiment shown in FIG. The electrode terminal 11 has a protruding electrode structure.
In the semiconductor device 1 according to the fifth embodiment, in the manufacturing process of the semiconductor device 1 according to the fourth embodiment, after the resin layer 22 is formed (see FIG. 21C), the semiconductor wafer 20, the lead frame 21, and the resin layer 22 are formed. Prior to separation (see FIG. 21D), a bump electrode 55 made of a solder ball or the like can be formed on the coating film 10 to be the external electrode terminal 11.

According to the fifth embodiment, in addition to the effects of the fourth embodiment, there is an effect of improving the mountability of the CSP.
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

1 is a perspective view showing an appearance of a semiconductor device that is Embodiment 1 of the present invention. 1 is a plan view of a semiconductor device of Example 1. FIG. It is sectional drawing which follows the AA line of FIG. 2 is a bottom view of the semiconductor device of Example 1. FIG. In the bottom view of the semiconductor device of Example 1, it is the figure which removed some sealing bodies. FIG. 3 is a cross-sectional view showing a mounted state of the semiconductor device of Example 1. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of Example 1; FIG. 8 is a plan view showing an overlapping state of the semiconductor wafer and the lead frame corresponding to FIG. It is a top view which shows the unit lead pattern of the said lead frame. It is a top view which shows the semiconductor wafer part fixed to the said unit lead pattern. In the manufacturing method of the semiconductor device of Example 1, it is a top view which shows the overlapping state of the metal mold | die for transfer molding, a semiconductor wafer, and a lead frame. It is sectional drawing which shows the overlapping state of the said metal mold | die for transfer molding, a semiconductor wafer, and a lead frame. In the manufacturing method of the semiconductor device of Example 1, it is a top view showing the state where the resin layer was formed by transfer molding. It is a schematic diagram showing a unit lead pattern portion of a lead frame covered with the resin layer. FIG. 6 is a schematic plan view showing a unit lead pattern portion of a lead frame that is a modification of the first embodiment. It is the bottom view which removed the sealing body of the semiconductor device which is Example 2 of this invention. It is a bottom view of the semiconductor device of the present Example 2. It is sectional drawing which follows the AA line and BB line of FIG. It is sectional drawing of the semiconductor device which is Example 3 of this invention. It is sectional drawing of the semiconductor device which is Example 4 of this invention. 10 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device of Example 4; It is sectional drawing of the semiconductor device which is Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 2a ... 1st surface, 2b ... 2nd surface, 3 ... Sealing body, 3a ... Surface, 4 ... Electrode plate, 4a ... 1st surface, 4b ... 2nd 5 ... Thin part, 6 ... Thick part, 7 ... Adhesive, 8 ... Electrode, 9 ... Wire, 10 ... Coating, 11 ... External electrode terminal, 15 ... Mounting substrate, 16 ... Land, 17 ... Bonding material 20 ... Semiconductor wafer, 20a ... First surface, 20b ... Second surface, 20c ... Orientation flat, 21 ... Lead frame, 21a ... First surface, 21b ... Second surface, 21c ... Lead pattern, 21d ... Horizontal frame, 21e ... Vertical frame, 21f ... Rectangular frame, 21h ... Lead, 22 ... Resin layer, 23 ... Mold, 23a ... Lower mold, 23b ... Upper mold, 24 ... Cal, 25 ... Runner, 26 ... Gate, 27 ... cavity, 28 ... air vent, 29 ... sheet, 35 ... tape, 3 ... groove, 37 ... dicing blade, 50, 55 ... protruding electrode, 60 ... gap, 61 ... laser light.

Claims (8)

A semiconductor chip having a first surface having an electrode, a second surface opposite to the first surface, and a plurality of side surfaces connecting these surfaces;
It said first surface is disposed with a predetermined gap on the first surface of the semiconductor chip, thin second surface to be the front Symbol surface opposite the first surface is removed partially predetermined thickness the first part have a second part thicker than the first part, projecting the first part from the first surface is melted by a portion thereof laser beam irradiates the first plane direction of the chip A plurality of electrode plates including protrusions formed to be connected to the electrodes of the semiconductor chip ;
It said semiconductor chip covering said first surface and said electrode plate, and a sealing body made of an insulating resin to embed the inter gap between the electrode plate and the semiconductor chip,
Said second portion of said second surface of said electrode plate wherein a exposed from the sealing body. The semiconductor device according to claim 1, wherein a conductive film is formed in contact with the second portion of the second surface of the electrode plate. Claims surfaces of the sealing body positioned in the electrode plates is characterized in that it does not protrude from the surface of the coating film provided on the second part or the second part of the second surface of the electrode plate The semiconductor device according to claim 1 or 2. The semiconductor device according to claim 1, wherein a protruding electrode is provided on the second portion of the second surface of the electrode plate. Preparing a semiconductor wafer having circuit elements arranged in vertical and horizontal directions and having electrodes of the circuit elements on a first surface;
A lead plate comprising a metal plate having a first surface and a second surface opposite to the first surface, the lead pattern comprising a plurality of leads provided corresponding to the circuit elements; The first surface of the lead is a flat surface, and the lead is a first portion where the second surface is partially removed by a predetermined thickness to become thin, and a second portion which is thicker than the first portion. Part of preparing a lead frame corresponding to the electrode;
The lead frame is positioned so as to have a predetermined gap on the first surface side of the semiconductor wafer, and the first portion corresponding to the electrode of the lead of the lead frame is melted by laser light irradiation to form the semiconductor. Forming a protrusion in the first surface direction of the wafer and connecting the protrusion to the electrode;
Exposing a second part of the second surface of the lead and covering the electrode, the first part of the lead and the exposed first surface of the semiconductor wafer with an insulating resin, and forming a resin layer;
Applying a tape to the entire exposed surface of the semiconductor wafer or the lead frame;
Grooves that reach the surface of the tape are formed vertically and horizontally in the lead frame and the semiconductor wafer so as to divide the circuit elements, and each lead is formed on an independent electrode plate connected to the electrodes by this groove formation. Process,
A method of manufacturing a semiconductor device, comprising: manufacturing a plurality of semiconductor devices by a step of removing the tape. 6. The semiconductor device according to claim 5, wherein, in the step of preparing the lead frame, a lead frame in which a conductive film is formed in contact with the second portion of the second surface of the lead is prepared. Manufacturing method. In the step of preparing the lead frame, a lead frame in which a conductive film is formed in contact with the second portion of the second surface of the lead is prepared,
6. The method for manufacturing a semiconductor device according to claim 5, wherein a protruding electrode is formed on the conductive film after the step of forming the resin layer. In the step of forming the pre-Symbol resin layer, manufacturing of a semiconductor device according to claim 5, characterized in that forming the height of the resin layer lower than the second part of the second surface of the lead Method.

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