JPH11186481A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH11186481A JPH11186481A JP35746597A JP35746597A JPH11186481A JP H11186481 A JPH11186481 A JP H11186481A JP 35746597 A JP35746597 A JP 35746597A JP 35746597 A JP35746597 A JP 35746597A JP H11186481 A JPH11186481 A JP H11186481A
- Authority
- JP
- Japan
- Prior art keywords
- island
- lead
- resin
- lead frame
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/01005—Boron [B]
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- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/01047—Silver [Ag]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は外形寸法を小型化し
た半導体装置に適したリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame suitable for a semiconductor device having a reduced external size.
【０００２】[0002]
【従来の技術】ＩＣ、ディスクリート素子等の半導体素
子を製造する際には、図８に示すようなリードフレーム
を用いることが多い。同図を参照して、リードフレーム
は、半導体チップを搭載するためのアイランド１と、ア
イランド１に先端を近接するリード端子２と、これらを
保持するための枠体３と、樹脂封止予定部４の間に設け
たタイバー５を具備し、全体が銅素材または鉄素材から
なるフープ状あるいは短冊状の形状を有する。該リード
フレームには例えば半導体装置２０個分のアイランド１
とリード端子２が形成されている。2. Description of the Related Art When manufacturing semiconductor devices such as ICs and discrete devices, a lead frame as shown in FIG. 8 is often used. Referring to FIG. 1, a lead frame includes an island 1 for mounting a semiconductor chip, a lead terminal 2 having a tip close to the island 1, a frame 3 for holding these, and a resin sealing scheduled portion. The tie bar 5 is provided between the fins 4 and has a hoop shape or a strip shape made entirely of a copper material or an iron material. The lead frame includes, for example, an island 1 for 20 semiconductor devices.
And the lead terminal 2 are formed.
【０００３】そして、図９（Ａ）に示すように、リード
フレームのアイランド１上に半田等の接着剤６によって
半導体チップ７を実装（ダイボンド）し、半導体チップ
７の表面に形成したトランジスタ素子のベース電極、エ
ミッタ電極とリード端子２とをそれぞれボンディングワ
イヤー８で電気的に接続（ワイヤボンド）し、半導体チ
ップ７をエポキシ樹脂等の熱硬化性樹脂９で半導体チッ
プ７とリード端子２の一部を被覆保護（トランスファー
モールド）することで、所望の半導体装置が製造され
る。樹脂９の外部に導出されたリード端子２はＺ字型に
折り曲げられて表面実装用途に適したものとしてある。
例えばＮＰＮ型トランジスタ素子を形成した半導体チッ
プ１を封止する場合は、アイランド２をコレクタ電極と
して３端子構造の半導体装置が提供される。Then, as shown in FIG. 9A, a semiconductor chip 7 is mounted (die-bonded) on an island 1 of a lead frame by an adhesive 6 such as solder, and a transistor element formed on the surface of the semiconductor chip 7 is formed. The base electrode, the emitter electrode, and the lead terminal 2 are each electrically connected (wire-bonded) with a bonding wire 8, and the semiconductor chip 7 is partly bonded to the semiconductor chip 7 with a thermosetting resin 9 such as an epoxy resin. A desired semiconductor device is manufactured by coating (transfer molding). The lead terminal 2 led out of the resin 9 is bent in a Z-shape to be suitable for surface mounting applications.
For example, when sealing the semiconductor chip 1 on which the NPN transistor element is formed, a semiconductor device having a three-terminal structure using the island 2 as a collector electrode is provided.
【０００４】上記のトランスファーモールドにあって
は、図９（Ｂ）を参照して、上金型１０及び下金型１１
によって個々の半導体装置の外形形状に合致した空間で
あるキャビティ１２を構成し、該キャビティの内部にダ
イボンド及びワイヤボンドを施したリードフレームを設
置し、この状態でキャビティ１２内に樹脂９を注入・硬
化することによりトランスファーモールドが行われる。
そして、樹脂封止した後に前記リードフレームからリー
ド部分他を切断することで半導体装置を個々の素子に分
離しているIn the above transfer mold, referring to FIG. 9B, an upper mold 10 and a lower mold 11 are provided.
To form a cavity 12 which is a space conforming to the outer shape of each semiconductor device. A lead frame on which die bonding and wire bonding are performed is installed inside the cavity. In this state, the resin 9 is injected into the cavity 12. The transfer molding is performed by curing.
Then, the semiconductor device is separated into individual elements by cutting lead portions and the like from the lead frame after resin sealing.
【０００５】[0005]
【発明が解決しようとする課題】第１の課題：リードフ
レームは、上記のダイボンド、ワイヤボンド、及びトラ
ンスファーモールド工程において製造途中の半導体装置
の取り扱いを簡便にする為のものである。また、１つの
素子に１つのキャビティを設けるように設計されている
ことから樹脂封止予定部４の間隔を狭めることが困難で
あり、故に機械的強度を維持するためのタイバー５等が
不可欠となる。その為、小型の半導体装置を製造する場
合であっても、枠体３、タイバー５等の為に消費する材
料の量を減らすことができない欠点があった。逆に言え
ば、同じサイズのリードフレームに形成できるアイラン
ドの個数に限界があるという欠点があった。First Problem: A lead frame is for simplifying the handling of a semiconductor device during manufacture in the above-described die bonding, wire bonding, and transfer molding processes. Further, since it is designed to provide one cavity for one element, it is difficult to narrow the interval between the resin sealing portions 4, and therefore, the tie bar 5 for maintaining the mechanical strength is indispensable. Become. Therefore, even when manufacturing a small-sized semiconductor device, there is a disadvantage that the amount of material consumed for the frame 3, the tie bar 5, and the like cannot be reduced. Conversely, there is a disadvantage that the number of islands that can be formed on a lead frame of the same size is limited.
【０００６】第２の課題：半導体装置のパッケージサイ
ズを小型化した場合、樹脂９の残り膜厚が少なくなり、
樹脂９内部に埋設されるリード端子２と樹脂９との密着
面積が小さくなる。これによってリード端子２が抜け易
くなるので、パッケージサイズを増大させない、何らか
の抜け防止策が必要不可欠である。Second problem: When the package size of the semiconductor device is reduced, the remaining film thickness of the resin 9 decreases,
The contact area between the lead terminal 2 embedded in the resin 9 and the resin 9 is reduced. This makes it easier for the lead terminals 2 to come off. Therefore, it is essential to take some measures to prevent the lead terminals 2 from coming out without increasing the package size.
【０００７】第３の課題：樹脂モールドされた半導体装
置は、通常、ガラスエポキシ基板等のプリント基板に実
装され、同じくプリント基板上に実装された他の素子と
電気的に接続することにより、所望の回路網を構成す
る。この時、リード端子３が樹脂５の外部に導出された
半導体装置では、リード端子３の先端から先端までの距
離を実装面積として占有するので、実装面積が大きいと
いう欠点がある。Third problem: A resin-molded semiconductor device is usually mounted on a printed board such as a glass epoxy board, and electrically connected to other elements also mounted on the printed board, so that a desired device is obtained. Is configured. At this time, the semiconductor device in which the lead terminal 3 is led out of the resin 5 has a disadvantage that the mounting area is large because the distance from the tip of the lead terminal 3 to the tip is occupied as the mounting area.
【０００８】[0008]
【課題を解決するための手段】本発明は、半導体チップ
を固着するためのアイランドと、前記アイランドに先端
を近接する複数本の外部接続用のリード端子と、前記ア
イランド及びリード端子を保持するための枠体部とを具
備し、前記アイランドと前記リード端子とが多数個行列
状に配置され、前記アイランドが互いに連結され、かつ
前記枠体に保持され、１つのアイランドに対応するリー
ド端子を、その隣に位置するアイランドに連結保持させ
たものである。SUMMARY OF THE INVENTION The present invention is directed to an island for fixing a semiconductor chip, a plurality of lead terminals for external connection proximate to the island, and for holding the island and the lead terminal. A plurality of islands and the lead terminals are arranged in a matrix, the islands are connected to each other, and are held by the frame body, the lead terminals corresponding to one island, It is connected and held to the island located next to it.
【０００９】[0009]
【発明の実施の形態】以下に本発明のリードフレームを
詳細に説明する。図１は本発明の位置実施の形態を説明
するための（Ａ）平面図、（Ｂ）断面図であり、図１
（Ｂ）は図１（Ａ）のＡＡ線断面図を示すものである。
本発明のリードフレーム３０は、半導体チップを搭載す
るための多数の素子搭載部３１、３１Ａ．．．．が行・
列方向（又はそれらの一方方向にのみ）に複数個、繰り
返しパターンで配置されており、該多数個の素子搭載部
３１は、それらの周囲を取り囲む様に配置した枠体部３
２によって保持されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The lead frame of the present invention will be described below in detail. 1A and 1B are a plan view and a cross-sectional view for explaining a position embodiment of the present invention.
FIG. 2B is a cross-sectional view taken along the line AA in FIG.
The lead frame 30 of the present invention has a large number of element mounting portions 31, 31A. . . . Is a line
A plurality of the element mounting portions 31 are arranged in the column direction (or only in one direction thereof) in a repetitive pattern, and the plurality of element mounting portions 31 are arranged so as to surround the periphery thereof.
2.
【００１０】素子搭載部３１は、半導体チップを固着す
るアイランド３３と、外部接続用電極となる複数のリー
ド端子３４を少なくとも具備する。アイランド３３は連
結バー３５によって同じ向きで互いに連結され、連結さ
れた複数個のアイランド３３が、同じく連結バー３５に
よって枠体部３２に連結されている。互いに連結する個
数は２〜１０個程度である。この様に互いに連結したア
イランド３３群を、更に同じ向きで並列に枠体３２に保
持させることで、行列状のパターンとしてある。The element mounting portion 31 includes at least an island 33 for fixing a semiconductor chip and a plurality of lead terminals 34 serving as external connection electrodes. The islands 33 are connected to each other in the same direction by connecting bars 35, and the plurality of connected islands 33 are connected to the frame 32 by the connecting bars 35. The number connected to each other is about 2 to 10. The islands 33 connected to each other in this manner are further held in parallel in the same direction by the frame 32, thereby forming a matrix-like pattern.
【００１１】素子搭載部３１のリード端子３４は、アイ
ランド３３に連結されている。この時、特定のアイラン
ド３３に対しては、その隣に隣接するアイランド３３Ａ
に連結保持されたリード端子３４が対応して１つの素子
搭載部３１を構成する。３端子型の半導体装置であれば
コレクタ、エミッタ用に２本のリード端子３４を設け
る。The lead terminals 34 of the element mounting section 31 are connected to the island 33. At this time, for a specific island 33, an adjacent island 33A
And the lead terminals 34 connected and held together constitute one element mounting portion 31. In the case of a three-terminal type semiconductor device, two lead terminals 34 are provided for the collector and the emitter.
【００１２】アイランド３３Ａとリード端子３４との連
結部分近傍のリード端子３４には、その切断予定箇所に
Ｖ字型にくびれた凹部３６を形成している。凹部３６は
リード端子３４の両側辺に設けてあり、その線幅が最も
細くなる箇所と切断予定中心線とが合致している。この
様に素子搭載部３１を行・列方向に複数配置すること
で、１本の短冊状のリードフレーム３０に例えば縦×横
が５個×２５個で合計１００個の素子搭載部３１を配置
する。The lead terminal 34 in the vicinity of the connection between the island 33A and the lead terminal 34 has a V-shaped concavity 36 at a location where the lead terminal 34 is to be cut. The concave portions 36 are provided on both sides of the lead terminal 34, and the portion where the line width becomes narrowest matches the center line to be cut. By arranging a plurality of the element mounting portions 31 in the row and column directions in this manner, a total of 100 element mounting portions 31 of, for example, 5 × 25 in length × width are arranged in one strip-shaped lead frame 30. I do.
【００１３】素子搭載部３１群を取り囲む枠体部３２に
は、複数個の合わせマーク３７を形成する。合わせマー
ク３７は、貫通孔またはスタンピングによって部分的に
凹ませたもの等、製造工程における自動認識機能が働く
ものであればよい。また、形状も正方形、長方形、矩
形、円形等があげられる。そして、素子搭載部３１毎に
１個、または複数個毎に１個等間隔で配置する。更に、
枠体部３２には各種製造装置においてリードフレームを
一定ピッチで移動させるための送り孔（図示せず）が別
途設けられている。A plurality of alignment marks 37 are formed on the frame 32 surrounding the group of element mounting portions 31. The alignment mark 37 may be any as long as it has an automatic recognition function in the manufacturing process, such as a through-hole or a mark partially recessed by stamping. Further, the shape may be a square, a rectangle, a rectangle, a circle, or the like. Then, one device is provided for each element mounting portion 31 or one device is provided for each device at equal intervals. Furthermore,
The frame 32 is provided with a feed hole (not shown) for moving the lead frame at a constant pitch in various manufacturing apparatuses.
【００１４】上記のリードフレーム３０は、例えば、約
０．２ｍｍ厚の銅系の金属材料で形成された帯状あるい
は矩形状の金属薄板を用意し、この金属薄板をエッチン
グ加工またはスタンピング加工によって図示したパター
ンに開口することにより製造される。リードフレーム３
０の板厚は必要に応じて適宜に設定することができる。
また、必要に応じて、アイランド３３の表面には部分的
にＡｇメッキなどのダイボンド工程に必要なメッキ処理
が施されている。斯かるリードフレーム３０は、各リー
ド端子３４をアイランド３３に直接連結してある。その
為、リード端子３４を枠体３２に保持するためのタイバ
ーが不要になり、また、素子搭載部３１間の距離を狭め
ることができる。従って、例えば同じサイズのリードフ
レームに形成できる素子搭載部３１の個数を増大して、
リードフレーム３０の無駄な部分を少なくすることが可
能になるのである。尚、強度不足であれば連結部３５に
直交するようなタイバーを設ければ良いが、いずれにし
ても従来例よりはその数を減らすことができる。For the lead frame 30, for example, a strip-shaped or rectangular metal thin plate made of a copper-based metal material having a thickness of about 0.2 mm is prepared, and this metal thin plate is illustrated by etching or stamping. It is manufactured by opening in a pattern. Lead frame 3
The plate thickness of 0 can be appropriately set as needed.
If necessary, the surface of the island 33 is partially subjected to a plating treatment such as Ag plating necessary for a die bonding process. In such a lead frame 30, each lead terminal 34 is directly connected to the island 33. Therefore, a tie bar for holding the lead terminal 34 on the frame 32 is not required, and the distance between the element mounting portions 31 can be reduced. Therefore, for example, by increasing the number of element mounting portions 31 that can be formed on a lead frame of the same size,
This makes it possible to reduce unnecessary parts of the lead frame 30. If the strength is insufficient, a tie bar may be provided so as to be orthogonal to the connecting portion 35, but in any case, the number can be reduced as compared with the conventional example.
【００１５】この様に形成したリードフレーム３０は、
アイランド３３とリード端子３４とが電気的に導通して
いるので、組立後に分離する必要がある。以下に図１の
リードフレーム３０を用いた半導体装置の製造方法を説
明する。 第１工程：（図２） 先ず、図１に示したリードフレーム３０に対してダイボ
ンド工程とワイヤボンド工程を行う。図２（Ｂ）は図２
（Ａ）のＡＡ線断面図である。The lead frame 30 thus formed is
Since the islands 33 and the lead terminals 34 are electrically connected, they need to be separated after assembly. Hereinafter, a method for manufacturing a semiconductor device using the lead frame 30 of FIG. 1 will be described. First Step: (FIG. 2) First, a die bonding step and a wire bonding step are performed on the lead frame 30 shown in FIG. FIG. 2 (B) is FIG.
FIG. 3A is a sectional view taken along line AA of FIG.
【００１６】各アイランド３３、３３Ａの一主面上にＡ
ｇペースト、半田等の導電ペースト３８を塗布し、その
導電ペースト３８を介して各アイランド３３、３３Ａ上
に半導体チップ３９を固着する。各アイランド表面に金
メッキを行い、そのメッキ上に半導体チップを共晶接続
することも可能である。更に、半導体チップ３９の表面
に形成されたボンディングパッドと、これに対応するリ
ード端子３４とをワイヤ４０でワイヤボンディングす
る。ワイヤ４０は例えば直径が２０μの金線から成る。
ここで、ワイヤ４０は各アイランド３３上に固着した半
導体チップ３９の表面電極と、その隣に隣接した他のア
イランド３３Ａから延在するリード端子３４とを接続す
る。半導体チップ３９が固着されたアイランド３３の裏
面は、係る半導体チップ３９の外部接続用の電極として
用いることができる。アイランド３３の裏面を接続用端
子の１つとして用いる形態は、半導体チップ３９として
例えばトランジスタ、パワーＭＯＳＦＥＴ等の、電流経
路が垂直方向になる半導体デバイス素子に適している。A is provided on one main surface of each of the islands 33 and 33A.
A conductive paste 38 such as g paste or solder is applied, and the semiconductor chip 39 is fixed on each of the islands 33 and 33A via the conductive paste 38. Gold plating can be performed on the surface of each island, and a semiconductor chip can be eutectic-connected on the plating. Further, the bonding pads formed on the surface of the semiconductor chip 39 and the corresponding lead terminals 34 are wire-bonded with the wires 40. The wire 40 is made of, for example, a gold wire having a diameter of 20 μ.
Here, the wire 40 connects the surface electrode of the semiconductor chip 39 fixed on each island 33 to the lead terminal 34 extending from another adjacent island 33A. The back surface of the island 33 to which the semiconductor chip 39 is fixed can be used as an electrode for external connection of the semiconductor chip 39. The mode in which the back surface of the island 33 is used as one of the connection terminals is suitable as a semiconductor chip 39 such as a transistor or a power MOSFET, for example, a semiconductor device element having a vertical current path.
【００１７】半導体チップ３９を固着するために塗布し
た導電性ペースト３８は、図２（Ａ）から明らかなよう
に、半導体チップ３９が固着されるアイランド３３上に
選択的に塗布形成する。リード端子３４上に導電性ペー
スト３８が付着すると、ワイヤボンディングを行う場合
に、ボンディング装置のキャピラリーの先端部分に導電
性ペーストがつまりボンディング不良が生じ生産性が低
下する恐れがあるためである。この様な問題がない場合
には、導電性ペーストを素子搭載部３１全面に塗布して
も良い。The conductive paste 38 applied for fixing the semiconductor chip 39 is selectively applied on the island 33 to which the semiconductor chip 39 is fixed, as is apparent from FIG. 2A. This is because, when the conductive paste 38 adheres to the lead terminals 34, when performing wire bonding, the conductive paste may be clogged at the tip end of the capillary of the bonding apparatus, which may result in poor bonding and lower productivity. If there is no such problem, a conductive paste may be applied to the entire surface of the element mounting portion 31.
【００１８】第２工程：（図３） 次に、全体を樹脂モールドする。図３（Ｂ）は図３
（Ａ）のＡＡ線断面図である。リードフレーム３０上に
エポキシ樹脂等の熱硬化性の封止用樹脂層４１を形成
し、各素子搭載部３１、３１Ａ．．、半導体チップ３９
及びワイヤ４０を封止保護する。樹脂４１は、各半導体
チップ３９．．．を個別にパッケージングするものでは
なく、全ての半導体チップ３９を共通に被うように形成
する。また、リードフレーム３０の裏面側にも０．０５
ｍｍ程度の厚みで樹脂４１を被着する。これで、アイラ
ンド３３とリード端子３４は完全に樹脂４１内部に埋設
されることになる。Second step: (FIG. 3) Next, the whole is resin-molded. FIG.
FIG. 3A is a sectional view taken along line AA of FIG. A thermosetting sealing resin layer 41 such as an epoxy resin is formed on the lead frame 30, and each of the element mounting portions 31, 31A. . , Semiconductor chip 39
And the wire 40 is sealed and protected. The resin 41 is used for each semiconductor chip 39. . . Are not individually packaged, but are formed so as to cover all the semiconductor chips 39 in common. Also, 0.05 on the back side of the lead frame 30.
The resin 41 is applied with a thickness of about mm. Thus, the island 33 and the lead terminal 34 are completely embedded in the resin 41.
【００１９】この樹脂層４１は、射出成形用の上下金型
が形成する空間（キャビティ）内にリードフレーム３０
を設置し、該空間内にエポキシ樹脂を充填、成形する事
によって形成する。あるいは、枠体３２に高さ数ｍｍ、
幅数ｍｍの環状のダムを形成しておき、該ダムで囲まれ
た領域を満たすように液状の樹脂を充填し、これを熱処
理で硬化したものであっても良い。多数個の素子搭載部
３１を一塊りとしてモールドするので、１つのリードフ
レーム３０に対して１個あるいは２〜４個のキャビティ
を設ければ良い。従ってキャビティ内に樹脂を注入する
為に金型表面に形成する注入溝の本数も大幅に減らすこ
とが可能である。The resin layer 41 is provided in a space (cavity) formed by upper and lower molds for injection molding.
Is formed, and the space is filled with an epoxy resin and molded. Alternatively, the frame 32 has a height of several mm,
An annular dam having a width of several mm may be formed, a liquid resin may be filled so as to fill a region surrounded by the dam, and the resin may be cured by heat treatment. Since a large number of element mounting portions 31 are molded as one lump, one or two to four cavities may be provided for one lead frame 30. Therefore, the number of injection grooves formed on the surface of the mold for injecting the resin into the cavity can be significantly reduced.
【００２０】第３工程：（図４） 次に、素子搭載部３１毎に樹脂層４１を切断して各々の
素子Ａ、素子Ｂ、素子Ｃ．．．．を分離する。図４
（Ｂ）は図４（Ａ）のＡＡ線断面図である。分離に先立
ち、先ずはリードフレーム３０の裏面側の樹脂４１を部
分的に除去してスリット孔４２を形成する。スリット孔
４１は、後で外部接続端子を構成する為に形成するもの
である。約０．５ｍｍの幅を有し、ダイシング装置のブ
レードによって樹脂４２を切削することにより形成し
た。前記ブレードには様々な板厚のものが準備されてお
り、用いるブレードの板厚に応じて、１回であるいは複
数回繰り返すことで所望の幅に形成する。この時、樹脂
４１を切削すると同時にリード端子３４の裏面側も約
０．１ｍｍ程切削して、リードフレーム３０の金属表面
を露出させる。このスリット孔４２は、各リード端子３
４にくさび状に形成した「凹部３６」の付近に形成す
る。そして、スリット孔４２の内部に露出したリード端
子３４の表面に半田メッキ等のメッキ層４３を形成す
る。このメッキ層４３は、リードフレーム３０を電極の
一方とする電解メッキ法により行われる。この様にスリ
ット孔４２を形成した後、樹脂４１とリード端子３４及
び連結バー３５を素子搭載部３１毎に切断して各々の素
子Ａ、素子Ｂ、素子Ｃ．．．．を分離する。分離はアイ
ランド３３とこの上に固着された半導体チップ３９に接
続されたリード端子３４を囲む領域（同図の切断ライン
４４）で切断することにより行われる。切断にはダイシ
ング装置が用いられ、ダイシング装置のブレードによっ
て凹部３６の中心部に沿って樹脂層４１とリードフレー
ム３０とを同時に切断する。切断するときの概略斜視図
面を図５に示した。図５の符号６０がダイシングブレー
ドである。Third step: (FIG. 4) Next, the resin layer 41 is cut for each of the element mounting portions 31 so that each of the elements A, B, C. . . . Is separated. FIG.
FIG. 4B is a cross-sectional view taken along line AA of FIG. Prior to the separation, first, the resin 41 on the back surface side of the lead frame 30 is partially removed to form a slit hole 42. The slit hole 41 is formed to form an external connection terminal later. It had a width of about 0.5 mm and was formed by cutting the resin 42 with a blade of a dicing device. The blade is prepared in various thicknesses, and the blade is formed once or a plurality of times according to the thickness of the blade to be formed into a desired width. At this time, at the same time as the resin 41 is cut, the back surface of the lead terminal 34 is also cut by about 0.1 mm to expose the metal surface of the lead frame 30. This slit hole 42 is formed in each lead terminal 3.
4 is formed near the wedge-shaped "recess 36". Then, a plating layer 43 such as solder plating is formed on the surface of the lead terminal 34 exposed inside the slit hole 42. The plating layer 43 is formed by an electrolytic plating method using the lead frame 30 as one of the electrodes. After forming the slit holes 42 in this manner, the resin 41, the lead terminals 34, and the connection bars 35 are cut for each of the element mounting portions 31, and each of the elements A, B, and C. . . . Is separated. The separation is performed by cutting the island 33 and the area surrounding the lead terminal 34 connected to the semiconductor chip 39 fixed thereon (the cutting line 44 in the figure). A dicing device is used for the cutting, and the resin layer 41 and the lead frame 30 are simultaneously cut along the center of the concave portion 36 by a blade of the dicing device. FIG. 5 shows a schematic perspective view when cutting. Reference numeral 60 in FIG. 5 denotes a dicing blade.
【００２１】スリット孔４２が位置する箇所では、少な
くともスリット孔４２の側壁に付着したメッキ層４３を
残すように形成する。この様に残存させたメッキ層４３
は、半導体装置をプリント基板上に実装する際に利用さ
れる。また、切断したリード端子３４の他方はアイラン
ド３３に連続する突起部３３ａとして残存し、切断した
連結バー３５はアイランド３３に連続する突起部３３ｂ
として残存する。切断されたリード端子３４及び突起部
３３ａ、３３ｂの切断面は、樹脂層４１の切断面と同一
平面を形成し、該同一平面に露出する。ダイシング工程
においては裏面側（スリット孔４２を設けた側）にブル
ーシート（たとえば、商品名：ＵＶシート、リンテック
株式会社製）を貼り付け、前記ダイシングブレードがブ
ルーシートの表面に到達するような切削深さで切断す
る。更に、ダイシングブレードの板厚はスリット孔４２
の幅よりも薄い（例えば、幅０．１ｍｍ）ものを用い、
スリット孔４２の中心線に沿って、ダイシングブレード
がリード端子３３の凹部３６の中心線上を通過するよう
にダイシングした。これで、切断後のリード端子３３の
先端部が先細りの形状となり、樹脂４１から容易には抜
け落ちない形状に加工できる。At the position where the slit hole 42 is located, the plating layer 43 is formed so as to leave at least the plating layer 43 attached to the side wall of the slit hole 42. The plating layer 43 thus left
Is used when a semiconductor device is mounted on a printed circuit board. In addition, the other of the cut lead terminals 34 remains as a protrusion 33 a continuing to the island 33, and the cut connection bar 35 becomes a protrusion 33 b continuing to the island 33.
To remain. The cut surfaces of the cut lead terminals 34 and the protrusions 33a and 33b form the same plane as the cut surface of the resin layer 41, and are exposed on the same plane. In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Co., Ltd.) is attached to the back side (the side provided with the slit holes 42), and cutting is performed so that the dicing blade reaches the surface of the blue sheet Cut at depth. Further, the thickness of the dicing blade is determined by the slit hole 42.
Use a thinner than the width of (for example, 0.1 mm width),
Dicing was performed so that the dicing blade passed over the center line of the concave portion 36 of the lead terminal 33 along the center line of the slit hole 42. Thus, the tip of the lead terminal 33 after cutting has a tapered shape, and can be processed into a shape that does not easily fall off the resin 41.
【００２２】図６は完成後の半導体装置を裏面側からみ
たときの斜視図である。半導体チップ３９とボンディン
グワイヤ４０を含めて、アイランド３３とリード端子３
４が樹脂４１でモールドされて、大略直方体のパッケー
ジ形状を形成する。樹脂４１は熱硬化性エポキシ樹脂で
ある。樹脂４１の外形寸法は、縦×横×高さが、約０．
７ｍｍ×１．０ｍｍ×０．６ｍｍである。FIG. 6 is a perspective view of the completed semiconductor device as viewed from the back side. The island 33 and the lead terminal 3 including the semiconductor chip 39 and the bonding wire 40
4 is molded with a resin 41 to form a substantially rectangular parallelepiped package shape. The resin 41 is a thermosetting epoxy resin. The outer dimensions of the resin 41 are about 0.
It is 7 mm x 1.0 mm x 0.6 mm.
【００２３】直方体のパッケージ外形を形成する６面の
うち、少なくとも側面４１ａ、４１ｂ、４１ｃ、４１ｄ
は樹脂４１を切断した（第３工程参照）切断面で構成さ
れる。該切断面に沿ってリード端子３４の切断面が露出
する。アイランド３３には切断されたリード端子３４の
名残である突起部３３ａと連結部３５の名残である突起
部３３ｂを有し、これらの突起部３３ａ、３３ｂの切断
面も露出する。At least the side surfaces 41a, 41b, 41c and 41d of the six surfaces forming the rectangular package outer shape
Is constituted by a cut surface obtained by cutting the resin 41 (see the third step). The cut surface of the lead terminal 34 is exposed along the cut surface. The island 33 has a protruding portion 33a remaining on the cut lead terminal 34 and a protruding portion 33b remaining on the connecting portion 35, and the cut surfaces of these protruding portions 33a and 33b are also exposed.
【００２４】側面４１ｂ、４１ｄの裏面側には第４工程
で形成したスリット孔４２の名残である段差部４５を有
し、該段差部４５の表面にアイランド３３の突起部３３
ａの裏面側と、リード端子３４の裏面側の一部が露出す
る。アイランド３３とリード端子３４の露出した表面に
は半田メッキなどの金属メッキ層４３が形成される。リ
ード端子３４の露出部分とアイランド３３の露出部との
間は、樹脂４１で被覆される。On the back side of the side surfaces 41b and 41d, there is provided a step 45 which is a remnant of the slit hole 42 formed in the fourth step, and the protrusion 33 of the island 33 is provided on the surface of the step 45.
The back surface side of a and a part of the back surface side of the lead terminal 34 are exposed. A metal plating layer 43 such as solder plating is formed on the exposed surfaces of the island 33 and the lead terminals 34. The space between the exposed portion of the lead terminal 34 and the exposed portion of the island 33 is covered with the resin 41.
【００２５】リード端子３４の先端部と、アイランドの
突起部３３ａの先端部は、凹部３６の中心線で切断した
ことにより先細りの形状に加工される。つまり、樹脂４
１の切断面４１ｂ、４１ｄ表面に露出する部分のリード
端子３４の線幅は樹脂４１内部のアイランド３３近傍で
の線幅よりも細い。この様に加工されることで、リード
端子３４が樹脂４１からは引き抜けない状態になってい
る。The leading end of the lead terminal 34 and the leading end of the island projection 33a are cut into a tapered shape by cutting along the center line of the recess 36. That is, resin 4
The line width of the lead terminal 34 at the portion exposed on the surface of the cut surface 41b, 41d is smaller than the line width near the island 33 inside the resin 41. By being processed in this manner, the lead terminals 34 are not pulled out of the resin 41.
【００２６】この装置をプリント基板上に実装した状態
を図７に示す。実装基板２４上に形成した素子間接続用
のプリント配線２５に対して段差部４５に露出したリー
ド端子３４アイランド３３の突起部３３ａを位置合わせ
し、半田２６等によって両者を接続する。この時、上記
の第５工程で形成した金属メッキ層４３が半田の塗れ性
を良好にする。FIG. 7 shows a state in which this device is mounted on a printed circuit board. The protrusion 33a of the lead terminal 34 island 33 exposed at the step 45 is aligned with the printed wiring 25 for element connection formed on the mounting board 24, and the two are connected by solder 26 or the like. At this time, the metal plating layer 43 formed in the fifth step improves the wettability of the solder.
【００２７】以上の方法によって製造された半導体装置
は、以下のメリットを有する。金属製リード端子がパッ
ケージから突出しないので、実装面積を半導体装置の大
きさと同じ程度の大きさにすることができる。従って、
半導体装置の実装面積に対する能動部分（半導体チップ
３９のチップサイズを意味する意味する）の比である実
装有効面積を、図９に示したものに比べて大幅に向上で
きる。これにより、実装基板上に実装したときの実装面
積のデッドスペースを小さくすることができ、実装基板
の小型化に寄与することができる。The semiconductor device manufactured by the above method has the following advantages. Since the metal lead terminals do not protrude from the package, the mounting area can be made as large as the size of the semiconductor device. Therefore,
The effective mounting area, which is the ratio of the active portion (meaning the chip size of the semiconductor chip 39) to the mounting area of the semiconductor device, can be greatly improved as compared with that shown in FIG. Thereby, the dead space of the mounting area when mounted on the mounting board can be reduced, which can contribute to the miniaturization of the mounting board.
【００２８】パッケージの外形をダイシング装置のブレ
ードで切断することにより構成したので、リードフレー
ム３０のパターンに対する樹脂４１外形の位置あわせ精
度を向上できる。即ち、トランスファーモールド技術に
よるモールド金型とリードフレーム３０との合わせ精度
がプラス・マイナス５０μ程度であるのに対して、ダイ
シング装置によるダイシングブレードとリードフレーム
３０との合わせ精度はプラス・マイナス１０μ程度に小
さくできる。合わせ精度を小さくできることは、アイラ
ンド３３の面積を増大して、搭載可能な半導体チップ３
９のチップ面積を増大できることを意味し、これも上記
有効実装面積効率を向上させる。Since the outer shape of the package is formed by cutting the outer shape of the package with a blade of a dicing apparatus, the positioning accuracy of the outer shape of the resin 41 with respect to the pattern of the lead frame 30 can be improved. That is, while the alignment accuracy between the molding die and the lead frame 30 by the transfer molding technique is approximately ± 50 μ, the alignment accuracy between the dicing blade and the lead frame 30 by the dicing device is approximately ± 10 μ. Can be smaller. The fact that the alignment accuracy can be reduced means that the area of the island 33 is increased, and
9 means that the chip area can be increased, which also improves the effective mounting area efficiency.
【００２９】多数個の素子を１つのキャビティでまとめ
てパッケージングするので、個々にパッケージングする
場合に比べて無駄にする材料（樹脂）を少なくでき、材
料費の低減につながる。切断ライン４４で切断すること
で、その一方をリード端子３４、他方をアイランド３３
の外部接続端子（突起部３３ａ）として活用することが
できる。従って、リード端子３４近傍には無駄な箇所が
無く、しかも素子搭載部３１を密接配置できるので、こ
のリードフレームは枠体３２だけが廃棄対象となり、材
料の有効使用効率を向上できる。Since a large number of elements are packaged together in one cavity, wasteful material (resin) can be reduced as compared with the case of packaging individually, leading to a reduction in material cost. By cutting at the cutting line 44, one is the lead terminal 34 and the other is the island 33.
Can be used as external connection terminals (projections 33a). Therefore, there is no useless portion near the lead terminal 34 and the element mounting portion 31 can be closely arranged. Therefore, in this lead frame, only the frame 32 is to be discarded, and the effective use efficiency of the material can be improved.
【００３０】分割された半導体装置のリード端子３４の
終端は、図６に示すように、樹脂４１表面付近で先細り
の形状に形成されるために、リード端子３４が樹脂層４
１の側面から抜け落ちることを防止している。尚、上述
した実施形態では、３端子用のリードフレームを用いて
説明をしたが、リード端子を３本以上具備するような複
合素子や、ＢＩＰ、ＭＯＳ型等の集積回路等にも応用す
ることができる。As shown in FIG. 6, the ends of the lead terminals 34 of the divided semiconductor device are formed in a tapered shape near the surface of the resin 41, so that the lead terminals 34
It is prevented from falling off from one side. Although the above embodiment has been described using a lead frame for three terminals, the present invention is also applicable to a composite device having three or more lead terminals, an integrated circuit of BIP, MOS type, or the like. Can be.
【００３１】[0031]
【発明の効果】以上説明したように、本発明によれば、
リード端子３４をアイランドに保持させることにより、
リードフレームの無駄な部分を極力少なくし、更には素
子搭載部３１を密接配置する事で１つのリードフレーム
で製造できる素子の個数を倍増できる。従って装置製造
のコスト低減に寄与できる。As described above, according to the present invention,
By holding the lead terminal 34 on the island,
By minimizing useless portions of the lead frame and by closely arranging the element mounting portions 31, the number of elements that can be manufactured with one lead frame can be doubled. Therefore, it is possible to contribute to a reduction in the cost of manufacturing the device.
【００３２】このリードフレームを用いてモールド後に
分割するような製造方法を採用することにより、リード
端子３４がパッケージから突出しない、高密度実装に適
した半導体装置を得ることができる。パッケージの外形
をダイシングブレードによる切断面で構成することによ
り、アイランド３３と樹脂４１の端面との寸法精度を向
上できる。これにより、パッケージサイズを小型化でき
ると同時に、アイランド３３の面積を増大して、収納可
能な半導体チップ３９のチップサイズを増大できる。A semiconductor device suitable for high-density mounting, in which the lead terminals 34 do not protrude from the package, can be obtained by employing a manufacturing method in which the lead frame is divided after molding using the lead frame. By configuring the outer shape of the package with a cut surface by a dicing blade, the dimensional accuracy between the island 33 and the end face of the resin 41 can be improved. Thereby, the package size can be reduced, and at the same time, the area of the island 33 can be increased, and the chip size of the semiconductor chip 39 that can be stored can be increased.
【００３３】小型パッケージにも関わらず、凹部３６に
よって、リード端子３４の先端部を先細りの形状に加工
したので、リード端子３４が樹脂４１からは容易に抜け
落ちない形状に加工できる。Despite the small package, the leading end of the lead terminal 34 is formed into a tapered shape by the recess 36, so that the lead terminal 34 can be formed into a shape that does not easily fall off the resin 41.
【図１】本発明のリードフレームを説明する為の（Ａ）
平面図、（Ｂ）断面図である。FIG. 1 (A) for explaining a lead frame of the present invention.
It is a top view, (B) sectional drawing.
【図２】組立工程を説明する為の（Ａ）平面図、（Ｂ）
断面図である。FIG. 2A is a plan view for explaining an assembling process, and FIG.
It is sectional drawing.
【図３】組立工程を説明する為の（Ａ）平面図、（Ｂ）
断面図である。FIG. 3A is a plan view for explaining an assembling process, and FIG.
It is sectional drawing.
【図４】組立工程を説明する為の（Ａ）平面図、（Ｂ）
断面図である。FIG. 4A is a plan view for explaining an assembling process, and FIG.
It is sectional drawing.
【図５】切断するときの状態を示すための斜視図であ
る。FIG. 5 is a perspective view showing a state at the time of cutting.
【図６】完成後の半導体装置を裏面側からみた斜視図で
ある。FIG. 6 is a perspective view of the completed semiconductor device as viewed from the back side.
【図７】完成後の半導体装置を実装したときの状態を説
明する断面図である。FIG. 7 is a cross-sectional view illustrating a state when the completed semiconductor device is mounted.
【図８】従来のリードフレームを説明するための斜視図
である。FIG. 8 is a perspective view illustrating a conventional lead frame.
【図９】従来の半導体装置を説明する為の図である。FIG. 9 is a diagram illustrating a conventional semiconductor device.
Claims (3)
ドと、前記アイランドに先端を近接する複数本の外部接
続用のリード端子と、前記アイランド及びリード端子を
保持するための枠体部とを具備し、 前記アイランドと前記リード端子とが多数個行列状に配
置され、 前記アイランドが互いに連結され、かつ互いに連結され
たアイランドが前記枠体に保持され、 １つのアイランドに対応するリード端子が、その隣に位
置するアイランドに連結保持されていることを特徴とす
るリードフレーム。1. An island for fixing a semiconductor chip, a plurality of lead terminals for external connection near the tip of the island, and a frame for holding the island and the lead terminal. A plurality of the islands and the lead terminals are arranged in a matrix, the islands are connected to each other, and the connected islands are held by the frame; a lead terminal corresponding to one island is adjacent to the island; A lead frame, which is connected and held to an island located in a lead frame.
に、部分的に線幅を細くした凹部を有することを特徴と
する請求項１記載のリードフレーム。2. The lead frame according to claim 1, wherein a concave portion having a partially reduced line width is provided between the lead terminal and the island.
を示す位置合わせマークを具備することを特徴とする請
求項１記載のリードフレーム。3. The lead frame according to claim 1, wherein said frame has an alignment mark indicating a tip portion of said lead terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35746597A JP3831504B2 (en) | 1997-12-25 | 1997-12-25 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35746597A JP3831504B2 (en) | 1997-12-25 | 1997-12-25 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11186481A true JPH11186481A (en) | 1999-07-09 |
| JP3831504B2 JP3831504B2 (en) | 2006-10-11 |
Family
ID=18454271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35746597A Expired - Fee Related JP3831504B2 (en) | 1997-12-25 | 1997-12-25 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3831504B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244399A (en) * | 2000-03-02 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Lead frame and method of manufacturing resin sealed semiconductor device using |
| JP2006261525A (en) * | 2005-03-18 | 2006-09-28 | Disco Abrasive Syst Ltd | Package substrate |
| WO2013084842A1 (en) * | 2011-12-06 | 2013-06-13 | Kato Nobukazu | Led package and production method for led package |
| JP2015056540A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
| JP2017038051A (en) * | 2015-08-10 | 2017-02-16 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method of the same |
| JP2017199897A (en) * | 2016-04-20 | 2017-11-02 | ローム株式会社 | Semiconductor device |
| US10115870B2 (en) | 2008-09-03 | 2018-10-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
-
1997
- 1997-12-25 JP JP35746597A patent/JP3831504B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244399A (en) * | 2000-03-02 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Lead frame and method of manufacturing resin sealed semiconductor device using |
| JP2006261525A (en) * | 2005-03-18 | 2006-09-28 | Disco Abrasive Syst Ltd | Package substrate |
| US10115870B2 (en) | 2008-09-03 | 2018-10-30 | Nichia Corporation | Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body |
| WO2013084842A1 (en) * | 2011-12-06 | 2013-06-13 | Kato Nobukazu | Led package and production method for led package |
| JP2015056540A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
| JP2017038051A (en) * | 2015-08-10 | 2017-02-16 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method of the same |
| JP2017199897A (en) * | 2016-04-20 | 2017-11-02 | ローム株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3831504B2 (en) | 2006-10-11 |
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