JP2005202070A - Display device and pixel circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can suppress a change due to leakage of a gate potential of an output transistor even during a sampling period of another circuit, can obtain a uniform current source free of a variation in the current value of an output stage, and can display a high-grade image free of the occurrence of luminance unevenness, and also provide a pixel circuit. <P>SOLUTION: A sample hold circuit is provided with a TFT 121-1 whose source is connected to the prescribed potential, a TFT-123-1 which is connected between the drain of the TFT 121-1 and a supply line ISL of a signal current, a C 121-1 which is connected between the gate of the TFT 121-1 and a ground potential, a TFT 122-1 and TFT 123-1 which are connected in series between the drain and gate of the TFT 121-1, and a C 121-1 which is connected therebetween and a fixed potential. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is particularly provided in each pixel circuit among image display devices in which pixel circuits having electro-optic elements whose luminance is controlled by a current value, such as an organic EL (Electroluminescence) display, are arranged in a matrix. The present invention relates to a so-called active matrix image display device in which the value of a current flowing through an electro-optic element is controlled by an insulated gate field effect transistor, and a pixel circuit.

In an image display device, such as a liquid crystal display, an image is displayed by arranging a large number of pixels in a matrix and controlling the light intensity for each pixel in accordance with image information to be displayed.
This is the same for an organic EL display or the like, but the organic EL display is a so-called self-luminous display having a light emitting element in each pixel circuit, and has a higher image visibility than a liquid crystal display. There are advantages such as unnecessary and high response speed.
The luminance of each light emitting element is greatly different from a liquid crystal display or the like in that a color gradation is obtained by controlling the luminance of the light emitting element according to the current value flowing therethrough, that is, the light emitting element is a current control type.

In the organic EL display, as with the liquid crystal display, a simple matrix method and an active matrix method can be used. However, although the former has a simple structure, it is difficult to realize a large and high-definition display. There's a problem.
For this reason, active matrix systems have been actively developed in which the current flowing in the light emitting elements in each pixel circuit is controlled by active elements provided in the pixel circuits, generally TFTs (Thin Film Transistors). .

FIG. 25 is a block diagram showing a configuration of the organic EL display device.
As shown in FIG. 25, the display device 1 includes a pixel array unit 2 in which pixel circuits (PXLC) 2a are arranged in an m × n matrix, a horizontal selector (HSEL) 3, a light scanner (WSCN) 4, a horizontal Data lines DTL1 to DTLn selected by the selector 3 and supplied with data signals corresponding to luminance information, and scanning lines WSL1 to WSLm selectively driven by the write scanner 4 are provided.

FIG. 26 is a circuit diagram showing a configuration example of the pixel circuit 2a of FIG. 25 (see, for example, Patent Documents 1 and 2).
The pixel circuit in FIG. 26 has the simplest circuit configuration among many proposed circuits, and is a so-called two-transistor driving circuit.

A pixel circuit 2a shown in FIG. 26 includes a p-channel thin film field effect transistor (hereinafter referred to as TFT) 11 and TFT 12, a capacitor C11, and an organic EL element (OLED) 13 which is a light emitting element. In FIG. 26, DTL indicates a data line through which an input signal is propagated as a voltage, and WSL indicates a scanning line.
Since organic EL elements often have rectifying properties, they are sometimes called OLEDs (Organic Light Emitting Diodes). In FIG. 26 and others, the symbol of a diode is used as a light emitting element. It does not necessarily require rectification.
In FIG. 26, the source of the TFT 11 is connected to the power supply potential VCC (supply line of the power supply voltage VCC), and the cathode (cathode) of the light emitting element 13 is connected to the ground potential GND. The operation of the pixel circuit 2a in FIG. 26 is as follows.

  In step ST1, as shown in FIG. 26, when the scanning line WSL is selected (here, low level) and the write potential Vdata is applied to the data line DTL, the TFT 12 becomes conductive and the capacitor C11 is charged or discharged. The gate potential becomes Vdata.

  In step ST2, if the scanning line WSL is in a non-selected state (here, high level), the data line DTL and the TFT 11 are electrically disconnected, but the gate potential of the TFT 11 is stably held by the capacitor C11.

In step ST3, the current flowing through the TFT 11 and the light emitting element 13 has a value corresponding to the gate-source voltage Vgs of the TFT 11, and the light emitting element 13 continues to emit light with a luminance corresponding to the current value.
The operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 is hereinafter referred to as “writing”.
As described above, in the pixel circuit 2a of FIG. 26, once Vdata is written, the light emitting element 13 continues to emit light with substantially constant luminance until the next rewriting.

As described above, in the pixel circuit 2a, the value of the current flowing through the EL light emitting element 13 is controlled by changing the gate application voltage of the TFT 11 which is a drive transistor.
At this time, the source of the p-channel drive transistor is connected to the power supply potential VCC, and the TFT 11 always operates in the saturation region. Therefore, the constant current source has a value represented by the following formula 1.

[Equation 1]
Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² (1)

  Here, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the gate width, L is the gate length, Vgs is the gate-source voltage of the TFT 11, and Vth is the threshold Vth of the TFT 11. Respectively.

  In the simple matrix image display device, each light emitting element emits light only at the selected moment, whereas in the active matrix, as described above, the light emitting element continues to emit light even after the writing is completed. This is particularly advantageous for large-sized and high-definition displays in that the peak luminance and peak current of the light-emitting element can be reduced.

FIG. 27 is a circuit diagram illustrating a configuration example of a pixel circuit to which a current signal is input.
A pixel circuit 2b illustrated in FIG. 27 includes TFTs 21 to 24, a capacitor C21, and an organic EL element (OLED) 25. In FIG. 27, DTL indicates a data line through which an input signal is propagated as a current.
In FIG. 27, the source of the TFT 21 is connected to the power supply voltage VCC (supply line of the power supply voltage VCC), and the cathode (cathode) of the light emitting element 25 is connected to the ground potential GND. The operation of the pixel circuit 2b in FIG. 27 is as follows.

When the input signal (current signal) SI is written, the TFTs 23 and 24 are held in a conductive state while the TFT 22 is held in a non-conductive state.
As a result, a current corresponding to the signal current flows through the TFT 21 which is a drive transistor.
At this time, the gate and drain of the TFT 21 are connected and driven in the saturation region.
Therefore, the gate voltage corresponding to the input current is written based on the above formula 1, and is held in the capacitor C21 which is a pixel capacitance.
Thereafter, the TFT 24 is held in a non-conductive state, and the TFT 22 is held in a conductive state.
As a result, a current corresponding to the input signal current flows to the TFT 21 and the light emitting element 25, and the light emitting element 25 emits light with a luminance corresponding to the current value.

FIG. 28 is a circuit diagram showing a configuration of a main part of a horizontal selector that inputs a current signal to the pixel circuit shown in FIG. 27, for example.
As shown in FIG. 28, the horizontal selector is provided corresponding to the data lines DTL1, DTL2,..., DTLn, which are wired for each column with respect to the matrix arrangement of the pixel circuits and to which data signals corresponding to the luminance information are supplied. Current sample and hold circuits 31-1, 31-2,..., 31-n, and horizontal switches (HSW) 32-1, 32-2,. .

As shown in FIG. 28, the current sample and hold circuit 31-1 includes a TFT 33-1, a TFT 34-1, a TFT 35-1, a capacitor C31-1, and nodes ND31-1 and ND32-1.
Similarly, as shown in FIG. 28, the current sample and hold circuit 31-2 includes a TFT 33-2, a TFT 34-2, a TFT 35-2, a capacitor C31-2, and nodes ND31-2 and ND32-2. .
Although not shown, the current sample and hold circuit 31-n includes a TFT 33-n, a TFT 34-n, a TFT 35-n, a capacitor C31-n, and nodes ND31-n and ND32-n, as shown in FIG. doing.

The sample hold operation of the horizontal selector 3 will be described with reference to FIGS. 29 (A) to (M).
Note that SHSW in FIG. 29A indicates a switching signal of the horizontal switch. 29H shows the drain potential Vd331 of the TFT 33-1 in the first column, FIG. 29I shows the drain potential Vd332 of the TFT 33-2 in the second column, and FIG. The drain potential Vd33n of the TFT 33-n in the column, FIG. 29K shows the potential VC111 of the capacitor C11-1 in the first column, and FIG. 29L shows the potential VC112 of the capacitor C11-2 in the second column. FIG. 29M shows the potential VC11n of the capacitor C11-n in the nth column.

As shown in FIG. 29A, in the state where the switching signal SHSW is at a low level and the all horizontal switches HSW are turned off, as shown in FIGS. 29B and 29C, the current sample hold of the first column is shown. The sample hold lines SHL31-1, 32-1 to which the TFTs 34-1, 35-1 of the circuit 31-1 are connected are set to a high level, and the TFTs 34-1, 35-1 are turned on (turned on).
At this time, the input signal current Iin flows in the current sample hold circuit 31-1. At this time, the TFT 33-1 has a gate-drain connected via the TFT 34-1 and operates in a saturation region. The gate voltage is determined based on the above equation 1, and held in the capacitor C31-1, as shown in FIG.
After a predetermined gate voltage is written to the capacitor C31-1, the sample hold line SHL31-1 is set to a low level to make the TFT 34-1 non-conductive, and then the sample hold line SHL32-1 is set to a low level to set the TFT 35-1 to a low level. Non-conducting state.

Next, similarly, as shown in FIGS. 29D and 29E, the sample hold line SHL31-2 to which the TFTs 34-2 and 35-2 of the current sample hold circuit 31-2 in the second column are connected. , 32-2 are set to a high level, and the TFTs 34-2 and 35-2 are turned on (turned on).
At this time, the input signal current Iin flows in the current sample and hold circuit 31-2. At this time, the gate of the TFT 33-2 is connected via the TFT 34-2, and operates in a saturated state. The gate voltage is determined based on the above equation 1, and is held in the capacitor C31-2 as shown in FIG.
After a predetermined gate voltage is written to the capacitor C31-2, the sample hold line SHL31-2 is set to a low level to make the TFT 34-2 nonconductive.
Thereafter, the adjacent sample and hold circuits sequentially operate, and the video signal Iin is sampled and held in dot sequential order in all the circuits.
Thereafter, as shown in FIG. 29A, the horizontal switches HSW are turned on simultaneously in all stages, and the TFTs 33-1 to 33-n function as constant current sources. As shown in FIG. Are output to the data lines DTL1 to DTLn.

USP 5,684,365 JP-A-8-234683

In the pixel circuit 2a shown in FIG. 26 described above, for example, the scanning line WSL is selected, the write potential Vdata1 is applied to the data line DTL, the TFT 12 is turned on to charge or discharge the capacitor C11, and the TFT 11 After the gate potential is set to Vdata1, the scanning line WSL is in a non-selected state, and the data line DTL and the TFT 11 are electrically disconnected, the potential of the data line DTL is set to charge or discharge the capacitor C11 of the pixel circuit 2a in the next stage. When Vdata2 is set, a potential difference is generated between the source and drain of the TFT 112.
Then, a leakage current corresponding to this potential difference flows out (leaks) from the capacitor C11, the potential held in the capacitor C11 changes with time, and Vgs in Equation 1 changes, so that the current flowing in the light emitting element 13 The value changes and the image quality uniformity deteriorates.

In order to improve this leakage problem, for example, a pixel circuit shown in FIG. 31 has been proposed.
A pixel circuit 2c in FIG. 31 includes a p-channel TFT 41, n-channel TFTs 42 to 44, a capacitor C41, and an organic EL light emitting element (OLED) 45 that is a light emitting element. In FIG. 31, DTL indicates a data line through which an input signal is propagated as a voltage, WSL indicates a scanning line, and CL indicates a control line.
In FIG. 31, the source of the TFT 41 is connected to the power supply potential VCC, and the cathode of the light emitting element 45 is connected to the ground potential GND. A first electrode of the capacitor C41 is connected to the node ND41, and a second electrode is connected to the power supply potential VCC. Between the data line DTL and the gate of the TFT 41, the sources and drains of the TFTs 42 and 43 are connected in series via the node ND41, and the gates of the TFTs 42 and 43 are connected to the scanning line WSL. The source and drain of the TFT 44 are connected between the node ND41 between the TFTs 42 and 43 and the set potential V0. A control line CL is connected to the gate of the TFT 44.

The operation of the pixel circuit 2c will be described.
As shown in FIG. 32, when the input signal Vin supplied to the data line DTL is written, when the TFTs 42 and 43 are turned on with the TFT 44 turned off, the capacitor C41 is charged or discharged, and the gate potential of the TFT 41 becomes Vin. Become.
Then, as shown in FIG. 33, the TFTs 42 and 43 are turned off, the TFT 44 is turned on, and the source / drain voltage (Vin−V0) of the TFT 41 is decreased by setting the set potential V0.

However, since the source / drain voltage of the TFT 41 is 0 as shown in FIG. 33 during monochrome raster display, the leakage current flows conversely to the capacitor C41, and the value of the input voltage held by the capacitor C41 increases with time. The image quality is deteriorated as compared with the pixel circuit 2a.
This problem becomes a problem for all display devices having a storage capacitor in a pixel such as a liquid crystal, regardless of the organic EL.

By the way, in the horizontal selector shown in FIG. 30, the drain potential of the TFT 33 (-1 to -n) functioning as a constant current source, particularly the drain potential of the TFT 33 in which the sample hold operation is performed first, drops and becomes constant. There is a disadvantage that it cannot be held.
This problem will be described in more detail.

Here, the potential of each node at the time of sample hold of the current sample hold circuit 31-1 in the first column is examined.
In the current sample and hold circuit 31-1, as shown in FIG. 34A, the TFT 35-1 is held in a non-conductive state, and the input current Iin is sampled and held. During this period, since the TFT 33-1 continues to be on, the drain potential of the TFT 33-1 (the potential of the ND31-1) disappears, and falls to the ground potential GND level.
At this time, attention is paid to the TFT 34-1. The TFT 34-1 is off, and the capacitor C31-1 holds a gate potential corresponding to the current Iin.

  However, as the potential of the node ND31-1 falls to the ground potential GND level, the drain-source voltage Vds is applied to the TFT 34-1 as shown in FIG. Leak current. When this leakage current flows out from the capacitor C31-1, the gate voltage of the TFT 33-1 decreases. As a result, the gate-source voltage Vgs of the TFT 33-1 is reduced compared to the sample-and-hold state, and only a current value smaller than the current Iin flows even if the horizontal switch HSW is turned on and enters a saturation region. End up. This leak amount is proportional to the leak time.

Since the current sample and hold circuit operates dot-sequentially as described above, the time at which the gate potential is held in each capacitor differs between the scan start unit and the scan end unit. That is, the holding time is longer in the scan start part than in the end part.
For this reason, the leak time also becomes longer at the scan start portion, and the gate voltage drop amount becomes larger than that at the scan end portion. That is, even if a single color raster display is performed on the entire screen, the luminance gradations toward the end of scanning as shown in FIG.
In particular, TFTs for driving organic EL or the like have a high leakage current, so this problem appears remarkably.

Regardless of the organic EL, this problem becomes a problem at any time when the current is sampled.
For example, when the current is sampled dot-sequentially and output in a batch, the output current value differs between the sampling start part and the end part for the same reason.

  The present invention has been made in view of such circumstances, and the object of the present invention is to suppress changes due to leakage of the gate potential of the output transistor even during the sampling period of other circuits, and to prevent variations in the current value of the output stage. It is an object of the present invention to provide a display device and a pixel circuit that can obtain a high-quality image that does not cause uneven luminance and can provide a uniform current source.

  In order to achieve the above object, a display device according to a first aspect of the present invention is a display device to which a video signal is supplied as a signal current, and includes a plurality of pixel circuits arranged in a matrix, A data line wired for each column with respect to the matrix array and supplied with a signal current corresponding to luminance information, and a plurality of sample hold circuits provided corresponding to the data lines and sample-holding the input video signal current Each sample-and-hold circuit is operated in the column direction sequentially, and all the sample-and-hold circuits sample and hold the video signal dot-sequentially, and the current values sampled and held by the plurality of sample-and-hold circuits correspond to the corresponding data. The horizontal selector to be output to the line and the horizontal selector include a signal current supply line, and each of the sample and hold circuits has a source connected to a predetermined potential. A field effect transistor, a first switch connected between the drain of the field effect transistor and the signal current supply line, and a first switch connected between the gate of the field effect transistor and a predetermined potential. 1 capacitor, a second switch and a third switch connected in series between the drain and gate of the field effect transistor, and between the second and third switches and a fixed potential. And a second capacitor connected.

  Preferably, at the time of sample and hold, the sample and hold circuit holds charges corresponding to the signal current from the supply line in the first and second capacitors through the second and third switches. The second and third switches are turned off.

According to the display device of the first aspect of the present invention, the sample hold circuit is provided corresponding to the data line, and samples and holds the input video signal current.
The horizontal selector operates each sample-and-hold circuit sequentially in the column direction, causes all the sample-and-hold circuits to sample and hold the video signal dot-sequentially, and corresponds to the current values sampled and held by the plurality of sample-and-hold circuits. Output to data line, including signal current supply line.
Each of the sample and hold circuits includes a field effect transistor having a source connected to a predetermined potential, a first switch connected between the drain of the field effect transistor and the signal current supply line, and the field effect transistor. A first capacitor connected between the gate of the transistor and a predetermined potential; a second switch and a third switch connected in series between the drain and gate of the field effect transistor; A second capacitor connected between the third switch and a fixed potential;
At the time of sample-holding, the first and second capacitors are held with electric charges according to the signal current from the supply line through the second and third switches, and the second and third switches are turned off. Make it conductive.

  Further, in order to achieve the above object, a display device according to a second aspect of the present invention is a display device to which a video signal is supplied as a signal current, and a plurality of pixel circuits arranged in a matrix and the pixel A data line wired for each column with respect to the matrix arrangement of the circuit and supplied with a signal current according to luminance information, and a plurality of sample holds provided corresponding to the data line for sampling and holding the input video signal current Each sample and hold circuit is operated sequentially in the column direction, and the video signals are sampled and held in dot-sequential order by all the sample and hold circuits, and the current values sampled and held by the plurality of sample and hold circuits are supported. A horizontal selector that outputs to the data line to be output, and the horizontal selector includes a signal current supply line. Each of the sample and hold circuits has a predetermined source Connected between the drain of the field effect transistor and the signal current supply line, and connected between the gate of the field effect transistor and a predetermined potential. Between the connected capacitor, the second switch and the third switch connected in series between the drain and gate of the field effect transistor, between the second and third switches, and a fixed potential And a fourth switch connected thereto.

  In order to achieve the above object, a pixel circuit according to a third aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes depending on a flowing current, and is supplied with a data signal corresponding to luminance information. Drive transistor for forming a current supply line between the data line, the power supply voltage source, the reference potential, the first terminal and the second terminal, and controlling the current flowing through the current supply line in accordance with the potential of the control terminal A first capacitor connected between the power supply voltage source and the control terminal, first and second switches connected in series between the data line and the control terminal, and the first and second switches A second capacitor connected between the second switch and a fixed potential, and between the power supply voltage source and a reference potential, the current supply line of the driving transistor, the first capacitor Node, and above Optic elements are connected in series.

  In order to achieve the above object, a pixel circuit according to a fourth aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes according to a flowing current, and is supplied with a data signal corresponding to luminance information. Connected to the first node, the first and second control lines, the first, second, and third nodes, the power supply voltage source, the reference potential, the fixed potential, and the first node. A drive transistor configured to form a current supply line between the first terminal and the second terminal and control a current flowing through the current supply line in accordance with a potential of a control terminal connected to the second node; A first switch connected to a node; a second and third switch connected in series between the first node and the second node; and between the second and third switches , The first connected between the fixed potential A capacitor, a fourth switch connected between the data line and the third node and controlled to be conducted by the first control line, and between the second node and the third node. A second capacitor connected to the first capacitor, a third capacitor connected between the third node and the power supply voltage source, and a second capacitor connected between the third node and the power supply voltage source, A fifth switch whose conduction is controlled by a second control line, and a current supply line of the drive transistor, the first node, and the electro-optic between the power supply voltage source and a reference potential Elements are connected in series.

  In order to achieve the above object, a pixel circuit according to a fifth aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes depending on a flowing current, and a data signal corresponding to luminance information is supplied. Connected to the first node, the first and second control lines, the first, second, and third nodes, the power supply voltage source, the reference potential, the fixed potential, and the first node. A drive transistor configured to form a current supply line between the first terminal and the second terminal and control a current flowing through the current supply line in accordance with a potential of a control terminal connected to the second node; A first switch connected to a node; a second and third switch connected in series between the first node and the second node; and between the second and third switches , Connected between the fixed potential and the fourth And a fifth switch connected between the data line and the third node and controlled to be conductive by the first control line, and between the second node and the third node. A first capacitor connected to the second capacitor, a second capacitor connected between the third node and the power supply voltage source, and a connection between the third node and the power supply voltage source, A sixth switch whose conduction is controlled by a second control line, and a current supply line of the drive transistor, the first node, and the electro-optic between the power supply voltage source and a reference potential Elements are connected in series.

  According to the present invention, it is possible to suppress a change due to the leakage of the gate potential of the output transistor even in the sampling period of other circuits, and to obtain a uniform current source with no variation in the current value of the output stage. It is possible to provide a display device and a pixel circuit capable of displaying a high-quality image without unevenness.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration example of an organic EL display device according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration of the pixel circuit according to the present embodiment in the organic EL display device shown in FIG.

  As shown in FIGS. 1 and 2, an organic EL display device (display device) 100 according to the present embodiment includes a pixel array unit 102 in which pixel circuits (PXLC) 101 are arranged in an m × n matrix, a horizontal selector. (HSEL) 103, write scanner (WSCN) 104, drive scanner (DSCN) 105, data lines DTL101 to DTL10n to which data signals corresponding to luminance information selected by the horizontal selector 103 are sequentially supplied as voltage signals, write scanner 104 The scanning lines WSL101 to WSL10m that are selectively driven by the above and the driving lines DSL101 to DSL10m that are selectively driven by the drive scanner 105.

In the pixel array unit 102, the pixel circuits 101 are arranged in an m × n matrix, but FIG. 1 shows an example in which the pixel circuits 101 are arranged in a 2 × 3 matrix for simplification of the drawing.
FIG. 2 also shows a specific configuration of one pixel circuit for simplifying the drawing.

As shown in FIG. 2, the pixel circuit 101 according to the present embodiment includes a p-channel TFT 111, an n-channel TFT 112, a TFT 113, a capacitor C111, a capacitor C112, a light emitting element 114 composed of an organic EL element (OLED: electro-optical element), It has one node ND111 and a second node ND112.
In FIG. 2, DTL 101 represents a data line, WSL 101 represents a scanning line, and DSL 101 represents a drive line.

In the pixel circuit 101, a TFT 111 and a light emitting element 114 are connected in series between the power supply potential VCC and the ground potential GND.
Specifically, the source of the TFT 111 as the drive transistor is connected to the supply line of the power supply voltage VCC, the drain is connected to the anode of the light emitting element 114, and the cathode of the light emitting element 114 is connected to the ground potential GND. The gate of the TFT 111 is connected to the first node ND111.
The source and drain of the TFT 112 are connected to the first node ND111 and the second node ND112, and the gate of the TFT 112 is connected to the drive line WL101.
A first electrode of the capacitor C111 is connected to the first node ND111, and a second electrode is connected to the power supply potential VCC.
The source / drain of the TFT 113 is connected to the data line DTL101 and the second node ND112, and the gate of the TFT 113 is connected to the drive line DSL101.
The first electrode of the capacitor C112 is connected to the second node ND112, and the second electrode is connected to the fixed potential Vf.

FIG. 3 is a timing chart of the pixel circuit shown in FIG. 4 and 5 are diagrams for explaining the operation of the pixel circuit shown in FIG.
3A shows the potential of the driving line DSL101, FIG. 3B shows the potential of the scanning line WSL101, the dotted line in FIG. 3C shows the potential of the node ND111, and the solid line in FIG. The potential of the node ND112 is shown.

In the non-light emitting period of the light emitting element 114, as shown in FIGS. 3A and 3B, the driving line DSL101 and the scanning line WSL101 are set to a high level, and the TFT 112 and the TFT 113 are turned on (turned on).
As shown in FIG. 4, the input voltage Vin is written into the capacitors C111 and 112, and a current corresponding to the input voltage Vin flows through the light emitting element 114 by the TFT 111.
At this time, as shown in FIGS. 3C and 3D, the potentials of the node ND111 and the node ND112 are both held at Vin.

  Next, as shown in FIG. 3A, the drive line DSL101 is set to a low level, the TFT 113 is turned off, the node ND111 and the node ND112 are set to the same potential, and then scanned as shown in FIG. 3B. The line WSL101 is set to a low level, and the TFT 112 is turned off.

Next, when the input voltage Vin_N is set to apply a new input voltage Vin_N to the capacitor C of the pixel circuit of the next stage to the data line DTL101, the TFT 113 has a source-drain connection as shown in FIG. Although the voltage Vin-Vin_N is applied, the source-drain voltage of the TFT 112 is zero.
A leak current corresponding to the source-drain voltage Vin-Vin_N flows through the TFT 113. When the leak current flows out from C112, the potential of the node ND112 decreases as shown in FIG.
On the other hand, in the TFT 112, with the change of the node ND112 described above, the source-drain voltage increases from 0 and a leak current flows.
However, as the potential of the node ND112 leaks the charge held by the capacitor C112, the voltage between the source and drain of the TFT 112 gradually changes from zero.
Therefore, the potential of node ND111 decreases as shown in FIG. 3D, for example. As shown in FIGS. 3C and 3D, the potential decrease amount ΔV1 of the node ND111 is smaller than the potential decrease amount ΔV2 of the node ND112.
Further, the decrease amount ΔV1 of the potential of the node ND111 is smaller than the decrease amount ΔV of the gate / source potential in the pixel circuit 2a shown in FIG. 26 as a conventional example, for example.

  Further, even during monochromatic raster display, the source-drain voltage of the TFT 113 is 0, so that no leakage current flows. Therefore, the potential of the node ND111 is not changed and the image quality is not affected.

FIG. 6 is a block diagram showing a configuration example of an organic EL display device according to the second embodiment of the present invention.
FIG. 7 is a circuit diagram showing a specific configuration of the pixel circuit according to the second embodiment in the organic EL display device shown in FIG.

  As shown in FIGS. 6 and 7, the display device 100 a according to the present embodiment includes a pixel array unit 102 a in which pixel circuits (PXLC) 101 a are arranged in an m × n matrix, a horizontal selector (HSEL) 103, a light Data lines DTL101 to DTL10n selected by the scanner (WSCN) 104, drive scanner (DSCN) 105, pre-scanner 106, horizontal selector 103 and data signals corresponding to luminance information are sequentially supplied as current signals, and selected by the write scanner 104 The scanning lines WSL101 to WSL10m are driven, the driving lines DSL101 to DSL10m are selectively driven by the drive scanner 105, and the pre-scanning lines PSL101 to 10m are selectively driven by the prescanner 106.

In the pixel array unit 102a, the pixel circuits 101a are arranged in an m × n matrix, but FIG. 6 shows an example in which the pixel circuits 101a are arranged in a 2 × 3 matrix for simplification of the drawing.
FIG. 7 also shows a specific configuration of one pixel circuit for simplification of the drawing.

As shown in FIG. 7, the pixel circuit 101a according to the present embodiment includes capacitors C201 to C203, p-channel TFT 211, n-channel TFTs 212 to TFT216, a light-emitting element 217 including an organic EL element (OLED: electro-optical element), a first Node ND201, second node ND202, and third node ND203.
In FIG. 7, DTL 101 represents a data line through which an input signal is propagated as a voltage, WSL 101 represents a scanning line, DSL 101 represents a drive line, and PSL 101 represents a pre-scanning line.

In the pixel circuit 101a, a TFT 211, a node ND201, a TFT 212, and a light emitting element 217 are connected in series between the power supply potential VCC and the ground potential GND.
Specifically, the source of the TFT 211 as a drive transistor is connected to the supply line of the power supply voltage VCC, and the drain is connected to the first node ND201. The source of the TFT 212 is connected to the first node ND201, the drain is connected to the anode of the light emitting element 217, and the cathode of the light emitting element 217 is connected to the ground potential GND. The gate of the TFT 111 is connected to the second node ND202.
The source / drain of the TFT 213 is connected to the first node ND201 and the third node ND203, and the TFT 214 is connected to the second node ND202 and the third node ND203. The gate of the TFT 213 is connected to the scanning line WSL101, and the gate of the TFT 214 is connected to the scanning line WSL101.

  The first electrode of the capacitor C201 is connected to the third node ND203, and the second electrode is connected to the fixed potential Vf. The first electrode of the capacitor C202 is connected to the second node ND202, and the second electrode is connected to the fourth node ND204. The first electrode of the capacitor C203 is connected to the power supply potential VCC, and the second electrode is connected to the fourth node ND204.

  The drain of the TFT 215 is connected to the fourth node ND204, the source is connected to the power supply potential VCC, and the gate is connected to the scanning line WSL101. The drain of the TFT 216 is connected to the fourth node ND204, the source is connected to the DTL101, and the gate is connected to the pre-scan line PSL101.

FIG. 8 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 8A shows a signal applied to the scanning line WSL101 in the first row of the pixel array, and FIG. 8B shows a signal applied to the driving line DSL101 in the first row of the pixel array. (C) shows signals applied to the pre-scan line PSL101 in the first row of the pixel array.
9 and 10 are equivalent circuit diagrams of the pixel circuit shown in FIG.
The operation of the above configuration will be described with reference to FIGS. 8 to 10 focusing on the operation of the pixel circuit 101a.

As shown in FIG. 9, in the non-emission period of the light emitting element 217, the pre-scan line PSL101 is at a low level and the drive line DSL101 is at a low level, so that the TFTs 212 and 216 are in a non-conduction state (off state).
Next, the scanning line WSL101 is set to a high level, the TFTs 213, 214, and 215 are turned on (on state), and the drive transistor TFT 211 is cut off.
In the cut-off state, no current flows in the TFT 211, so the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor of each pixel, and the fluctuation of Vth for each pixel is cancelled.

Next, as shown in FIG. 10, the scanning line WSL101 is set to a low level and the TFTs 213, 214, and 215 are turned off (off state), and then the drive line DSL101 is set to a high level as shown in FIG. 8B. As a result, the TFT 212 is turned on (turned on). Next, as shown in FIG. 8C, the pre-scan line PSL101 is set to the high level, the TFT 216 is turned on for a predetermined time (turned on), and the drive line DSL101 is set to the low level as shown in FIG. 8B. .
When the TFT 212 is turned on, the signal line voltage Vin is coupled to the gate of the TFT 211 via the capacitor C202 in the pixel, and the light emitting element 217 emits light.

  If the gate voltage of the TFT 211 is changed to Vg due to coupling, a potential difference is generated between the gate and drain of the driving transistor. This potential difference becomes the largest during black display. When the voltage of the light emitting element 217 during black display is Vel, a potential difference of Vg−Vel is generated between the gate and drain of the TFT 211.

Hereinafter, the case of black display will be considered.
In the pixel circuit 101a according to this embodiment, the potential of the node ND203 is VCC-Vth, and the potential difference between the source and drain of the TFT 214 is zero. Although the potential of the node ND203 gradually changes due to leakage of the TFT 213, the source-drain voltage of the TFT 214 is 0. Therefore, even if the potential of the node ND203 changes due to the leakage current of the TFT 213, Since the drain-to-drain voltage is small, the leakage current is also small and uniform image quality can be obtained.
Similarly, when white is displayed, the leak current of the TFT 214 is reduced, so that a uniform image quality without unevenness can be obtained.

  In this embodiment, the capacitor C201 is connected to the fixed potential Vf. However, the fixed potential is preferably the power supply voltage VCC or the ground potential GND in view of the layout and the like.

FIG. 11 is a circuit diagram showing a specific configuration of the pixel circuit according to the third embodiment in the organic EL display device of the present invention.
As shown in FIG. 11, the pixel circuit 101b according to the present embodiment includes capacitors C202 and C203, p-channel TFT 211, n-channel TFTs 212 to 216, TFT 218, a light-emitting element 217 including an organic EL element (OLED: electro-optical element), It has a first node ND201, a second node ND202, and a third node ND203.
Only differences between the second embodiment and the third embodiment will be described.

The difference between the pixel circuit 101b according to the present embodiment and the pixel circuit 101a according to the second embodiment is that the pixel circuit 101b includes a TFT 218 between the third node ND203 and the fixed potential Vf instead of the capacitor C201. It is a point provided.
Specifically, the source / drain of the TFT 218 is connected between the third node ND203 and the fixed potential Vf, and the gate is connected to the second pre-scan line PPSL101 that is driven by the second pre-scan (not shown).
The other components are substantially the same as those in the second embodiment, and thus the same reference numerals are given and the description thereof is omitted.

FIG. 12 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 12A shows a signal applied to the first scanning line WSL101 in the pixel array, and FIG. 12B shows a signal applied to the second pre-scanning line PPSL101 in the first row of the pixel array. FIG. 12C shows a signal applied to the drive line DSL101 in the first row of the pixel array, and FIG. 12D shows a signal applied to the pre-scan line (first pre-scan line) PSL101. ing.
Next, the operation of the above configuration will be described with reference to FIGS.

  As shown in FIG. 13, in the non-emission period of the light emitting element 217, the pre-scan line PSL101 is set to a low level as shown in FIG. 12D, and the drive line DSL101 is set to a low level as shown in FIG. The TFT 212 and the TFT 216 are turned off (off state).

Next, the second pre-scan line PPSL101 is set to a low level as shown in FIG. 12B, the FT 218 is turned off (off state), and the scan line WSL101 is set to a high level as shown in FIG. Then, the TFT 213, the TFT 214, and the TFT 215 are turned on (on state), and the driving transistor TFT 211 is cut off.
In the cut-off state, no current flows in the TFT 211, so the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor of each pixel, and the fluctuation of Vth for each pixel is cancelled.

Next, as shown in FIG. 12B, the second pre-scan line PPSL is set to a high level, and as shown in FIG. 14, the TFT 218 is turned on (turned on), and the node ND203 of the node ND203 is turned on. Is fixed at a fixed potential Vf. Further, as shown in FIG. 12A, the scanning line WSL101 is set to a low level and the TFTs 213, 214, and 215 are turned off (off state), and then the drive line DSL101 is set to a high level as shown in FIG. After that, the pre-scan line PSL101 is set to a high level for a predetermined time as shown in FIG. 12D, the TFT 212 and the TFT 216 are turned on (turned on), and driven as shown in FIG. Line DSL101 is set to a low level.
When the TFT 212 is turned on, the signal line voltage Vin is coupled to the gate of the TFT 211 via the capacitor C202 in the pixel, and the light emitting element 217 emits light.

If the gate voltage of the TFT 211 is changed to Vg due to the coupling, a potential difference is generated between the gate and the source of the driving transistor. This potential difference becomes the largest during black display. When the voltage of the light emitting element 217 during black display is Vel, a potential difference of Vg−Vf occurs between the gate and drain of the TFT 211.
This is because the potential of the node ND203 becomes Vf when the TFT 218 is on. For this reason, a leak current determined by Equation 1 and Vg−Vf flows, but by setting the fixed potential Vf, the leak current can be reduced and uniform image quality can be obtained.

FIG. 15 is a block diagram showing a configuration example of an organic EL display device according to the fourth embodiment of the present invention.
FIG. 16 is a circuit diagram showing a specific configuration of a pixel circuit and a horizontal selector of the organic EL display device adopting the current driving method shown in FIG.

  15 and 16, the display device 100b according to this embodiment includes a pixel array unit 102b in which pixel circuits 101b are arranged in an m × n matrix, a horizontal selector (HSEL) 103b, and a light scanner (WSCN) 104. , Drive scanner (DSCN) 105, data lines DTL101 to DTL10n in which data signals corresponding to luminance information selected by horizontal selector 103b are sequentially supplied as current signals, and scanning lines WSL101 to WSL10m selectively driven by write scanner 104 , And drive lines DSL101 to DSL10m that are selectively driven by the drive scanner 105.

In the pixel array unit 102b, the pixel circuits 101b are arranged in an m × n matrix, but FIG. 15 shows an example in which the pixel circuits 101b are arranged in a 2 × 3 matrix for simplification of the drawing. In FIG. 1, one pixel circuit 101b is shown.
In FIG. 16, for simplification of the drawing, the horizontal selector 103 b includes a current sample hold circuit and a horizontal switch HSW in the first to n-th columns.

As shown in FIG. 16, the pixel circuit 101b according to this embodiment includes a p-channel TFT 311, TFT 312, an n-channel TFT 313, a TFT 314, a capacitor C311, a light-emitting element 315 including an organic EL (OLED: electro-optical element), a first It has a node ND311 and a second node ND312.
In FIG. 16, DTL 101 indicates a data line to which a current signal is input, WSL 101 indicates a scanning line, and DSL 101 indicates a drive line.

In the pixel circuit 101b, a TFT 311 and a light emitting element 315 are connected in series between the power supply potential VCC and the ground potential GND.
Specifically, the source of the TFT 311 as a drive transistor is connected to the supply line of the power supply voltage VCC, the drain is connected to the anode of the light emitting element 315, and the cathode of the light emitting element 315 is connected to the ground potential GND.
The gate of the TFT 311 is connected to the first node ND311.
The source and drain of the TFT 313 are connected to the first node ND311 and the second node ND312 and the gate of the TFT 113 is connected to the drive line DSL101.
The first electrode of the capacitor C311 is connected to the first node ND311 and the second electrode is connected to the power supply potential VCC.
The source / drain of the TFT 314 is connected to the data line DTL101 and the third node ND313, and the gate of the TFT 314 is connected to the scanning line WSL101.
The gate of the TFT 312 is connected to the second node ND312, the drain is connected to the third node ND313, the gate and the source (second node ND312 and third node ND313) are connected, and the source is the power supply potential VCC. It is connected to the.

  As shown in FIG. 16, the horizontal selector 103 is wired for each column in the matrix arrangement of the pixel circuit 101b, and corresponds to the data lines DTL101, DTL102,..., DTL10n to which data signals corresponding to the luminance information are supplied. Current sample and hold circuits 1031-1, 1031-2,..., 1031-n and horizontal switches (HSW) 1032-1, 1032-2,. ing.

  As shown in FIG. 16, the current sample and hold circuit 1031-1 includes n-channel TFTs 121-1 to 124-1, capacitors C121-1 and C122-1, and nodes ND121-1 to ND123-1.

In the current sample and hold circuit 1031-1, the source of the TFT 121-1 is connected to the ground potential GND, the drain is connected to the node ND121-1, and the gate is connected to the node ND122-1. The source and drain of the TFT 122-1 are connected to the node ND 121-1 and the node ND 123-1, respectively. The gate of the TFT 122-1 is connected to the sample hold line SHL 121-1.
The source and drain of the TFT 123-1 are connected to the node ND123-1 and the node 121-1, respectively. The gate of the TFT 123-1 is connected to the sample hold line SHL122-1.

A first electrode of the capacitor C121-1 is connected to the node ND122-1, and a second electrode is connected to the ground potential GND. A first electrode of the capacitor C122-1 is connected to the node ND123-1, and a second electrode is connected to the fixed potential Vf.
The source and drain of the TFT 124-1 are connected to the node ND 121-1 and the first supply line ISL for the video input signal current Iin. The gate of the TFT 124-1 is connected to the sample hold line SHL123-1.
Further, the node ND121-1 is connected to the horizontal switch HSW1032-1. The switching signal SHSW is input to the switching signal line L at the gate of the horizontal switch HSW1032-1.

  The configurations and connection forms of the other current sample and hold circuits 1031-2 to 1031-n are substantially the same as those of the current sample and hold circuit 1031-1 described above, and thus the details thereof are omitted here.

Next, the operation of the pixel circuit 101b having the above configuration will be briefly described.
In the pixel circuit 101b, when the input signal (current signal) SI is written through the data line DTL by the current sample and hold circuit 1031, the drive line DSL101 is set to the high level, the TFT 313 is turned on, the scan line WSL101 is set to the high level, and the TFT 314 is set. Hold in the conductive state.
Thereby, the gate and drain of the TFT 311 are electrically connected by the TFT 313 in a conductive state, and the TFT 311 is driven in a saturated state.
Therefore, the gate voltage corresponding to the input current is written based on the above formula 1, and held in the capacitor C311 which is a pixel capacitance.
Thereafter, the TF 314 is held in a non-conductive state, and the TFT 313 is held in a conductive state.
Thereby, the light emitting element 315 emits light with a luminance corresponding to the current value according to the input signal current.

  Next, the operation of the horizontal selector configured as described above will be described with reference to FIGS. 17A to 17K, FIGS.

  Note that SHSW in FIG. 17A indicates a switching signal of the horizontal switch HSW. 18B shows the gate potential V124-1 of the TFT 124-1 in the first column, FIG. 17C shows the gate potential V122-1 of the TFT 122-1 in the first column, and FIG. The gate potential V123-1 of the TFT 123-1 in the first column, FIG. 17E shows the gate potential V124-n of the TFT 124-n in the nth column, and FIG. 17F shows the TFT 122 in the nth column. The gate potential V122-n of −n, FIG. 17G shows the gate potential V123-n of the TFT 123-n in the nth column, and FIG. 17H shows the potential VC121 of the capacitor C121-1 in the first column. 17 (I) shows the potential VND122-1 of the node ND122-1 in the first column, FIG. 17 (J) shows the potential VC121-n of the capacitor C121-n in the nth column, (K) is the power of the node ND122-n in the nth column. VND122-n to indicate respectively.

First, as shown in FIG. 17A, the switching signal SHSW is set to a low level and the all horizontal switches HSW are turned off, and as shown in FIG. 18, the TFTs 122-1, TFT 123-3 of the current sample hold circuit 1031-1 are displayed. The sample hold lines SHL 121-1 and 122-1 connected to 1 are set to the high level, that is, the gate voltages of the TFTs 1221-1 and 123-1 are set to the high level as shown in FIGS. 17 (C) and 17 (D). The TFTs 122-1 and 123-1 are turned on (turned on), and the TFT 121-1 is operated in the saturation region. At this time, the potentials of the node ND121-1 and the node ND123-1 are equal.
Thereafter, the sample hold line SHL 123-1 to which the TFT 124-1 is connected is set to a high level, that is, the gate voltage of the TFT 124-1 is set to a high level as shown in FIG. Turn on). At that time, the gate voltage of the TFT 121-1 is determined based on the above formula 1, and is held at C121-1, C122-1, as shown in FIG.
At this time, the node ND121-1 and the node ND123-1 are at the same potential.

After the predetermined voltage is written to the capacitors C121-1, C122-1, the sample hold lines SHL 121-1, 122-1 are set to a low level, that is, as shown in FIGS. 19, 17C, and 17D. The gate voltages V122-1, V123-1 of the TFT 122-1 and TFT 123-1 are set to a low level, the TFT 122-1 and TFT 123-1 are turned off, and a node ND121-1, a node as shown in FIG. The potential Vgs of the ND 122-1 and the node ND 123-1 is determined.
Thereafter, when the sample hold line SHL 123-1 is set to a low level, that is, the gate voltage V124-1 of the TFT 124-1 is set to a low level as shown in FIG. As shown in (I), the potential VND121-1 of the node ND121-1 decreases to the GND level.
At this time, the source-drain voltage of the TFT 122-1 is 0, but the source-drain voltage of the TFT 123-1 is Vgs. As a result, the potential of the ND 121-1 changes with time due to the leakage current due to the source / drain voltage of the TFT 123-1, but the voltage between the source and drain of the TFT 122-1 was 0. Even if the potential changes due to the leakage current of the TFT 123-1, the source-drain voltage of the TFT 122-1 is small and the leakage current is also small.
That is, the voltage VC121-1 of the capacitor C121-1 decreases by ΔV from the peak as shown in FIG.

In parallel with this, the sample and hold lines SHL121-n and 122-n to which the TFTs 122-n and 123-n of the current sample and hold circuit 1031-n are connected are set to the high level, that is, FIGS. G), the gate voltages V122-n and V123-n of the TFT 122-n and TFT 123-n are set to a high level, the TFT 122-n and TFT 123-n are turned on (turned on), and the TFT 121-n is saturated. Operate in the area. At this time, the potentials of the nodes ND121-n and ND123-n are equipotential.
Thereafter, the sample hold line SHL123-n to which the TFT 124-n is connected is set to the high level, that is, the gate voltage V124-n of the TFT 124-n is set to the high level as shown in FIG. (Turn on). At that time, the gate voltage of the TFT 121-n is determined based on the above formula 1, and is held in C121-n and C122-n as shown in FIG.
At this time, the node ND121-n and the node ND123-1 are at the same potential.

Similarly, after a predetermined voltage is written in the capacitors C121-n and C122-n, the sample hold lines SHL121-n and 122-n are set to a low level, that is, as shown in FIGS. 17 (F) and 17 (G). −n and the gate voltages V122-n and V123-n of the TFT 123-n are set to a low level, the TFT 122-n and the TFT 123-n are turned off, and the potentials of the node ND121-n, the node ND122-n, and the node ND123-n Determine Vgs. Thereafter, when the sample hold line SHL123-n is set to a low level, that is, the gate voltage V124-n of the TFT 124-n is set to a low level as shown in FIG. As shown in (K), the potential of the node ND121-n decreases to the GND level.
At this time, the source-drain voltage of the TFT 122-n is 0, but the source-drain voltage of the TFT 123-n is Vgs. As a result, the potential of the ND 121-n changes with time due to the leakage current due to the source / drain voltage of the TFT 123-n. However, since the voltage between the source and drain of the TFT 122-n is 0, the potential of the node 121-n Even if the potential changes due to the leakage current of the TFT 123-n, the voltage between the source and the drain of the TFT 122-n is small and the leakage current is also small.
That is, the voltage VC121-n of the capacitor C121-n is decreased by ΔV from the peak as shown in FIG.

As described above, the video signal Iin is sampled and held dot-sequentially in all the current sample and hold circuits 1031-1 to 1031-1.
Thereafter, the horizontal switches HSW are turned on simultaneously in all stages, the TFTs 121-1 to 121-n function as constant current sources, and the sampled and held current values are output to the data lines DTL101 to DTL10n.

As described above, since the voltage between the source and the drain of the TFT 122-n is 0 in the current sample and hold circuit 1031 according to this embodiment as compared with the current sample and hold circuit shown in FIG. Even if the potential of n changes due to the leakage current of the TFT 123-n, the source-drain voltage of the TFT 122-n is small and the leakage current is also small.
Thus, the variation in the output current value can be suppressed, and a uniform constant current source can be formed. This effect of suppressing variation is remarkable in a TFT having a large leakage current. Therefore, it is possible to obtain an image quality with high uniformity in a current driven organic EL display using TFTs.
That is, it is possible to obtain a uniform current source without variation in the current value of the output stage, and to display a high-quality image that does not cause luminance unevenness toward the scan end portion.

  In this embodiment, the capacitor C112 is connected to the fixed potential Vf, but it is preferable that the fixed potential is the power supply voltage VCC or the ground potential GND in view of the layout and the like.

  FIG. 20 is a block diagram showing a current sample and hold circuit of an organic EL display device adopting a current driving method according to the fourth embodiment of the present invention.

As shown in FIG. 20, the current sample and hold circuit 1031a-1 according to the present embodiment includes n-channel TFTs 121-1 to 125-1, a capacitor C121-1, and nodes ND121-1 to ND123-1. .
Only differences between the current sample and hold circuit 1031a according to the present embodiment and the current sample and hold circuit 1031-1 according to the first embodiment will be described.
The difference between the current sample and hold circuit 1031 a-1 and the current sample and hold circuit 1031-1 according to the third embodiment is that a TFT 125 − is used instead of the capacitor C 122-1 between the fixed potential Vf and the node ND 123-1. 1 is connected to the sample-and-hold line SHL 124-1.
Since other components are substantially the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted.
The configurations and connection forms of the other current sample and hold circuits 1031a-2 to 1031a-2n are substantially the same as those of the above-described current sample and hold circuit 1031a-1, and therefore the details thereof are omitted here.

Next, the operation of the above configuration, particularly the operation of the horizontal selector, will be mainly described with reference to FIGS.
FIG. 21 is a timing chart for explaining the operation of the horizontal selector shown in FIG.
Note that SHSW in FIG. 21A indicates a switching signal of the horizontal switch HSW. 21B shows the gate potential V124-1 of the TFT 124-1 in the first column, FIG. 21C shows the gate potential V123-1 of the TFT 123-1 in the first column, and FIG. 21E shows the gate potential V122-1 of the first row TFT 122-1, FIG. 21E shows the gate potential V125-1 of the first row TFT 125-1, and FIG. 21F shows the first row capacitor. FIG. 21G shows the potential VC122-1 of C121-1, and FIG. 21G shows the potential VND121-1 of the node ND121-1 in the first column.

First, as shown in FIG. 21A, with the switching signal SHSW set to a low level and the all horizontal switch HSW turned off, the TFT 125-1 of the current sample hold circuit 1031-1 is connected as shown in FIG. The sample hold line SHL124-1 thus set to a low level, that is, as shown in FIG. 21E, the gate voltage V125-1 of the TFT 125-1 is set to a low level, and the TFT 125-1 is turned off (turned off). The sample hold lines SHL 121-1 and 122-1 to which the TFTs 122-1 and 123-1 are connected are set to a high level, that is, as shown in FIGS. 21D and 21C, the gates of the TFTs 122-1 and 123-1. The voltages V122-1, V123-1 are set to a high level, and the TFTs 122-1, TFT 123-1 are turned on. (Turns on), is operated in the saturation time region TFT121-1. At this time, the potentials of the node ND121-1 and the node ND123-1 are equal.
Thereafter, the sample hold line SHL 123-1 to which the TFT 124-1 is connected is set to a high level, that is, the gate voltage V124-1 of the TFT 124-1 is set to a high level as shown in FIG. (Turn on). At that time, the gate voltage of the TFT 121-1 is determined based on the above formula 1, and is held in C121-1 as shown in FIG.

After the predetermined voltage is written in the capacitor C121-1, as shown in FIG. 23, the sample hold lines SHL 121-1 and 122-1 are set to a low level, that is, as shown in FIGS. The gate voltages V122-1, V123-1 of the TFT 122-1, TFT 123-1 are set to a low level, the TFT 122-1, TFT 123-1 are turned off, and the node ND121-1, the node ND122-1, the node ND123-1 Is determined. Thereafter, the sample hold line SHL124-1 is set to a high level, that is, the gate voltage of the TFT 125-1 is set to a high level as shown in FIG. 21E, and the TFT 125-1 is turned on (turned on). The potential of the node ND123-1 is set to the fixed potential Vf. When the sample hold line SHL 123-1 is set to a low level, that is, as shown in FIG. 21B, the gate voltage V124-1 of the TFT 124-1 is set to a low level and the TFT 124-1 is turned off. ), The potential of the node ND121-1 decreases to the GND level.
At this time, the source-drain voltage of the TFT 122-1 is 0, but the source-drain voltage of the TFT 123-1 is Vgs-Vf. As a result, the potential of the ND 121-1 changes with time due to the leakage current due to the source / drain voltage of the TFT 123-1, but the voltage between the source and drain of the TFT 122-1 was 0. Even if the potential changes due to the leakage current of the TFT 123-1, the source-drain voltage of the TFT 122-1 is small and the leakage current is also small.
In addition, by appropriately setting the fixed potential Vf, the potential difference between the source and drain of the TFT 122-1 can be reduced. That is, as shown in FIG. 21F, the potential of the capacitor C121-1 is decreased by ΔV from the peak.
Further, the operations of the other current sample and hold circuits 103a-2 to 103-n are the same, and thus description thereof is omitted.

  As described above, the leakage current of the capacitor C121-1 can be reduced by setting the fixed potential Vf. Further, in the dot sequential current sampling, the difference in gate potential decrease due to the leakage current between the first sampled and the last sampled can be reduced, and as shown in FIG. Therefore, it is possible to obtain a high-quality image with no uneven brightness.

1 is a block diagram illustrating a configuration example of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a specific configuration of a pixel circuit according to the present embodiment in the organic EL display device illustrated in FIG. 1. FIG. 3 is a timing chart of the pixel circuit shown in FIG. FIG. 3 is an equivalent circuit diagram of the pixel circuit shown in FIG. 2. FIG. 3 is an equivalent circuit diagram of the pixel circuit shown in FIG. 2. It is a block diagram which shows the structural example of the organic electroluminescence display which concerns on 2nd Embodiment of this invention. FIG. 7 is a circuit diagram illustrating a specific configuration of a pixel circuit according to a second embodiment in the organic EL display device illustrated in FIG. 6. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 1. 8 is an equivalent circuit of the pixel circuit shown in FIG. 8 is an equivalent circuit of the pixel circuit shown in FIG. It is a circuit diagram which shows the specific structure of the pixel circuit which concerns on 3rd Embodiment in the organic electroluminescent display apparatus of this invention. 12 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 11. FIG. 12 is an equivalent circuit diagram of the pixel circuit shown in FIG. 11. FIG. 12 is an equivalent circuit diagram of the pixel circuit shown in FIG. 11. It is a block diagram which shows the structural example of the organic electroluminescence display which concerns on 4th Embodiment of this invention. FIG. 16 is a circuit diagram illustrating a specific configuration of a pixel circuit and a horizontal selector of the organic EL display device adopting the current driving method illustrated in FIG. 15. 17 is a timing chart for explaining the operation of the horizontal selector shown in FIG. 16. FIG. 17 is an equivalent circuit diagram of the horizontal selector shown in FIG. 16. FIG. 17 is an equivalent circuit diagram of the horizontal selector shown in FIG. 16. It is a block diagram which shows the current sample hold circuit of the organic electroluminescence display which employ | adopted the current drive system which concerns on 4th Embodiment of this invention. 21 is a timing chart for explaining the operation of the horizontal selector shown in FIG. 20. FIG. 21 is an equivalent circuit diagram of the horizontal selector shown in FIG. 20. FIG. 21 is an equivalent circuit diagram of the horizontal selector shown in FIG. 20. It is a figure for demonstrating the advantage which concerns on this invention. It is a block diagram which shows the structure of an organic electroluminescence display. FIG. 21 is a circuit diagram illustrating a configuration example of a pixel circuit 2a in FIG. 20. It is a circuit diagram which shows one structural example of the pixel circuit into which a current signal is input. FIG. 28 is a circuit diagram illustrating a configuration of a main part of a horizontal selector that inputs a current signal to the pixel circuit illustrated in FIG. 27. It is a figure for demonstrating operation | movement of the horizontal selector shown in FIG. FIG. 29 is an equivalent circuit diagram of the horizontal selector shown in FIG. 28. It is a circuit diagram which shows one specific example of a pixel circuit. FIG. 32 is an equivalent circuit diagram of the pixel circuit shown in FIG. 31. FIG. 32 is an equivalent circuit diagram of the pixel circuit shown in FIG. 31. It is a figure for demonstrating the subject of the horizontal selector shown in FIG. FIG. 31 is a diagram for describing a problem of the circuit illustrated in FIG. 30.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101 ... Pixel circuit (PXLC), 102 ... Pixel array part, 103 ... Horizontal selector (HSEL), 104 ... Write scanner (WSCN), 105 ... Drive scanner (DSCN), 106 ... Pre-scanner, 111- 113 ... TFT, 114, 217 ... Light emitting element (OLED), 121 (-1 to n) to 125 (-1 to n) ... TFT, 1031 (-1 to n) ... Current sample hold circuit, DSL101 to DSL10n ... Drive Line, HSW ... Horizontal switch, ISL ... Supply line, ND111 to ND112, ND121 to ND123, ND201 to ND204 ... Node, PSL101 ... Pre-scan line, SHL121 (-1 to n) to SHL124 (-1 to n) ... Sample hold Line, WSL101 to WSL10n... Scanning line, PPSL101. Li scan line.

Claims (12)

A display device in which a video signal is supplied as a signal current,
A plurality of pixel circuits arranged in a matrix;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a signal current according to luminance information;
A plurality of sample and hold circuits are provided corresponding to the data lines and sample and hold the input video signal current. Each sample and hold circuit is sequentially operated in the column direction so that the video signals are sent to all the sample and hold circuits. A horizontal selector that performs sample-and-hold in a dot-sequential manner and outputs the current value sampled and held by the plurality of sample-and-hold circuits to a corresponding data line;
The horizontal selector includes a signal current supply line,
Each of the sample and hold circuits is
A field effect transistor having a source connected to a predetermined potential;
A first switch connected between the drain of the field effect transistor and the signal current supply line;
A first capacitor connected between the gate of the field effect transistor and a predetermined potential;
A second switch and a third switch connected in series between the drain and gate of the field effect transistor;
A display device comprising: a second capacitor connected between the second and third switches and a fixed potential. The sample and hold circuit holds charges corresponding to the signal current from the supply line to the first and second capacitors through the second and third switches at the time of sample and hold. The display device according to claim 1, wherein the third switch is turned off. The display device according to claim 1, wherein the fixed potential is a reference potential or a power supply potential. A display device in which a video signal is supplied as a signal current,
A plurality of pixel circuits arranged in a matrix;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a signal current according to luminance information;
A plurality of sample and hold circuits are provided corresponding to the data lines and sample and hold the input video signal current. Each sample and hold circuit is sequentially operated in the column direction so that the video signals are sent to all the sample and hold circuits. A horizontal selector that performs sample-and-hold in a dot-sequential manner and outputs the current value sampled and held by the plurality of sample-and-hold circuits to a corresponding data line;
The horizontal selector includes a signal current supply line,
Each of the sample and hold circuits is
A field effect transistor having a source connected to a predetermined potential;
A first switch connected between the drain of the field effect transistor and the signal current supply line;
A capacitor connected between the gate of the field effect transistor and a predetermined potential;
A second switch and a third switch connected in series between the drain and gate of the field effect transistor;
A display device comprising: a fourth switch connected between the second and third switches and a fixed potential. The sample and hold circuit holds charges corresponding to the signal current from the supply line to the first and second capacitors through the second and third switches at the time of sample and hold. The display device according to claim 4, wherein the fourth switch is set to a conductive state after the third switch is set to a non-conductive state. The display device according to claim 4, wherein the fixed potential is a reference potential or a power supply potential. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a data signal corresponding to luminance information is supplied;
A power supply voltage source;
A reference potential;
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls the current flowing through the current supply line in accordance with the potential of the control terminal;
A first capacitor connected between the power supply voltage source and the control terminal;
First and second switches connected in series between the data line and the control terminal;
A second capacitor connected between the first and second switches and a fixed potential;
A pixel circuit in which a current supply line of the drive transistor, the first node, and the electro-optic element are connected in series between the power supply voltage source and a reference potential. When driving the electro-optic element, the first and second capacitors are charged through the first and second switches and the electric charge corresponding to the data signal from the data line is held in the first and second capacitors. The pixel circuit according to claim 7, wherein the switch of 2 is held in a non-conductive state, and a current corresponding to the data signal is supplied to the electro-optical element. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a data signal corresponding to luminance information is supplied;
First and second control lines;
First, second and third nodes;
A power supply voltage source;
A reference potential;
A fixed potential;
A current supply line is formed between the first terminal and the second terminal connected to the first node, and the current flowing through the current supply line is controlled according to the potential of the control terminal connected to the second node. A driving transistor to
A first switch connected to the first node;
A second and a third switch connected in series between the first node and the second node;
A first capacitor connected between the second and third switches and the fixed potential;
A fourth switch connected between the data line and the third node and controlled in conduction by the first control line;
A second capacitor connected between the second node and the third node;
A third capacitor connected between the third node and the power supply voltage source;
A fifth switch connected between the third node and a power supply voltage source and controlled in conduction by the second control line;
A pixel circuit in which a current supply line of the drive transistor, the first node, and the electro-optic element are connected in series between the power supply voltage source and a reference potential. When driving the electro-optic element, the second, third, and fifth switches are turned on for a predetermined time to electrically connect the first node and the second node;
After a predetermined time, the second, third, and fifth switches are held in a non-conductive state, the first and fourth switches are turned on, and the data line propagated through the data line is the first 10. The pixel circuit according to claim 9, wherein the fourth switch is held in a non-conductive state after being written to the node 3, and supplies a current corresponding to the data signal to the electro-optic element. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a data signal corresponding to luminance information is supplied;
First and second control lines;
First, second and third nodes;
A power supply voltage source;
A reference potential;
A fixed potential;
A current supply line is formed between the first terminal and the second terminal connected to the first node, and the current flowing through the current supply line is controlled according to the potential of the control terminal connected to the second node. A driving transistor to
A first switch connected to the first node;
A second and a third switch connected in series between the first node and the second node;
A fourth switch connected between the second and third switches and the fixed potential;
A fifth switch connected between the data line and the third node and controlled in conduction by the first control line;
A first capacitor connected between the second node and the third node;
A second capacitor connected between the third node and the power supply voltage source;
A sixth switch connected between the third node and a power supply voltage source and controlled to be conductive by the second control line;
A pixel circuit in which a current supply line of the drive transistor, the first node, and the electro-optic element are connected in series between the power supply voltage source and a reference potential. When driving the electro-optic element, the second, third, fourth, and sixth switches are turned on for a predetermined time to electrically connect the first node and the second node;
After a predetermined time, the second, third, and sixth switches are held in a non-conductive state, the first and fifth switches are turned on, and the data line propagated through the data line is the first 12. The pixel circuit according to claim 11, wherein after the data is written to the third node, the fourth and fifth switches are held in a non-conductive state, and a current corresponding to the data signal is supplied to the electro-optical element.

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