JP2008175945A - Pixel circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of high picture quality while suppressing variation of the luminance. <P>SOLUTION: The device includes n-channel TFT 112a and TFT 112b in the same conductivity type, both of which are connected in series, with the respective gates connected to the same scanning line WSL and with a first terminal of the TFT 112a connected to a signal line SGL, wherein the manufacturing process is controlled to make the threshold voltage of the n-channel TFT 112a different from that of the n-channel TFT 112. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pixel circuit including a light emitting element such as an organic EL (Electroluminescence) or a liquid crystal, and an active matrix display device.

In an image display device such as a liquid crystal display (LCD, hereinafter referred to as LCD), a large number of pixels are arranged in a matrix, and an image is displayed by controlling the light intensity for each pixel in accordance with image information to be displayed.
Similarly, the organic EL display is a self-luminous display having a light-emitting element in each pixel circuit, and has advantages such as higher image visibility, no need for a backlight, and faster response speed than an LCD.
Further, the luminance of each light emitting element is controlled by the value of the current flowing therethrough to obtain a color gradation. That is, the property is greatly different from LCD in that the light emitting element is a current control type.

  As with the LCD, the organic EL display has a simple matrix system and an active matrix system as driving systems. Although the former is simple in structure, it is not suitable for increasing the size and resolution of the display. Therefore, the former is generally provided with an active element provided inside each pixel circuit, generally a thin film transistor (TFT). Active matrix systems are under active development.

  Next, the operation principle of the active matrix display device will be described.

  FIG. 1 is a block diagram illustrating a configuration of an active matrix display device.

In the display device 1, the pixel circuit (PXLC) 2a is selected by the pixel array unit 2, the horizontal selector (HSEL) 3, the light scanner (WSCN) 4, and the horizontal selector 3 arranged in a matrix of m × n. Signal lines SGL1 to SGLn to which the corresponding data signals are supplied, and scanning lines WSL1 to WSLm selectively driven by the write scanner 4 are provided.
Note that the horizontal selector 3 and the light scanner 4 may be formed on the periphery of the pixel when formed on polycrystalline silicon or with MOSIC or the like.

FIG. 2 is a circuit diagram showing a configuration example of the pixel circuit 2a shown in FIG. (For example, refer to Patent Documents 1 and 2).
The pixel circuit in FIG. 2 has the simplest circuit configuration among many proposed circuits, and is a so-called two-transistor driving circuit.

2 includes a p-channel thin film field effect transistor (hereinafter referred to as TFT) 11 and TFT 12, a capacitor C11, and an organic EL light emitting element (OLED) 13 which is a light emitting element. In FIG. 2, SGL represents a signal line, and WSL represents a scanning line.
Since organic EL light-emitting elements are often rectifying, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 2 and other figures, diode symbols are used as light-emitting elements. It does not necessarily require rectification.
In FIG. 2, the source of the TFT 11 is connected to the power supply voltage VCC, and the cathode (cathode) of the light emitting element 13 is connected to the ground potential GND. The operation of the pixel circuit 2a in FIG. 2 is as follows.

Step ST1:
When the scanning line WSL is in a selected state (here, at a low level) and the writing potential Vdata is applied to the signal line SGL, the TFT 12 becomes conductive and the capacitor C11 is charged or discharged, and the gate potential of the TFT 11 becomes Vdata.

Step ST2:
When the scanning line WSL is in a non-selected state (here, high level), the signal line SGL and the TFT 11 are electrically disconnected, but the gate potential of the TFT 11 is stably held by the capacitor C11.

Step ST3:
The current flowing through the TFT 11 and the light emitting element 13 has a value corresponding to the gate-source voltage Vgs of the TFT 11, and the light emitting element 13 continues to emit light with a luminance corresponding to the current value.
The operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 is hereinafter referred to as “writing”.
As described above, in the pixel circuit 2a of FIG. 2, once Vdata is written, the light emitting element 13 continues to emit light with a constant luminance until it is rewritten next time.

As described above, in the pixel circuit 2a, the value of the current flowing through the EL light emitting element 13 is controlled by changing the gate application voltage of the TFT 11 which is a drive transistor.
At this time, the source of the p-channel drive transistor is connected to the power supply voltage VCC, and the TFT 11 always operates in the saturation region. Therefore, the constant current source has a value represented by the following formula 1.

(Equation 1)
Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² (1)

  Here, μ is the carrier mobility, Cox is the gate capacity per unit area, W is the gate width, L is the gate length, Vgs is the gate-source voltage of the TFT 11, Vth indicates the threshold value of the TFT 11.

  In the simple matrix type image display device, each light emitting element emits light only at the selected moment, whereas in the active matrix, as described above, the light emitting element continues to emit light even after the writing is completed. In comparison, the peak luminance and peak current of the light emitting element can be lowered, and this is particularly advantageous in a large-sized and high-definition display.

  FIG. 3 is a diagram showing a change with time of current-voltage (IV) characteristics of the organic EL light emitting device. In FIG. 3, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time.

In general, the IV characteristics of an organic EL light emitting element deteriorate as time passes, as shown in FIG.
However, since the two-transistor drive in FIG. 2 is driven at a constant current, the constant current continues to flow through the organic EL light emitting element as described above, and even if the IV characteristic of the organic EL light emitting element deteriorates, the light emission luminance remains with time. There is no deterioration.

  Next, a basic pixel circuit in which transistors are replaced with n-channel TFTs will be described.

  FIG. 4 is a circuit diagram showing a pixel circuit in which the p-channel TFT in the circuit of FIG. 2 is replaced with an n-channel TFT.

  The pixel circuit 2b in FIG. 4 includes n-channel TFTs 21 and 22, a capacitor C21, and an organic EL light emitting element (OLED) 23 that is a light emitting element. In FIG. 4, SGL represents a data line, and WSL represents a scanning line.

  In the pixel circuit 2b, the drain side of the TFT 21 as a drive transistor is connected to the power supply voltage VCC, and the source is connected to the anode of the EL light emitting element 23, thereby forming a source follower circuit.

  FIG. 5 is a diagram showing operating points of the TFT 21 as the drive transistor and the EL light emitting element 23 in the initial state. In FIG. 5, the horizontal axis indicates the drain-source voltage Vds of the TFT 21, and the vertical axis indicates the drain-source current Ids.

As shown in FIG. 5, the source voltage is determined by the operating point of the TFT 21 as a drive transistor and the EL light emitting element 23, and the voltage has a different value depending on the gate voltage.
Since the TFT 21 is driven in a saturation region, a current Ids having a current value of the equation shown in the above equation 1 is supplied with respect to Vgs with respect to the source voltage at the operating point.

USP 5,684,365 JP-A-8-234683

  In the pixel circuit as shown in FIG. 2 or FIG. 4, when the TFT 12 or the TFT 22 that controls data writing leaks off, the pixel circuit cannot normally write luminance information, and the organic EL light emitting element 13 or the organic EL light emitting element. Thus, the luminance of the 23 will vary. Therefore, high image quality cannot be expected as a display device.

  An object of the present invention is to provide a pixel circuit and a high-quality display device in which variation in luminance is suppressed.

  A pixel circuit according to a first aspect of the present invention includes a signal line to which a data signal is supplied, at least two switching transistors of the same conductivity type that are connected in series, and a driving signal. A driving line for driving the transistor, a terminal of the switching transistor arranged at one end among the plurality of switching transistors is connected to the signal line, and a control terminal of the plurality of switching transistors is the scanning line And the plurality of switching transistors have different threshold voltages.

  A pixel circuit according to a second aspect of the present invention includes a signal line to which a data signal is supplied, at least two switching transistors of the same conductivity type connected in series, and a driving signal. A driving line for driving the transistor, a terminal of the switching transistor arranged at one end among the plurality of switching transistors is connected to the signal line, and a control terminal of the plurality of switching transistors is the scanning line And the plurality of switching transistors have different gate lengths.

  A pixel circuit according to a third aspect of the present invention includes a signal line to which a data signal is supplied, at least two switching transistors of the same conductivity type connected in series, and a driving signal. A driving line for driving the transistor, a terminal of the switching transistor arranged at one end among the plurality of switching transistors is connected to the signal line, and a control terminal of the plurality of switching transistors is the scanning line And the plurality of switching transistors have different gate areas.

  Preferably, the pixel circuit includes a first switching transistor and a second switching transistor, and the first and second switching transistors have the same conductivity type and are connected in series, and the first switching transistor is connected to the first switching transistor. The terminal of the switching transistor is connected to the signal line, the control terminals of the first and second switching transistors are connected in common to the drive line, and the absolute value of the threshold voltage of the first switching transistor is It is smaller than the absolute value of the threshold voltage of the two switching transistors.

  Preferably, the pixel circuit includes a first switching transistor and a second switching transistor, and the first and second switching transistors have the same conductivity type and are connected in series, and the first switching transistor is connected to the first switching transistor. The terminal of the switching transistor is connected to the signal line, the control terminals of the first and second switching transistors are connected in common to the drive line, and the gate length of the first switching transistor is the second switching transistor. Shorter than the gate length.

  Preferably, the pixel circuit includes a first switching transistor and a second switching transistor, and the first and second switching transistors have the same conductivity type and are connected in series, and the first switching transistor is connected to the first switching transistor. The terminal of the switching transistor is connected to the signal line, the control terminals of the first and second switching transistors are commonly connected to the drive line, and the gate area of the first switching transistor is the second switching transistor. Greater than gate area.

  A display device according to a fourth aspect of the present invention includes a pixel circuit including light emitting elements arranged in a matrix, and at least one scanner that outputs a drive signal to a control terminal of a switching transistor forming the pixel circuit. A selector that outputs a data signal to a first terminal of a switching transistor forming the pixel circuit, and the pixel circuit is connected in series with at least two or more signal lines to which the data signal is supplied. A switching transistor of the same conductivity type, and a drive line that is supplied with a drive signal and drives the plurality of switching transistors, and a terminal of the switching transistor arranged at one end of the plurality of switching transistors is The control terminals of the plurality of switching transistors connected to the signal line are connected to the scanning line. Commonly connected to said plurality of switching transistors, the threshold voltages are different.

  According to the present invention, there are at least two switching transistors of the same conductivity type, which are connected in series, their gates are respectively connected to the same scanning line, and the first terminal of the switching transistor at one end Adjusts the threshold voltage of the switching transistor connected to the signal line to be different.

  According to the present invention, it is possible to suppress variations in luminance and improve the image quality of the pixel circuit and the display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 6 is a block diagram showing a configuration example of an organic EL display device employing the pixel circuit according to the first embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating a specific configuration example of the pixel circuit according to the first embodiment.

  As shown in FIGS. 6 and 7, the display device 100 includes a pixel array unit 102 in which pixel circuits 101 are arranged in an m × n matrix, a horizontal selector (HSEL) 103, a light scanner (WSCN) 104, a power Drive scanner (PDSCN) 105, signal lines SGL101 to SGL10n to which a data signal Vsig selected by the horizontal selector 103 and an input signal SIN of an offset signal Vofs corresponding to luminance information are supplied, and a gate pulse (scanning pulse) GP by the write scanner 104 The power lines PSL101 to WSL10m as drive wirings selectively driven by the power supply scanner 105 and the power signal PSG selectively set to VCC (for example, power supply voltage) or VSS (for example, negative side voltage) are applied and driven. Driving arrangement Having a power drive line PSL101~PSL10m as.

In the pixel array unit 102, the pixel circuits 101 are arranged in a matrix of m × n. However, in FIG. 6, in order to simplify the drawing, a matrix of 2 (= m) × 3 (= n) is used. An example of arrangement is shown.
FIG. 7 also shows a specific configuration of one pixel circuit for simplification of the drawing.

As shown in FIG. 7, the pixel circuit 101 according to the present embodiment includes an n-channel TFT 111 as a driving transistor (hereinafter, n-channel TFT is referred to as an nTFT), an nTFT 112a as a first switching transistor, and a second switching transistor. It has an nTFT 112b, a capacitor C111, a light emitting element 113 made of an organic EL light emitting element (OLED: electro-optical element), a first node ND111, and a second node ND112. The gate group 112 is formed of an nTFT 112a and an nTFT 112b.
Note that the threshold voltage of the nTFT 112a is Vth1, the gate capacitance per unit area is Cox1, the gate width is W1, and the gate length is L1.
Further, the threshold voltage of the nTFT 112b is Vth2, the gate capacitance per unit area is Cox2, the gate width is W2, and the gate length is L2.
The capacitance of the capacitor C111 is Cs.

In the pixel circuit 101, an nTFT 111, a node ND111, and a light emitting element (OLED) 113 as drive transistors are provided between a power drive line (power supply line) PSL (101 to 10 m) and a predetermined reference potential Vcat (for example, ground potential). Connected in series.
Specifically, the cathode of the light emitting element 113 is connected to the reference potential Vcat, the anode is connected to the first node ND111, the source of the nTFT 111 is connected to the first node ND111, and the drain of the nTFT 111 is the power drive line PSL. It is connected to the. The gate of the nTFT 111 is connected to the second node ND112. The first electrode of the capacitor C111 is connected to the first node 111, and the second electrode of the capacitor C111 is connected to the second node ND112. In the nTFT 112a to nTFT 112b forming the gate group 112, the drain of the nTFT 112a and the source of the nTFT 112b are connected. A gate group 112 is provided between the signal line SGL and the second node ND212, the source of the nTFT 112a is connected to the signal line SGL, and the drain of the nTFT 112b is connected to the node ND112. The gates of the nTFT 112a to nTFT 112b are connected to the scanning line WSL.

8A to 8C are timing charts showing the basic operation of the pixel circuit of FIG.
8A shows a gate pulse (scanning pulse) GP applied to the scanning line WSL, FIG. 8B shows a power signal PSG applied to the power driving line PSL, and FIG. 8C shows a signal line SGL. The input signal SIN applied to each is shown.

In order to cause the light emitting element 113 of the pixel circuit 101 to emit light, a power signal VSS (for example, a negative voltage) is applied to the power drive line PSL as shown in FIGS. The offset signal Vofs is propagated to the line SGL and inputted to the second node ND112 through the gate group 112, and then the power signal VCC (corresponding to the power supply voltage) is applied to the power drive line PSL to correct the threshold value of the TFT 111.
Thereafter, the data signal Vsig corresponding to the luminance information is applied to the signal line SGL, and the signal is written to the second node ND112 through the gate group 112. At this time, writing is performed while a current is supplied to the TFT 111, and thus mobility correction is performed in parallel.
Then, the gate group 112 is turned off, and the light emitting element 113 emits light according to the luminance information.

  By the way, a structure having two switching transistors like the gate group 112 may be called a double gate structure. This is a redundant design in which even when one of the TFTs is off-leaked, the other TFT can suppress off-leakage.

Although the pixel circuit 101 has redundancy, the TFT has a large variation in the threshold voltage Vth, and the threshold voltage of the TFT 112a and the TFT 112b may be different. In this case, in the redundant design described above, when the voltage supplied from the scanning line is switched from the high level to the low level, the timing at which the TFTs 112a to 112b are turned off (non-conducting state) is different. As a result, noise is mixed in the signal and the luminance of the organic EL light emitting element 113 varies.
The reason why the luminance varies will be described with reference to FIG.

FIG. 9 is a diagram for explaining the relationship between the threshold voltages of the TFTs 112a to 112b and the timing at which the TFTs 112a to 112b are turned off.
Here, the vertical axis in FIG. 9 is an axis indicating the voltage of the scanning line WSL, and the horizontal axis in FIG. 9 is an axis indicating time.

Here, it is assumed that the signal line SGL illustrated in FIG. 7 has the signal line capacitance Cdata, and the relationship between the signal line capacitance Cdata and the capacitance Cs of the capacitor C111 is (Cdata >> Cs). .
For simplicity of explanation, it is assumed that the threshold voltage Vth2 is constant.

(Case 1)
If the threshold voltage difference between the threshold voltage Vth1 and the threshold voltage Vth2 is defined as ΔVth21a when the threshold voltage Vth1 is higher than the threshold voltage Vth2, the difference ΔVth21a can be described as follows.

(Equation 2)
Vth1−Vth2 = ΔVth21a> 0 (2)

Equation (2) represents a case where the TFT 112a is switched off before the TFT 112b.
The case 1 will be described with reference to FIG.

Thereafter, for simplicity of explanation, the voltage Vgate is applied to the scanning line WSL until time t1, the voltage Vgate decreases linearly from time t1 to time t4, and the voltage applied to the scanning line WSL at time t4 becomes 0. It shall be switched.
The off point P1 indicates the time and voltage when the TFT 12a is turned off, and the off point P2 indicates the time and voltage when the TFT 12b is turned off.

Until time t1, the voltage Vgate is applied to the scanning line WSL, the TFTs 112a to 112b are held on, the voltage Vdata is applied to the signal line SGL, and the data voltage is written to the capacitor C111. At this time t1, the voltage Vgate is applied to the TFTs 112a to 112b.
At time t2, the TFT 112a is turned off at the voltage Vdata + Vth1. For this reason, the charge remaining in the channel of the TFT 112b flows into the capacitor C111.
At this time, the charge Qa flowing into the capacitor C111 is expressed by the following equation.

(Equation 3)
Qa = Cox 2 · W 2 · L 2 · ΔVth21a / Cs (3)

  The voltage fluctuation amount ΔVa of the capacitor C111 due to the charge Qa is expressed by the following equation.

(Equation 4)
ΔVa = Qa / Cs = Cox2, W2, L2, ΔVth21a / Cs (4)

(Case 2)
The case where the threshold voltage Vth1 is higher than the threshold voltage Vth2 can be described as follows.

(Equation 5)
Vth1−Vth2 = ΔVth21a <0 (5)

Equation (5) represents a case where the TFT 112b is switched off before the TFT 112a.
Case 2 will be described with reference to FIG.

Until time t1, the voltage Vgate is applied to the scanning line WSL, the TFTs 112a to 112b are held on, the voltage Vdata is applied to the signal line SGL, and the data voltage is written to the capacitor C111. At this time t1, the voltage Vgate is applied to the TFTs 112a to 112b.
At time t2, for simplicity of explanation, it is assumed that the TFT 112b is turned off while the potentials at both ends of the TFT 112a are kept parallel. The charge remaining in the channel of the TFT 112a flows into the signal line SGL.
At this time, the charge Qb flowing into the light emitting element 113 is expressed by the following equation.

(Equation 6)
Qb = 0 (6)

  A voltage fluctuation amount ΔVb of the capacitor C111 due to the charge Qb is expressed by the following equation.

(Equation 7)
ΔVb = Qb / Cs = 0 (7)

  In the double gate structure, the threshold voltage Vth1 and the threshold voltage Vth2 vary, and at this time, the timing with which the TFTs 111a to 112b are turned off differs depending on the threshold voltage. In the process in which the voltage supplied to the scanning line WSL is switched from the voltage Vgate to the voltage 0, the amount of charge flowing into the capacitor C111 as shown in the equations (3) and (6) depending on which TFT is turned off first. There is a difference. Regarding the voltage fluctuation amount, the voltage fluctuation amount with respect to the capacitor C11 is different as shown in the equations (4) and (7).

  Therefore, in the first embodiment, the threshold voltage is adjusted in the manufacturing process so that the threshold voltage Vth1 is lower than the threshold voltage Vth2 (Vth1 <Vth2) in order to suppress the luminance variation due to the voltage fluctuation amount with respect to the capacitor C111.

Since the threshold voltage Vth1 of the nTFT 112a is set lower than the threshold voltage Vth2 of the nTFT 112b, in the process in which the voltage of the scanning line WSL is switched from the high level to the low level, the nTFT 112b is first switched off and the charge flows into the node ND112. There is no.
Accordingly, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a second embodiment according to the present invention will be described.

Second Embodiment
FIG. 10 is a circuit diagram illustrating a specific configuration example of the pixel circuit according to the second embodiment of the present invention.
Also in FIG. 10, a specific configuration of one pixel circuit is shown in the drawing for simplification.

As shown in FIG. 10, the pixel circuit 101a according to the present embodiment includes an nTFT 111 as a drive transistor, a p-channel TFT 112c as a first switching transistor, and a p-channel TFT 112d as a first switching transistor (hereinafter, p-channel TFTs are referred to as pTFTs). A capacitor C111, a light emitting element 113 made of an organic EL light emitting element, a first node ND111, and a second node ND112. Note that the gate group 112a includes a pTFT 112c and a pTFT 112d.
The threshold voltage of the pTFT 112c is Vth3, the gate capacitance per unit area is Cox3, the gate width is W3, and the gate length is L3.
Further, the threshold voltage of the p-channel TFT 22d is Vth4, the gate capacitance per unit area is Cox4, the gate width is W4, and the gate length is L4.
The capacitance of the capacitor C111 is Cs.

In the pTFT 112c and the pTFT 112d forming the gate group 112a, the drain of the pTFT 112c and the source of the pTFT 112d are connected.
The pixel circuit 101a is obtained by replacing the gate group 112 formed by the nTFT 112a and the nTFT 112b with a gate group 112a formed by the pTFT 112c and the pTFT 112d, and other configurations are the same as those of the pixel circuit 101 according to the first embodiment. It is a configuration.

11A to 11C are timing charts showing basic operations of the pixel circuit of FIG.
11A shows a gate pulse (scanning pulse) GP applied to the scanning line WSL, FIG. 11B shows a power signal PSG applied to the power driving line PSL, and FIG. 11C shows a signal line SGL. The input signal SIN applied to each is shown.

In order to cause the light emitting element 113 of the pixel circuit 101a to emit light, a power signal VSS (for example, a negative voltage) is applied to the power drive line PSL as shown in FIGS. The offset signal Vofs is propagated to the line SGL and input to the second node ND112 through the gate group 112a, and then the power signal VCC (corresponding to the power supply voltage) is applied to the power drive line PSL to correct the threshold value of the TFT 111. .
Thereafter, the data signal Vsig corresponding to the luminance information is applied to the signal line SGL, and the signal is written to the second node ND112 through the gate group 112a. At this time, writing is performed while a current is supplied to the TFT 111, and thus mobility correction is performed in parallel.
Then, the gate group 112a is turned off, and the light emitting element 113 emits light according to the luminance information.

  In the second embodiment, in the pixel circuit 101a described above, the threshold voltage is adjusted in the manufacturing process so that the threshold voltage Vth3 is higher than the threshold voltage Vth4 (Vth3> Vth4).

Since the threshold voltage Vth3 of the pTFT 112c is set lower than the threshold voltage Vth4 of the pTFT 112d, in the process in which the voltage of the scanning line WSL is switched from the low level to the high level, the pTFT 112d is first switched off and charge flows into the node ND112. There is no.
Accordingly, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a third embodiment according to the present invention will be described.

<Third Embodiment>
The third embodiment according to the present invention has the same configuration as the pixel circuit 101 according to the first embodiment (see FIG. 7), but the threshold voltage Vth1 is higher than the threshold voltage Vth2 in the manufacturing process (Vth1> Vth2). Adjust so that

In the third embodiment, since the threshold voltage Vth1 of the nTFT 112a is adjusted to be higher than the threshold voltage Vth2 of the nTFT 112b, the nTFT 112a is switched off first in the process of switching the voltage of the scanning line WSL from the high level to the low level. For this reason, the signal charge of the charge Qa shown by the equation (3) flows into the node ND112.
However, if the magnitude relationship between the threshold voltage Vth1 and the threshold voltage Vth2 is clear in advance, the amount of charge flowing into the node ND112 can be predicted and measures can be taken. Therefore, the threshold voltage Vth1 and the threshold voltage Vth2 can be arbitrarily set. It has less influence on the brightness than the scattered state.
Therefore, adjustment is made so that the relationship between the threshold voltage Vth1 and the threshold voltage Vth2 is (Vth1> Vth2).
By this adjustment, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a fourth embodiment according to the present invention will be described.

<Fourth embodiment>
The fourth embodiment according to the present invention has the same configuration as the pixel circuit 101a according to the second embodiment (see FIG. 10), but the threshold voltage Vth3 is lower than the threshold voltage Vth4 in the manufacturing process (Vth3 <Vth4). Adjust so that

In the fourth embodiment, since the threshold voltage Vth3 of the pTFT 112c is adjusted to be lower than the threshold voltage Vth4 of the pTFT 112d, the pTFT 112c is first switched off in the process of switching the voltage of the scanning line WSL from the low level to the high level. For this reason, the signal charge of the charge Qa shown by the equation (3) flows into the node ND112.
However, if the magnitude relationship between the threshold voltage Vth3 and the threshold voltage Vth4 is clear in advance, the amount of charge flowing into the node ND112 can be predicted and countermeasures can be taken. Therefore, the threshold voltage Vth3 and the threshold voltage Vth4 can be arbitrarily set. It has less influence on the brightness than the scattered state.
Therefore, adjustment is made so that the relationship between the threshold voltage Vth3 and the threshold voltage Vth4 is (Vth3 <Vth4).
By this adjustment, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a fifth embodiment according to the invention will be described.

<Fifth Embodiment>
The fifth embodiment according to the present invention has the same configuration as the pixel circuit 101 according to the first embodiment (see FIG. 7), but the gate length L1 is shorter than the gate length L2 in the manufacturing process (L1 <L2). Adjust so that
In the n-channel TFTs 112a to 112b, the threshold voltage increases as the gate length increases. Therefore, by adjusting the gate length L1 of the nTFT 112a to be shorter than the gate length L2 of the nTFT 112b, the threshold voltage Vth1 becomes lower than the threshold voltage Vth2 (Vth1 <Vth2).
As a result, in the process in which the voltage of the scanning line WSL is switched from the high level to the low level, the nTFT 112b is switched off first, and no charge flows into the node ND112. Accordingly, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a sixth embodiment according to the invention will be described.

<Sixth Embodiment>
The sixth embodiment according to the present invention has the same configuration as the pixel circuit 101a according to the second embodiment (see FIG. 10), but the gate length L3 is shorter than the gate length L4 (L3 <L4) in the manufacturing process. Adjust so that
In the p-channel TFTs 112c to 112d, the absolute value of the threshold voltage increases (threshold voltage Vth <0) as the gate length increases. Therefore, by adjusting the gate length L3 of the pTFT 112c to be shorter than the gate length L4 of the pTFT 112d, the threshold voltage Vth3 becomes higher than the threshold voltage Vth4 (Vth3> Vth4).
As a result, in the process in which the voltage of the scanning line WSL is switched from the low level to the high level, the pTFT 112d is switched off first, and no charge flows into the node ND112. Accordingly, variation in luminance of the light emitting element 113 can be suppressed.

  Next, a seventh embodiment according to the present invention will be described.

<Seventh embodiment>
The seventh embodiment according to the present invention has the same configuration as the pixel circuit 101 (see FIG. 7) according to the first embodiment, but the gate length L1 is longer than the gate length L2 in the manufacturing process (L1> L2). Adjust so that

The detailed reason is the same as the reason described in the third embodiment. If the magnitude relationship between the gate length L1 of the nTFT 112a and the gate length L2 of the nTFT 112b is clear, the amount of charge flowing into the node ND112 can be predicted and measures can be taken. Therefore, the gate length L1 and the gate length L2 can be taken. The influence on the luminance is less than that in the case where is arbitrarily scattered.
For this reason, if the relationship between the gate length L1 and the gate length L2 is adjusted so as to satisfy (L1> L2), the same effect as that of the fifth embodiment can be obtained, and variation in luminance of the light emitting element 113 can be suppressed.

  Next, an eighth embodiment according to the present invention will be described.

<Eighth Embodiment>
The eighth embodiment according to the present invention has the same configuration as the pixel circuit 101a according to the second embodiment (see FIG. 10), but the gate length L3 is longer than the gate length L4 in the manufacturing process (L3> L4). Adjust so that

The detailed reason is the same as the reason described in the fourth embodiment. If the magnitude relationship between the gate length L3 of the pTFT 112c and the gate length L4 of the pTFT 112d is clear, the amount of charge flowing into the node ND112 can be predicted and measures can be taken. Therefore, the gate length L3 and the gate length L4 can be taken. The influence on the luminance is less than that in the case where is arbitrarily scattered.
For this reason, if the relationship between the gate length L3 and the gate length L4 is adjusted so as to satisfy (L3> L4), the same effect as in the sixth embodiment can be obtained, and variation in luminance of the light emitting element 113 can be suppressed.

  Next, a ninth embodiment according to the present invention will be described.

<Ninth Embodiment>
The ninth embodiment according to the present invention is the same as the pixel circuit 101 according to the first embodiment (see FIG. 7), but the gate area S1 of the nTFT 112a is larger than the gate area S2 of the nTFT 112b in the manufacturing process (S1> S2). ) To adjust.

In the ninth embodiment, the gate area S1 (= W1 · L1) due to the gate width W1 and the gate length L1 of the nTFT 112a is larger than the gate area S2 (= W2 · L2) due to the gate width W2 and the gate length L2 of the nTFT 112b. It adjusts and the inflow by the absolute value of the signal charge from nTFT 112b to node ND112 is suppressed.
That is, since the gate area S2 is smaller than the gate area S1, the gate capacitance Cox2 of the nTFT 112b is smaller than the gate capacitance Cox1 of the nTFT 112a. As a result, the inflow due to the absolute value of the signal charge from the nTFT 112b to the node ND112 is reduced, and variation in luminance of the light emitting element 113 can be suppressed.

  However, in order to sufficiently write the data voltage to the node ND112, the on-resistances of the nTFT 112a and the nTFT 112b are set to be equal to or lower than a predetermined value.

  Next, a tenth embodiment according to the present invention will be described.

<Tenth embodiment>
The tenth embodiment according to the present invention has the same configuration as the pixel circuit 101a according to the second embodiment, but the gate area S3 of the pTFT 112c is larger than the gate area S4 of the pTFT 112d in the manufacturing process (S3> S4). Adjust to.

In the tenth embodiment, the gate area S3 (= W3 · L3) due to the gate width W3 and the gate length L3 of the pTFT 112c is larger than the gate area S4 (= W4 · L4) due to the gate width W4 and the gate length L4 of the pTFT 112d. It adjusts and the inflow by the absolute value of the signal charge from pTFT112d to node ND112 is suppressed.
That is, since the gate area S4 is smaller than the gate area S3, the gate capacitance Cox4 of the pTFT 112d is smaller than the gate capacitance Cox3 of the pTFT 112c. As a result, the inflow due to the absolute value of the signal charge from the pTFT 112d to the node ND112 is reduced, and variation in luminance of the light emitting element 113 can be suppressed.

  However, in order to sufficiently write the data voltage to the node ND112, the on-resistances of the pTFT 112c and the pTFT 112d are set to be a predetermined value or less.

  As described above, the pixel circuits according to the first to tenth embodiments employ two switching transistors called a double gate structure that emphasizes redundancy.

  The present invention may have a configuration other than the pixel circuit according to the above-described embodiment as long as the pixel circuit has a double gate structure. As an example, a configuration example of a pixel circuit formed of five switching transistors, one drive transistor, and one capacitor will be described as an eleventh embodiment.

<Eleventh embodiment>
FIG. 12 is a block diagram showing a configuration example of an organic EL display device employing a pixel circuit according to the second embodiment of the present invention.
FIG. 13 is a circuit diagram illustrating a specific configuration example of the pixel circuit according to the present embodiment.

  As shown in FIGS. 12 and 13, the display device 200 includes a pixel array unit 202 in which pixel circuits 201 are arranged in an m × n matrix, a horizontal selector (HSEL) 203, a write scanner (WSCN) 204, a drive A scanner (DSCN) 205, a first auto-zero circuit (AZRD1) 206, a second auto-zero circuit (AZRD2) 207, a signal line SGL selected by the horizontal selector 203 and supplied with a data signal corresponding to luminance information, a write scanner 204 The scanning line WSL as the second drive wiring selectively driven by the drive, the drive line DSL as the first drive wiring selectively driven by the drive scanner 205, and the fourth drive selectively driven by the first auto-zero circuit 206. First auto zero line AZL1 as wiring and second auto zero times The 207 has a second auto-zero line AZL2 as the third driving wiring to be selectively driven.

As shown in FIGS. 12 and 13, the pixel circuit 201 according to the present embodiment includes a pTFT 211, nTFT212 to nTFT213, an nTFT 214a as a first switching transistor, an nTFT 214b, an nTFT 215, a capacitor C211, and an organic EL light emitting as a second switching transistor. A light emitting element 216 including an element (OLED: electro-optical element), a first node ND211 and a second node ND212 are included.
The nTFT 214a forms a first switching transistor, the nTFT 214b forms a second switching transistor, the pTFT 211 forms a third switching transistor, the nTFT 213 forms a fourth switching transistor, and the nTFT 215 forms a fifth switching transistor. A transistor is formed. The gate group 214 is formed of an nTFT 214a and an nTFT 214b.
The supply line (power supply potential) of the power supply voltage Vcc corresponds to the first reference potential, and the ground potential GND corresponds to the second reference potential. VSS1 corresponds to the fourth reference potential, and VSS2 corresponds to the third reference potential.
The nTFT 214a is equivalent to the nTFT 112a according to the first embodiment, and has a threshold voltage of Vth1, a gate capacitance per unit area of Cox1, a gate width of W1, and a gate length of L1.
Further, the nTFT 214b is equivalent to the nTFT 112b according to the first embodiment, and the threshold voltage is Vth2, the gate capacitance per unit area is Cox2, the gate width is W2, and the gate length is L2.
Further, the capacitance of the capacitor C211 is assumed to be Cs.

In the pixel circuit 201, an nTFT 211, a TFT 212 as a drive transistor, a first transistor between a first reference potential (power supply voltage Vcc in this embodiment) and a second reference potential (ground potential GND in this embodiment). A node ND211 and a light emitting element (OLED) 216 are connected in series.
Specifically, the cathode of the light emitting element 216 is connected to the ground potential GND, the anode is connected to the first node ND211, the source of the nTFT 212 is connected to the first node ND211, and the drain of the pTFT 211 is connected to the drain of the TFT 211. The source of the TFT 211 is connected to the power supply voltage Vcc. The gate of the TFT 212 is connected to the second node ND212, and the gate of the TFT 211 is connected to the drive line DSL. The drain of the TFT 213 is connected to the first node 211 and the first electrode of the capacitor C 211, the source is connected to the fixed potential VSS 2, and the gate of the TFT 213 is connected to the second auto zero line AZL 2. The second electrode of the capacitor C211 is connected to the second node ND212. A gate group 214 is provided between the signal line SGL and the second node ND212, the source of the nTFT 214a is connected to the signal line SGL, and the drain of the nTFT 214b is connected to the node ND212. The gates of the nTFT 214a to nTFT 214b are connected to the scanning line WSL.
Further, the source and drain of the TFT 215 are connected between the second node ND212 and the predetermined potential Vss1, respectively. The gate of the TFT 215 is connected to the first auto zero line AZL1.

  As described above, in the pixel circuit 201 according to this embodiment, the capacitor C211 as the pixel capacitor is connected between the gate and the source of the TFT 212 as the driving transistor, and the source potential of the TFT 212 is connected to the TFT 213 as the switch transistor during the non-light emitting period. The threshold voltage Vth is corrected by connecting to a fixed potential through the TFT 212 and connecting between the gate and drain of the TFT 212.

  Next, the operation of the above configuration will be described with reference to FIGS. 14A to 14F, focusing on the operation of the pixel circuit.

  FIG. 14 is a timing chart showing the basic operation of the pixel circuit of FIG.

  14A shows a drive signal DS applied to the drive line DSL, and FIG. 14B shows a drive signal WS applied to the scanning line WSL (corresponding to the gate pulse GP in the first embodiment). 14C shows the drive signal AZ1 applied to the first auto zero line AZL1, FIG. 14D shows the drive signal AZ2 applied to the second auto zero line AZL2, and FIG. FIG. 14F shows the potential of the node ND212, and FIG. 14F shows the potential of the first node ND211.

The drive signal DS of the drive line DSL by the drive scanner 205 is held at a high level, the drive signal WS to the scanning line WSL by the write scanner 204 is held at a low level, and the drive signal AZ1 to the auto zero line AZL1 by the auto zero circuit 206 is held at a low level. The driving signal AZ2 to the auto zero line AZL2 by the auto zero circuit 207 is held at a high level.
As a result, the nTFT 213 is turned on. At this time, a current flows through the nTFT 213, and the source potential Vs of the nTFT 212 (the potential of the node ND211) drops to VSS2. Therefore, the voltage applied to the EL light emitting element 216 is also 0 V, and the EL light emitting element 216 does not emit light.
In this case, even if the nTFT 214a to nTFT 214b of the gate group 214 are turned on, the voltage held in the capacitor C211, that is, the gate voltage of the nTFT 212 does not change.

Next, in the non-emission period of the EL light emitting element 217, as shown in FIGS. 14C and 14D, the drive signal AZ2 to the auto zero line AZL2 is held at the high level, and the auto zero line AZL1 is applied. The drive signal AZ1 is set to a high level. As a result, the potential of the second node ND212 becomes VSS1.
Then, after the drive signal AZ2 to the auto zero line AZL2 is switched to the low level, the drive signal DS of the drive line DSL by the drive scanner 205 is switched to the low level only for a predetermined period.
Thereby, the nTFT 213 is turned off and the nTFT 215 and the nTFT 212 are turned on, whereby a current flows through the path of the nTFT 212 and the pTFT 211, and the potential of the first node rises.
Then, the drive signal DS of the drive line DSL by the drive scanner 205 is switched to the high level, and the drive signal AZ1 is switched to the low level.
As a result, the threshold value Vth of the drive transistor nTFT 212 is corrected, and the potential difference between the second node ND212 and the first node ND211 becomes Vth.
In this state, after the elapse of a predetermined period, the drive signal WS to the scanning line WSL by the write scanner 204 is held at a high level for a predetermined period, data is written to the node ND212 from the data line, The drive signal DS of the drive line DSL is switched to the high level, and the drive signal WS is eventually switched to the low level.
At this time, the nTFT 212 is turned on, and the nTFT 214a to nTFT 214b are turned off, so that the mobility is corrected.
In this case, since the nTFT 214a to nTFT 214b are off and the gate-source voltage of the nTFT 212 is constant, the nTFT 212 passes a constant current Ids to the EL light emitting element 216. As a result, the potential of the first node ND211 rises to the voltage Vx through which the current Ids flows through the EL light emitting element 216, and the EL light emitting element 216 emits light.

  In the eleventh embodiment, in the pixel circuit 201 described above, the threshold voltage is adjusted so that the threshold voltage Vth1 is lower than the threshold voltage Vth2 (Vth1 <Vth2) in the manufacturing process.

Since the threshold voltage Vth1 of the nTFT 214a is set lower than the threshold voltage Vth2 of the nTFT 214b, in the process in which the voltage of the scanning line WSL is switched from the high level to the low level, the nTFT 214b is first switched off and charge flows into the node ND212. There is no.
Therefore, variation in luminance of the EL light emitting element 216 is suppressed.

In the display device 200 according to the eleventh embodiment, the method of the third embodiment can also be adopted. In this case, variation in luminance can be suppressed by adjusting the threshold voltage so that the threshold voltage Vth1 is higher than the threshold voltage Vth2 (Vth1> Vth2) in the manufacturing process.
Alternatively, as in the fifth embodiment or the seventh embodiment, the variation in luminance can be suppressed by adjusting the gate length L1 and the gate length L2 to different lengths.
Furthermore, as in the ninth embodiment, by adjusting the gate area S1 (= W1 · L1) to be larger than the gate area S2 (= W2 · L2), variation in luminance can be suppressed.

The pixel circuit 201 according to the eleventh embodiment can suppress variations in luminance even if the n-channel TFTs 214a to 214b forming the gate group 214 are replaced with, for example, the p-channel pTFT 112c to pTFT 112d according to the second embodiment.
Also in this case, it is possible to suppress variation in luminance similarly to the second embodiment, the fourth embodiment, the sixth embodiment, the eighth embodiment, or the tenth embodiment.

  In the first to eleventh embodiments, an organic EL light emitting element is used as an example of a light emitting element. However, for example, a liquid crystal element is used as the light emitting element, which is equivalent to the first to eleventh embodiments. The effect is obtained.

  In the pixel circuits according to the first to eleventh embodiments, an n-channel TFT or a p-channel TFT is used as a switching transistor as one configuration example. As long as it has a function as a switching transistor, the same effects as those of the first to eleventh embodiments can be obtained even if the n-channel TFT or the p-channel TFT is replaced with another switching transistor.

As described above, according to the first to eleventh embodiments of the present invention, the first switching transistor and the second switching transistor having the same conductivity type, which are connected in series, The threshold voltages of the switching transistors whose gates are respectively connected to the same scanning line WSL and whose first terminal is connected to the signal line SGL are adjusted to be different.
By performing such adjustment, even when the threshold voltages of the two switching transistors vary due to individual differences or the like, variation in luminance of the display device can be suppressed while maintaining redundancy due to the series connection of the switching transistors.

1 is a block diagram illustrating a configuration of an active matrix display device. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit 2a illustrated in FIG. It is a figure which shows the time-dependent change of the electric current-voltage (IV) characteristic of an organic electroluminescent light emitting element. FIG. 3 is a circuit diagram illustrating a pixel circuit in which a p-channel TFT in the circuit of FIG. 2 is replaced with an n-channel TFT. It is a figure which shows the operating point of TFT21 and the EL light emitting element 23 as a drive transistor in an initial state. 1 is a block diagram illustrating a configuration example of an organic EL display device that employs a pixel circuit according to a first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a specific configuration example of a pixel circuit according to the first embodiment. 8 is a timing chart showing the basic operation of the pixel circuit of FIG. It is a figure for demonstrating the relationship between the threshold voltage of TFT112a-TFT112b, and the timing which TFT112a-TFT112b switches off. It is a circuit diagram which shows one specific structural example of the pixel circuit which concerns on 2nd Embodiment of this invention. 11 is a timing chart showing basic operations of the pixel circuit of FIG. 10. It is a block diagram which shows the example of 1 structure of the organic electroluminescence display which employ | adopted the pixel circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows one specific structural example of the pixel circuit which concerns on this embodiment. 14 is a timing chart showing the basic operation of the pixel circuit of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101, 101a ... Pixel circuit, 102 ... Pixel array part, 103 ... Horizontal selector, 104 ... Write scanner, 105 ... Power drive scanner, nTFT112a, nTFT112b ... N channel TFT, pTFT112c, pTFT112d ... P channel TFT, C111: capacitor, 111: driving transistor, 113: light emitting element, 112, 112a ... gate group, SGL ... signal line, WSL ... scanning line, ND112 ... node, Vth, Vth1, Vth2, Vth3, Vth4 ... threshold voltage, Cox1, Cox2, Cox3, Cox4: gate capacitance per unit area, W1, W2, W3, W4 ... gate width, L1, L2, L3, L4 ... gate length, S1, S2, S3, S4 ... gate area.

Claims (7)

A signal line to which a data signal is supplied;
At least two or more switching transistors of the same conductivity type connected in series;
A drive line to which a drive signal is supplied to drive the plurality of switching transistors;
Have
Among the plurality of switching transistors, a terminal of the switching transistor arranged at one end is connected to the signal line,
Control terminals of the plurality of switching transistors are commonly connected to the scanning line,
The plurality of switching transistors are:
Pixel circuits with different threshold voltages. A signal line to which a data signal is supplied;
At least two or more switching transistors of the same conductivity type connected in series;
A drive line to which a drive signal is supplied to drive the plurality of switching transistors;
Have
Among the plurality of switching transistors, a terminal of the switching transistor arranged at one end is connected to the signal line,
Control terminals of the plurality of switching transistors are commonly connected to the scanning line,
The plurality of switching transistors are:
Pixel circuits with different gate lengths. A signal line to which a data signal is supplied;
At least two or more switching transistors of the same conductivity type connected in series;
A drive line to which a drive signal is supplied to drive the plurality of switching transistors;
Have
Among the plurality of switching transistors, a terminal of the switching transistor arranged at one end is connected to the signal line,
Control terminals of the plurality of switching transistors are commonly connected to the scanning line,
The plurality of switching transistors are:
Pixel circuits with different gate areas. The pixel circuit is
A first switching transistor;
A second switching transistor;
Have
The first and second switching transistors are:
With the same conductivity type, each connected in series,
A terminal of the first switching transistor is connected to the signal line;
The control terminals of the first and second switching transistors are commonly connected to the drive line,
The absolute value of the threshold voltage of the first switching transistor is
The pixel circuit according to claim 1, wherein the pixel circuit is smaller than an absolute value of a threshold voltage of the second switching transistor. The pixel circuit is
A first switching transistor;
A second switching transistor;
Have
The first and second switching transistors are:
With the same conductivity type, each connected in series,
A terminal of the first switching transistor is connected to the signal line;
The control terminals of the first and second switching transistors are commonly connected to the drive line,
The gate length of the first switching transistor is
The pixel circuit according to claim 3, wherein the pixel circuit is shorter than a gate length of the second switching transistor. The pixel circuit is
A first switching transistor;
A second switching transistor;
Have
The first and second switching transistors are:
With the same conductivity type, each connected in series,
A terminal of the first switching transistor is connected to the signal line;
The control terminals of the first and second switching transistors are commonly connected to the drive line,
The gate area of the first switching transistor is
The pixel circuit according to claim 5, wherein the pixel circuit is larger than a gate area of the second switching transistor. A pixel circuit including light emitting elements arranged in a matrix;
At least one scanner for outputting a drive signal to a control terminal of a switching transistor forming the pixel circuit;
A selector that outputs a data signal to a first terminal of a switching transistor that forms the pixel circuit,
The pixel circuit is
A signal line to which a data signal is supplied;
At least two or more switching transistors of the same conductivity type connected in series;
A drive line to which a drive signal is supplied to drive the plurality of switching transistors;
Have
Among the plurality of switching transistors, a terminal of the switching transistor arranged at one end is connected to the signal line,
Control terminals of the plurality of switching transistors are commonly connected to the scanning line,
The plurality of switching transistors are:
Display devices with different threshold voltages.

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