JP2006039521A - Active matrix type display apparatus and driving device of load - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation of a drive current due to an unnecessary leak current by suppressing drive current in a dark state. <P>SOLUTION: An active matrix type display apparatus has a plurality of pixel circuits 1 arranged in a matrix shape. Each pixel circuit 1 has: a display device EL; a drive transistor M1 of a first conductivity type for controlling a current flowing in the display device; a capacitor C1 provided at a control electrode of the drive transistor; and a transistor M2a of a first conductivity type and a transistor M2b of a 2nd conductivity type which are connected in series as switches, connected to the control electrode of the drive transistor, for holding a drive control signal at the capacitor. One of the other main electrodes of those transistors is connected to the control electrode of the drive transistor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a television receiver, a monitor such as a computer, a cellular phone, a digital camera or a digital video camera, an exposure apparatus for an electrophotographic printer, an exposure light source for photolithography, and an active matrix display device used for driving a load, and driving of a load. In particular, the present invention relates to an active matrix display device and a load driving device that are preferably used for current-driven display elements.

  As an active matrix electroluminescent display device, for example, there is a device disclosed in Patent Document 1. FIG. 12 is a circuit diagram of a conventional pixel circuit.

  In the circuit operation shown in FIG. 12, the switches (transistors) 37 and 32 are closed, the switch (transistor) 33 is opened, and an input signal Iin corresponding to the element current required for light emission of the electroluminescent element 20 as an active element is input. . The voltage across the capacitance 38 in the steady state becomes the gate-source voltage required to drive the current flowing through the channel of the drive transistor 30. When the switches 37 and 32 are opened, the gate-source voltage determined according to the input signal Iin is held in the capacitance 38.

  Next, when the switch 33 is closed, a driving current corresponding to the held voltage level flows to the electroluminescent element 20 through the driving transistor 30 and emits light. Reference numeral 34 denotes a power supply line 34 for setting the voltage (V2) on the anode side of the electroluminescent element 20, and reference numeral 31 denotes a power supply line 31 for setting the voltage (V1) on the source side of the transistor.

  Patent Document 1 describes that n-type MOS transistors are used as the transistors 32, 37, and 30, and p-type MOS transistors are used as the transistors 33.

There is also known a pixel circuit using a p-type MOS transistor as a drive transistor and a p-type MOS transistor as a switching transistor for short-circuiting between the gate and drain of the drive transistor. (See Patent Document 2)
JP-T-2002-517806 International Publication Number WO01 / 91094

  In the active matrix display device and the drive device for the active element as the load, there is still room for improvement from the two viewpoints of setting the drive current in the dark to zero and preventing fluctuation of the drive current due to unnecessary leakage current. .

  An object of the present invention is to provide an active matrix display device and a load drive device that can suppress drive current in the dark and suppress unnecessary leakage current.

  Another object of the present invention is to drive an active matrix display device and a load that can reduce luminance in the dark due to variation in holding voltage caused by switching, and can suppress variation in luminance due to unnecessary leakage current. To provide an apparatus.

The first invention of the present application is an active matrix display device having a plurality of pixel circuits arranged in a matrix,
The pixel circuit is
A display element;
A first conductivity type driving transistor for controlling a current flowing through the display element;
A capacitor provided on the control electrode of the drive transistor;
A switch connected to the control electrode of the drive transistor for causing the capacitor to hold a drive control signal;
With
The switch includes a first conductivity type switching transistor and a second conductivity type switching transistor connected in series with one main electrode connected to each other,
One of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the control electrode of the drive transistor.

The second invention of the present application is a drive device for a load element,
A first conductivity type driving transistor for controlling a current flowing through the load;
A capacitor provided on the control electrode of the drive transistor;
A switch connected to the control electrode of the drive transistor for causing the capacitor to hold a drive control signal;
With
The switch includes a first conductivity type switching transistor and a second conductivity type switching transistor connected in series with one main electrode connected to each other,
One of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the control electrode of the drive transistor.

Here, as will be described in detail later with reference to FIG. 1, the other one of the other main electrodes of the first conductivity type switching transistor M2a and the second conductivity type switching transistor M2b is the drive transistor. Connected to one main electrode (drain) of M1,
The control electrode (gate) and the one main electrode (drain) of the drive transistor are short-circuited by turning on both the first conductivity type switching transistor and the second conductivity type switching transistor. It is also preferable that this is done.

  It is also preferable that the other main electrode of the first conductivity type switching transistor is connected to a control electrode of the driving transistor.

Furthermore, a second-conductivity-type row selection switching transistor M3 is provided between the one main electrode (drain) of the driving transistor and the signal line (Idata, d (x, y)),
A first conductivity type light emission selection switching transistor M4 is provided in a path of a current flowing through the display element (EL),
The control electrode of the second conductivity type switching transistor M2b, the control electrode of the row selection switching transistor M3, and the control electrode of the light emission selection switching transistor M4 are commonly connected to the second scanning signal line. It is also preferable.

  As shown in FIG. 2, after the time when the first conductivity type switching transistor transitions from on to off (the timing when P2 transitions from low level to high level), the second conductivity type switching transistor It is also preferable to transition from on to off (P2 transitions from a high level to a low level).

  Alternatively, as described later with reference to FIG. 9, it is also preferable that the other main electrode of the second conductivity type switching transistor is connected to one main electrode of the driving transistor.

In the case of FIG. 9 as well, a second conductivity type row selection switching transistor is provided between the one main electrode of the driving transistor and the signal line.
A switching transistor for light emission selection of the first conductivity type is provided in a path of a current flowing through the display element;
The control electrode of the second conductivity type switching transistor, the control electrode of the row selection switching transistor, and the control electrode of the light emission selection switching transistor are commonly connected to the second scanning signal line. Is preferred.

As will be described later with reference to FIGS. 10 and 11, the other of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the output terminal of the voltage buffer X. ,
It is also preferable that the input terminal of the voltage buffer is connected to a signal line (Idata, d (x, y)).

  As shown in FIG. 10, the other of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the output terminal of the source follower circuit, and It is also preferable that the input terminal is connected to the signal line.

  Further, as shown in FIG. 11, the other one of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to an output terminal of a feedback type operational amplifier, and the feedback type It is also preferable that the input terminal of the operational amplifier is connected to the signal line.

  In the present invention, the first conductivity type driving transistor and the first conductivity type switching transistor may be P-channel type thin film transistors, and the second conductivity type switching transistor may be an N-channel type thin film transistor. It is preferable.

  According to the present invention, it is possible to suppress drive current in the dark and suppress unnecessary leakage current.

  The inventor employs a p-type MOS transistor using low-temperature polysilicon as a drive transistor in the pixel circuit shown in FIG. 6, and uses low-temperature polysilicon as a switching transistor for short-circuiting between the gate and drain of the drive transistor. A pixel circuit was fabricated by employing the n-type MOS transistor used. In this case, sufficient darkness was not achieved during black display due to a decrease in the gate-source holding voltage accompanying switching. This causes a reduction in contrast when used in a display device, an exposure device, or an exposure light source.

  In addition, a p-type MOS transistor using low-temperature polysilicon is adopted as a drive transistor, and a p-type MOS transistor using low-temperature polysilicon is adopted as a switching transistor for short-circuiting between the gate and drain of the drive transistor. Thus, a pixel circuit was manufactured. In this case, it was found that a sufficient darkness was obtained during black display, but a leak current was generated via the switching transistor.

  Hereinafter, a preferred embodiment for solving such a problem will be described in detail with reference to the drawings.

  According to a preferred embodiment of the present invention, it is possible to suppress a decrease in contrast and a generation of leakage current due to a change in holding voltage caused by switching.

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a pixel circuit according to the first embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the pixel circuit of FIG.

  FIG. 3 is a configuration diagram showing a configuration of an active matrix light emitting display device according to the present invention.

  In FIG. 3, 1 is a pixel circuit arranged in a matrix, 2 is connected to a pixel circuit 1 arranged in the column direction, and a line sequential data line current is connected to the pixel circuit 1 via a signal line d (x, y). A voltage-current conversion circuit as a signal line driving circuit for supplying the signal Idata, 3 is a column shift register connected to the voltage-current conversion circuit 2, and 4 is connected to the pixel circuit 1 arranged in the row direction. Reference numeral 1 denotes a row shift register as a scanning line driving circuit that outputs a row scanning signal P1 and a row scanning signal P2. A plurality of pixel circuits 1 are arranged in a matrix to form a pixel portion.

  FIG. 4 is a timing chart for explaining the generation operation of the line sequential data line signal. A clock signal K is input to the column shift register 3, and a video signal is input to the voltage-current conversion circuit 2, and based on signals SP (n−1) to SP (n + 1) from the column shift register 3. Line-sequential data line current signals Idata (d (n−1) to d (n + 1)) are supplied to the columns of the pixel circuits.

  FIG. 5 is a timing chart for explaining a row scanning signal generation operation of the pixel circuit shown in FIG. A clock signal LK is input to the row shift register 4, and a row scanning signal P 1 (P 1 (m−1) to P 1 (m + 1)) and a row scanning signal P 2 (P 2 (m 2)) are input from the row shift register 4 to the row of the pixel circuit 1. -1) to P2 (m + 1)) are sequentially output.

  Here, FIG. 6 is a diagram showing a configuration of a pixel circuit of a comparative example with respect to the embodiment of the present invention. FIG. 7 is a timing chart for explaining the operation of the pixel circuit of FIG. FIG. 8 is a timing chart for explaining the generation operation of the row scanning signal of the pixel circuit shown in FIG.

  The comparison example of FIG. 6 has the same basic configuration for the programming operation of the current signal Idata as the pixel circuit shown in FIG. 12, the switch 32 of FIG. 12 is the nMOS transistor M2, the switch 37 is the nMOS transistor M3, and the switch 30 is the pMOS. It can be regarded as corresponding to the transistor M1.

  First, prior to the description of the present embodiment, a comparative example will be described in order to facilitate understanding of the configuration of the present invention.

  Now, considering the operation of the pixel circuit shown in FIG. 6 in the x column and the y row when the pixels in the x column and the y row are displayed in black, in FIG. 7, when the row scanning signal P1 becomes a high level, the first program The nMOS transistor M3 serving as a (row selection) switch is turned on, and the pMOS transistor M4 serving as a light emission selection switch is turned off. When the row scanning signal P2 becomes high level, the nMOS transistor M2 serving as the second program switch is turned on. The voltage of the capacitor C1 connected to the gate of the pMOS transistor M1 serving as the drive transistor is set to a gate-source voltage sufficient to allow a current for driving the electroluminescent element EL as an active element to flow through the pMOS transistor M1. Is set. Next, when the row scanning signal P2 becomes low level, the nMOS transistor M2 serving as the second program switch is turned off, and the voltage of the capacitor C1 is held. The period so far is called the programming period.

  Thereafter, when the row scanning signal P1 becomes low level, the nMOS transistor M3 serving as the first program (row selection) switch is turned off and the pMOS transistor M4 serving as the light emission selection switch is turned on. The supply of driving current to the electroluminescent element EL is controlled by the gate potential of the driving transistor M1, and the current flowing through the electroluminescent element EL is controlled. A period in which the electroluminescence element EL emits light (non-light emission in the case of black display data) is called a light emission period.

  Here, in the pixel circuit of FIG. 6, in order to stably hold the voltage of the capacitor C1, a transistor serving as the second program switch is an nMOS transistor with a small leakage current. This is because if the leakage current is large, the driving current in the light emission period varies.

  However, when the gate of the nMOS transistor M2 is switched from the high level to the low level in the programming period as shown in FIG. 7, the voltage to be held by the potential of the capacitor C1 being swung by the parasitic capacitance between the gate and the drain of the nMOS transistor M2. Vd (x, y) decreases by VM, and thereby the current flowing through the drive transistor M1 increases by IM. In such a case, a small current flows through the pMOS transistor M4 due to a decrease in the gate potential (holding voltage) even when the pixels in the x column and the y row display black during the light emission period. Then, although the display is black, minute light emission is observed. That is, the darkest state cannot be normally obtained, and it becomes difficult to ensure contrast.

  In this embodiment, as shown in FIG. 1, the second program switch connected between the capacitor C1 (the gate of the driving transistor M1) and the drain of the gate of the driving transistor M1 is connected in series. The pMOS transistor M2a and the nMOS transistor M2b are used. That is, the difference between the configuration of the pixel circuit of FIG. 1 and the configuration of the comparative example of FIG. 6 is that the nMOS transistor M2 of FIG. 6 has two switching transistors (pMOS transistor M2a and It is replaced with an nMOS transistor M2b).

  When the voltage is held in the capacitor C1, the gate of the pMOS transistor M2a is changed from the low level to the high level in the programming period. And the voltage Vd (x, y) to be held increases by VL, and thereby the current flowing through the drive transistor M1 decreases by IL. Therefore, it is possible to eliminate or reduce the pixel current that flows during black display.

  In black display, the current of the line sequential data line current signal is preferably zero, but in practice it is difficult to make the current zero because of the circuit configuration. If the current of the line sequential data line current signal does not become zero, the pixel current Id cannot be zero. In the configuration of FIG. 6, when the nMOS transistor M <b> 2 is turned off, the holding voltage due to the capacitor C <b> 1 is reduced and lowered, so that the pixel current Id further increases and it becomes more difficult to make the pixel current Id zero.

  If one of the second program switches is a pMOS transistor as in this embodiment, the direction of the potential at which the capacitor C1 is oscillated is reversed. Therefore, even if the current of the line sequential data line current signal does not become zero. The pixel current Id during black display can be made zero or sufficiently small by increasing the potential of the capacitor C1.

  On the other hand, the pMOS transistor used in the present embodiment has a larger leakage current than the nMOS transistor. However, as in this embodiment, the addition of the nMOS transistor M2b in series with the pMOS transistor suppresses the leakage current, and the light emission period. The holding voltage Vd at can be stabilized.

  The capacitor C1 may be individually formed as a capacitor element, but a parasitic capacitor formed between the gate and the drain (such as an overlapping capacitor between the gate electrode and the drain region) may be used without being formed as an element.

  FIG. 13 is a diagram illustrating a manufacturing process of a pMOS transistor M2a and an nMOS transistor M2b as a field effect thin film transistor using low-temperature polysilicon. FIG. 14 is a cross-sectional view showing the structure of an EL display device manufactured by the manufacturing method of FIG.

  As shown in FIG. 13A, after depositing an amorphous silicon layer on a glass substrate 100 using a plasma CVD method, a heat treatment (laser annealing) is performed by laser light or the like to form a polysilicon layer, and patterning is performed. Then, a polysilicon layer for the pMOS transistor M2a and the nMOS transistor M2b is formed.

  Here, if necessary, at least one of the polysilicon layers may be channel-doped with a dopant (phosphorus or boron) for exhibiting the opposite conductivity type to the source / drain, and the threshold value may be adjusted.

  Next, as shown in FIG. 13B, a gate insulating film 102 of SiO, SiN or the like is formed, polysilicon is formed and patterned to form a gate electrode 103.

  As shown in FIG. 13C, p-type impurities (phosphorus, etc.) and n-type impurities (boron, etc.) are ion-implanted and thermal diffusion is performed, so that the source of the pMOS transistor M2a, the drain region 105 and the source of the nMOS transistor M2b The drain region 104 is formed.

  As shown in FIG. 13D, after forming an insulating film such as SiO or SiN, contact holes are formed, and a metal layer (metal layer) to be a source, drain electrode, and wiring is laminated and patterned. Thereafter, after the planarization film 106 is formed, a through hole is formed, an anode electrode (not shown) is formed, and after patterning, an electroluminescent layer (EL layer) 107 is formed by a liquid discharge method such as vapor deposition or inkjet. Then, an ITO film 108 is formed. The EL layer is preferably composed of a plurality of layers constituting a so-called organic LED, and further preferably the EL layer is divided and independent for each pixel.

  As shown in FIG. 14, the substrate 100 is sealed with a glass container 109 to complete an EL display element.

  In the embodiment described above, a pMOS transistor having a leakage current that is orders of magnitude greater than that of an nMOS transistor is manufactured. However, depending on the manufacturing process, on the contrary, there may be a transistor in which the leakage current of the nMOS transistor is larger than that of the pMOS transistor. In such a case, the present invention is preferably used.

(Second Embodiment)
FIG. 9 is a diagram showing a configuration example of a pixel circuit according to the second embodiment of the present invention. Signals for operating the pixel circuit are the same as those shown in FIG. In the first embodiment, as shown in FIG. 1, the pMOS transistor M2a is connected to the gate of the pMOS transistor M1, and the nMOS transistor M2b is connected to the drain of the pMOS transistor M1, but in this embodiment, as shown in FIG. The nMOS transistor M2b is connected to the gate of the pMOS transistor M1, and the pMOS transistor M2a is connected to the drain of the pMOS transistor M1.

Other configurations are the same as those in the first embodiment.
Even in the pixel circuit having such a connection configuration, an effect similar to that of the first embodiment can be obtained by feedthrough of the nMOS transistor M2b in the on state.

(Third embodiment)
In order to operate the pixel circuit shown in FIG. 1 or FIG. 9, it is required to charge the capacitance C1 and the parasitic capacitance due to the intersection of the wiring by the line sequential data line current signal. In order to obtain a high contrast ratio, the pixel circuit 1 is required to be controlled with a small current. However, the charging time of the capacitor C1 and the parasitic capacitance becomes long with a small current, and the small current setting operation in one horizontal scanning period is insufficient May be. This becomes a more significant problem in a TFT circuit in which the threshold voltage variation ΔVth of the current drive transistor M1 of the pixel circuit 1 in each row is large. On the other hand, the capacity value of the capacitor C1 cannot be made very small because the current driving operation for one frame period of the video signal Video must be maintained.

  The present embodiment provides a configuration capable of shortening the set operation time even when the current signal input to the pixel circuit is a small current. A configuration in which a voltage buffer is added to the pixel circuit as in this embodiment is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-118181. As the voltage buffer, a source follower circuit or a feedback operational amplifier can be used. These circuits described below can be regarded as a feedback circuit that detects a current flowing through a driving transistor or an active element and inputs a voltage signal based on the current to a gate that is a control electrode of the driving transistor. As a result, it is possible to compensate for variations in the active element drive current due to variations in drive transistor threshold voltage and amplification characteristics for each drive transistor.

  FIG. 10 is a diagram showing a configuration example of a pixel circuit and a voltage buffer circuit according to the third embodiment of the present invention.

  In this embodiment, the voltage buffer X whose output voltage is determined by the input voltage is provided for each pixel circuit column. The voltage buffer X is composed of a source follower circuit composed of a pMOS transistor and a current source. The output terminal side (connection point between the pMOS transistor and the current source) of the voltage buffer X is connected to the nMOS transistor M2b, and the input terminal side (gate of the pMOS transistor) is connected to the input signal line of the line sequential data line current signal Idata. The

  Other configurations are the same as those in the first embodiment.

  Further, instead of the source follower circuit, as shown in FIG. 11, a feedback type operational amplifier may be used as a voltage buffer.

  Also in this case, the configuration other than the portion shown in FIG. 11 is the same as that of the first embodiment.

  According to this embodiment, the voltage having the same potential as the drain of the drive transistor M1 is held in the capacitor C1 by the action of the voltage buffer, and a current corresponding to the current signal Idata programmed in the pixel circuit is supplied to the active element. Can flow to EL.

  In this way, similarly to the first and second embodiments, it is possible to perform driving while suppressing adverse effects due to characteristic variations of the driving transistors for each pixel.

  In each of the embodiments described above, an example in which a pMOS transistor is used as the drive transistor M1 has been described. However, when an nMOS transistor is used as the drive transistor M1, the polarity of the active element, signal, or power source may be reversed. . Specifically, the drain of the driving nMOS transistor is connected to the cathode side of the LED as an active element, the anode of the LED is connected to the high potential power source, and the source of the driving nMOS transistor is connected to the low potential power source. .

  In addition, as an active element used as a load of the present invention, various emission elements such as an inorganic LED, an organic LED (organic EL), an electron emission element, and a semiconductor laser can be used.

  Further, the present invention is preferably used for a crystalline semiconductor thin film transistor including a crystal grain boundary represented by so-called low-temperature polysilicon. The circuit configuration of the present invention includes an amorphous silicon TFT, a single crystal silicon TFT, and a high-temperature polysilicon TFT. Or may be configured.

  The present invention is particularly suitable for use in an active matrix display device using a current-driven light emitting element such as an electroluminescent element (EL element) as an active element.

It is a figure which shows one structural example of the pixel circuit concerning the 1st Embodiment of this invention. 3 is a timing chart for explaining the operation of the pixel circuit according to the first embodiment of the present invention. 1 is a configuration diagram illustrating a configuration of an active matrix electroluminescent display device according to the present invention. 6 is a timing chart for explaining a generation operation of a line sequential data line signal. 3 is a timing chart for explaining an operation of generating a row scanning signal of the pixel circuit shown in FIG. It is a figure which shows the structure of the comparative example concerning the 1st Embodiment of this invention. 7 is a timing chart for explaining the operation of the pixel circuit of FIG. 6. 7 is a timing chart for explaining an operation of generating a row scanning signal of the pixel circuit shown in FIG. 6. It is a figure which shows the example of 1 structure of the pixel circuit concerning the 2nd Embodiment of this invention. It is a figure which shows one structural example of the pixel circuit and voltage buffer circuit concerning the 3rd Embodiment of this invention. It is a figure which shows the modification of the pixel circuit and voltage buffer circuit concerning the 3rd Embodiment of this invention. It is a circuit diagram of the conventional pixel circuit. It is a figure which shows the manufacturing process of the pMOS transistor M2a used for this invention, and the nMOS transistor M2b part. It is sectional drawing which shows the structure of the EL display element produced with the manufacturing method of FIG.

Explanation of symbols

1 pixel circuit 2 signal line drive circuit 3 column shift register 4 row shift register M1 drive transistor C1 capacitance M2a, M2b switch EL load (display element)

Claims (13)

An active matrix display device,
A plurality of pixel circuits arranged in a matrix;
The pixel circuit is connected to a display element, a first conductivity type driving transistor for controlling a current flowing in the display element, a capacitor provided in a control electrode of the driving transistor, and the control electrode of the driving transistor; A switch for holding the drive control signal in the capacitor,
The switch includes a first conductivity type switching transistor and a second conductivity type switching transistor connected in series with one main electrode connected to each other,
One of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the control electrode of the drive transistor. The other of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to one main electrode of the drive transistor;
2. The control transistor of the drive transistor and the one main electrode are short-circuited by turning on both the first conductivity type switching transistor and the second conductivity type switching transistor. The active matrix display device described.   3. The active matrix display device according to claim 2, wherein the other main electrode of the first conductivity type switching transistor is connected to the control electrode of the drive transistor. A second conductivity type row selection switching transistor is provided between the one main electrode of the driving transistor and the signal line;
A switching transistor for light emission selection of the first conductivity type is provided in a path of a current flowing through the display element;
The control electrode of the second conductivity type switching transistor, the control electrode of the row selection switching transistor, and the control electrode of the light emission selection switching transistor are commonly connected to a second scanning signal line. Item 4. The active matrix display device according to any one of Items 1 to 3.   The active matrix type according to any one of claims 2 to 4, wherein the second conductivity type switching transistor transitions from on to off after a time when the first conductivity type switching transistor transitions from on to off. Display device.   6. The active matrix display device according to claim 2, wherein the other main electrode of the second conductivity type switching transistor is connected to the control electrode of the drive transistor. A second conductivity type row selection switching transistor is provided between the one main electrode of the driving transistor and the signal line;
A switching transistor for light emission selection of the first conductivity type is provided in a path of a current flowing through the display element;
The control electrode of the second conductivity type switching transistor, the control electrode of the row selection switching transistor, and the control electrode of the light emission selection switching transistor are commonly connected to a second scanning signal line. Item 7. The active matrix display device according to Item 6. The other of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the output terminal of the voltage buffer;
The active matrix display device according to claim 1, wherein an input terminal of the voltage buffer is connected to a signal line. The other of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the output terminal of the source follower circuit,
The active matrix display device according to claim 1, wherein an input terminal of the source follower circuit is connected to a signal line. The other one of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the output terminal of the feedback type operational amplifier,
The active matrix display device according to claim 1, wherein an input terminal of the feedback operational amplifier is connected to a signal line.   11. The first conductivity type driving transistor and the first conductivity type switching transistor are P-channel type thin film transistors, and the second conductivity type switching transistor is an N-channel type thin film transistor. The active matrix display device according to item. A load driving device,
A first conductivity type driving transistor for controlling a current flowing through the load;
A capacitor provided on the control electrode of the drive transistor;
A switch connected to the control electrode of the drive transistor for holding a drive control signal in the capacitor,
The switch includes a first conductivity type switching transistor and a second conductivity type switching transistor connected in series with one main electrode connected to each other,
One of the other main electrodes of the first conductivity type switching transistor and the second conductivity type switching transistor is connected to the control electrode of the drive transistor.   The load driving device according to claim 12, wherein a plurality of pixel circuits each including the first conductivity type driving transistor, the capacitor, and the switch are arranged in a matrix.

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