JP2010060868A - Method of driving pixel circuit, light emitting device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress drive-current errors with respect to a plurality of grayscale values. <P>SOLUTION: Each of pixel circuits U includes a light emitting element E, a drive transistor TDR, a holding capacitor C1 disposed between a gate and source of the drive transistor TDR, a selection switch TSL and a control switch TCR1 disposed between the gate of a drive transistor TDR and a signal line 14. In a compensation period PCP, a voltage VGS between both ends of the holding capacitor C1 is gradually approximated to the threshold voltage VTH of the drive transistor TDR. In a writing period PWR, a grayscale potential VDATA corresponding to the grayscale value D is supplied to the signal line 14, and the selection switch TSL is turned on. In an active period PA having a time length corresponding to the grayscale value D within the writing period PWR, the control switch TCR1 is turned on, then, the gate potential of the drive transistor TDR is changed to the grayscale potential VDATA, and also, the voltage VGS is gradually approximated to the threshold voltage VTH. A drive current IDR corresponding to the voltage VGS is supplied to the light emitting element E. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for driving a light emitting element such as an organic EL (Electroluminescence) element.

In a light-emitting device in which a drive transistor controls the amount of drive current supplied to a light-emitting element, an error in the electrical characteristics of the drive transistor or light-emitting element (difference from a target value or variation between elements) is a problem. Become. Japanese Patent Application Laid-Open No. 2004-133867 discloses that a voltage across a storage capacitor interposed between a gate and a source of a driving transistor is set to a threshold voltage of the driving transistor and then changed to a voltage corresponding to a gradation value. Disclosed is a technique for compensating for an error in threshold voltage and mobility (and thus an error in the amount of drive current).
JP 2007-310311 A

  However, the error of the drive current is effectively compensated by the technique of Patent Document 1 only when a specific gradation value is designated, and the error of the drive current may not be eliminated depending on the gradation value. In view of the above circumstances, an object of the present invention is to suppress a drive current error for a plurality of gradation values.

  In order to solve the above problems, a driving method of a pixel circuit according to the present invention includes a light emitting element and a driving transistor connected in series, a path between the light emitting element and the driving transistor, a gate of the driving transistor, A pixel circuit including a storage capacitor interposed between the gate electrode and a signal line and a selection switch and a first control switch (for example, a control switch TCR1) connected in series between the gate and the signal line of the driving transistor. In the compensation period, the voltage across the storage capacitor is made asymptotic to the threshold voltage of the driving transistor, and in the writing period after the compensation period, the gradation potential corresponding to the gradation value designated for the pixel circuit is set. An operation period of a time length (for example, a time length T) variably set in accordance with the gradation value in the writing period is supplied to the signal line and the selection switch is turned on. The first control switch is controlled to be turned on by changing the gate potential of the driving transistor in accordance with the gradation potential, and the voltage across the storage capacitor is gradually approached to the threshold voltage of the driving transistor, thereby writing. In the driving period after the elapse of the period, the supply of the potential to the gate of the driving transistor is stopped, so that a driving current corresponding to the voltage across the storage capacitor is supplied to the light emitting element. In the above driving method, the time length of the operation period in which the voltage across the storage capacitor asymptotically approaches the threshold voltage of the driving transistor in the writing period is variably set according to the gradation value (or gradation potential). Therefore, it is possible to effectively suppress the drive current error for a plurality of gradation values.

  More specifically, as the amount of change in voltage between both ends of the storage capacitor when the gradation potential is supplied in the writing period (for example, the voltage VIN), the length of the operation period in which the drive current error can be suppressed becomes shorter. Assuming this tendency, the time length of the operation period is shortened as the amount of change in voltage across the storage capacitor (for example, voltage VIN) when the gradation potential is supplied in the writing period is larger. The time length of the operation period is variably set according to the gradation value designated for the pixel circuit. For example, the level specified for the pixel circuit is set so that the product of the amount of change in the voltage across the storage capacitor and the time length of the operation period when a gradation potential is supplied during the writing period approaches a predetermined value. The time length of the operation period is variably set according to the adjustment value.

  However, the smaller the gradation value is, the longer the length of the operation period during which the drive current error is suppressed.Therefore, it is attempted to minimize the drive current error even when the gradation value is small. For example, it is necessary to secure an excessively long time length as the operation period. Therefore, in a preferred aspect of the present invention, when the gradation value is lower than the predetermined value, the time length of the operation period is set to a predetermined value independent of the gradation value (for example, the time length Tmax in FIG. 10) ( That is, an upper limit is set for the time length of the operation period). The above driving method has an advantage that the time length of the operation period is suppressed to an appropriate length even when the gradation value is small.

  In the compensation period of the driving method according to the preferred embodiment of the present invention, the reference potential is supplied to the gate of the driving transistor from a power supply line different from the signal line. In the above aspect, since the reference potential is supplied to the gate of the driving transistor from the power supply line different from the signal line in the compensation period, the common signal line is shared for the supply of the gradation potential and the supply of the reference potential. Compared to the case, there is an advantage that it is possible to ensure a long time length for an operation in which the voltage across the storage capacitor asymptotically approaches the threshold voltage of the driving transistor in the compensation period.

  A light emitting device according to the present invention includes a light emitting element and a driving transistor connected in series with each other, a storage capacitor interposed between a path between the light emitting element and the driving transistor, and a gate of the driving transistor, A pixel circuit including a selection switch and a first control switch connected in series between the gate and the signal line; and a driving circuit for driving the pixel circuit. The driving circuit has a storage capacitor in the compensation period. The voltage between both ends is made asymptotic to the threshold voltage of the drive transistor, and in the writing period after the compensation period has elapsed, a gradation potential corresponding to the gradation value designated for the pixel circuit is supplied to the signal line and the selection switch Is turned on, and the first control switch is turned on during the operation period with a time length variably set according to the gradation value in the writing period. The gate of the transistor is changed in accordance with the grayscale potential, and the voltage across the storage capacitor is made asymptotic to the threshold voltage of the driving transistor, so that the potential is supplied to the gate of the driving transistor in the driving period after the writing period has elapsed. By stopping, a driving current corresponding to the voltage across the storage capacitor is supplied to the light emitting element. According to the above light emitting device, the same effect as that of the pixel circuit driving method of the present invention is realized.

  In a preferred aspect of the light emitting device according to the present invention, the pixel circuit includes a second control switch (for example, the control switch TCR2) interposed between the gate of the driving transistor and the power supply line to which the reference potential is supplied, and the driving circuit Controls the second control switch to the on state during the compensation period, and controls the second control switch to the off state during the writing period. In the above aspect, since the reference potential is supplied to the gate of the driving transistor from the power supply line different from the signal line in the compensation period, the common signal line is shared for the supply of the gradation potential and the supply of the reference potential. Compared to the case, there is an advantage that it is possible to ensure a long time length for an operation in which the voltage across the storage capacitor asymptotically approaches the threshold voltage of the driving transistor in the compensation period.

  A light emitting device according to another aspect of the present invention includes a light emitting element and a driving transistor connected in series to each other, a storage capacitor interposed between a path between the light emitting element and the driving transistor and a gate of the driving transistor, A signal line to which a gradation potential corresponding to a gradation value is supplied, a selection switch and a first control switch connected in series between the gate of the driving transistor and the signal line, and a scanning signal for controlling the selection switch The selection switch is turned on in at least a writing period among a scanning line to be supplied, a control line to which a control signal for controlling the first control switch is supplied, and a period in which the gradation potential is supplied to the signal line. In this way, the control signal is supplied so that the operation period in which the first control switch is turned on in the writing period has a time length that is variably set according to the gradation value. The includes a supply drive circuit to the control line. In the above configuration, the time length of the operation period in which both the selection switch and the first control switch are turned on (that is, the operation period in which the voltage between both ends of the storage capacitor gradually approaches the threshold voltage of the driving transistor) is the gradation value. Therefore, the drive current error can be effectively suppressed for a plurality of gradation values.

  If the signal lines and the control lines are extended in a direction intersecting with the extending direction of the scanning lines, for example, the number of pixel circuits arranged in the extending direction of the scanning lines is equal to the extending direction of the signal lines. In the light-emitting device that exceeds the number of pixel circuits arranged in the control line, the load on the control line is reduced. Therefore, it is possible to control the time length of the operation period with high accuracy as compared with the configuration in which the control line extends in the same direction as the scanning line.

  The light emitting device according to each aspect described above is used in various electronic devices. A typical example of an electronic device is a device that uses a light-emitting device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone. However, the use of the light emitting device according to the present invention is not limited to image display. For example, the light emitting device of the present invention is also applied as an exposure device (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

<A: Embodiment>
FIG. 1 is a block diagram of a light emitting device according to an embodiment of the present invention. The light emitting device 100 is mounted on an electronic device as a display body that displays an image. As shown in FIG. 1, the light emitting device 100 includes an element unit 10 in which a plurality of pixel circuits U are arranged, and a drive circuit 30 that drives each pixel circuit U. The drive circuit 30 includes a scanning line drive circuit 32, a signal line drive circuit 34, and a potential control circuit 36. The drive circuit 30 is distributed and mounted on a plurality of integrated circuits, for example. However, at least a part of the drive circuit 30 can be constituted by a thin film transistor formed on a substrate.

  In the element portion 10, m scanning lines 12 extending in the X direction and n signal lines 14 extending in the Y direction intersecting the X direction are formed (m and n are natural numbers). The plurality of pixel circuits U are arranged at the intersections of the scanning lines 12 and the signal lines 14 and are arranged in a matrix of vertical m rows × horizontal n columns. The element unit 10 includes m feed lines 16 and m control lines 22 extending in the X direction together with the scanning lines 12 and n control lines extending in the Y direction together with the signal lines 14. 24 are formed.

  The scanning line driving circuit 32 outputs scanning signals GA [1] to GA [m] to each scanning line 12 and outputs control signals GB [1] to GB [m] to each control line 22. Note that a configuration in which separate circuits generate the scanning signals GA [1] to GA [m] and the control signals GB [1] to GB [m] is also employed. The potential control circuit 36 generates a potential VEL [1] to a potential VEL [m] and outputs it to each feeder line 16.

  The signal line drive circuit 34 outputs signals S [1] to S [n] to each signal line 14 and outputs control signals GT [1] to GT [n] to each control line 24. As shown in FIG. 1, the signal line drive circuit 34 includes n unit circuits 40 corresponding to the signal lines 14. The unit circuit 40 in the j-th column (j = 1 to n) generates the signal S [j] and the control signal GT [j] and outputs them to the signal line 14 in the j-th column. A configuration in which separate circuits generate the signals S [1] to S [n] and the control signals GT [1] to GT [n] is also employed.

  FIG. 2 is a circuit diagram of the pixel circuit U. In FIG. 2, only one pixel circuit U in the j-th column belonging to the i-th row (i = 1 to m) is representatively illustrated. As shown in FIG. 2, the pixel circuit U includes a light emitting element E, a driving transistor TDR, a holding capacitor C1, a selection switch TSL, a control switch TCR1, and a control switch TCR2. Each switch (selection switch TSL, control switch TCR1, control switch TCR2) in the pixel circuit U is, for example, an N-channel transistor (for example, a thin film transistor).

  The light emitting element E and the drive transistor TDR are connected in series on a path connecting the power supply line 16 and the power supply line (ground line) 18. The power supply line 18 is supplied with a predetermined potential VCT from a power supply circuit (not shown). The light emitting element E is an organic EL element in which a light emitting layer of an organic EL (Electroluminescence) material is interposed between an anode and a cathode that face each other. As shown in FIG. 2, the light emitting element E is accompanied by a capacitor C2 (capacitance value cp2).

  The drive transistor TDR is an N-channel transistor (for example, a thin film transistor) having a drain connected to the power supply line 16 and a source connected to the anode of the light emitting element E. The holding capacitor C1 (capacitance value cp1) is interposed between the source of the driving transistor TDR (that is, the path between the light emitting element E and the driving transistor TDR) and the gate of the driving transistor TDR.

  The selection switch TSL and the control switch TCR1 are connected in series between the signal line 14 and the gate of the driving transistor TDR to control electrical connection (conduction / non-conduction) between the signal line 14 and the gate of the driving transistor TDR. To do. The gates of the selection switches TSL of the pixel circuits U belonging to the i-th row are commonly connected to the scanning line 12 of the i-th row, and the gates of the control switches TCR1 of the pixel circuits U belonging to the j-th column are controlled in the j-th column. Commonly connected to the line 24. In FIG. 2, the selection switch TSL is disposed on the drive transistor TDR side and the control switch TCR1 is disposed on the signal line 14 side. However, the selection switch TSL is disposed on the signal line 14 side and the control switch TCR1 is disposed on the drive transistor. A configuration arranged on the TDR side is also employed.

  The control switch TCR2 is interposed between the gate of the driving transistor TDR and the power supply line 28 to control the electrical connection between them. A reference potential VREF is supplied to the power supply line 28. For example, as shown in FIG. 2, the power supply line 28 is a wiring extending in the X direction for each row of the pixel circuits U (or a wiring extending in the Y direction for each column), or each pixel circuit U in the element unit 10. It is a continuous wiring. The gates of the control switches TCR2 of the pixel circuits U belonging to the i-th row are commonly connected to the control line 22 of the i-th row.

  Next, with reference to FIG. 3, the operation of the drive circuit 30 (method for driving the pixel circuit U) will be described with particular attention paid to the pixel circuit U in the j-th column belonging to the i-th row. The scanning line driving circuit 32 sequentially selects the pixel circuits U in units of rows by setting the scanning signals GA [1] to GA [m] to the active level in a predetermined order. That is, as shown in FIG. 3, the scanning signal GA [i] is set to the active level (high level meaning selection of the scanning line 12) in the i-th horizontal scanning period H [i] in the vertical scanning period. The inactive level (low level) is maintained outside the horizontal scanning period H [i]. In the horizontal scanning period H [i] in which the scanning line driving circuit 32 selects the i-th row, the signal line driving circuit 34 designates the signal S [j] to the pixel circuit U in the j-th column belonging to the i-th row. The gradation potential VDATA [i] corresponding to the gradation value D thus set is set.

  As shown in FIG. 3, the horizontal scanning period H [i] is used as a writing period PWR for supplying the gradation potential VDATA [i] to each pixel circuit U in the i-th row. Also, a plurality of horizontal scanning periods (horizontal scanning period [i-2] and horizontal scanning period H [i-1] in FIG. 3) before the start of the writing period PWR (horizontal scanning period H [i]) of the i-th row. ) Is used as the compensation period PCP of the i-th row, and one horizontal scanning period H [i-3] before the start of the compensation period PCP is used as the initialization period PRS of the i-th row.

  The voltage VGS between the gate and the source of the driving transistor TDR (that is, the voltage across the holding capacitor C1) VGS is initialized to a predetermined voltage in the initialization period PRS and then the threshold of the driving transistor TDR in the compensation period PCP. Asymptotically approaching the voltage VTH, it is set to a voltage corresponding to the gradation potential VDATA [i] in the writing period PWR. In the driving period PDR after the writing period PWR has elapsed, the driving current IDR corresponding to the voltage VGS of the driving transistor TDR is supplied from the power supply line 16 to the light emitting element E via the driving transistor TDR. The light emitting element E emits light with luminance according to the drive current IDR.

  As shown in FIG. 3, the scanning line driving circuit 32 controls the control signal GB [i during the initialization period PRS and the compensation period PCP (horizontal scanning periods H [i-3] to H [i-1]) of the i-th row. ] Is set to the active level (high level), and the control signal GB [i] is maintained at the inactive level (low level) in other periods. The potential control circuit 36 sets the potential VEL [i] to the potential V2 in the initialization period PRS of the i-th row, and maintains the potential VEL [i] at the potential V1 outside the initialization period PRS.

  As shown in FIG. 3, within each writing period PWR (each of the horizontal scanning periods H [1] to H [m]), there is a time from a point delayed by a predetermined time from the starting point of the writing period PWR. An operation period PA over a length T is set. The operation period PA is a period during which the gradation potential VDATA [i] is actually supplied to the pixel circuit U. As shown in FIG. 3, the signal line drive circuit 34 sets the control signal GT [j] to the active level (high level) in the operation period PA in each write period PWR, and sets the control signal GT [j] in each write period PWR. The control signal GT [j] is maintained at an inactive level (low level) outside the operation period PA.

  Next, a specific operation of the pixel circuit U will be described by dividing it into an initialization period PRS, a compensation period PCP, a writing period PWR, and a driving period PDR. In the following, the operation will be described focusing on the pixel circuit U in the j-th column belonging to the i-th row, but the same operation is performed for each pixel circuit U in the element unit 10.

[1] Initialization period PRS (Fig. 4)
As shown in FIGS. 3 and 4, in the initialization period PRS (horizontal scanning period H [i-3]) of the i-th row, the control signal GB [i] is set to the active level, so that the control switch TCR2 Is controlled to be on. Since the selection switch TSL and the control switch TCR1 are kept off, the potential VG of the gate of the drive transistor TDR is set to the reference potential VREF of the feeder line 28 via the control switch TCR2. On the other hand, the potential control circuit 36 supplies the potential V2 (potential VEL [i]) to the power supply line 16, so that the source potential VS of the drive transistor TDR is set to the potential V2. That is, the voltage VGS between the gate and source of the drive transistor TDR (the voltage across the holding capacitor C1) is initialized to the voltage VGS1 (VGS1 = VREF−V2) which is the difference between the reference potential VREF and the potential V2.

The reference potential VREF and the potential V2 are different from each other in the voltage VGS1 of the difference as shown in the following formula (1) and the threshold voltage VTH of the driving transistor TDR, and the both ends of the light emitting element E as shown in the formula (2). The voltage (V2-VCT) between them is set to be sufficiently lower than the threshold voltage VTH_OLED of the light emitting element E. Therefore, in the initialization period PRS, the driving transistor TDR is turned on, and the light emitting element E is turned off (non-light emitting state).
VGS1 = VREF-V2 >> VTH (1)
V2−VCT << VTH_OLED …… (2)

[2] Compensation period PCP (Fig. 5)
As shown in FIGS. 3 and 5, when the compensation period PCP starts, the potential control circuit 36 changes the potential VEL [i] of the power supply line 16 (the potential of the drain of the driving transistor TDR) to the potential V1. As shown in FIG. 3, the potential V1 is sufficiently higher than the potential V2 and the reference potential VREF. On the other hand, the control switch TCR2 is controlled to be in an ON state continuously from the initialization period PRS. Since the driving transistor TDR is turned on in the initialization period PRS, as shown in FIG. 5, the current Ids expressed by the following equation (3) is changed to the driving transistor TDR under the above state. Flows between the drain and the source. In the equation (3), μ is the mobility of the driving transistor TDR. W / L is a relative ratio of the channel width W to the channel length L of the driving transistor TDR, and Cox is a capacitance per unit area of the gate insulating film of the driving transistor TDR.
Ids = 1/2 ・ μ ・ W / L ・ Cox ・ (VGS−VTH) ² …… (3)

  When the current Ids flows from the power supply line 16 via the driving transistor TDR, the storage capacitor C1 and the capacitor C2 are charged. Therefore, as shown in FIG. 3, the source potential VS of the drive transistor TDR gradually rises. Since the gate potential VG of the drive transistor TDR is maintained at the reference potential VREF of the power supply line 28, the gate-source voltage VGS of the drive transistor TDR decreases as the source potential VS increases. As understood from the equation (3), the current Ids decreases as the voltage VGS decreases and approaches the threshold voltage VTH. Therefore, in the compensation period PCP, the voltage VGS of the drive transistor TDR is gradually approached from the voltage VGS1 (VGS1 = VREF−V2) set in the initialization period PRS to the threshold voltage VTH (hereinafter referred to as “first compensation operation”). Is executed). As shown in FIGS. 3 and 5, the time length of the compensation period PCP (the number of horizontal scanning periods H) is such that the voltage VGS of the drive transistor TDR is sufficiently close to the threshold voltage VTH at the end of the compensation period PCP (ideal). To match). Therefore, the drive transistor TDR is almost turned off at the end point of the compensation period PCP.

[3] Write period PWR (FIG. 6)
As shown in FIG. 3, when the writing period PWR (horizontal scanning period H [i]) of the i-th row starts, the control signal GB [i] is set to the inactive level, so that the control switch TCR2 is turned off. Transition to. That is, the supply of the reference potential VREF to the gate of the drive transistor TDR is stopped. Further, in the writing period PWR of the i-th row, the signal S [j] supplied to the signal line 14 is set to the gradation potential VDATA [i], and the scanning signal GA [i] is set to the active level. By changing, the selection switch TSL is controlled to be on. However, before the start of the operation period PA in the write period PWR, the control signal GT [j] is set to the inactive level, so that the control switch TCR1 is maintained in the off state (that is, the gate of the drive transistor TDR is Therefore, the gradation potential VDATA [i] of the signal S [j] is not supplied to the gate of the driving transistor TDR.

As shown in FIGS. 3 and 6, when the operation period PA starts, the control signal GT [j] is set to the active level, so that the control switch TCR1 is turned on. That is, the gate of the drive transistor TDR is conducted to the signal line 14 via the selection switch TSL and the control switch TCR1. Therefore, the gate potential VG of the drive transistor TDR changes from the reference potential VREF before the start of the operation period PA to the gradation potential VDATA. Since the storage capacitor C1 is interposed between the gate and source of the drive transistor TDR, the source potential VS of the drive transistor TDR changes (increases) in conjunction with the gate potential VG, as shown in FIG. The change amount of the potential VS immediately after the start of the operation period PA is a voltage obtained by dividing the change amount ΔVG (ΔVG = VDATA−VREF) of the potential VG according to the capacitance ratio between the holding capacitor C1 and the capacitor C2 (ΔVG · cp1 / (Cp1 + cp2)). Therefore, the voltage VGS2 between the gate and source of the driving transistor TDR (between both ends of the storage capacitor C1) immediately after the start of the operation period PA is expressed by the following formula (4) as shown in FIG. The voltage VIN in Equation (4) corresponds to the amount of change in the gate-source voltage VGS (ΔVG · cp2 / (cp1 + cp2)) when the gradation potential VDATA is supplied to the gate of the driving transistor TDR.
VGS2 = VTH + ΔVG · cp2 / (cp1 + cp2)
= VIN + VTH (4)

  As described above, the gate-source voltage VGS2 is set to a voltage exceeding the threshold voltage VTH in accordance with the gradation potential VDATA (more specifically, the difference ΔVG between the gradation potential VDATA and the reference potential VREF). The drive transistor TDR transitions to the on state. Therefore, the current Ids of Expression (3) flows between the drain and source of the driving transistor TDR.

As the holding capacitor C1 and the capacitor C2 are charged by the current Ids, the source potential VS (voltage across the capacitor C2) of the drive transistor TDR gradually increases. On the other hand, the gate potential VG of the driving transistor TDR is maintained at the gradation potential VDATA during the operation period PA. Accordingly, the gate-source voltage VGS of the drive transistor TDR decreases from the voltage VGS2 immediately after the start of the operation period PA as the potential VS increases. Since the current Ids decreases as the voltage VGS approaches the threshold voltage VTH, in the operation period PA of the writing period PWR, the voltage VGS of the driving transistor TDR is supplied by the supply of the gradation potential VDATA, as in the compensation period PCP. An operation (hereinafter referred to as “second compensation operation”) for gradually approaching the set voltage VGS2 to the threshold voltage VTH is performed. Therefore, as shown in FIG. 3, the voltage VGS at the end point of the operation period PA is set to the voltage VGS3 of the formula (5) lower than the voltage VGS2 of the formula (4) by the voltage ΔV. The voltage ΔV corresponds to the amount of change in the source potential VS of the drive transistor TDR due to the second compensation operation.
VGS3 = VGS2-ΔV
= VIN + VTH-ΔV (5)

  The time length T of the operation period PA in which the control signal GT [j] is set to the active level in the writing period PWR (horizontal scanning period H [i]) of the i-th row is that of the j-th column belonging to the i-th row. It is variably set according to the gradation value D (gradation potential VDATA [i]) of the pixel circuit U. That is, as shown in FIG. 3, the time length T when the gradation value D designates a high gradation (high luminance) is the time length T when the gradation value D designates a low gradation (low luminance). Short compared to. Since the time length from the start point of the operation period PA to the drive transistor TDR changing to the ON state is sufficiently short, the time length T of the operation period PA corresponds to the time length for executing the second compensation operation. In consideration of the fact that the voltage ΔV in Equation (5) depends on the time length T of the operation period PA, the operation for controlling the time length T of the operation period PA according to the gradation value D is the voltage VGS3 (voltage ΔV ) Is variably controlled according to the gradation value D.

  The time length T of the operation period PA is such that the voltage VGS3 between the gate and source of the drive transistor TDR at the end point of the operation period PA is equal to the threshold voltage VTH (when the gradation value D specifies the lowest gradation) or It is set within a range where the voltage exceeds the threshold voltage VTH. That is, when the gradation value D designates a gradation other than the lowest gradation, the driving transistor TDR maintains the ON state at the end point of the operation period PA. A specific method for setting the time length T will be described later.

[4] Driving period PDR (FIG. 7)
When the operation period PA in the writing period PWR ends, the control signal GT [j] changes to the inactive level, so that the control switch TCR1 changes to the off state. Therefore, the gate of the drive transistor TDR is disconnected from the signal line 14 and is in an electrically floating state. That is, the supply of potential to the gate of the drive transistor TDR is stopped. When the driving transistor TDR is in an ON state at the end point of the operation period PA (that is, when the gradation value D specifies a gradation other than the lowest gradation), the expression (3) continues even after the operation period PA elapses. When the current Ids flows between the drain and source of the driving transistor TDR, the capacitor C2 is charged. Therefore, as shown in FIG. 3, while the voltage VGS of the driving transistor TDR is maintained at the voltage VGS3 at the end of the operation period PA, the voltage across the capacitor C2 (the source potential VS of the driving transistor TDR) gradually increases. To increase. When the voltage across the capacitor C2 reaches the threshold voltage VTH_OLED of the light emitting element E, the current Ids flows through the light emitting element E as the drive current IDR. Therefore, the drive current IDR is expressed by the following formula (6).
IDR = 1/2 ・ μ ・ W / L ・ Cox ・ (VGS3−VTH) ²
= 1/2 · μ · W / L · Cox · {(VIN + VTH−ΔV) −VTH} ²
＝ K ・ （VIN－ΔV） ² …… (6)
K = 1/2 ・ μ ・ W / L ・ Cox

  The supply of the driving current IDR to the light emitting element E is continued from the time when the voltage across the capacitor C2 reaches the threshold voltage VTH_OLED of the light emitting element E after the start of the driving period PDR, and the scanning signal GA [i] is next supplied. It ends at the start point of the horizontal scanning period H [i] at which the active level is reached. As described above, since the drive current IDR depends on the voltage VGS3 reflecting the gradation potential VDATA [i], the light emitting element E has a luminance corresponding to the gradation potential VDATA [i] (that is, the gradation value D). Emits light.

  In FIG. 3, the time when the voltage across the capacitor C2 reaches the threshold voltage VTH_OLED of the light emitting element E (that is, when the rise of the gate potential VG and the source potential VS of the drive transistor TDR stops). The case where it is within the writing period PWR is illustrated. However, depending on the time length from the end point of the operation period PA to the end point of the write period PWR and the voltage VGS3 at the end point of the operation period PA, the voltage across the capacitor C2 reaches the threshold voltage VTH_OLED after the start of the drive period PDR. There is also a case.

  Since the voltage VGS3 in Equation (5) is a voltage obtained by changing the threshold voltage VTH set in the compensation period PCP according to the gradation potential VDATA [i], the drive current IDR is expressed as shown in Equation (6). It does not depend on the threshold voltage VTH. Therefore, even when there is an error in the threshold voltage VTH of the drive transistor TDR of each pixel circuit U, the drive current IDR is set to a target value corresponding to the gradation potential VDATA. That is, the error of the drive current IDR caused by the threshold voltage VTH of the drive transistor TDR of each pixel circuit U is compensated by the first compensation operation in the compensation period PCP.

  In addition, the voltage ΔV (the amount of change in the voltage VGS between the gate and the source of the driving transistor TDR due to the second compensation operation) in Expression (6) depends on the mobility μ of the driving transistor TDR. More specifically, the voltage ΔV increases as the mobility μ of the drive transistor TDR increases. As described above, the mobility μ of the drive transistor TDR is reflected in the drive current IDR in the second compensation operation. Therefore, the error of the drive current IDR caused by the mobility μ of the drive transistor TDR is represented by the writing period PWR (operation period It is possible to compensate by the second compensation operation in PA).

  However, under the configuration in which the time length T of the second compensation operation is fixed to a predetermined value that does not depend on the gradation value D (hereinafter referred to as “proportional”), as described below, the movement of the drive transistor TDR There is a problem that the error of the degree μ can be effectively compensated only when a specific gradation value D (gradation potential VDATA) is designated.

  FIG. 8 is a graph showing the correlation between the gradation potential VDATA and the error in the current amount of the driving current IDR in the comparative example. The horizontal axis in FIG. 8 represents the voltage value of the gradation potential VDATA with the reference potential VREF as the reference value (0.0), and the vertical axis in FIG. 8 represents the drive current when the predetermined gradation value D is designated. It means the relative ratio (maximum error ratio) between the maximum value and the minimum value of the current amount of IDR. As can be understood from FIG. 8, when the time length T of the second compensation operation is a fixed value, the error of the drive current IDR is surely reduced when the gradation potential VDATA is set to the predetermined value VD0. However, the error of the drive current IDR increases as the gradation potential VDATA is separated from the predetermined value VD0. That is, in contrast, there is a problem that it is difficult to suppress the error of the drive current IDR caused by the mobility μ of the drive transistor TDR over a wide range of the gradation potential VDATA.

  On the other hand, FIG. 9 shows the relationship between the time length T of the operation period PA and the error (maximum error ratio) of the drive current IDR in the case where the gradation potential VDATA is changed (VD1 <VD2 <VD3 <VD4 <VD5). ). It can be seen from FIG. 9 that the time length T at which the error of the drive current IDR is minimized differs depending on the gradation potential VDATA. That is, the higher the gradation potential VDATA, the shorter the time length T at which the error of the drive current IDR is minimized. From the above knowledge, in this embodiment, the drive current IDR is set regardless of the level of the gradation potential VDATA by variably setting the time length T of the operation period PA according to the gradation value D (gradation potential VDATA). Suppress errors. For example, when the gradation potential VDATA is set to the potential VD1 in FIG. 9, the time length T is set to the predetermined value T1, and when the gradation potential VDATA is set to the potential VD2 higher than the potential VD1, the time is set. For example, the length T is set to a predetermined value T2 (T2 <T1).

Next, the second compensation operation within the operation period PA will be examined in detail. Between the current Ids flowing between the drain and source of the drive transistor TDR during execution of the second compensation operation and the capacitance value of the capacitors (holding capacitor C1 and capacitor C2) charged by the current Ids, the following formula ( The relationship of 7) is established. C in Expression (7) is the sum of the capacitance values of the storage capacitor C1 and the capacitor C2 (C = cp1 + cp2).
Ids = dQ / dt = C · (dVS / dt) (7)
Considering that the temporal change of the source potential VS of the driving transistor TDR is equivalent to the temporal change of the voltage ΔV (dVS / dt = dΔV / dt), the equations (6) and (7) From the above, the following formula (8) is derived. Note that the voltage ΔV (t) in the equation (8) means that the voltage ΔV in the equation (6) changes according to the time t elapsed from the start of the second compensation operation (starting point of the operation period PA).
C (dΔV / dt) = K (VIN−ΔV (t)) ² (8)

When Equation (8) is integrated under the condition that the voltage ΔV (t) (ΔV (0)) is zero at the start point (t = 0) of the operation period PA, the end point (t = T) of the operation period PA The following equation (9) representing the drain-source current Ids (T) of the driving transistor TDR in FIG.

Since the coefficient K in Equation (9) includes the mobility μ of the drive transistor TDR as described in Equation (6), it corresponds to an index representing the degree of error in the mobility μ. Since the drive current IDR supplied to the light emitting element E in the drive period PDR depends on the current Ids (T) of the equation (9), in order to minimize the error of the drive current IDR, the coefficient K (mobility μ ) To minimize the error in the current Ids (T). The error of the current Ids (T) is minimized with respect to the fluctuation of the coefficient K when the result obtained by differentiating the equation (9) by the coefficient K is zero. Equation (10) is derived from the above conditions.

Accordingly, the condition that maximizes the effect of the compensation of the drive current IDR by the second compensation operation is expressed by the following formula (11).
C = KVINT (11)
Since the voltage VIN in the equation (11) is set according to the gradation potential VDATA, the same conditions (scales) as those described with reference to FIG. 9 regarding the gradation potential VDATA and the time length T of the operation period PA. (The time length T is shortened as the adjustment potential VDATA is higher). More specifically, when the multiplication value of the voltage VIN and the time length T of the operation period PA (or the multiplication value of the gradation potential VDATA and the time length T) becomes a predetermined value, the driving current IDR by the second compensation operation is obtained. The effect of compensation is maximized.

  From the above knowledge described with reference to FIG. 9 and Equation (11), in this embodiment, the relationship between the gradation potential VDATA and the time length T is set as shown in FIG. As shown in FIG. 10, the time length T of the operation period PA is shorter as the gradation potential VDATA is higher (the amount of change VIN of the gate-source voltage VGS of the driving transistor TDR due to the supply of the gradation potential VDATA is higher). Set to time. More specifically, as can be understood from Equation (11), the multiplication value of the gradation potential VDATA (voltage VIN) and the time length T becomes a predetermined value (the time length T is inversely proportional to the gradation potential VDATA. Time length T is set as follows. For example, the time length T corresponding to each of a plurality of types of gradation potential VDATA reduces the error of the drive current IDR set according to the gradation potential VDATA to, for example, 1% or less (ideally minimized). To be set.

  However, since the time length T for minimizing the error of the driving current IDR is longer as the gradation potential VDATA is lower, the driving is performed even when the gradation potential VDATA is sufficiently low (for example, when the lowest gradation is designated). In order to strictly minimize the error of the current IDR, it is necessary to excessively lengthen the time length T. Therefore, as shown in FIG. 10, the signal line driving circuit 34 according to the present embodiment operates when the gradation value D lower than the predetermined value is designated (when the gradation potential VDATA is lower than the potential VD_th in FIG. 10). The time length T of PA is set (clipped) to a predetermined value Tmax that does not depend on the gradation value D. The maximum value Tmax is limited to a time shorter than the time length required for the voltage VGS of the driving transistor TDR to drop to the threshold voltage VTH in the second compensation operation. According to the above configuration, the operation period PA can be shortened.

  As described with reference to FIG. 3, the operation period PA in the writing period PWR ends when the control switch TCR1 changes from the on state to the off state. Therefore, each unit circuit 40 of the signal line driving circuit 34 adjusts the time point when the control signal GT [j] is changed from the active level to the inactive level in each writing period PWR according to the gradation value D. The time length T of the operation period PA is set variably. Therefore, as a circuit for generating the control signal GT [j] in the unit circuit 40, the control signal GT [j] is shifted to the active level at the start point of the operation period PA and counting is started. A counting circuit that transitions the control signal GT [j] to the inactive level when the numerical value corresponding to the value D is reached (when the time length T has elapsed from the start of counting) is preferably used.

  FIG. 11 is a graph showing the relationship (solid line) between the gradation potential VDATA and the error of the drive current IDR in this embodiment. In FIG. 11, the correlation (FIG. 8) between the grayscale potential VDATA and the error of the drive current IDR in the proportional proportion is also shown by a broken line. As shown in FIG. 11, according to the present embodiment, the time length T of the second compensation operation is compared with the fixed proportionality (for example, Patent Document 1) regardless of the gradation value D. There is an advantage that the error of the drive current IDR is suppressed to 1% or less over a wide range.

  In FIG. 11, the slight increase in the error of the drive current IDR in the lower region of the gradation potential VDATA is considered to be the effect of limiting the upper limit of the time length T to the maximum value Tmax. However, it is clear from FIG. 11 that the error of the drive current IDR is greatly improved compared to the proportionality even though the error of the drive current IDR increases on the lower side.

  FIG. 12 is a graph showing the relationship between the gradation value D and the drive current IDR when the time length T of the operation period PA is set as shown in FIG. By setting the time length T so that the multiplication value of the gradation potential VDATA and the time length T becomes a predetermined value, the drive current IDR (and the luminance of the light emitting element E) is increased to the 2.2th power of the gradation value D. The current is adjusted to the corresponding amount. That is, there is an advantage that a gamma characteristic with a gamma value of 2.2 is realized by setting the time length T.

The current Ids (drive current IDR) when the condition of Expression (11) is satisfied is expressed by the following Expression (12). That is, the current Ids depends on the capacitance value C (C = cp1 + cp2), the voltage VIN, and the time length T.
Ids = CVIN / 4T (12)
Therefore, in order to secure a sufficient amount of current for the driving current IDR to such an extent that the image displayed on the element unit 10 has the desired brightness, it is necessary to increase the capacitance value C or the voltage VIN or shorten the time length T. It is. However, in order to increase the capacitance value C, it is necessary to increase the area of the storage capacitor C1, and there is a problem that the arrangement (layout) of other elements of the pixel circuit U is restricted. Further, in order to increase the voltage VIN, it is necessary to increase the amplitude of the potential of the gate of the selection switch TSL. Therefore, it is necessary to increase the breakdown voltage of the scanning line driving circuit 32. In this embodiment, since the drive current Ids is adjusted according to the time length T of the operation period PA, there is an advantage that a problem as in the case where the capacitance value C and the voltage VIN are increased does not occur.

  By the way, when the load (number of pixel circuits U) associated with the control line 24 for supplying the control signal GT [j] is large, the distortion of the waveform of the control signal GT [j] becomes obvious. In particular, when the pulse width (time length T) of [j] is short, there is a problem that the control accuracy of the time length T of the operation period PA is lowered. On the other hand, for example, in a configuration in which the pixel circuits U corresponding to each of a plurality of display colors (for example, red, green, and blue) are arranged in the X direction, the number of columns n (signal lines 14) of the pixel circuits U in the element unit 10 is determined. In many cases) exceeds the number of rows m (total number of scanning lines 12). In the present embodiment in which the control line 24 extends in the Y direction together with the signal line 14, the total number m of pixel circuits U serving as a load for one control line 24 is less than the total number n of pixel circuits U in one row. Compared with the configuration in which n pixel circuits U arranged in the X direction share one control line 24 in the X direction, the load on the control line 24 is reduced. Therefore, the pulse width (time length T) of the control signal GT [j] is sufficiently shortened while suppressing a decrease in accuracy of adjusting the time length T of the operation period PA (waveform distortion of the control signal GT [j]). There is also an advantage that a desired drive current IDR can be generated.

  In order to initialize the voltage VGS of the driving transistor TDR and supply the reference potential VREF for the first compensation operation to each pixel circuit U, the selection switch TSL is controlled to be in the ON state in the initialization period PRS and the compensation period PCP. In addition, a configuration in which the reference potential VREF is supplied to each pixel circuit U as the signal S [j] of the signal line 14 is also assumed. However, in the configuration in which one signal line 14 is used for both the supply of the gradation potential VDATA and the supply of the reference potential VREF as described above, during the horizontal scanning period H [i] in which the selection switch TSL is controlled to be on. Thus, it is necessary to initialize the voltage VGS and execute the first compensation operation. Therefore, in order to ensure that the gate-source voltage VGS of the driving transistor TDR reaches the threshold voltage VTH by the first compensation operation, it is necessary to sufficiently secure the time length of the horizontal scanning period H [i]. However, there is a problem that as the horizontal scanning period H [i] becomes longer, higher definition (increase in the number of rows) of the pixel circuit U is restricted.

  In this embodiment, since the reference potential VREF is supplied to each pixel circuit U from the power supply line 28 separate from the signal line 14, the first compensation operation is executed regardless of the time length of one horizontal scanning period H. Is possible. For example, as shown in FIG. 3, a plurality of horizontal scanning periods H are secured for the first compensation operation. Therefore, there is an advantage that both the certainty of the first compensation operation (accuracy that the voltage VGS reaches the threshold voltage VTH) and the shortening of the horizontal scanning period H (and higher definition of the pixel circuit U) can be achieved.

<B: Modification>
Each of the above forms is variously modified. Specific modes of deformation for each form are exemplified below. Two or more aspects may be arbitrarily selected from the following examples and combined.

(1) Modification 1
The conductivity type of each transistor (driving transistor TDR, selection switch TSL, control switch TCR1, control switch TCR2) constituting the pixel circuit U is arbitrary. For example, as shown in FIG. 13, a configuration in which the drive transistor TDR and each switch (selection switch TSL, control switch TCR1, control switch TCR2) are P-channel type is also employed. In the pixel circuit U of FIG. 13, the anode of the light emitting element E is connected to the power supply line 18 (potential VCT), the drain of the drive transistor TDR is connected to the power supply line 16 (potential VEL [i]), and the source emits light. Connected to the cathode of element E. A configuration in which the holding capacitor C1 is interposed between the gate and the source of the driving transistor TDR, a configuration in which the selection switch TSL and the control switch TCR1 are interposed in series between the gate of the driving transistor TDR and the signal line 14, and a driving transistor The configuration in which the control switch TCR2 is interposed between the gate of the TDR and the feeder line 28 is the same as in FIG. As described above, when the P-channel type drive transistor TDR is adopted, the voltage relationship (high and low) is reversed as compared with the case where the N-channel type drive transistor TDR is adopted. Therefore, the description of the specific operation is omitted.

(2) Modification 2
The relationship between the write period PWR and the operation period PA is changed as appropriate. For example, a configuration in which the time length T is variably controlled by moving the end point of the operation period PA starting from the start point of the write period PWR back and forth on the time axis, or the operation period PA that ends at the end point of the write period PWR. A configuration is adopted in which the time length T is variably controlled by moving the start point back and forth on the time axis. Further, the operation period PA is set so that the midpoint of the writing period PWR and the midpoint of the operation period PA coincide with each other, and both the start point and the end point of the operation period PA are moved back and forth on the time axis. A configuration is also employed that variably controls.

(3) Modification 3
In each of the above embodiments, the capacitor C2 associated with the light emitting element E is used. However, as shown in FIG. 14, a configuration in which a capacitor CX formed separately from the light emitting element E is used together with the capacitor C2. The electrode e1 of the capacitor CX is connected to a path connecting the drive transistor TDR and the light emitting element E (source of the drive transistor TDR). The electrode e2 of the capacitor CX is connected to a wiring to which a predetermined potential is supplied (for example, the power supply line 18 to which the potential VCT is supplied and the power supply line 28 to which the reference potential VREF is supplied). In the configuration of FIG. 14, the capacitance value cp2 is the total value of the capacitance CX and the capacitance C2 of the light emitting element E. Therefore, the voltage VGS2 of the formula (4) and the voltage VGS3 of the formula (5) (and the driving current IDR of the formula (6)) can be appropriately adjusted according to the capacitance CX.

(4) Modification 4
The period during which the gradation potential VDATA is supplied to the signal line 14 does not necessarily coincide with the writing period PWR in which the selection switch TSL is controlled to be on. For example, a configuration in which a part of a period during which the gradation potential VDATA is supplied to the signal line 14 is set as the writing period PWR and the selection switch TSL is turned on is also employed.

(5) Modification 5
In the above embodiment, both the first compensation operation and the second compensation operation are executed. However, for example, if the error of the drive current IDR is suppressed within a predetermined range only by the second compensation operation, the first compensation operation is performed. Is omitted. That is, the intended effect of the present invention to suppress the error of the drive current IDR for a plurality of gradation values D is that the time length T of the second compensation operation (more specifically, both the selection switch TSL and the control switch TCR1 are The first compensation operation is not an essential requirement for the present invention.

(6) Modification 6
An organic EL element is only an example of a light emitting element. For example, the present invention is applied to a light-emitting device in which light-emitting elements such as inorganic EL elements and LED (Light Emitting Diode) elements are arranged as in the above embodiments. The light-emitting element in the present invention is a current-driven driven element that is driven by supply of current (typically, gradation (brightness) is controlled).

<C: Application example>
Next, an electronic apparatus using the light emitting device 100 according to each of the above aspects will be described. 15 to 17 show forms of electronic devices that employ the light emitting device 100 as a display device.

  FIG. 15 is a perspective view illustrating a configuration of a mobile personal computer employing the light emitting device 100. The personal computer 2000 includes a light emitting device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. Since the light emitting device 100 uses an organic EL element as the light emitting element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 16 is a perspective view illustrating a configuration of a mobile phone to which the light emitting device 100 is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the light emitting device 100 is scrolled.

  FIG. 17 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the light emitting device 100 is applied. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device 100 that displays various images. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device 100.

  Note that examples of electronic devices to which the light-emitting device according to the present invention is applied include the digital still camera, television, video camera, car navigation device, pager, electronic notebook, electronic paper, in addition to the devices illustrated in FIGS. Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like. Further, the use of the light emitting device according to the present invention is not limited to the display of images. For example, the light emitting device of the present invention is also used as an exposure device for forming a latent image on a photosensitive drum by exposure in an electrophotographic image forming device.

1 is a block diagram of a light emitting device according to an embodiment of the present invention. It is a circuit diagram of a pixel circuit. It is a timing chart of operation of a light emitting device. It is a circuit diagram which shows the mode of the pixel circuit in an initialization period. It is a circuit diagram which shows the mode of the pixel circuit in a compensation period. It is a circuit diagram which shows the mode of the pixel circuit immediately after the start of the operation period in a writing period. It is a circuit diagram which shows the mode of the pixel circuit in a drive period. It is a graph which shows the correlation with the error of the gradation electric potential and drive current in contrast. It is a graph which shows the correlation with the time length of an operation period, and the error of a drive current. It is a graph which shows the correlation with a gradation potential and the time length of an operation period. It is a graph for demonstrating the effect of embodiment. It is a graph which shows the correlation with a gradation value and a drive current. It is a circuit diagram of a pixel circuit according to a modification. It is a partial circuit diagram of the pixel circuit which concerns on a modification. It is a perspective view of an electronic device (personal computer). It is a perspective view of an electronic device (cellular phone). It is a perspective view of an electronic device (personal digital assistant).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Light-emitting device, 10 ... Element part, 12 ... Scanning line, 14 ... Signal line, 16 ... Feed line, 22, 24 ... Control line, 28 ... Feed line, 30 ... Drive circuit, 32... Scanning line drive circuit 34... Signal line drive circuit 36... Potential control circuit 40... Unit circuit U. Pixel circuit TDR ... Drive transistor TSL ... Select switch TCR 1, TCR 2 …… Control switch, E …… Light emitting element, H (H [i]) …… Horizontal scanning period, PRS …… Initialization period, PCP …… Compensation period, PWR …… Writing period, PA …… Operating period, PDR: drive period, VDATA: gradation potential.

Claims (9)

A light emitting element and a driving transistor connected in series with each other; a storage capacitor interposed between a path between the light emitting element and the driving transistor and a gate of the driving transistor; and a gate and a signal line of the driving transistor A pixel circuit including a selection switch and a first control switch connected in series with each other, comprising:
In the compensation period, the voltage across the storage capacitor is asymptotic to the threshold voltage of the drive transistor,
In a writing period after the compensation period has elapsed, a gradation potential corresponding to a gradation value designated for the pixel circuit is supplied to the signal line, and the selection switch is controlled to be turned on, and the writing period The first control switch is controlled to be in an ON state during an operation period that is variably set according to the gradation value, so that the gate potential of the driving transistor depends on the gradation potential. And changing the voltage across the holding capacitor asymptotically to the threshold voltage of the driving transistor,
In the driving period after the lapse of the writing period, the driving current corresponding to the voltage across the storage capacitor is supplied to the light emitting element by stopping the supply of the potential to the gate of the driving transistor. Driving method. The gradation value designated for the pixel circuit is such that the time length of the operation period becomes shorter as the amount of change in the voltage across the storage capacitor when the gradation potential is supplied in the writing period is larger. The driving method of the pixel circuit according to claim 1, wherein the time length of the operation period is variably set according to. The pixel circuit is designated so that a multiplication value of the amount of change in voltage across the storage capacitor when the gradation potential is supplied in the writing period and the time length of the operation period approaches a predetermined value. The pixel circuit driving method according to claim 2, wherein the time length of the operation period is variably set in accordance with the gradation value. 4. The pixel circuit driving method according to claim 1, wherein a reference potential is supplied to a gate of the driving transistor from a power supply line different from the signal line in the compensation period. 5. A light emitting element and a driving transistor connected in series with each other; a storage capacitor interposed between a path between the light emitting element and the driving transistor and a gate of the driving transistor; and a gate and a signal line of the driving transistor A pixel circuit including a selection switch and a first control switch connected in series between
A drive circuit for driving the pixel circuit,
The drive circuit is
In the compensation period, the voltage across the storage capacitor is asymptotic to the threshold voltage of the drive transistor,
In a writing period after the compensation period has elapsed, a gradation potential corresponding to a gradation value designated for the pixel circuit is supplied to the signal line, and the selection switch is controlled to be turned on, and the writing period The gate of the driving transistor is changed according to the gradation potential by controlling the first control switch to be in an ON state during an operation period variably set according to the gradation value. And the voltage across the holding capacitor asymptotically approaches the threshold voltage of the driving transistor,
A light-emitting device that supplies a drive current corresponding to a voltage across the storage capacitor to the light-emitting element by stopping the supply of a potential to the gate of the drive transistor in a drive period after the writing period has elapsed. The pixel circuit includes a second control switch interposed between a gate of the driving transistor and a power supply line to which a reference potential is supplied,
The light-emitting device according to claim 5, wherein the driving circuit controls the second control switch to an on state during the compensation period and controls the second control switch to an off state during the writing period. A light emitting element and a driving transistor connected in series with each other;
A storage capacitor interposed between a path between the light emitting element and the driving transistor and a gate of the driving transistor;
A signal line to which a gradation potential corresponding to a gradation value is supplied;
A selection switch and a first control switch connected in series between the gate of the driving transistor and the signal line;
A scanning line to which a scanning signal for controlling the selection switch is supplied;
A control line to which a control signal for controlling the first control switch is supplied;
The scanning signal is supplied to the scanning line so that the selection switch is turned on in at least the writing period of the period in which the gradation potential is supplied to the signal line, and the first of the writing period is supplied. 1. A light-emitting device comprising: a drive circuit that supplies the control signal to the control line so that an operation period in which one control switch is turned on has a time length variably set according to the gradation value. The light emitting device according to claim 7, wherein the signal line and the control line extend in a direction crossing a direction in which the scanning line extends. An electronic apparatus comprising the light-emitting device according to claim 5.

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