CN112753064B

CN112753064B - Display device

Info

Publication number: CN112753064B
Application number: CN201880097978.0A
Authority: CN
Inventors: 冈部达; 家根田刚士
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2023-08-01
Anticipated expiration: 2038-09-28
Also published as: US11335237B2; WO2020065961A1; CN112753064A; US20210343226A1

Abstract

A pixel circuit including a driving transistor (T1) and a capacitor (Cp) electrically connected to a control terminal of the driving transistor; a light emitting Element (ES); a first power supply voltage line (PF (n)) crossing the data signal line (SL (m)); and a second power supply voltage line (PS (m)) electrically connected to the control terminal via a capacitor, wherein the first power supply voltage line is not conductive to the second conductive terminal of the driving transistor during a writing period in which the scanning signal line (GL (n)) is activated, and the first power supply voltage line is conductive to the second conductive terminal of the driving transistor during a light emission period of the light emitting element.

Description

Display device

Technical Field

The present invention relates to a display device.

Background

Patent document 1 discloses a pixel circuit of a display device including a light emitting diode.

Prior art literature

Patent literature

Patent document 1: japanese laid-open patent publication No. 2014-109707 (12 days of 2014, 6 month) "

Disclosure of Invention

The invention aims to solve the technical problems

In the configuration of patent document 1, when a data signal is written into a pixel circuit, the potential of the power supply line fluctuates according to parasitic capacitance formed at the intersection of the power supply line and the data signal line that supplies power to the pixel circuit, and the written data signal may fluctuate (be pushed up or pulled down) until the light emission period.

Technical scheme for solving technical problems

The display device includes: a plurality of scanning signal lines; a plurality of light emission control lines; a plurality of first power supply voltage lines; a plurality of initialization power lines; a plurality of data signal lines; and a plurality of second power supply voltage lines, the plurality of scan signal lines, the plurality of light emission control lines, the plurality of first power supply voltage lines, and the plurality of initialization power supply lines extending in parallel and intersecting the plurality of data signal lines and the plurality of second power supply voltage lines extending in parallel, respectively, a plurality of sub-pixels composed of pixel circuits and light emitting elements being provided corresponding to a plurality of intersections of the plurality of scan signal lines and the plurality of data signal lines, the light emitting elements including a first electrode; a light emitting layer; and a second electrode common to the plurality of sub-pixels, the pixel circuit including a driving transistor, a threshold compensation transistor, a power supply connection transistor, a writing transistor, and a capacitor, one electrode of the capacitor being electrically connected to a control terminal of the driving transistor, the other electrode of the capacitor being electrically connected to the second power supply voltage line, a first conduction terminal of the power supply connection transistor being electrically connected to a first power supply voltage line, a conduction voltage being input to a corresponding scanning signal line during a writing period of the pixel circuit, a data signal being input to the capacitor from a corresponding data signal line via the writing transistor and the threshold compensation transistor, and the other electrode of the capacitor not being in conduction with the first power supply voltage line, a conduction voltage being input to a corresponding light emission control line during light emission of the light emitting element, the other electrode of the capacitor being in conduction with the first power supply voltage line via the power supply connection transistor during at least a part of the light emission period.

Advantageous effects

According to one aspect of the present invention, the possibility of fluctuation of the written data signal during the light emission period can be reduced.

Drawings

Fig. 1 is a schematic plan view of the structure of a display device of a first embodiment.

Fig. 2 (a) is a schematic cross-sectional view showing the structure of the display device of the first embodiment, and (b) is a cross-sectional view including a data signal line and a first power supply voltage line.

Fig. 3 (a) is a circuit diagram showing the configuration of the sub-pixel according to the first embodiment, and (b) is a flowchart showing the operation of the sub-pixel.

Fig. 4 is a circuit diagram showing a structure of a conventional pixel circuit.

Fig. 5 (a) is a flowchart illustrating a problem of a conventional pixel circuit, and (b) is a schematic plan view showing an example of a display pattern.

Fig. 6 (a) is a flowchart illustrating the effect of the first embodiment, and (b) is a schematic plan view showing an example of a display pattern.

Fig. 7 (a) is a circuit diagram showing another configuration of the sub-pixel according to the first embodiment, and (b) is a flowchart showing the operation of the sub-pixel.

Fig. 8 (a) is a circuit diagram showing still another configuration of the sub-pixel according to the first embodiment, and (b) is a flowchart showing an operation of the sub-pixel.

Fig. 9 (a) is a circuit diagram showing the configuration of a sub-pixel according to the second embodiment, and (b) is a flowchart showing the operation of the sub-pixel.

Fig. 10 (a) is a circuit diagram showing the configuration of a sub-pixel according to the third embodiment, and (b) is a flowchart showing the operation of the sub-pixel.

Fig. 11 is a schematic plan view of the structure of a display device of the fourth embodiment.

Detailed Description

Fig. 1 (a) is a schematic plan view showing the structure of the display device. Hereinafter, K and L are integers of 2 or more, m is an integer of 1 or more and K or less, and n is an integer of 1 or more and L or less. As shown in fig. 1, the display device 2 includes a display area DA and a frame area NA surrounding the display area DA. The display area DA includes sub-pixels PX (at the m-th row and m-th column) including light emitting elements ES and pixel circuits PC; a scanning signal line GL (n), a light emission control line EM (n), a first power supply voltage line PF (n), and an initialization power supply line Pi (n) which are electrically connected to the pixel circuit PC and extend in the X direction; and a data signal line SL (m) and a second power supply voltage line PS (m) which are electrically connected to the pixel circuit PC and extend in the Y direction (orthogonal to the X direction). The sub-pixel PX is disposed at an intersection of the data signal line SL (m) corresponding to the scanning signal line GL (n), and the data signal line SL (m) and the first power supply voltage line PF (n) intersect.

In addition, the scan signal line, the light emission control line, the first power supply voltage line PF, and the initialization power supply line are provided with K numbers, the data signal line and the second power supply voltage line are provided with L numbers, respectively, and the sub-pixels are provided with k×l numbers. The X direction is also referred to as the row direction, and the Y direction is referred to as the column direction.

The frame area NA is provided with driving circuits DRa and DRb and a terminal portion TS disposed on both sides of the display area DA. The external substrate is mounted on the terminal portion TS.

First embodiment

Fig. 2 (a) is a schematic cross-sectional view showing the structure of the display device of the first embodiment, and fig. 2 (b) is a cross-sectional view including a data signal line and a first power supply voltage line. As shown in fig. 2 (a), the display device 2 is formed by stacking a barrier layer 3, a TFT layer 4, a light-emitting element layer 5, a sealing layer 6, and a functional thin film 39 in this order on a substrate 12. The laminate of the base material 12, the barrier layer 3, the TFT layer 4, the light-emitting element layer 5, and the sealing layer 6 may be formed on a support substrate, and then the laminate may be peeled off from the support substrate, and a lower surface film may be attached to the peeled surface.

As the base material 12, a glass substrate or a flexible resin substrate (for example, a polyimide substrate) can be used. The barrier layer 3 is a layer that prevents penetration of foreign matter such as water, oxygen, and free ions into the TFT layer 4 and the light-emitting element layer 5, and is formed of, for example, a silicon oxide film or a silicon nitride film formed by a CVD method, or a laminated film thereof.

The TFT layer 4 is formed by stacking a semiconductor layer 15, a lower inorganic insulating layer 16, a first metal layer LM, a first inorganic insulating layer 18, a second metal layer MM, a second inorganic insulating layer 20, a third metal layer HM, and a planarization layer 21 in this order.

The first metal layer LM includes a scan signal line GL (n) and a light emission control line EM (n), the second metal layer MM includes a first power supply voltage line PF (n) and an initialization power supply line Pi (n), and the third metal layer HM includes a data signal line SL (m) and a second power supply voltage line PS (m). The term "including" as used herein means that the scanning signal line GL (n) and the emission control line EM (n) are formed by the same process as the film formation and patterning of the first metal layer LM, for example.

As shown in fig. 2 (b), the first power supply voltage line PF (n) overlaps the data signal line SL (m) and the second power supply voltage line PS (m) with the second inorganic insulating layer 20 interposed therebetween. In particular, the first power supply voltage line PF (n) and the second power supply voltage line PS (m) are not electrically connected at the intersection of the two (the second inorganic insulating layer 20 is not provided with a contact hole at the intersection of the two).

The semiconductor layer 15 may use amorphous silicon, low Temperature Polysilicon (LTPS). Each metal layer is composed of, for example, a single-layer metal film or a multi-layer metal film containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. The lower inorganic insulating layer 16, the first inorganic insulating layer 18, and the second inorganic insulating layer 20 are formed of, for example, a silicon oxide film or a silicon nitride film formed by a CVD method, or a laminated film thereof. The planarizing layer 21 (interlayer insulating film) is made of an organic material that can be coated, such as polyimide or acrylic, having a planarizing effect.

The light-emitting element layer 5 is formed by sequentially stacking a first electrode (anode 22), an edge cover (partition wall) 23 covering the edge of the anode 22, an EL (electroluminescence) layer 24 (including a light-emitting layer), and a second electrode (cathode 25). That is, the light emitting element ES includes a first electrode, a light emitting layer, and a second electrode common to a plurality of sub-pixels from the substrate side. Here, the first electrode is an electrode on the TFT layer side, and the second electrode is an electrode shared by a plurality of sub-pixels on an upper layer than the first electrode. In the present embodiment, the first electrode is the anode 22 and the second electrode is the cathode 25, but as shown in the following embodiments, the first electrode may be the cathode and the second electrode may be the anode. The edge cover 23 is made of, for example, an organic material such as polyimide or acrylic that can be applied, and the anode 22 is exposed at the opening of the edge cover 23. The anode 22 is a pixel electrode, and the cathode 25 is a common electrode common to a plurality of pixels.

The sub-pixel PX is provided with a self-luminous light emitting element ES (e.g., OLED: organic light emitting diode, QLED: quantum dot light emitting diode) including an anode 22, an EL layer 24, and a cathode 25. The light emitting element ES is driven by various wirings (scanning signal line GL (n), data signal line SL (m), light emission control line EM (n), etc.) formed on the upper layer of the TFT layer 4 and the pixel circuit PC, and the current between the anode and the cathode is set to a value corresponding to the data signal (gradation signal).

The EL layer 24 (also referred to as an active layer or a functional layer) is formed by stacking, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in this order. The light-emitting layer is formed by vapor deposition, ink jet, or the like so as to overlap with the opening of the edge cover 23 defining the light-emitting region. One or more layers selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer may not be formed.

In the case of forming a light emitting layer of an OLED by vapor deposition, an FMM (fine metal mask) is used. The FMM is a sheet material (for example, made of invar material) having a plurality of through holes, and an island-like light emitting layer (corresponding to one light emitting element ES) is formed of an organic substance passing through one through hole.

For the light-emitting layer of the QLED, for example, a solvent that diffuses quantum dots by inkjet coating, or a quantum dot layer coated using a coater is patterned by photolithography, an island-shaped light-emitting layer (corresponding to one light-emitting element ES) can be formed.

The anode 22 is formed by stacking ITO (indium tin oxide) and Ag (silver) or an alloy containing Ag, for example, and has light reflectivity. The cathode 25 may be made of a light-transmitting conductive material such as MgAg alloy (extremely thin film), ITO, or IZO (indium zinc oxide).

In the case where the light emitting element ES is an OLED, holes and electrons are recombined in the light emitting layer by a current between the anode 22 and the cathode 25, and light is emitted in the process of migration of excitons thus generated to a base state. Since the cathode 25 is light-transmissive and the anode 22 is light-reflective, light emitted from the EL layer 24 is directed upward and emits light as top light.

In the case where the light emitting element ES is a QLED, holes and electrons are recombined in the light emitting layer by a current between the anode 22 and the cathode 25, and excitons generated thereby emit light (fluorescence) in the process of transition from the conduction band level (conduction band) of the quantum dot to the valence band level (valence band).

In the light-emitting element layer 5, a light-emitting element (an inorganic light-emitting diode or the like) other than the OLED or QLED may be formed.

The sealing layer 6 has light transmittance and includes an inorganic sealing film 26 covering the cathode 25, an organic buffer film 27 located above the inorganic sealing film 26, and an inorganic sealing film 28 located above the organic buffer film 27. The sealing layer 6 covering the light emitting element layer 5 prevents penetration of foreign substances such as water, oxygen, free ions, and the like into the light emitting element layer 5.

The inorganic sealing films 26 and 28 are light-transmitting insulating films, and may be formed of, for example, a silicon oxide film or a silicon nitride film formed by a CVD method, or a laminated film thereof. The organic buffer film 27 is a light-transmissive organic film having a planarizing effect, and can be formed by ink-jet coating an organic material that can be coated, such as an acrylic resin.

The functional film 39 has at least one of a protection function, an optical compensation function, and a touch sensor function, for example.

Fig. 3 (a) is a circuit diagram showing the configuration of the sub-pixel (pixel circuit and light emitting element in the nth row and m column) according to the first embodiment, and fig. 3 (b) is a flowchart showing the operation of the display element. "electrically connected" means that conductive materials such as a metal material and a doped semiconductor layer are in a conductive state with each other without passing through a transistor. ON the other hand, "ON" includes a case where transistors are turned ON and are in a conductive state with each other via channels.

The pixel circuit PC of the sub-pixel PX includes a driving transistor T1, a threshold compensation transistor T2, a power supply connection transistor T3, a first initialization transistor T4, a second initialization transistor T5, a writing transistor T6, a power supply transistor T7, a light emission control transistor T8, and a capacitor Cp. Transistor with a high-voltage power supplyIs a P-channel transistor. The first power supply voltage line PF, the second power supply voltage line PS are turned on with the first power supply ELVDD (same power supply), and the cathode (second electrode) is turned on with the second power supply ELVSS lower than the first power supply ELVDD.

The pixel circuit PC (n rows and m columns) will be specifically described with reference to fig. 3 (a).

One electrode of the capacitor Cp is electrically connected to the control terminal of the driving transistor T1, and the other electrode of the capacitor Cp is electrically connected to the second power supply voltage line PS (m).

The first conductive terminal of the driving transistor T1 is electrically connected to the first conductive terminal of the light emission control transistor T8, the second conductive terminal is electrically connected to the second conductive terminal of the writing transistor T6, and the control terminal is electrically connected to the node Nd and one electrode of the capacitor Cp.

The first conductive terminal of the threshold compensation transistor T2 is electrically connected to the first conductive terminal of the driving transistor T1, the second conductive terminal is electrically connected to the control terminal of the driving transistor T1, and the control terminal is electrically connected to the scanning signal line GL (n) of the present stage (this stage means the nth row corresponding to the pixel circuit PC described).

The first conductive terminal of the power supply connection transistor T3 is electrically connected to the first power supply voltage line PF (n), the second conductive terminal is electrically connected to the second power supply voltage line PS (m), and the control terminal is electrically connected to the emission control line EM (n) of the present stage.

The first turn-on terminal of the first initializing transistor T4 is electrically connected to the control terminal of the driving transistor T1, the second turn-on terminal is electrically connected to the initializing power line Pi (n), and the control terminal is electrically connected to the scanning signal line GL (n-1) of the preceding stage (the preceding stage refers to the n-1 th row).

The first conductive terminal of the second initializing transistor T5 is electrically connected to the first conductive terminal of the driving transistor T1, the second conductive terminal is electrically connected to the initializing power line Pi (n), and the control terminal is electrically connected to the scanning signal line GL (n-1) of the preceding stage. The control terminal of the second initializing transistor T5 may be electrically connected to the scanning signal line GL (n) of the present stage.

The first conductive terminal of the write transistor T6 is electrically connected to the corresponding data signal line SL (m), the second conductive terminal is electrically connected to the second conductive terminal of the drive transistor T1, and the control terminal is electrically connected to the scanning signal line GL (n) of the present stage.

The first conductive terminal of the power supply transistor T7 is electrically connected to the second conductive terminal of the driving transistor T1, the second conductive terminal is electrically connected to the second conductive terminal of the driving transistor T1, the first conductive terminal is electrically connected to the second power supply voltage line PS (m), and the control terminal is electrically connected to the emission control line EM (n) of the present stage.

The first conductive terminal of the light emission control transistor T8 is electrically connected to the first conductive terminal of the driving transistor T1, the second conductive terminal is electrically connected to the first electrode (anode) of the light emitting element ES, and the control terminal is electrically connected to the light emission control line EM (n) of the present stage.

In the pixel circuit PC (n rows and m columns), during the period of selecting the scanning signal line GL (n-1) in the preceding stage (the period of low level to be activated), the driving transistor T1, the first initializing transistor T4, and the second initializing transistor T5 are turned ON, and the node Nd and the drain terminal (first ON terminal) of the driving transistor T1 are turned ON with the initializing power supply line Pi (n), and reset to the initializing voltage.

Next, in the selection period (low level period to be activated: write period of the pixel circuit PC) of the scanning signal line GL (n) of the present stage, the power supply connection transistor T3, the first initialization transistor T4, the second initialization transistor T5, the power supply transistor T7, the light emission control transistor T8 are turned OFF, the threshold compensation transistor T2, and the write transistor T6 are turned ON, and the data signal (gradation voltage) from the data signal line SL (m) is set to the node Nd via the write transistor T6, the drive transistor T1, and the threshold compensation transistor T2.

Then, in the selection period (low level period to be activated: light emission period of the light emitting element ES) of the light emission control line EM (n) of the present stage, the power supply transistor T3, the power supply transistor T7, and the light emission control transistor T8 are turned ON, the threshold compensation transistor T2, the first initialization transistor T4, the second initialization transistor T5, and the write transistor T6 are turned OFF, a current corresponding to the voltage set at the node Nd flows through the light emitting element ES, and the light emitting element ES emits light at a luminance corresponding to the data signal.

During the writing period of the pixel circuit PC corresponding to the sub-pixel PX (n rows and m columns), the on voltage is input to the corresponding scanning signal line GL (n), the data is input from the corresponding data signal line SL (m) to the capacitor Cp via the writing transistor T6 and the threshold compensation transistor T2, and the other electrode of the capacitor Cp is not turned on with the first power supply voltage line PF (n).

As shown in fig. 3 (a) and (b), during the light emission period of the light emitting element ES corresponding to the sub-pixel PX (n rows), the on voltage is input to the corresponding light emission control line EM (n), and the other electrode of the capacitor Cp is turned on with the first power supply voltage line PF (n) via the power supply connection transistor T3.

In the present embodiment, the control terminal of the power supply connection transistor T3 is electrically connected to the emission control line EM (n) of the present stage, and therefore, the other electrode of the capacitor Cp is turned on with the first power supply voltage line PF (n) via the power supply connection transistor T3 during the entire emission period. In the modification shown later, an example of a display device is shown in which, during light emission of the light emitting element ES corresponding to the subpixel PX (n-th row), the other electrode of the capacitor is turned on with the first power supply voltage line PF (n) via the power supply connection transistor T3 during at least a part of the light emission period.

Fig. 4 is a circuit diagram showing a configuration of a conventional pixel circuit. Fig. 5 (a) is a flow chart illustrating a problem of a conventional pixel circuit, and fig. 5 (b) is a schematic plan view showing an example of a display mode. As shown in fig. 4 and 5, in the conventional pixel circuit, due to parasitic capacitance between the power supply line PW and the data line Vdata, which supply the power supply voltage (ELVDD) for the pixel circuit, fluctuation occurs in the potential of the power supply line PW when writing a data signal, and the data signal written in the capacitor 122 is different from a desired data signal. Thus, the dark display becomes bright and the outline is blurred. On the other hand, in writing of a subpixel (selection period of Scan (n+k)) which is a boundary from dark display to bright display, the bright display is darkened by parasitic capacitance, and the contour is blurred. This phenomenon is particularly likely to occur when a bright or dark area is displayed in a part of the display area.

Fig. 6 (a) is a flowchart illustrating the effect of the first embodiment, and fig. 6 (b) is a schematic plan view showing an example of a display pattern. In the first embodiment, the power supply connection transistor T3 is provided, one electrode of the capacitor Cp is electrically connected to the node Nd, and the other electrode is electrically connected to the drain terminal of the power supply connection transistor T3, and therefore, the first power supply voltage line PF (n) becomes OFF during writing, and thus is not conductive to the second conductive terminal of the driving transistor T1 and the other electrode of the capacitor Cp, and during light emission after writing, the power supply transistor T7 and the power supply connection transistor T3 become ON, and is conductive to the second conductive terminal of the driving transistor T1 and the other electrode of the capacitor Cp.

As shown in fig. 6 (a), the second power supply voltage line PS (m) is free from coupling (parasitic capacitance) with the data signal line SL (m), and thus is flat. The second power supply voltage line PS (m) is electrically connected to the other electrode of the capacitor Cp at the time of writing, and thus is not affected by the fluctuation of the first power supply voltage line PF (n). Therefore, appropriate display without whitening can be performed during the light emission period.

In addition, in at least a part of the light emission period of the light emitting element ES corresponding to the sub-pixel PX (n rows and m columns), the power supply voltage (ELVDD) is supplied from the first power supply voltage line PF (n) and the second power supply voltage line PS (m) to the second on terminal of the driving transistor T1, respectively, and the current flows to the light emitting element ES via the first power supply voltage line PF (n) and the second power supply voltage line PS (m), so that the driving capability of the light emitting element ES is improved.

In the example shown in fig. 3 b, the control terminal of the power supply connection transistor T3 is electrically connected to the emission control line EM (n) of the current electrode, and therefore, in the entire emission period of the light emitting element ES corresponding to the sub-pixel PX (n rows and m columns), the power supply voltage (ELVDD) is supplied from the first power supply voltage line PF (n) and the second power supply voltage line PS (m) to the second conduction terminal of the driving transistor T1, respectively, and the current flows through the first power supply voltage line PF (n) and the second power supply voltage line PS (m) to the light emitting element ES.

Fig. 7 (a) is a circuit diagram showing a modification of the sub-pixel according to the first embodiment, and fig. 7 (b) is a flowchart showing the operation of the sub-pixel. As shown in fig. 7, the control terminal of the power supply connection transistor T3 is electrically connected to the emission control line EM (n-1) of the preceding stage.

In the light-emitting period in fig. 7 b, the first power supply voltage line PF (n) is turned on with the other electrode of the capacitor Cp and the second conduction terminal of the transistor T1 (the other electrode of the capacitor Cp is turned on with the first power supply voltage line PF (n)) except for the portion of the period KE that is the end period (i.e., at least a portion of the light-emitting period).

Fig. 8 (a) is a circuit diagram showing another modification of the sub-pixel of the first embodiment, and fig. 8 (b) is a flowchart showing the operation of the sub-pixel. As shown in fig. 8, when the ON signal is not input to the light emission control line of the subsequent stage at the time of writing the present stage, the control terminal of the power supply connection transistor T3 may be electrically connected to the light emission control line EM (n+1) of the subsequent stage.

In the light-emitting period of fig. 8 b, the first power supply voltage line PF (n) is turned on with the other electrode of the capacitor Cp and the second conduction terminal of the transistor T1 (the other electrode of the capacitor Cp is turned on with the first power supply voltage line PF (n)) except for the portion KS which becomes the start period (i.e., at least a portion of the light-emitting period).

The embodiment and the modification shown above can be appropriately selected by designing the pixel circuit PC, and the like.

Second embodiment

Fig. 9 (a) is a circuit diagram showing the configuration of a sub-pixel according to the second embodiment, and fig. 9 (b) is a flowchart showing the operation of the sub-pixel. In fig. 3, the other electrode of the capacitor Cp is electrically connected to the first power supply voltage line PF (n) via the power supply connection transistor T3, but is not limited thereto. As shown in fig. 9, the second conductive terminal of the driving transistor T1 may be electrically connected to the first power supply line PF (n) via the power supply connection transistor T3 (the second conductive terminal of the power supply connection transistor T3 is electrically connected to the second conductive terminal of the driving transistor T1).

In the pixel circuit PC (n rows and m columns), during the selection period of the scanning signal line GL (n-1) in the preceding stage, the driving transistor T1, the first initializing transistor T4, and the second initializing transistor T5 are turned ON, and the node Nd and the drain terminal (first ON terminal) of the driving transistor T1 are turned ON with the initializing power supply line Pi (n) and reset to the initializing voltage.

During selection of the scanning signal line GL (n) of the present stage, the power supply connection transistor T3, the first initialization transistor T4, the second initialization transistor T5, the power supply transistor T7, the light emission control transistor T8 are turned OFF and the driving transistor T1, the threshold compensation transistor T2, the writing transistor T6 are turned ON, and the data signal (gradation voltage) from the data signal line SL (m) is set as the node Nd via the writing transistor T6, the driving transistor T1, the threshold compensation transistor T2.

Next, during the selection period of the emission control line EM (n) of the present stage, the power supply transistor T3, the power supply transistor T7, and the emission control transistor T8 are turned ON, the threshold compensation transistor T2, the first initialization transistor T4, the second initialization transistor T5, and the write transistor T6 are turned OFF, a current corresponding to the voltage set at the node Nd flows through the light emitting element ES, and the light emitting element ES emits light at a luminance corresponding to the data signal.

In the first power supply voltage line PF (n), the power supply transistor T7 and the power supply connection transistor T3 are OFF during the writing period, are not electrically connected to the second conduction terminal (source terminal) of the driving transistor T1 and the other electrode of the capacitor Cp, and in the light emission period after the writing period, the power supply transistor T7 and the power supply connection transistor T3 are ON and are electrically connected to the second conduction terminal (source terminal) of the driving transistor T1 and the other electrode of the capacitor Cp.

As in the first embodiment, the control terminal of the power supply connection transistor T3 may be electrically connected to the emission control line EM (n) of the present stage as shown in fig. 9 (b). As described in the first embodiment, the light emission control line EM (n-1) of the front stage may be electrically connected to the light emission control line EM (n+1) of the rear stage.

Third embodiment

Fig. 10 (a) is a circuit diagram showing the configuration of a sub-pixel according to the third embodiment, and fig. 10 (b) is a flowchart showing the operation of the sub-pixel. In this embodiment, the first electrode is a cathode which is a pixel electrode, and the second electrode is an anode which is common to a plurality of sub-pixels.

The transistor of fig. 10Is a semiconductor having an oxide semiconductor, such as In-Ga-Zn-O typeN-type channel transistor of the channel. The first power supply voltage line PF (n) and the second power supply voltage line PS (m) are turned on with the first power supply ELVSS (same power supply), and the anode (second electrode) is turned on with the second power supply ELVDD of a higher voltage than the first power supply ELVSS.

In the pixel circuit PC (n rows and m columns), during the period of selection (the period of high level to be activated) of the scanning signal line GL (n-1) in the preceding stage, the driving transistor T1, the first initializing transistor T4, and the second initializing transistor T5 are turned ON, and the node Nd and the drain terminal (first ON terminal) of the driving transistor T1 are turned ON with the initializing power supply line Pi (n), and reset to the initializing voltage.

Next, in the selection period (high level period to be activated: write period of the pixel circuit PC) of the scanning signal line GL (n) of the present stage, the power supply connection transistor T3, the first initialization transistor T4, the second initialization transistor T5, the power supply transistor T7, the light emission control transistor T8 are turned OFF, the threshold compensation transistor T2, and the write transistor T6 are turned ON, and the data signal (gradation voltage) from the data signal line SL (m) is set to the node Nd via the write transistor T6, the drive transistor T1, and the threshold compensation transistor T2.

Then, in the selection period (High period to be activated: light emission period of the light emitting element ES) of the light emission control line EM (n) of this stage, the power supply transistor T3, the power supply transistor T7, and the light emission control transistor T8 are turned ON, the threshold compensation transistor T2, the first initialization transistor T4, the second initialization transistor T5, and the write transistor T6 are turned OFF, a current corresponding to the voltage set at the node Nd flows through the light emitting element ES, and the light emitting element ES emits light at a luminance corresponding to the data signal.

The first power supply voltage line PF (n) is turned OFF in the writing period, and is not electrically connected to the second conduction terminal of the driving transistor T1 and the other electrode of the capacitor Cp, and is turned ON in the light emission period after the writing period, and is electrically connected to the second conduction terminal of the driving transistor T1 and the other electrode of the capacitor Cp, and the power supply transistor T7 and the power supply connection transistor T3 are turned ON.

The control terminal of the transistor T3 may be electrically connected to the emission control line EM (n) of the present stage, the emission control line EM (n-1) of the preceding stage, or the emission control line EM (n+1) of the subsequent stage, as in the first embodiment.

Fourth embodiment

FIG. 11 (a)Fig. 11 (c) is a plan view schematically showing a plurality of configurations of the display area DA of the fourth embodiment. The display device 2 has a display area DA having a special shape in which a cutout NT is provided in a part of a rectangle. The display area DA in fig. 11 (a) has a shape in which a cutout NT is provided at one side of the display area DA, the display area DA in fig. 11 (b) has a shape in which a cutout NT (rounded) is provided at four corners of the display area DA, and the display area DA in fig. 11 (c) has a shape in which a cutout NT (may be circular) is provided inside the display area DA. The notched portion NT in fig. 11 is an example, and may be a combination thereof.

The display area DA is described as being divided into a deformed portion Dx including the first power supply voltage line PF intersecting the cutout portion NT and other normal portions Dk. The shaped portion Dx is a region of the display area DA adjacent to the cutout portion NT and the extending direction of the scanning signal line GL (the same extending direction as the first power supply voltage line PF (i)). Even if the notch portion NT is formed, the parasitic capacitance of the first power supply voltage line PF and the data signal line SL is made to coincide with each other in the shaped portion Dx and the normal portion Dk, so that the first power supply voltage line PF (i) intersecting the notch portion NT is made to detour around the notch portion NT in fig. 11 (a) and (c), that is, in the configuration of fig. 11 (a) and (c), the first power supply voltage line PF (i) intersecting the shaped portion Dx overlaps with the data signal line SL (j) intersecting the shaped portion Dx in fig. 11 (c), the data signal line SL (j) intersecting the shaped portion Dx is made to detour around the notch portion NT.

In the data signal line SL (j) intersecting the shaped portion Dx, there is no video signal to be displayed during a plurality of horizontal scanning periods corresponding to the cutout portion NT, and thus the data signal corresponding to black or white is continuously supplied. Therefore, in the first power supply voltage line PF (i) intersecting the abnormal portion Dx, similarly to the block in which the bright or dark is displayed in the part of the display area DA, the fluctuation is likely to occur due to the coupling with the data signal line SL (j) (see fig. 6).

Therefore, the power supply connection transistor T3 is provided only in the pixel circuit PC corresponding to the first power supply line PF (i) intersecting the irregular portion Dx, and thus, occurrence of fluctuation can be prevented. In this case, the power supply connection transistor T3 may be provided over the entire or part of the pixel circuit PC corresponding to the first power supply voltage line PF intersecting the irregular portion Dx. In addition, in the case where the cutout NT is provided on one side of the display area DA as in fig. 11 (a), the power supply connection transistor T3 may be provided only in the pixel circuit corresponding to the first power supply voltage line PF (i) farthest from the one side among the first power supply voltage lines PF (n) intersecting the irregular-shaped portion Dx. This is because the first power supply voltage line PF (i) that generates fluctuation based on the data signal line SL (j) is the wiring. Similarly, in the case where the notch portion NT is provided in the display area DA as in fig. 11 (c), the power supply connection transistor T3 may be provided only in the pixel circuit corresponding to the first power supply voltage line PF (n) first intersecting the shaped portion Dx and the first power supply voltage line PF last intersecting the shaped portion Dx among the first power supply voltage lines PF (n) intersecting the shaped portion Dx in the extending direction of the data signal line SL (j).

Of course, the same as in the first embodiment may be provided in all the pixel circuits.

The light-emitting element is an element whose luminance and transmittance are controlled by current control, and examples of a display device including the current-controlled light-emitting element include an organic EL (Electro Luminescence: electroluminescence) display including an OLED (Organic Light Emitting Diode: organic light-emitting diode), an EL display such as an inorganic EL display including an inorganic light-emitting diode, and a QLED display including a QLED (Quantum dot Light Emitting Diode: quantum dot light-emitting diode).

The foregoing embodiments are for the purpose of illustration and description, and are not intended to be limiting. Based on these illustrations and descriptions, those skilled in the art will recognize that numerous variations are possible.

[ summary ]

Mode 1

A display device is provided with:

a plurality of scanning signal lines; a plurality of light emission control lines; a plurality of first power supply voltage lines; a plurality of initialization power lines; a plurality of data signal lines; and a plurality of second power supply voltage lines, the plurality of scan signal lines, the plurality of light emission control lines, the plurality of first power supply voltage lines, and the plurality of initialization power supply lines extending in parallel and intersecting the plurality of data signal lines and the plurality of second power supply voltage lines, respectively, extending in parallel,

A plurality of sub-pixels including pixel circuits and light emitting elements are provided corresponding to a plurality of intersections of the plurality of scanning signal lines and the plurality of data signal lines, the light emitting elements including a first electrode; a light emitting layer; and a second electrode shared among the plurality of sub-pixels,

the pixel circuit includes a driving transistor, a threshold compensation transistor, a power supply connection transistor, a writing transistor, and a capacitor, one electrode of the capacitor is electrically connected to a control terminal of the driving transistor, the other electrode of the capacitor is electrically connected to the second power supply voltage line,

the first conduction terminal of the power supply connection transistor is electrically connected to a first power supply voltage line, a conduction voltage is input to a corresponding scanning signal line during a writing period of the pixel circuit, a data signal is input to the capacitor from a corresponding data signal line via the writing transistor and the threshold compensation transistor, the other electrode of the capacitor is not conducted to the first power supply voltage line, a conduction voltage is input to a corresponding light emission control line during a light emission period of the light emitting element, and the other electrode of the capacitor is conducted to the first power supply voltage line via the power supply connection transistor during at least a part of the light emission period.

Mode 2

As in the display device described in the mode 1,

the pixel circuit further includes: a first initialization transistor, a second initialization transistor, a power supply transistor, and a light emission control transistor,

the first conducting terminal of the first initializing transistor is electrically connected with the control terminal of the driving transistor, the second conducting terminal of the second initializing transistor is electrically connected with the first conducting terminal of the driving transistor, the second conducting terminal of the second initializing transistor is electrically connected with the initializing power line, the first conducting terminal of the writing transistor is electrically connected with the corresponding data signal line, the second conducting terminal of the writing transistor is electrically connected with the second conducting terminal of the driving transistor, and in the threshold compensating transistor, the first conducting terminal of the threshold compensating transistor is electrically connected with the first conducting terminal of the driving transistor, the second conducting terminal of the threshold compensating transistor is electrically connected with the control terminal of the driving transistor, the first conducting terminal of the light emitting control transistor is electrically connected with the first conducting terminal of the driving transistor, and the second conducting terminal of the light emitting control transistor is electrically connected with the first electrode of the light emitting element.

Mode 3

The display device according to mode 2, wherein the control terminal of the power supply connection transistor is electrically connected to a light emission control line corresponding to the present stage.

Mode 4

The display device according to mode 3, wherein the other electrode of the capacitor is connected to the first power supply voltage line via the power supply connection transistor during the entire light emission period.

Mode 5

The display device according to mode 2, wherein the control terminal of the power supply connection transistor is electrically connected to a light emission control line of a preceding stage or a succeeding stage corresponding to the current stage.

Mode 6

In the display device according to claim 5, in the light emission period, the other electrode of the capacitor is turned on with the first power supply voltage line via the power supply connection transistor except for a portion of the start period or a portion of the end period.

Mode 7

The display device according to any one of claims 1 to 6, wherein a second conduction terminal of the power supply connection transistor is electrically connected to the other electrode of the capacitor.

Mode 8

The display device according to claim 7, wherein the second conductive terminal of the power supply connection transistor is electrically connected to the second conductive terminal of the driving transistor.

Mode 9

The display device according to any one of claims 1 to 8, wherein the display device comprises a substrate, a first metal layer, a first inorganic insulating layer, a second metal layer, a second inorganic insulating layer, and a third metal layer are provided in this order from the substrate,

The plurality of scan signal lines and the plurality of light emission control lines are included in the first metal layer,

the plurality of first power voltage lines and the plurality of initialization power voltage lines are included in the second metal layer,

the plurality of data signal lines and the plurality of second power voltage lines are included in the third metal layer.

Mode 10

The display device according to mode 9, wherein the first power supply voltage line overlaps the data signal line via the second inorganic insulating layer.

Mode 11

The display device according to any one of modes 1 to 10, wherein the driving transistor is a P-type transistor,

the first electrode is an anode.

Mode 12

The display device according to any one of modes 1 to 10, wherein the driving transistor is an N-type transistor,

the first electrode is a cathode.

Mode 13

The display device according to any one of modes 1 to 12, wherein the plurality of first power supply voltage lines and the plurality of second power supply voltage lines are turned on with the same power supply.

Mode 14

The display device according to any one of claims 1 to 13, having a display region of a special shape obtained by providing a cutout portion on a part of a rectangle, the display region including the cutout portion and a special-shaped portion adjacent in an extending direction of the plurality of scanning signal lines, a plurality of first power supply voltage lines intersecting the special-shaped portion, and a plurality of data signal lines intersecting the special-shaped portion intersecting.

Mode 15

The display device according to claim 14, wherein the power supply connection transistor is provided only in the pixel circuit corresponding to each of the plurality of first power supply voltage lines intersecting the shaped portion.

Mode 16

The display device according to claim 15, wherein the cutout portion is provided on one side of the display region,

the power supply connection transistor is provided only in a pixel circuit corresponding to a first power supply voltage line farthest from the one side among a plurality of first power supply voltage lines intersecting the shaped portion.

Mode 17

The display device according to claim 15, wherein the cutout portion is provided in the display region,

the power connection transistor is provided only in a pixel circuit corresponding to a first power supply voltage line that initially crosses the shaped portion and a first power supply voltage line that finally crosses the shaped portion in an extending direction of the plurality of data signal lines.

Description of the reference numerals

2 display device

3 barrier layer

4TFT layer

5 light emitting element layer

6 sealing layer

PX sub-pixel

PC pixel circuit

ES light-emitting element

Cp capacitor

T1 driving transistor

T2 threshold compensation transistor

T3 power supply connection transistor

T6 write transistor

GL (n) scanning signal line

SL (m) data signal line

PF (n) first power supply voltage line

PS (m) second power supply voltage line

Claims

1. A display device is characterized by comprising:

a plurality of scan signal lines, a plurality of light emission control lines, a plurality of first power voltage lines, a plurality of initialization power voltage lines, a plurality of data signal lines, a plurality of second power voltage lines,

the plurality of scan signal lines, the plurality of light emission control lines, the plurality of first power supply voltage lines, and the plurality of initialization power supply lines extend in parallel and respectively intersect the plurality of data signal lines and the plurality of second power supply voltage lines extending in parallel,

a plurality of sub-pixels composed of pixel circuits and light emitting elements are provided corresponding to a plurality of intersections of the plurality of scanning signal lines and the plurality of data signal lines,

the light emitting element includes a first electrode, a light emitting layer, and a second electrode shared among a plurality of sub-pixels,

The first conductive terminal of the power connection transistor is electrically connected to a first power voltage line,

in the write period of the pixel circuit, an on voltage is input to a corresponding scanning signal line, a data signal is input from a corresponding data signal line to the capacitor via the write transistor and the threshold compensation transistor, and the other electrode of the capacitor is not turned on with a first power supply voltage line,

during a light emission period of the light emitting element, an on voltage is input to a corresponding light emission control line, and during at least a part of the light emission period, the other electrode of the capacitor is turned on with a first power supply voltage line via the power supply connection transistor.

2. The display device of claim 1, wherein,

a first conduction terminal of the first initialization transistor is electrically connected with a control terminal of the driving transistor, a second conduction terminal of the first initialization transistor is electrically connected with an initialization power line,

a first conductive terminal of the second initialization transistor is electrically connected with a first conductive terminal of the driving transistor, a second conductive terminal of the second initialization transistor is electrically connected with an initialization power line,

The first conductive terminal of the writing transistor is electrically connected with the corresponding data signal line, the second conductive terminal of the writing transistor is electrically connected with the second conductive terminal of the driving transistor,

a first conductive terminal of the threshold compensation transistor is electrically connected with a first conductive terminal of the drive transistor, a second conductive terminal of the threshold compensation transistor is electrically connected with a control terminal of the drive transistor,

the first conductive terminal of the light emission control transistor is electrically connected to the first conductive terminal of the driving transistor, and the second conductive terminal of the light emission control transistor is electrically connected to the first electrode of the light emitting element.

3. The display device according to claim 2, wherein a control terminal of the power supply connection transistor is electrically connected to a light emission control line corresponding to the present stage.

4. A display device as claimed in claim 3, characterized in that the other electrode of the capacitor is in conduction with the first supply voltage line via the supply connection transistor during the whole of the light emission.

5. The display device according to claim 2, wherein a control terminal of the power supply connection transistor is electrically connected to a light emission control line of a preceding stage or a succeeding stage corresponding to the present stage.

6. The display device according to claim 5, wherein in the light-emitting period, the other electrode of the capacitor is on with the first power supply voltage line via the power supply connection transistor except for a portion of a start period or a portion of an end period.

7. The display device according to any one of claims 1 to 6, wherein the second conduction terminal of the power supply connection transistor is electrically connected to the other electrode of the capacitor.

8. The display device according to any one of claims 1 to 6, wherein a second conduction terminal of the power supply connection transistor is electrically connected to a second conduction terminal of the driving transistor.

9. The display device according to any one of claims 1 to 8, wherein the display device comprises a substrate,

a first metal layer, a first inorganic insulating layer, a second metal layer, a second inorganic insulating layer and a third metal layer are arranged in sequence from the base material,

10. The display device according to claim 9, wherein the first power supply voltage line overlaps with the data signal line via the second inorganic insulating layer.

11. The display device according to any one of claims 1 to 10, wherein the driving transistor is a P-type transistor,

the first electrode is an anode.

12. The display device according to any one of claims 1 to 10, wherein the driving transistor is an N-type transistor,

the first electrode is a cathode.

13. The display device according to any one of claims 1 to 12, wherein the plurality of first power supply voltage lines and the plurality of second power supply voltage lines are turned on with the same power supply.

14. The display device according to any one of claims 1 to 13, wherein there is a display area having a deformed shape obtained by providing a cutout portion on a part of a rectangle, the display area including the cutout portion and deformed portions adjacent in an extending direction of the plurality of scanning signal lines,

a plurality of first power supply voltage lines crossing the shaped portion and a plurality of data signal lines crossing the shaped portion.

15. The display device according to claim 14, wherein the power supply connection transistor is provided only to the pixel circuits respectively corresponding to the plurality of first power supply voltage lines intersecting the shaped portion.

16. The display device according to claim 15, wherein the cutout portion is provided on one side of the display area,

17. The display device according to claim 15, wherein the cutout portion is provided inside the display area,