WO2019176066A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2019176066A1
WO2019176066A1 PCT/JP2018/010305 JP2018010305W WO2019176066A1 WO 2019176066 A1 WO2019176066 A1 WO 2019176066A1 JP 2018010305 W JP2018010305 W JP 2018010305W WO 2019176066 A1 WO2019176066 A1 WO 2019176066A1
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WO
WIPO (PCT)
Prior art keywords
circuit
display device
deformed portion
unit
signal line
Prior art date
Application number
PCT/JP2018/010305
Other languages
French (fr)
Japanese (ja)
Inventor
武彦 河村
山田　淳一
真 横山
Original Assignee
シャープ株式会社
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Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2018/010305 priority Critical patent/WO2019176066A1/en
Publication of WO2019176066A1 publication Critical patent/WO2019176066A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present invention relates to a display device.
  • Patent Document 1 discloses a technique for arranging driver unit circuits on the outside (non-display portion) of a curved edge of a display portion.
  • the conventional method has a problem that the non-display portion (frame portion) becomes large.
  • the display device includes a driver outside the display region, and the edge of the display region has a curved shape or a diagonal shape with reference to the extending direction of the signal line in the display region
  • the display device includes a deformed portion that is a first side that is inclined with respect to the extending direction and an outer side of the deformed portion that is orthogonal to the first side and shorter than the first side.
  • a plurality of circuit blocks in which unit circuits of the driver are formed in a rectangular region having two sides are included, and the shape of the rectangular region is the same for each circuit block, and the first side and the extending direction are formed.
  • the acute angle is the same value.
  • FIG. 1 It is a flowchart which shows an example of the manufacturing method of a display device. It is sectional drawing which shows the structural example of the display part of a display device. It is a top view which shows the structural example of a display device. It is a circuit diagram which shows the structural example of the sub pixel of a display area.
  • (A) is a top view which shows the corner part of the display device of Example 1
  • (b) is a top view which shows a rectangular area.
  • (A) is a circuit diagram showing the configuration of the gate driver
  • (b) is a timing chart showing the configuration of the gate driver
  • (c) is a circuit diagram showing the configuration of the unit circuit. It is a top view which shows the example of a connection of a circuit unit.
  • (A) is a top view which shows the modification of the corner part of a display device, (b) is the elements on larger scale of (a).
  • (A) is a top view which shows the further modification of the corner part of a display device, (b) is the elements on larger scale of (a).
  • “same layer” means formed in the same process (film formation step), and “lower layer” means formed in a process prior to the layer to be compared.
  • the “upper layer” means that it is formed in a later process than the layer to be compared.
  • FIG. 1 is a flowchart showing an example of a display device manufacturing method.
  • FIG. 2 is a cross-sectional view illustrating a display unit of the display device.
  • FIG. 3 is a plan view showing the configuration of the display device.
  • a resin layer 12 is formed on a translucent support substrate (for example, mother glass) (step S1).
  • the barrier layer 3 is formed (step S2).
  • the TFT layer 4 is formed (step S3).
  • a top emission type light emitting element layer for example, OLED element layer
  • the sealing layer 6 is formed (step S5).
  • an upper surface film is pasted on the sealing layer 6 (step S6).
  • step S7 the lower surface of the resin layer 12 is irradiated with laser light through the support substrate to reduce the bonding force between the support substrate and the resin layer 12, and the support substrate is peeled from the resin layer 12 (step S7).
  • step S8 the lower film 10 is attached to the lower surface of the resin layer 12 (step S8).
  • step S9 the laminate including the lower film 10, the resin layer 12, the barrier layer 3, the TFT layer 4, the light emitting element layer 5, and the sealing layer 6 is divided to obtain a plurality of pieces (step S9).
  • the functional film 39 is affixed on the obtained piece (step S10).
  • an electronic circuit board for example, an IC chip
  • step S11 Each step is performed by a display device manufacturing apparatus described later.
  • Examples of the material of the resin layer 12 include polyimide, and examples of the material of the lower surface film 10 include polyethylene terephthalate (PET).
  • Examples of the material of the resin layer 12 include polyimide, and examples of the material of the lower surface film 10 include polyethylene terephthalate (PET).
  • the barrier layer 3 is a layer that prevents foreign matters such as water and oxygen from reaching the TFT layer 4 and the light emitting element layer 5.
  • a silicon oxide film, a silicon nitride film, or an oxynitride formed by a CVD method is used.
  • a silicon film or a laminated film thereof can be used.
  • the TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (gate insulating film) above the semiconductor film 15, a gate electrode GE above the inorganic insulating film 16, and an inorganic insulating film above the gate electrode GE.
  • a planarizing film 21 (interlayer insulating film).
  • the semiconductor film 15 is made of, for example, low-temperature polysilicon (LTPS) or an oxide semiconductor, and a thin film transistor Tr (TFT) is formed so as to include the semiconductor film 15, the inorganic insulating film 16, and the gate electrode GE.
  • LTPS low-temperature polysilicon
  • TFT thin film transistor Tr
  • FIG. 2 the thin film transistor Tr is shown with a top gate structure, but may have a bottom gate structure.
  • the gate electrode GE, the capacitor electrode CE, and the source wiring SH are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu). It is comprised by the metal single layer film or laminated film containing at least 1 of these.
  • the inorganic insulating films 16, 18, and 20 can be formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method.
  • the planarizing film 21 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
  • the light-emitting element layer 5 (for example, an organic light-emitting diode layer) includes an anode 22 above the planarizing film 21, an insulating anode cover film 23 covering the edge of the anode 22, and an EL (Electro) layer above the anode 22.
  • a light emitting element ES (for example, OLED: organic light emitting diode) including an island-shaped anode 22, an EL layer 24, and a cathode 25 for each sub-pixel. ) And a sub-pixel circuit for driving the same.
  • the anode cover film 23 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
  • the EL layer 24 is configured, for example, by laminating a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order from the lower layer side.
  • the light emitting layer is formed in an island shape for each sub-pixel by an evaporation method or an inkjet method.
  • the other layers are formed in an island shape or a solid shape (common layer).
  • the structure which does not form one or more layers among a positive hole injection layer, a positive hole transport layer, an electron carrying layer, and an electron injection layer is also possible.
  • the anode 22 is composed of, for example, a laminate of ITO (IndiumITOTin Oxide) and Ag (silver) or an alloy containing Ag, and has light reflectivity.
  • the cathode 25 can be made of a light-transmitting conductive material such as MgAg alloy (ultra-thin film), ITO (Indium Tin Oxide), IZO (Indium zinc Oxide) or the like.
  • the light-emitting element layer 5 is an OLED layer
  • holes and electrons are recombined in the EL layer 24 by a driving current between the anode 22 and the cathode 25, and the exciton generated thereby falls to the ground state, whereby light is emitted. Released. Since the cathode 25 is light-transmitting and the anode 22 is light-reflective, the light emitted from the EL layer 24 is directed upward and becomes top emission.
  • the light emitting element layer 5 is not limited to constituting an OLED element, and may constitute an inorganic light emitting diode or a quantum dot light emitting diode.
  • the sealing layer 6 is translucent, and includes an inorganic sealing film 26 that covers the cathode 25, an organic sealing film 27 that is above the inorganic sealing film 26, and an inorganic sealing that is above the organic sealing film 27. A film 28.
  • the sealing layer 6 covering the light emitting element layer 5 prevents penetration of foreign substances such as water and oxygen into the light emitting element layer 5.
  • Each of the inorganic sealing film 26 and the inorganic sealing film 28 can be formed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof formed by a CVD method.
  • the organic sealing film 27 is a light-transmitting organic film having a flattening effect, and can be made of a coatable organic material such as acrylic.
  • the lower surface film 10 is for realizing a display device with excellent flexibility by being attached to the lower surface of the resin layer 12 after peeling off the support substrate.
  • Examples of the material include PET.
  • the functional film 39 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like.
  • step S5 in FIG. 1 the process proceeds from step S5 in FIG. 1 to step S9.
  • FIG. 4 is a circuit diagram illustrating a configuration example of sub-pixels in the display area.
  • the TFT layer 4 in FIG. 2 includes scanning signal lines GL (n ⁇ 1) and GL (n) and light emission signal lines EMn extending in the x direction (row direction), and a data line DL extending in the y direction (column direction). And are provided.
  • the sub-pixel SP includes a drive transistor Ta, a switch transistor Tb, a power supply control transistor Tc, a light emission control transistor Td, a threshold voltage compensation transistor Te, an initialization transistor Tf, and a capacitor Cp formed in the TFT layer 4 of FIG.
  • the 2 includes a light emitting element ES (for example, an organic light emitting diode) formed in the light emitting element layer 5 of FIG. 2, and the switch transistor Tb is connected to the scanning signal line Gn and the data line DL.
  • the potential signal corresponding to the display gradation data is supplied from the data line DL to the subpixel SP during the period in which the scanning signal line Gn is active, and the light emitting element ES is in the display gradation data during the period in which the light emission signal line EMn is active. It emits light with a brightness corresponding to.
  • FIG. 5A is a plan view showing a corner portion (Ac) of the display device of Example 1
  • FIG. 5B is a plan view showing a rectangular region in the corner portion (Ac).
  • a part of the edge (corner portion) of the display area DA is a curved deformed portion JS that protrudes outward, and the outside of the deformed portion JS (frame region NA).
  • 2 is provided with a gate driver GD formed in the same process (in the same layer) as the TFT layer 4 (including the sub-pixel circuit) of FIG.
  • the first side Fa (long side) and the first side Fa that are oblique to the y direction (the direction in which the data signal line extends) are orthogonal to the first side Fa and shorter than the first side Fa.
  • a plurality of circuit blocks KB each having a unit circuit UC (for example, one stage of a shift register) of the driver GD are provided in a rectangular region having two sides Fb (short sides).
  • the shape of the rectangular area is the same, and the acute angle formed by the first side Fa and the y direction is the same value (45 °).
  • the six circuit blocks KB arranged in the direction orthogonal to the first side Fa constitute one circuit unit KU, and the fifteen circuit units KU are arranged on the outer side along the deformed portion JS. ing.
  • a plurality of circuit blocks KB are arranged along the deformed portion JS, and are located outside the one end of the deformed portion JS and outside the other end of the deformed portion JS.
  • the first side Fa and the y direction form the same acute angle (45 °) for each of the circuit block KB and the circuit block KB located outside the center of the deformed portion JS.
  • the circuit unit KU (1) including the circuit block located outside the one end of the deformed portion JS and the circuit unit KU (15) including the circuit block located outside the other end of the deformed portion JS are described.
  • the circuit unit KU (8) including the circuit block that is arranged so as to be separated from the adjacent circuit unit and is located outside the central portion of the deformed portion JS is in contact with the adjacent circuit unit KU (9). Has been placed.
  • the edge of the display area DA is connected to the deformed portion KS, includes a straight portion TS parallel to the y direction, and a unit circuit of the gate driver GD is formed in a rectangular region having sides parallel to and straight to the straight portion TS.
  • the formed circuit block Kb is provided so as to be adjacent to the circuit unit KU (15) including the circuit block located outside the one end portion of the deformed portion KS.
  • FIG. 6A is a circuit diagram showing the configuration of the gate driver
  • FIG. 6B is a flowchart showing the operation of the gate driver
  • FIG. 6C is a circuit diagram showing a configuration example of the unit circuit. is there.
  • the gate driver GD is composed of a plurality of unit circuits UC connected to each other.
  • the output terminal Un (see FIG. 6) of the n-th unit circuit UC is the nth scan.
  • the signal line Gn is connected to the reset terminal R of the (n ⁇ 1) th stage (previous stage) unit circuit UC and the set terminal S of the n + 1th stage (rear stage) unit circuit UC.
  • the unit circuit UC is a circuit that outputs a scanning signal (pulse signal) PS to the scanning signal line to be connected.
  • the wiring PW1 (high voltage side) and the power supply wiring PW2 (low voltage side) are configured.
  • the clock signal line CK1 is supplied with the clock signal CKa shown in FIG. 6B
  • the clock signal line CK2 is supplied with the clock signal CKb shown in FIG. 6B.
  • the power supply voltage is supplied from the power supply wirings PW1 and PW2 to the flip-flop FF and the output circuit SC.
  • FIG. 7 is a plan view showing a connection example of a circuit unit circuit (two-stage circuit block product).
  • the clock signal wiring CK1 is arranged along one short side
  • the power supply wiring PW1 is arranged along the other short side
  • the clock signal wiring CK1 and the power supply wiring PW1 are arranged.
  • an output circuit SC including a plurality of transistors TR is arranged between the power supply wiring PW2 and the clock signal wiring CK2.
  • the arrangement of the transistor TR in FIG. 7 is schematic.
  • the clock signal wiring CK1, the clock signal wiring CK2, the power supply wiring PW1, and the power supply wiring PW2 are inclined by + 45 ° or ⁇ 45 ° with respect to the y direction.
  • the channel direction of each transistor TR is inclined + 45 ° or ⁇ 45 ° with respect to the y direction. Note that the illustrated wirings and transistors are a part of circuit elements constituting the unit circuit UC.
  • Each circuit block KB has a common layout (shape and position) of circuit elements (for example, transistors, capacitors, resistors, wirings, terminals, etc.) constituting the unit circuit UC.
  • circuit elements for example, transistors, capacitors, resistors, wirings, terminals, etc.
  • the power supply trunk line MP1 is arranged, and outside the circuit unit KU, the power supply trunk line MP2, the clock trunk line MC1, and the clock trunk line MC2 are arranged in this order toward the outside.
  • the clock signal wiring CK1 is connected to the clock trunk wiring MC1
  • the clock signal wiring CK2 is connected to the clock trunk wiring MC2
  • the power supply wiring PW1 is connected to the power supply trunk wiring MP1
  • the power supply wiring PW2 is connected to the power supply trunk wiring MP2.
  • the clock trunk line MC1, clock trunk line MC2, power supply trunk line MP1, and power supply trunk line MP2 are inclined by + 45 ° or ⁇ 45 ° with respect to the y direction.
  • Adjacent circuit blocks are connected by inter-block wiring (not shown) for transmitting a set signal and inter-block wiring (not shown) for transmitting a reset signal, and a set signal is transmitted between adjacent circuit units.
  • the inter-unit wiring US and the inter-unit wiring UR that transmits the reset signal are connected.
  • the inter-block wiring and the inter-unit wiring US ⁇ UR are inclined + 45 ° or ⁇ 45 ° with respect to the y direction.
  • the circuit block KB storing the unit circuit UC of the gate driver is inclined by 45 ° with respect to the y direction, and the layout of circuit elements constituting the unit circuit is made common. Therefore, the characteristic variation of the circuit element between the unit circuits can be suppressed while the frame area NA outside the deformed portion JS is reduced. In addition, when the circuit block is radially arranged outside the deformed portion JS, the characteristic variation of the circuit element between unit circuits increases.
  • the tangent forms an acute angle within a predetermined range (including ⁇ e, for example, 30 ° to 60 °) with respect to the x direction.
  • a single block KB is arranged on the outside. Therefore, the frame area NA outside the deformed portion JS can be further reduced.
  • FIG. 5 shows a case where the deformed portion JS has a curved shape that protrudes outward, but the deformed portion JS may have a curved shape that protrudes inward as shown in FIG.
  • a plurality of circuit blocks KB are arranged along the deformed portion JS, the circuit block KB located outside one end of the deformed portion JS, and the circuit block located outside the other end of the deformed portion JS.
  • the first side Fa and the y direction form the same acute angle (45 °) for each of the circuit blocks KB located outside the center of the KB and the deformed portion JS.
  • circuit unit KU (1) including a circuit block positioned outside one end of the deformed portion JS and a circuit unit KU (17) including a circuit block positioned outside the other end of the deformed portion JS are described.
  • the circuit block KB containing the unit circuit UC of the gate driver may be inclined by 45 ° with respect to the y direction, and the circuit unit KU constituted by the six-stage product of the circuit block KB may be arranged outside the deformed portion JS. it can.
  • each circuit block is inclined 45 ° with respect to the y-axis direction, but the present invention is not limited to this. It suffices to incline the frame area NA by an angle that minimizes the frame area NA according to the shape of the deformed portion JS.
  • the deformed portion JS may have a configuration including a curved portion and a hatched portion, or may include a plurality of curved portions having different curvatures.
  • the circuit block KB is provided with the unit circuit UC of the gate driver GD that drives the scanning signal line, but is not limited thereto.
  • a unit circuit of an emission driver that drives the light emission signal line EMn of FIG. 4 may be provided in the circuit block KB.
  • the above description is based on the extending direction (y direction) of the data signal line, but the extending direction (x direction) of the scanning signal line or the extending direction (x direction) of the light emission signal line can also be used as a reference.
  • the electro-optical element (electro-optical element whose luminance and transmittance are controlled by current) included in the display device according to the present embodiment is not particularly limited.
  • an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, and an inorganic light-emitting diode as an electro-optical element are provided.
  • Inorganic EL displays, and QLED displays equipped with QLEDs (Quantum dot Light Emitting Diodes) as electro-optical elements are exemplified.
  • the display device includes a driver outside the display area, and includes a deformed portion that has a curved shape or an oblique line on the edge of the display area with respect to the extending direction of the signal line in the display area.
  • a unit circuit of the driver is disposed outside the deformed portion in a rectangular region having a first side that is inclined with respect to the extending direction and a second side that is orthogonal to the first side and shorter than the first side.
  • Including a plurality of formed circuit blocks For each circuit block, the shape of the rectangular area is the same, and the acute angle formed by the first side and the extending direction is the same value.
  • Aspect 2 The display device according to Aspect 1, for example, wherein the unit circuit includes a plurality of circuit elements, and each diagonal circuit block has a common layout of the plurality of circuit elements.
  • Display device comprising a plurality of circuit units in which a plurality of the circuit blocks are arranged in a direction orthogonal to the first side, wherein each circuit unit is arranged along the deformed portion.
  • a circuit unit including a circuit block located outside one end of the deformed portion and a circuit unit including a circuit block located outside the other end of the deformed portion are separated from adjacent circuit units. Arranged, for example, the display device according to aspect 5, wherein the circuit unit including the circuit block located outside the central portion of the deformed portion is disposed so as to be in contact with an adjacent circuit unit.
  • the edge of the display area is connected to the deformed portion, and includes a straight portion parallel to the extending direction, A circuit block in which a unit circuit of the driver is formed in a rectangular region having a side parallel to the straight line part and a side perpendicular to the straight line part is adjacent to a circuit unit including a circuit block located outside one end of the deformed part.
  • the display device according to aspect 5 is provided.
  • the deformed portion is curved, Two circuit units are arranged outside the portion of the deformed portion where the tangent forms an acute angle within a predetermined range with respect to the extending direction so that the circuit unit is in contact with the extending direction of the first side.
  • the display device according to, for example, the aspect 4, in which the circuit unit is arranged as a single unit outside the formed portion.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

According to the present invention, a driver (GD) is provided on the outer side of a display area (DA); a differently-shaped part (JS), which has a curved shape or an inclined shape with respect to the extension direction of a signal line of the display area, is provided at an edge of the display area; a plurality of circuit blocks (KB) are provided on the outer side of the differently-shaped part, the circuit blocks being obtained by forming unit circuits of the driver in rectangular areas, each having a first side (Fa) which forms an inclination with respect to the extension direction and a second side (Fb) which is perpendicular to the first side and is shorter than the first side; and in each of the circuit blocks, the rectangular areas have the same shape, and the acute angles formed by the first sides and the extension directions have the same value (45°).

Description

表示デバイスDisplay device
　本発明は表示デバイスに関する。 The present invention relates to a display device.
　特許文献１には、表示部の曲線エッジの外側（非表示部）にドライバの単位回路を並べる技術が開示されている。 Patent Document 1 discloses a technique for arranging driver unit circuits on the outside (non-display portion) of a curved edge of a display portion.
日本国公開特許公報「特開２００９-１２２６３６号公報」Japanese Patent Publication “JP 2009-122636 A”
　従来の手法では、非表示部（額縁部）が大きくなるという問題がある。 The conventional method has a problem that the non-display portion (frame portion) becomes large.
　本発明の一態様に係る表示デバイスは、表示領域よりも外側にドライバを備え、前記表示領域のエッジに、曲線状であるか、あるいは前記表示領域の信号線の延伸方向を基準にして斜線状である異形部が含まれる表示デバイスであって、前記異形部の外側に、前記延伸方向に対して斜めをなす第１辺および前記第１辺に直交し、かつ前記第１辺よりも短い第２辺を有する矩形領域に前記ドライバの単位回路が形成されてなる回路ブロックを複数含み、各回路ブロックについては、前記矩形領域の形状が同一であり、前記第１辺と前記延伸方向とが成す鋭角が同一の値である。 The display device according to one embodiment of the present invention includes a driver outside the display region, and the edge of the display region has a curved shape or a diagonal shape with reference to the extending direction of the signal line in the display region The display device includes a deformed portion that is a first side that is inclined with respect to the extending direction and an outer side of the deformed portion that is orthogonal to the first side and shorter than the first side. A plurality of circuit blocks in which unit circuits of the driver are formed in a rectangular region having two sides are included, and the shape of the rectangular region is the same for each circuit block, and the first side and the extending direction are formed. The acute angle is the same value.
　本発明の一態様によれば、表示部が異形の表示デバイスにおいて額縁領域を縮小させ、かつ単位回路間での回路素子の特性ばらつきを抑えることができる。 According to one embodiment of the present invention, it is possible to reduce a frame region in a display device having a deformed display portion and to suppress characteristic variations of circuit elements between unit circuits.
表示デバイスの製造方法の一例を示すフローチャートである。It is a flowchart which shows an example of the manufacturing method of a display device. 表示デバイスの表示部の構成例を示す断面図である。It is sectional drawing which shows the structural example of the display part of a display device. 表示デバイスの構成例を示す平面図である。It is a top view which shows the structural example of a display device. 表示領域のサブ画素の構成例を示す回路図である。It is a circuit diagram which shows the structural example of the sub pixel of a display area. （ａ）は実施例１の表示デバイスのコーナ部分を示す平面図であり、（ｂ）は矩形領域を示す平面図である。(A) is a top view which shows the corner part of the display device of Example 1, (b) is a top view which shows a rectangular area. （ａ）は、ゲートドライバの構成を示す回路図であり、（ｂ）は、ゲートドライバの構成を示すタイミングチャートであり、（ｃ）は単位回路の構成を示す回路図である。(A) is a circuit diagram showing the configuration of the gate driver, (b) is a timing chart showing the configuration of the gate driver, and (c) is a circuit diagram showing the configuration of the unit circuit. 回路ユニットの接続例を示す平面図である。It is a top view which shows the example of a connection of a circuit unit. （ａ）は表示デバイスのコーナ部分の変形例を示す平面図であり、（ｂ）は、（ａ）の一部拡大図である。(A) is a top view which shows the modification of the corner part of a display device, (b) is the elements on larger scale of (a). （ａ）は表示デバイスのコーナ部分のさらなる変形例を示す平面図であり、（ｂ）は、（ａ）の一部拡大図である。(A) is a top view which shows the further modification of the corner part of a display device, (b) is the elements on larger scale of (a).
　以下においては、「同層」とは同一のプロセス（成膜工程）にて形成されていることを意味し、「下層」とは、比較対象の層よりも先のプロセスで形成されていることを意味し、「上層」とは比較対象の層よりも後のプロセスで形成されていることを意味する。 In the following, “same layer” means formed in the same process (film formation step), and “lower layer” means formed in a process prior to the layer to be compared. The “upper layer” means that it is formed in a later process than the layer to be compared.
　図１は表示デバイスの製造方法の一例を示すフローチャートである。図２は、表示デバイスの表示部を示す断面図である。図３は表示デバイスの構成を示す平面図である。 FIG. 1 is a flowchart showing an example of a display device manufacturing method. FIG. 2 is a cross-sectional view illustrating a display unit of the display device. FIG. 3 is a plan view showing the configuration of the display device.
　フレキシブルな表示デバイスを製造する場合、図１～図３に示すように、まず、透光性の支持基板（例えば、マザーガラス）上に樹脂層１２を形成する（ステップＳ１）。次いで、バリア層３を形成する（ステップＳ２）。次いで、ＴＦＴ層４を形成する（ステップＳ３）。次いで、トップエミッション型の発光素子層（例えば、ＯＬＥＤ素子層）５を形成する（ステップＳ４）。次いで、封止層６を形成する（ステップＳ５）。次いで、封止層６上に上面フィルムを貼り付ける（ステップＳ６）。 When manufacturing a flexible display device, as shown in FIGS. 1 to 3, first, a resin layer 12 is formed on a translucent support substrate (for example, mother glass) (step S1). Next, the barrier layer 3 is formed (step S2). Next, the TFT layer 4 is formed (step S3). Next, a top emission type light emitting element layer (for example, OLED element layer) 5 is formed (step S4). Next, the sealing layer 6 is formed (step S5). Next, an upper surface film is pasted on the sealing layer 6 (step S6).
　次いで、支持基板越しに樹脂層１２の下面にレーザ光を照射して支持基板および樹脂層１２間の結合力を低下させ、支持基板を樹脂層１２から剥離する（ステップＳ７）。次いで、樹脂層１２の下面に下面フィルム１０を貼り付ける（ステップＳ８）。次いで、下面フィルム１０、樹脂層１２、バリア層３、ＴＦＴ層４、発光素子層５、封止層６を含む積層体を分断し、複数の個片を得る（ステップＳ９）。次いで、得られた個片に機能フィルム３９を貼り付ける（ステップＳ１０）。次いで、表示領域ＤＡ（図３参照）よりも外側の額縁領域ＮＡに電子回路基板（例えば、ＩＣチップ）をマウントする（ステップＳ１１）。なお、前記各ステップは、後述の表示デバイス製造装置が行う。 Next, the lower surface of the resin layer 12 is irradiated with laser light through the support substrate to reduce the bonding force between the support substrate and the resin layer 12, and the support substrate is peeled from the resin layer 12 (step S7). Next, the lower film 10 is attached to the lower surface of the resin layer 12 (step S8). Next, the laminate including the lower film 10, the resin layer 12, the barrier layer 3, the TFT layer 4, the light emitting element layer 5, and the sealing layer 6 is divided to obtain a plurality of pieces (step S9). Subsequently, the functional film 39 is affixed on the obtained piece (step S10). Next, an electronic circuit board (for example, an IC chip) is mounted on the frame area NA outside the display area DA (see FIG. 3) (step S11). Each step is performed by a display device manufacturing apparatus described later.
　樹脂層１２の材料としては、例えばポリイミド等が挙げられ、下面フィルム１０の材料としては、例えばポリエチレンテレフタレート（ＰＥＴ）が挙げられる。 Examples of the material of the resin layer 12 include polyimide, and examples of the material of the lower surface film 10 include polyethylene terephthalate (PET).
　バリア層３は、水、酸素等の異物がＴＦＴ層４や発光素子層５に到達することを防ぐ層であり、例えば、ＣＶＤ法により形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜で構成することができる。 The barrier layer 3 is a layer that prevents foreign matters such as water and oxygen from reaching the TFT layer 4 and the light emitting element layer 5. For example, a silicon oxide film, a silicon nitride film, or an oxynitride formed by a CVD method is used. A silicon film or a laminated film thereof can be used.
　ＴＦＴ層４は、半導体膜１５と、半導体膜１５よりも上層の無機絶縁膜１６（ゲート絶縁膜）と、無機絶縁膜１６よりも上層のゲート電極ＧＥと、ゲート電極ＧＥよりも上層の無機絶縁膜１８と、無機絶縁膜１８よりも上層の容量配線ＣＥと、容量配線ＣＥよりも上層の無機絶縁膜２０と、無機絶縁膜２０よりも上層のソース配線ＳＨと、ソース配線ＳＨよりも上層の平坦化膜２１（層間絶縁膜）とを含む。 The TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (gate insulating film) above the semiconductor film 15, a gate electrode GE above the inorganic insulating film 16, and an inorganic insulating film above the gate electrode GE. The film 18, the capacitive wiring CE above the inorganic insulating film 18, the inorganic insulating film 20 above the capacitive wiring CE, the source wiring SH above the inorganic insulating film 20, and the upper layer than the source wiring SH. And a planarizing film 21 (interlayer insulating film).
　半導体膜１５は、例えば低温ポリシリコン（ＬＴＰＳ）あるいは酸化物半導体で構成され、半導体膜１５、無機絶縁膜１６、およびゲート電極ＧＥを含むように薄膜トランジスタＴｒ（ＴＦＴ）が構成される。図２では、薄膜トランジスタＴｒがトップゲート構造で示されているが、ボトムゲート構造でもよい。 The semiconductor film 15 is made of, for example, low-temperature polysilicon (LTPS) or an oxide semiconductor, and a thin film transistor Tr (TFT) is formed so as to include the semiconductor film 15, the inorganic insulating film 16, and the gate electrode GE. In FIG. 2, the thin film transistor Tr is shown with a top gate structure, but may have a bottom gate structure.
　ゲート電極ＧＥ、容量電極ＣＥ、およびソース配線ＳＨは、例えば、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、銅（Ｃｕ）の少なくとも１つを含む金属の単層膜あるいは積層膜によって構成される。 The gate electrode GE, the capacitor electrode CE, and the source wiring SH are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu). It is comprised by the metal single layer film or laminated film containing at least 1 of these.
　無機絶縁膜１６・１８・２０は、例えば、ＣＶＤ法によって形成された、酸化シリコン（ＳｉＯｘ）膜あるいは窒化シリコン（ＳｉＮｘ）膜またはこれらの積層膜によって構成することができる。平坦化膜２１は、例えば、ポリイミド、アクリル等の塗布可能な感光性有機材料によって構成することができる。 The inorganic insulating films 16, 18, and 20 can be formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method. The planarizing film 21 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
　発光素子層５（例えば、有機発光ダイオード層）は、平坦化膜２１よりも上層のアノード２２と、アノード２２のエッジを覆う絶縁性のアノードカバー膜２３と、アノード２２よりも上層のＥＬ（エレクトロルミネッセンス）層２４と、ＥＬ層２４よりも上層のカソード２５とを含み、サブ画素ごとに、島状のアノード２２、ＥＬ層２４、およびカソード２５を含む発光素子ＥＳ（例えば、ＯＬＥＤ：有機発光ダイオード）と、これを駆動するサブ画素回路とが設けられる。アノードカバー膜２３は、例えば、ポリイミド、アクリル等の塗布可能な感光性有機材料によって構成することができる。 The light-emitting element layer 5 (for example, an organic light-emitting diode layer) includes an anode 22 above the planarizing film 21, an insulating anode cover film 23 covering the edge of the anode 22, and an EL (Electro) layer above the anode 22. A light emitting element ES (for example, OLED: organic light emitting diode) including an island-shaped anode 22, an EL layer 24, and a cathode 25 for each sub-pixel. ) And a sub-pixel circuit for driving the same. The anode cover film 23 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
　ＥＬ層２４は、例えば、下層側から順に、正孔注入層、正孔輸送層、発光層、電子輸送層、電子注入層を積層することで構成される。発光層は、蒸着法あるいはインクジェット法によって、サブ画素ごとに島状に形成される。他の層は、島状あるいはベタ状（共通層）に形成する。また、正孔注入層、正孔輸送層、電子輸送層、電子注入層のうち１以上の層を形成しない構成も可能である。 The EL layer 24 is configured, for example, by laminating a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order from the lower layer side. The light emitting layer is formed in an island shape for each sub-pixel by an evaporation method or an inkjet method. The other layers are formed in an island shape or a solid shape (common layer). Moreover, the structure which does not form one or more layers among a positive hole injection layer, a positive hole transport layer, an electron carrying layer, and an electron injection layer is also possible.
　アノード（陽極）２２は、例えばＩＴＯ（Indium Tin Oxide）とＡｇ（銀）あるいはＡｇを含む合金との積層によって構成され、光反射性を有する。カソード２５は、ＭｇＡｇ合金（極薄膜）、ＩＴＯ（Indium Tin Oxide）、ＩＺＯ（Indium zinc Oxide）等の透光性の導電材で構成することができる。 The anode 22 is composed of, for example, a laminate of ITO (IndiumＩＴＯTin Oxide) and Ag (silver) or an alloy containing Ag, and has light reflectivity. The cathode 25 can be made of a light-transmitting conductive material such as MgAg alloy (ultra-thin film), ITO (Indium Tin Oxide), IZO (Indium zinc Oxide) or the like.
　発光素子層５がＯＬＥＤ層である場合、アノード２２およびカソード２５間の駆動電流によって正孔と電子がＥＬ層２４内で再結合し、これによって生じたエキシトンが基底状態に落ちることによって、光が放出される。カソード２５が透光性であり、アノード２２が光反射性であるため、ＥＬ層２４から放出された光は上方に向かい、トップエミッションとなる。 When the light-emitting element layer 5 is an OLED layer, holes and electrons are recombined in the EL layer 24 by a driving current between the anode 22 and the cathode 25, and the exciton generated thereby falls to the ground state, whereby light is emitted. Released. Since the cathode 25 is light-transmitting and the anode 22 is light-reflective, the light emitted from the EL layer 24 is directed upward and becomes top emission.
　発光素子層５は、ＯＬＥＤ素子を構成する場合に限られず、無機発光ダイオードあるいは量子ドット発光ダイオードを構成してもよい。 The light emitting element layer 5 is not limited to constituting an OLED element, and may constitute an inorganic light emitting diode or a quantum dot light emitting diode.
　封止層６は透光性であり、カソード２５を覆う無機封止膜２６と、無機封止膜２６よりも上層の有機封止膜２７と、有機封止膜２７よりも上層の無機封止膜２８とを含む。発光素子層５を覆う封止層６は、水、酸素等の異物の発光素子層５への浸透を防いでいる。 The sealing layer 6 is translucent, and includes an inorganic sealing film 26 that covers the cathode 25, an organic sealing film 27 that is above the inorganic sealing film 26, and an inorganic sealing that is above the organic sealing film 27. A film 28. The sealing layer 6 covering the light emitting element layer 5 prevents penetration of foreign substances such as water and oxygen into the light emitting element layer 5.
　無機封止膜２６および無機封止膜２８はそれぞれ、例えば、ＣＶＤ法により形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜で構成することができる。有機封止膜２７は、平坦化効果のある透光性有機膜であり、アクリル等の塗布可能な有機材料によって構成することができる。 Each of the inorganic sealing film 26 and the inorganic sealing film 28 can be formed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof formed by a CVD method. The organic sealing film 27 is a light-transmitting organic film having a flattening effect, and can be made of a coatable organic material such as acrylic.
　下面フィルム１０は、支持基板を剥離した後に樹脂層１２の下面に貼り付けることで、柔軟性に優れた表示デバイスを実現するためのものであり、その材料としては、ＰＥＴ等が挙げられる。機能フィルム３９は、例えば、光学補償機能、タッチセンサ機能、保護機能等を有する。 The lower surface film 10 is for realizing a display device with excellent flexibility by being attached to the lower surface of the resin layer 12 after peeling off the support substrate. Examples of the material include PET. The functional film 39 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like.
　以上、フレキシブルな表示デバイスを製造する場合について説明したが、非フレキシブルな表示デバイスを製造する場合は、基板の付け替え等が不要であるため、例えば、図１のステップＳ５からステップＳ９に移行する。 As described above, the case of manufacturing a flexible display device has been described. However, in the case of manufacturing a non-flexible display device, since it is not necessary to change the substrate, for example, the process proceeds from step S5 in FIG. 1 to step S9.
　〔実施形態１〕
　図４は、表示領域のサブ画素の構成例を示す回路図である。図２のＴＦＴ層４には、ｘ方向（行方向）に伸びる、走査信号線ＧＬ（ｎ－１）・ＧＬ（ｎ）および発光信号線ＥＭｎと、ｙ方向（列方向）に伸びるデータ線ＤＬとが設けられる。サブ画素ＳＰは、図２のＴＦＴ層４に形成される、駆動トランジスタＴａ、スイッチトランジスタＴｂ、電源供給制御トランジスタＴｃ、発光制御トランジスタＴｄ、閾値電圧補償トランジスタＴｅ、初期化トランジスタＴｆ、および容量Ｃｐを含むサブ画素回路と、図２の発光素子層５に形成される発光素子ＥＳ（例えば、有機発光ダイオード）とを備え、スイッチトランジスタＴｂが走査信号線Ｇｎおよびデータ線ＤＬに接続される。走査信号線Ｇｎがアクティブとなる期間に、データ線ＤＬからサブ画素ＳＰに表示階調データに応じた電位信号が供給され、発光信号線ＥＭｎがアクティブとなる期間に発光素子ＥＳが表示階調データに応じた輝度にて発光する。 Embodiment 1
FIG. 4 is a circuit diagram illustrating a configuration example of sub-pixels in the display area. The TFT layer 4 in FIG. 2 includes scanning signal lines GL (n−1) and GL (n) and light emission signal lines EMn extending in the x direction (row direction), and a data line DL extending in the y direction (column direction). And are provided. The sub-pixel SP includes a drive transistor Ta, a switch transistor Tb, a power supply control transistor Tc, a light emission control transistor Td, a threshold voltage compensation transistor Te, an initialization transistor Tf, and a capacitor Cp formed in the TFT layer 4 of FIG. 2 includes a light emitting element ES (for example, an organic light emitting diode) formed in the light emitting element layer 5 of FIG. 2, and the switch transistor Tb is connected to the scanning signal line Gn and the data line DL. The potential signal corresponding to the display gradation data is supplied from the data line DL to the subpixel SP during the period in which the scanning signal line Gn is active, and the light emitting element ES is in the display gradation data during the period in which the light emission signal line EMn is active. It emits light with a brightness corresponding to.
　図５（ａ）は実施例１の表示デバイスのコーナ部分（Ａｃ）を示す平面図であり、図５（ｂ）はコーナ部分（Ａｃ）にある矩形領域を示す平面図である。図５（ａ）に示すように、表示領域ＤＡのエッジの一部（コーナ部分）は、外側に向けて凸型となる曲線状の異形部ＪＳであり、異形部ＪＳの外側（額縁領域ＮＡのコーナ部分）には、図２のＴＦＴ層４（サブ画素回路を含む）と同じプロセスにて（同層に）形成されたゲートドライバＧＤが配されている。 FIG. 5A is a plan view showing a corner portion (Ac) of the display device of Example 1, and FIG. 5B is a plan view showing a rectangular region in the corner portion (Ac). As shown in FIG. 5A, a part of the edge (corner portion) of the display area DA is a curved deformed portion JS that protrudes outward, and the outside of the deformed portion JS (frame region NA). 2 is provided with a gate driver GD formed in the same process (in the same layer) as the TFT layer 4 (including the sub-pixel circuit) of FIG.
　異形部ＪＳの外側には、ｙ方向（データ信号線の延伸方向）に対して斜めをなす第１辺Ｆａ（長辺）および第１辺Ｆａに直交し、かつ第１辺Ｆａよりも短い第２辺Ｆｂ（短辺）を有する矩形領域にドライバＧＤの単位回路ＵＣ（例えばシフトレジスタの１段分の回路）が形成されてなる回路ブロックＫＢが複数設けられる。各回路ブロックＫＢについては、矩形領域の形状が同一であり、第１辺Ｆａとｙ方向とが成す鋭角が同一の値（４５°）である。そして、第１辺Ｆａに直交する方向に並べられた６個の回路ブロックＫＢによって１個の回路ユニットＫＵが構成され、１５個の回路ユニットＫＵが異形部ＪＳに沿うようにその外側に配されている。 Outside the deformed portion JS, the first side Fa (long side) and the first side Fa that are oblique to the y direction (the direction in which the data signal line extends) are orthogonal to the first side Fa and shorter than the first side Fa. A plurality of circuit blocks KB each having a unit circuit UC (for example, one stage of a shift register) of the driver GD are provided in a rectangular region having two sides Fb (short sides). For each circuit block KB, the shape of the rectangular area is the same, and the acute angle formed by the first side Fa and the y direction is the same value (45 °). The six circuit blocks KB arranged in the direction orthogonal to the first side Fa constitute one circuit unit KU, and the fifteen circuit units KU are arranged on the outer side along the deformed portion JS. ing.
　図５に示すように、複数の回路ブロックＫＢが異形部ＪＳに沿って配されており、異形部ＪＳの一端部の外側に位置する回路ブロックＫＢ、異形部ＪＳの他端部の外側に位置する回路ブロックＫＢ、異形部ＪＳの中央の外側に位置する回路ブロックＫＢそれぞれについて、第１辺Ｆａとｙ方向とが同一の鋭角（４５°）をなす。 As shown in FIG. 5, a plurality of circuit blocks KB are arranged along the deformed portion JS, and are located outside the one end of the deformed portion JS and outside the other end of the deformed portion JS. The first side Fa and the y direction form the same acute angle (45 °) for each of the circuit block KB and the circuit block KB located outside the center of the deformed portion JS.
　また、異形部ＪＳの一端部の外側に位置する回路ブロックを含む回路ユニットＫＵ（１）と、異形部ＪＳの他端部の外側に位置する回路ブロックを含む回路ユニットＫＵ（１５）とについては、隣り合う回路ユニットから離隔するように単独配置され、異形部ＪＳの中央部の外側に位置する回路ブロックを含む回路ユニットＫＵ（８）については、隣り合う回路ユニットＫＵ（９）と接するように配置されている。 The circuit unit KU (1) including the circuit block located outside the one end of the deformed portion JS and the circuit unit KU (15) including the circuit block located outside the other end of the deformed portion JS are described. The circuit unit KU (8) including the circuit block that is arranged so as to be separated from the adjacent circuit unit and is located outside the central portion of the deformed portion JS is in contact with the adjacent circuit unit KU (9). Has been placed.
　また、表示領域ＤＡのエッジは、異形部ＫＳに繋がり、ｙ方向に平行な直線部ＴＳを含み、直線部ＴＳに平行な辺および垂直な辺を有する矩形領域にゲートドライバＧＤの単位回路が形成されてなる回路ブロックＫｂが、異形部ＫＳの一端部の外側に位置する回路ブロックを含む回路ユニットＫＵ（１５）と隣り合うように設けられている。 Further, the edge of the display area DA is connected to the deformed portion KS, includes a straight portion TS parallel to the y direction, and a unit circuit of the gate driver GD is formed in a rectangular region having sides parallel to and straight to the straight portion TS. The formed circuit block Kb is provided so as to be adjacent to the circuit unit KU (15) including the circuit block located outside the one end portion of the deformed portion KS.
　図６（ａ）はゲートドライバの構成を示す回路図であり、図６（ｂ）はゲートドライバの動作を示すフローチャートであり、図６（ｃ）は、単位回路の構成例を示す回路図である。 6A is a circuit diagram showing the configuration of the gate driver, FIG. 6B is a flowchart showing the operation of the gate driver, and FIG. 6C is a circuit diagram showing a configuration example of the unit circuit. is there.
　図６に示すように、ゲートドライバＧＤは、互いに接続された複数段の単位回路ＵＣによって構成され、例えば、ｎ段目の単位回路ＵＣの出力端子Ｕｎ（図６参照）は、ｎ番目の走査信号線Ｇｎと、ｎ－１段目（前段）の単位回路ＵＣのリセット端子Ｒおよびｎ＋１段目（後段）の単位回路ＵＣのセット端子Ｓに接続される。単位回路ＵＣは、接続する走査信号線に走査信号（パルス信号）ＰＳを出力する回路であり、例えば、セットリセット型のフリップフロップＦＦ、出力回路ＳＣ、クロック信号配線ＣＫ１、クロック信号配線ＣＫ２、電源配線ＰＷ１（高電圧側）、および電源配線ＰＷ２（低電圧側）で構成される。クロック信号配線ＣＫ１には、図６（ｂ）のクロック信号ＣＫａが供給され、クロック信号配線ＣＫ２には、図６（ｂ）のクロック信号ＣＫｂが供給される。フリップフロップＦＦおよび出力回路ＳＣには、電源配線ＰＷ１・ＰＷ２から電源電圧が供給される。 As shown in FIG. 6, the gate driver GD is composed of a plurality of unit circuits UC connected to each other. For example, the output terminal Un (see FIG. 6) of the n-th unit circuit UC is the nth scan. The signal line Gn is connected to the reset terminal R of the (n−1) th stage (previous stage) unit circuit UC and the set terminal S of the n + 1th stage (rear stage) unit circuit UC. The unit circuit UC is a circuit that outputs a scanning signal (pulse signal) PS to the scanning signal line to be connected. For example, the set circuit flip-flop FF, the output circuit SC, the clock signal wiring CK1, the clock signal wiring CK2, and the power The wiring PW1 (high voltage side) and the power supply wiring PW2 (low voltage side) are configured. The clock signal line CK1 is supplied with the clock signal CKa shown in FIG. 6B, and the clock signal line CK2 is supplied with the clock signal CKb shown in FIG. 6B. The power supply voltage is supplied from the power supply wirings PW1 and PW2 to the flip-flop FF and the output circuit SC.
　図７は、回路ユニット回路（回路ブロック２段積）の接続例を示す平面図である。図７に示すように、回路ブロックＫＢでは、一方の短辺に沿ってクロック信号配線ＣＫ１が配され、もう一方の短辺に沿って電源配線ＰＷ１が配され、クロック信号配線ＣＫ１および電源配線ＰＷ１の間（矩形領域の中央部）に電源配線ＰＷ２が配され、クロック信号配線ＣＫ１および電源配線ＰＷ２の間にクロック信号配線ＣＫ２が配され、電源配線ＰＷ１および電源配線ＰＷ２の間に複数のトランジスタＴＲを含むフリップフロップＦＦが配され、電源配線ＰＷ２およびクロック信号配線ＣＫ２の間に、複数のトランジスタＴＲを含む出力回路ＳＣが配されている。ただし、図７のトランジスタＴＲの配置は模式的なものである。 FIG. 7 is a plan view showing a connection example of a circuit unit circuit (two-stage circuit block product). As shown in FIG. 7, in the circuit block KB, the clock signal wiring CK1 is arranged along one short side, the power supply wiring PW1 is arranged along the other short side, and the clock signal wiring CK1 and the power supply wiring PW1 are arranged. Between the clock signal wiring CK1 and the power supply wiring PW2, and a plurality of transistors TR between the power supply wiring PW1 and the power supply wiring PW2. And an output circuit SC including a plurality of transistors TR is arranged between the power supply wiring PW2 and the clock signal wiring CK2. However, the arrangement of the transistor TR in FIG. 7 is schematic.
　図７では、クロック信号配線ＣＫ１、クロック信号配線ＣＫ２、電源配線ＰＷ１、および電源配線ＰＷ２は、ｙ方向に対して＋４５°あるいは－４５°傾いている。また、各トランジスタＴＲのチャネル方向はｙ方向に対して、＋４５°あるいは－４５°傾いている。なお、図示されている配線やトランジスタは単位回路ＵＣを構成する回路素子の一部である。 In FIG. 7, the clock signal wiring CK1, the clock signal wiring CK2, the power supply wiring PW1, and the power supply wiring PW2 are inclined by + 45 ° or −45 ° with respect to the y direction. The channel direction of each transistor TR is inclined + 45 ° or −45 ° with respect to the y direction. Note that the illustrated wirings and transistors are a part of circuit elements constituting the unit circuit UC.
　各回路ブロックＫＢでは、単位回路ＵＣを構成する回路素子（例えば、トランジスタ、容量、抵抗、配線、端子等）のレイアウト（形状および位置）が共通とされている。 Each circuit block KB has a common layout (shape and position) of circuit elements (for example, transistors, capacitors, resistors, wirings, terminals, etc.) constituting the unit circuit UC.
　回路ユニットＫＵの内側には、電源幹配線ＭＰ１が配され、回路ユニットＫＵの外側には、電源幹配線ＭＰ２、クロック幹配線ＭＣ１、およびクロック幹配線ＭＣ２が、外側に向けてこの順に配され、クロック信号配線ＣＫ１がクロック幹配線ＭＣ１に接続され、クロック信号配線ＣＫ２がクロック幹配線ＭＣ２に接続され、電源配線ＰＷ１が電源幹配線ＭＰ１に接続され、電源配線ＰＷ２が電源幹配線ＭＰ２に接続されている。クロック幹配線ＭＣ１、クロック幹配線ＭＣ２、電源幹配線ＭＰ１、および電源幹配線ＭＰ２は、ｙ方向に対して＋４５°あるいは－４５°傾いている。なお、隣り合う回路ブロックは、セット信号を伝送するブロック間配線（図示せず）およびリセット信号を伝送するブロック間配線（図示せず）によって接続され、隣り合う回路ユニット間は、セット信号を伝送するユニット間配線ＵＳおよびリセット信号を伝送するユニット間配線ＵＲによって接続されている。ブロック間配線およびユニット間配線ＵＳ・ＵＲは、ｙ方向に対して＋４５°あるいは－４５°傾いている。 Inside the circuit unit KU, the power supply trunk line MP1 is arranged, and outside the circuit unit KU, the power supply trunk line MP2, the clock trunk line MC1, and the clock trunk line MC2 are arranged in this order toward the outside. The clock signal wiring CK1 is connected to the clock trunk wiring MC1, the clock signal wiring CK2 is connected to the clock trunk wiring MC2, the power supply wiring PW1 is connected to the power supply trunk wiring MP1, and the power supply wiring PW2 is connected to the power supply trunk wiring MP2. Yes. The clock trunk line MC1, clock trunk line MC2, power supply trunk line MP1, and power supply trunk line MP2 are inclined by + 45 ° or −45 ° with respect to the y direction. Adjacent circuit blocks are connected by inter-block wiring (not shown) for transmitting a set signal and inter-block wiring (not shown) for transmitting a reset signal, and a set signal is transmitted between adjacent circuit units. The inter-unit wiring US and the inter-unit wiring UR that transmits the reset signal are connected. The inter-block wiring and the inter-unit wiring US · UR are inclined + 45 ° or −45 ° with respect to the y direction.
　実施形態１では、ゲートドライバの単位回路ＵＣを納める回路ブロックＫＢをｙ方向に対して４５°傾け、単位回路を構成する回路素子のレイアウトを共通としている。したがって、異形部ＪＳの外側の額縁領域ＮＡを縮小しながら、単位回路間での回路素子の特性ばらつきを抑えることができる。なお、異形部ＪＳの外側に放射線状に回路ブロックを配した場合には、単位回路間での回路素子の特性ばらつきが大きくなる。 In the first embodiment, the circuit block KB storing the unit circuit UC of the gate driver is inclined by 45 ° with respect to the y direction, and the layout of circuit elements constituting the unit circuit is made common. Therefore, the characteristic variation of the circuit element between the unit circuits can be suppressed while the frame area NA outside the deformed portion JS is reduced. In addition, when the circuit block is radially arranged outside the deformed portion JS, the characteristic variation of the circuit element between unit circuits increases.
　実施形態１では、図５（ａ）に示すように、異形部ＪＳのうち接線がｘ方向に対して所定範囲（θｅを含む、例えば３０°～６０°）の鋭角をなす部分の外側に２個のブロックＫＢを第１辺Ｆａの延伸方向に連結して配し、所定範囲外（θｄを含む、例えば０～３０°、およびθｆを含む、例えば６０°～９０°）の鋭角をなす部分の外側に単体のブロックＫＢを配している。よって、異形部ＪＳの外側の額縁領域ＮＡのさらなる縮小化を図ることができる。 In the first embodiment, as shown in FIG. 5A, 2 outside the portion of the deformed portion JS where the tangent forms an acute angle within a predetermined range (including θe, for example, 30 ° to 60 °) with respect to the x direction. A portion of the blocks KB connected in the extending direction of the first side Fa and having an acute angle outside a predetermined range (including θd, for example, 0 to 30 °, and including θf, for example, 60 ° to 90 °). A single block KB is arranged on the outside. Therefore, the frame area NA outside the deformed portion JS can be further reduced.
　図５は、異形部ＪＳが外側に凸となる曲線状である場合を示しているが、図８のように異形部ＪＳが内側に凸となる曲線状であってもよい。図８では、複数の回路ブロックＫＢが異形部ＪＳに沿って配されており、異形部ＪＳの一端部の外側に位置する回路ブロックＫＢ、異形部ＪＳの他端部の外側に位置する回路ブロックＫＢ、異形部ＪＳの中央の外側に位置する回路ブロックＫＢそれぞれについて、第１辺Ｆａとｙ方向とが同一の鋭角（４５°）をなす。 5 shows a case where the deformed portion JS has a curved shape that protrudes outward, but the deformed portion JS may have a curved shape that protrudes inward as shown in FIG. In FIG. 8, a plurality of circuit blocks KB are arranged along the deformed portion JS, the circuit block KB located outside one end of the deformed portion JS, and the circuit block located outside the other end of the deformed portion JS. The first side Fa and the y direction form the same acute angle (45 °) for each of the circuit blocks KB located outside the center of the KB and the deformed portion JS.
　また、異形部ＪＳの一端部の外側に位置する回路ブロックを含む回路ユニットＫＵ（１）と、異形部ＪＳの他端部の外側に位置する回路ブロックを含む回路ユニットＫＵ（１７）とについては、隣り合う回路ユニットから離隔するように単独配置され、異形部ＪＳの中央部の外側に位置する回路ブロックを含む回路ユニットＫＵ（９）については、隣り合う回路ユニットＫＵ（８）と接するように配置されている。 Further, a circuit unit KU (1) including a circuit block positioned outside one end of the deformed portion JS and a circuit unit KU (17) including a circuit block positioned outside the other end of the deformed portion JS are described. The circuit unit KU (9) including the circuit block that is arranged separately from the adjacent circuit unit and is located outside the central portion of the deformed portion JS is in contact with the adjacent circuit unit KU (8). Has been placed.
　また、図９のように異形部がｙ方向に対して斜線状になる構成も可能である。ゲートドライバの単位回路ＵＣを納める回路ブロックＫＢをｙ方向に対して４５°傾け、回路ブロックＫＢの６段積によって構成される回路ユニットＫＵを異形部ＪＳに沿うようにその外側に配することもできる。 Further, as shown in FIG. 9, a configuration in which the deformed portion is slanted with respect to the y direction is possible. The circuit block KB containing the unit circuit UC of the gate driver may be inclined by 45 ° with respect to the y direction, and the circuit unit KU constituted by the six-stage product of the circuit block KB may be arranged outside the deformed portion JS. it can.
　なお、図５・図８・図９では、各回路ブロックをｙ軸方向に対して４５°傾けているが、これに限定されない。異形部ＪＳの形状にあわせて額縁領域ＮＡが最小になる角度だけ傾ければよい。 In FIGS. 5, 8, and 9, each circuit block is inclined 45 ° with respect to the y-axis direction, but the present invention is not limited to this. It suffices to incline the frame area NA by an angle that minimizes the frame area NA according to the shape of the deformed portion JS.
　異形部ＪＳについては、曲線状の部分と斜線状の部分とが含まれる構成でもよいし、曲率の異なる複数の曲線状の部分を含む構成でもよい。 The deformed portion JS may have a configuration including a curved portion and a hatched portion, or may include a plurality of curved portions having different curvatures.
　図５・図８・図９では、回路ブロックＫＢには、走査信号線を駆動するゲートドライバＧＤの単位回路ＵＣが設けられているが、これに限定されない。回路ブロックＫＢに、図４の発光信号線ＥＭｎを駆動するエミッションドライバの単位回路を設けることもできる。 5, 8, and 9, the circuit block KB is provided with the unit circuit UC of the gate driver GD that drives the scanning signal line, but is not limited thereto. A unit circuit of an emission driver that drives the light emission signal line EMn of FIG. 4 may be provided in the circuit block KB.
　以上ではデータ信号線の延伸方向（ｙ方向）を基準として説明しているが、走査信号線の延伸方向（ｘ方向）あるいは発光信号線の延伸方向（ｘ方向）を基準とすることもできる。 The above description is based on the extending direction (y direction) of the data signal line, but the extending direction (x direction) of the scanning signal line or the extending direction (x direction) of the light emission signal line can also be used as a reference.
　〔まとめ〕
　本実施形態にかかる表示デバイスが備える電気光学素子（電流によって輝度や透過率が制御される電気光学素子）は特に限定されるものではない。本実施形態にかかる表示デバイスとしては、例えば、電気光学素子としてＯＬＥＤ（Organic Light Emitting Diode：有機発光ダイオード）を備えた有機ＥＬ（Electro Luminescence：エレクトロルミネッセンス）ディスプレイ、電気光学素子として無機発光ダイオードを備えた無機ＥＬディスプレイ、電気光学素子としてＱＬＥＤ（Quantum dot Light Emitting Diode：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイ等が挙げられる。 [Summary]
The electro-optical element (electro-optical element whose luminance and transmittance are controlled by current) included in the display device according to the present embodiment is not particularly limited. As a display device according to the present embodiment, for example, an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, and an inorganic light-emitting diode as an electro-optical element are provided. Inorganic EL displays, and QLED displays equipped with QLEDs (Quantum dot Light Emitting Diodes) as electro-optical elements are exemplified.
　〔態様１〕
　表示領域よりも外側にドライバを備え、前記表示領域のエッジに、曲線状であるか、あるいは前記表示領域の信号線の延伸方向を基準にして斜線状である異形部が含まれる表示デバイスであって、
　前記異形部の外側に、前記延伸方向に対して斜めをなす第１辺および前記第１辺に直交し、かつ前記第１辺よりも短い第２辺を有する矩形領域に前記ドライバの単位回路が形成されてなる回路ブロックを複数含み、
　各回路ブロックについては、前記矩形領域の形状が同一であり、前記第１辺と前記延伸方向とが成す鋭角が同一の値である表示デバイス。 [Aspect 1]
The display device includes a driver outside the display area, and includes a deformed portion that has a curved shape or an oblique line on the edge of the display area with respect to the extending direction of the signal line in the display area. And
A unit circuit of the driver is disposed outside the deformed portion in a rectangular region having a first side that is inclined with respect to the extending direction and a second side that is orthogonal to the first side and shorter than the first side. Including a plurality of formed circuit blocks,
For each circuit block, the shape of the rectangular area is the same, and the acute angle formed by the first side and the extending direction is the same value.
　〔態様２〕
　前記単位回路は複数の回路素子を含み、各斜め回路ブロックでは、前記複数の回路素子のレイアウトが共通とされている例えば態様１に記載の表示デバイス。 [Aspect 2]
The display device according to Aspect 1, for example, wherein the unit circuit includes a plurality of circuit elements, and each diagonal circuit block has a common layout of the plurality of circuit elements.
　〔態様３〕
　複数の前記回路ブロックが前記異形部に沿って配されている例えば態様１または２に記載の表示デバイス。 [Aspect 3]
The display device according to, for example, the aspect 1 or 2, wherein the plurality of circuit blocks are arranged along the deformed portion.
　〔態様４〕
　前記回路ブロックが前記第１辺に直交する方向に複数並べられてなる回路ユニットを複数備え、各回路ユニットが前記異形部に沿って配されている例えば態様１～３のいずれか１項に記載の表示デバイス。 [Aspect 4]
The circuit unit according to any one of aspects 1 to 3, for example, comprising a plurality of circuit units in which a plurality of the circuit blocks are arranged in a direction orthogonal to the first side, wherein each circuit unit is arranged along the deformed portion. Display device.
　〔態様５〕
　前記異形部の一端部の外側に位置する回路ブロック、前記異形部の他端部の外側に位置する回路ブロック、および前記異形部の中央の外側に位置する回路ブロックそれぞれについて、前記第１辺と前記延伸方向とが同一の鋭角をなす例えば態様４に記載の表示デバイス。 [Aspect 5]
For each of the circuit block located outside one end of the deformed portion, the circuit block located outside the other end of the deformed portion, and the circuit block located outside the center of the deformed portion, the first side and The display device according to Aspect 4, for example, wherein the stretching direction forms the same acute angle.
　〔態様６〕
　前記異形部の一端部の外側に位置する回路ブロックを含む回路ユニットと、前記異形部の他端部の外側に位置する回路ブロックを含む回路ユニットとについては、隣り合う回路ユニットから離隔するように配置され、
　前記異形部の中央部の外側に位置する回路ブロックを含む回路ユニットについては、隣り合う回路ユニットと接するように配置されている例えば態様５に記載の表示デバイス。 [Aspect 6]
A circuit unit including a circuit block located outside one end of the deformed portion and a circuit unit including a circuit block located outside the other end of the deformed portion are separated from adjacent circuit units. Arranged,
For example, the display device according to aspect 5, wherein the circuit unit including the circuit block located outside the central portion of the deformed portion is disposed so as to be in contact with an adjacent circuit unit.
　〔態様７〕
　前記表示領域のエッジは、前記異形部に繋がり、前記延伸方向に平行な直線部を含み、
　前記直線部に平行な辺および垂直な辺を有する矩形領域に前記ドライバの単位回路が形成されてなる回路ブロックが、前記異形部の一端部の外側に位置する回路ブロックを含む回路ユニットと隣り合うように設けられている例えば態様５に記載の表示デバイス。 [Aspect 7]
The edge of the display area is connected to the deformed portion, and includes a straight portion parallel to the extending direction,
A circuit block in which a unit circuit of the driver is formed in a rectangular region having a side parallel to the straight line part and a side perpendicular to the straight line part is adjacent to a circuit unit including a circuit block located outside one end of the deformed part. For example, the display device according to aspect 5 is provided.
　〔態様８〕
　前記鋭角が４５度である例えば態様１～７のいずれか１項に記載の表示デバイス。 [Aspect 8]
The display device according to any one of aspects 1 to 7, for example, wherein the acute angle is 45 degrees.
　〔態様９〕
　前記信号線は、データ信号線、走査信号線、および発光信号線のいずれかである例えば態様１～８のいずれか１項に記載の表示デバイス。 [Aspect 9]
The display device according to any one of aspects 1 to 8, for example, wherein the signal line is any one of a data signal line, a scanning signal line, and a light emission signal line.
　〔態様１０〕
　前記異形部は曲線状であり、
　前記異形部のうち接線が前記延伸方向に対して所定範囲の鋭角を成す部分の外側には２個の回路ユニットが前記第１辺の延伸方向に接するように配され、所定範囲外の鋭角を成す部分の外側には回路ユニットが単体で配されている例えば態様４に記載の表示デバイス。 [Aspect 10]
The deformed portion is curved,
Two circuit units are arranged outside the portion of the deformed portion where the tangent forms an acute angle within a predetermined range with respect to the extending direction so that the circuit unit is in contact with the extending direction of the first side. The display device according to, for example, the aspect 4, in which the circuit unit is arranged as a single unit outside the formed portion.
　〔態様１１〕
　前記異形部が曲線状であり、前記外側に向けて凸型である例えば態様１～１０のいずれか１項に記載の表示デバイス。 [Aspect 11]
The display device according to any one of aspects 1 to 10, for example, wherein the deformed portion has a curved shape and is convex toward the outside.
　〔態様１２〕
　発光素子と、前記発光素子に接続するサブ画素回路とを備え、
　前記ドライバが前記サブ画素回路と同層に形成されている例えば態様１～１１のいずれか１項に記載の表示デバイス。 [Aspect 12]
A light emitting element, and a sub-pixel circuit connected to the light emitting element,
The display device according to any one of aspects 1 to 11, for example, wherein the driver is formed in the same layer as the sub-pixel circuit.
　〔態様１３〕
　前記ドライバは走査信号線を駆動する例えば態様１～１２のいずれか１項に記載の表示デバイス。 [Aspect 13]
The display device according to any one of Embodiments 1 to 12, for example, wherein the driver drives a scanning signal line.
　〔態様１４〕
　前記ドライバは発光信号線を駆動する例えば態様１～１２のいずれか１項に記載の表示デバイス。 [Aspect 14]
The display device according to any one of Embodiments 1 to 12, for example, wherein the driver drives a light emitting signal line.
　２　　表示デバイス
　４　　ＴＦＴ層
　５　　発光素子層
　ＤＡ　表示領域
　ＮＡ　額縁領域
　ＧＤ　ゲートドライバ
　Ｇｎ　走査信号線
　ＫＢ　回路ブロック
　ＫＵ　回路ユニット
　ＤＬ　データ信号線
　ＵＣ　単位回路
　Ｆａ　第１辺（長辺）
　Ｆｂ　第２辺（短辺）
  2 Display device 4 TFT layer 5 Light emitting element layer DA Display area NA Frame area GD Gate driver Gn Scan signal line KB Circuit block KU Circuit unit DL Data signal line UC Unit circuit Fa First side (long side)
Fb 2nd side (short side)

Claims (14)

  1. 　表示領域よりも外側にドライバを備え、前記表示領域のエッジに、曲線状であるか、あるいは前記表示領域の信号線の延伸方向を基準にして斜線状である異形部が含まれる表示デバイスであって、
    　前記異形部の外側に、前記延伸方向に対して斜めをなす第１辺および前記第１辺に直交し、かつ前記第１辺よりも短い第２辺を有する矩形領域に前記ドライバの単位回路が形成されてなる回路ブロックを複数含み、
    　各回路ブロックについては、前記矩形領域の形状が同一であり、前記第１辺と前記延伸方向とが成す鋭角が同一の値である表示デバイス。     The display device includes a driver outside the display area, and includes a deformed portion that has a curved shape or an oblique line on the edge of the display area with respect to the extending direction of the signal line in the display area. And
    A unit circuit of the driver is disposed outside the deformed portion in a rectangular region having a first side that is inclined with respect to the extending direction and a second side that is orthogonal to the first side and shorter than the first side. Including a plurality of formed circuit blocks,
    For each circuit block, the shape of the rectangular area is the same, and the acute angle formed by the first side and the extending direction is the same value.
  2. 　前記単位回路は複数の回路素子を含み、各斜め回路ブロックでは、前記複数の回路素子のレイアウトが共通とされている請求項１に記載の表示デバイス。 The display device according to claim 1, wherein the unit circuit includes a plurality of circuit elements, and each of the diagonal circuit blocks has a common layout of the plurality of circuit elements.
  3. 　複数の前記回路ブロックが前記異形部に沿って配されている請求項１または２に記載の表示デバイス。 3. The display device according to claim 1, wherein a plurality of the circuit blocks are arranged along the deformed portion.
  4. 　前記回路ブロックが前記第１辺に直交する方向に複数並べられてなる回路ユニットを複数備え、各回路ユニットが前記異形部に沿って配されている請求項１～３のいずれか１項に記載の表示デバイス。 The circuit unit according to any one of claims 1 to 3, comprising a plurality of circuit units in which a plurality of the circuit blocks are arranged in a direction orthogonal to the first side, and each circuit unit is arranged along the deformed portion. Display device.
  5. 　前記異形部の一端部の外側に位置する回路ブロック、前記異形部の他端部の外側に位置する回路ブロック、および前記異形部の中央の外側に位置する回路ブロックそれぞれについて、前記第１辺と前記延伸方向とが同一の鋭角をなす請求項４に記載の表示デバイス。 For each of the circuit block located outside one end of the deformed portion, the circuit block located outside the other end of the deformed portion, and the circuit block located outside the center of the deformed portion, the first side and The display device according to claim 4, wherein the extending direction forms the same acute angle.
  6. 　前記異形部の一端部の外側に位置する回路ブロックを含む回路ユニットと、前記異形部の他端部の外側に位置する回路ブロックを含む回路ユニットとについては、隣り合う回路ユニットから離隔するように配置され、
    　前記異形部の中央部の外側に位置する回路ブロックを含む回路ユニットについては、隣り合う回路ユニットと接するように配置されている請求項５に記載の表示デバイス。     A circuit unit including a circuit block located outside one end of the deformed portion and a circuit unit including a circuit block located outside the other end of the deformed portion are separated from adjacent circuit units. Arranged,
    The display device according to claim 5, wherein a circuit unit including a circuit block located outside the central portion of the deformed portion is disposed so as to be in contact with an adjacent circuit unit.
  7. 　前記表示領域のエッジは、前記異形部に繋がり、前記延伸方向に平行な直線部を含み、
    　前記直線部に平行な辺および垂直な辺を有する矩形領域に前記ドライバの単位回路が形成されてなる回路ブロックが、前記異形部の一端部の外側に位置する回路ブロックを含む回路ユニットと隣り合うように設けられている請求項５に記載の表示デバイス。     The edge of the display area is connected to the deformed portion, and includes a straight portion parallel to the extending direction,
    A circuit block in which a unit circuit of the driver is formed in a rectangular region having a side parallel to the straight line part and a side perpendicular to the straight line part is adjacent to a circuit unit including a circuit block located outside one end of the deformed part. The display device according to claim 5, provided as described above.
  8. 　前記鋭角が４５度である請求項１～７のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 7, wherein the acute angle is 45 degrees.
  9. 　前記信号線は、データ信号線、走査信号線、および発光信号線のいずれかである請求項１～８のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 8, wherein the signal line is any one of a data signal line, a scanning signal line, and a light emission signal line.
  10. 　前記異形部は曲線状であり、
    　前記異形部のうち接線が前記延伸方向に対して所定範囲の鋭角を成す部分の外側には２個の回路ユニットが前記第１辺の延伸方向に接するように配され、所定範囲外の鋭角を成す部分の外側には回路ユニットが単体で配されている請求項４に記載の表示デバイス。     The deformed portion is curved,
    Two circuit units are arranged outside the portion of the deformed portion where the tangent forms an acute angle within a predetermined range with respect to the extending direction so that the circuit unit is in contact with the extending direction of the first side. The display device according to claim 4, wherein a circuit unit is arranged as a single unit outside the formed portion.
  11. 　前記異形部が曲線状であり、前記外側に向けて凸型である請求項１～１０のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 10, wherein the deformed portion has a curved shape and is convex toward the outside.
  12. 　発光素子と、前記発光素子に接続するサブ画素回路とを備え、
    　前記ドライバが前記サブ画素回路と同層に形成されている請求項１～１１のいずれか１項に記載の表示デバイス。     A light emitting element, and a sub-pixel circuit connected to the light emitting element,
    The display device according to any one of claims 1 to 11, wherein the driver is formed in the same layer as the sub-pixel circuit.
  13. 　前記ドライバは走査信号線を駆動する請求項１～１２のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 12, wherein the driver drives a scanning signal line.
  14. 　前記ドライバは発光信号線を駆動する請求項１～１２のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 12, wherein the driver drives a light emitting signal line.
PCT/JP2018/010305 2018-03-15 2018-03-15 Display device WO2019176066A1 (en)

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CN114667553A (en) * 2020-10-23 2022-06-24 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device

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CN114667553A (en) * 2020-10-23 2022-06-24 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device
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