JP2019032557A - Display device - Google Patents

Abstract

To provide a display device that has a circuit configuration element designed to contribute to a high accuracy.SOLUTION: The present invention includes: a thin film transistor DRT on a surface of a substrate B1, the transistor DRT having a semiconductor layer AS and a gate electrode GT; a source electrode ST connected to a region of the semiconductor layer AS which is doped with impurities; a pixel electrode AD connected to the source electrode ST; and a metal layer MT below the pixel electrode AD. The source electrode GT, the source electrode ST, the metal layer MT, and the pixel electrode AD are sequentially overlapped in a planar view in descending order of closeness to the substrate B1.SELECTED DRAWING: Figure 5A

Description

  The present invention relates to a display device.

  2. Description of the Related Art An organic EL display device is known as one of display devices including a self-light emitting element in a pixel circuit.

  In each pixel of the organic EL display device, a light emitting element including a common electrode, a pixel electrode (pixel electrode), and an organic layer sandwiched therebetween is disposed. In the organic layer, light is emitted by recombination of holes and electrons injected from the pixel electrode and the common electrode.

  In the pixel circuit in the organic EL display device, in addition to the light emitting elements, a plurality of switching elements and circuit constituent elements such as elements constituting a capacitance portion are arranged.

  Note that Patent Document 1 provides a mechanism that can prevent adverse effects caused by overlapping of scanning lines that supply signals to each pixel circuit of a pixel array unit with auxiliary wirings on the outer periphery of the pixel array unit. The effect is described.

JP 2009-175389 A

  In the display device as described above, higher definition of pixels is required.

  However, when the pixel size is reduced, the arrangement and structure of circuit components are limited.

  In view of the above problems, an object of the present invention is to provide a display device including a circuit component having a structure that can contribute to high definition.

  (1) A display device according to the present invention includes a thin film transistor having a semiconductor layer and a gate electrode provided on an insulating surface, a first electrode connected to a region to which an impurity is added in the semiconductor layer, A pixel electrode connected to the first electrode; and a conductive layer disposed under the pixel electrode, wherein the gate electrode, the first electrode, the conductive layer, and the pixel electrode are insulated from each other. They are superimposed in plan view in this order from the side close to the surface.

1 is a plan view schematically showing an organic EL display device according to a first embodiment. It is a figure for demonstrating the pixel circuit of the organic electroluminescence display in 1st Embodiment. It is a figure which shows the timing chart of the signal input from each wiring connected to the pixel circuit in 1st Embodiment. It is a figure for demonstrating the planar structure of the pixel of the organic electroluminescent display apparatus in 1st Embodiment. It is a figure which shows the mode of the II cross section in FIG. 3, II-II cross section, and the cross section outside a display area. It is a figure for demonstrating the pixel structure of the organic electroluminescent display apparatus of a comparative example. It is a figure for demonstrating the planar shape of each layer which comprises the pixel of the organic electroluminescence display in 1st Embodiment.

  Hereinafter, organic EL display devices according to embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic plan view for explaining the organic EL display device of the first embodiment. In the display area DP of the organic EL display device of the present embodiment, a plurality of pixels PX to be subjected to display control are arranged in a matrix, and an organic electroluminescence element (light emitting element) is arranged in each pixel PX. The organic electroluminescence element of each pixel PX includes an organic layer having a light emitting layer. Each pixel PX includes a video signal line driving circuit XDR disposed outside the display region DP, a first scanning line. Signals from the drive circuit Ydr1 and the second scanning line drive circuit Ydr2 are input.

  As shown in FIG. 1, the first scanning line BG, the second scanning line SG, the reset wiring Vrst, and the video signal line Data are connected to each pixel PX in the display area DP. The first scanning lines BG1 to BGM, the second scanning lines SG1 to SGM, and the reset lines Vrst1 to VrstM are laid so as to be parallel to the X direction, and the video signal lines Data1 to DataN are parallel to the Y direction. Will be laid.

  FIG. 2 is a diagram for explaining the configuration of the pixel circuit of the first organic EL display device. As shown in the figure, the pixel circuit of the organic EL display device of the present embodiment includes a pixel switch SST, a drive transistor DRT, an output switch BCT, a holding capacitor Cs, an auxiliary capacitor Cad, and an element capacitor. Cel is included, and the second scanning line driving circuit unit Ydr2 further includes a reset switch RST. The pixel switch SST and the like are constituted by thin film transistors.

  The output switch BCT and the drive transistor DRT are connected in series with the light emitting element between the high potential voltage power source Pvdd and the low potential voltage power source Pvss. In the output switch BCT, its gate electrode is connected to the first scanning line BG, and ON / OFF control is performed by a control signal from the first scanning line BG. The output switch BCT controls the light emission time of the light emitting element.

  The gate electrode of the drive transistor DRT is connected to the pixel switch SST and the storage capacitor Cs. The video signal input via the pixel switch SST is maintained as a gate control voltage by being written in the storage capacitor Cs, and the current supplied from the driving transistor DRT to the light emitting element is controlled. The storage capacitor Cs holds a potential difference between the gate electrode and the source electrode (electrode on the light emitting element side) in the driving transistor DRT.

  The pixel switch SST has a gate electrode connected to the second scanning line SG and a source electrode connected to the video signal line Data. A video signal and an initial potential are input from the video signal line Data to the pixel switch SST in synchronization with the scanning signal from the second scanning line SG.

  The reset switch RST is arranged in the second scanning line driving circuit Ydr2, and when the potential to be turned on is input from the wiring RG, the reset potential is supplied from the reset wiring Vrst to each pixel circuit. When the output switch BCT is in the OFF state, the pixel switch SST is in the OFF state, and the reset switch RST is in the ON state, the potential of the source / drain electrodes of the drive transistor DRT is set to the same potential as the potential of the reset power supply.

  The video signal writing operation is performed in synchronization with the control signal from the second scanning line SG that turns on the pixel switch SST and the control signal from the first scanning line BG that turns on the output switch BCT. This is executed by inputting the video signal from the line Data to the gate electrode of the drive transistor DRT. The auxiliary capacitor Cad is an element provided for adjusting the amount of current supplied to the light emitting element. In the display device of the present embodiment, the auxiliary capacitance Cad is ensured because the element capacitance Cel alone is insufficient.

  The operation of the pixel circuit shown in FIG. 2 will be described below using the timing chart shown in FIG. In FIG. 3, a period of 1H corresponds to one line period (one horizontal period). Here, for the sake of simplicity, a certain k-th row and the next k + 1-th row are shown.

  First, a source initialization operation is performed in a period indicated by Pis in FIG. In the source initialization operation, at a certain k-th row, the control signal for the second scanning line SGk is output at a level that turns off the pixel switch SST (off potential: low level here), and the control signal for the first scanning line BGk is output. The level at which the switch BCT is turned off (off potential: low level in this case), and the control signal of the wiring RGk is set at a level at which the reset switch RST is turned on (on potential: here high level).

  The output switch BCT and the pixel switch SST are turned off (non-conductive state), the reset switch RST is turned on (conductive state), and the source initialization operation is started. When the reset switch RST is turned on, the source electrode and the drain electrode of the drive transistor DRT are reset to the same potential as the potential of the reset power supply (the potential supplied to the reset wiring Vrst), and the source initialization operation is completed. Here, the reset power supply (the potential of the reset power supply) is set to −2 V, for example.

  Next, a gate initialization operation is performed in the period indicated by Pig in FIG. In the gate initialization operation, at a certain k-th row, the control signal for the second scanning line SGk is output at a level that turns on the pixel switch SST (ON potential: high level here), and the control signal for the first scanning line BGk is output. The level at which the switch BCT is turned off and the control signal for the wiring RGk are set at the level at which the reset switch RST is turned on. The output switch BCT is turned off, the pixel switch SST and the reset switch RST are turned on, and the gate initialization operation is started.

  In the gate initialization period Pig, the initialization signal Vini (initialization voltage) output from the video signal line is applied to the gate electrode of the driving transistor DRT through the pixel switch SST. As a result, the potential of the gate electrode of the drive transistor DRT is reset to a potential corresponding to the initialization signal Vini, and information of the previous frame is initialized. The voltage level of the initialization signal Vini is set to 2V, for example.

  Subsequently, an offset cancel operation is performed in a period indicated by Po in FIG. In the offset cancel operation, in a certain k-th row, the control signal for the second scanning line SGk is on potential, the control signal for the first scanning line BGk is on potential (high level), and the control signal for the wiring RGk is off potential (low level). ) As a result, the reset switch RST is turned off, the pixel switch SST and the output switch BCT are turned on, and the threshold value offset cancel operation is started.

  In the offset cancel period Po, the initialization signal Vini is applied to the gate electrode of the drive transistor DRT through the video signal line and the pixel switch SST, and the potential of the gate electrode of the drive transistor DRT is fixed.

  Further, the output switch BCT is in an on state, and a current flows from the high potential power supply Pvdd to the drive transistor DRT. The potential of the source electrode of the drive transistor DRT is initially set to the potential (reset potential Vrst) written in the source initialization period Pis, and the current flowing through between the drain electrode and the source electrode of the drive transistor DRT is gradually reduced. In the meantime, the TFT shifts to the high potential side while absorbing and compensating for the TFT characteristic variation of the drive transistor DRT. In the present embodiment, the offset cancellation period Po is set to a time of about 1 μsec, for example.

  At the end of the offset cancellation period Po, the potential of the source electrode of the drive transistor DRT becomes Vini−Vth. Vini is the voltage value of the initialization signal Vini, and Vth is the threshold voltage of the drive transistor DRT. As a result, the voltage between the gate electrode and the source electrode of the drive transistor DRT reaches the cancel point (Vgs = Vth), and the potential difference corresponding to the cancel point is stored (held) in the storage capacitor Cs.

  Subsequently, a video signal writing operation is performed in a period indicated by Pw in FIG. In the video signal writing period Pw, in a certain k-th row, the control signal for the second scanning line SGk is at a level for turning on the pixel switch SST, and the control signal for the first scanning line BGk is at a level for turning on the output switch BCT. The control signal for the wiring RGk is set to a level that turns off the reset switch RST. Then, the pixel switch SST and the output switch BCT are turned on, the reset switch RST is turned off, and the video signal writing operation is started.

  In the video signal writing period Pw, the video signal Vsig is written from the video signal line Data to the gate electrode of the drive transistor DRT through the pixel switch SST. Further, a current flows from the high potential power supply Pvdd through the output switch BCT and the drive transistor DRT to the low potential power supply line via the capacitance portion (parasitic capacitance) Cel of the diode OLED. By the operation so far, the potential based on the video signal Vsig and the threshold voltage acquired at the time of offset cancellation is written to the gate of the driving transistor DRT, and the variation in mobility of the driving transistor DRT is corrected.

  Finally, the display operation is performed in the period indicated by Pd in FIG. In the display period Pd, the control signal for the second scanning line SG is at a level for turning off the pixel switch SST, the control signal for the first scanning line BG is at a level for turning on the output switch BCT, and the control signal for the wiring RG is reset. It is set to a level at which the switch RST is turned off. The output switch BCT is turned on, the pixel switch SST and the reset switch RST are turned off, and the display operation is started.

  The drive transistor DRT outputs a drive current Iel having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Iel is supplied to the diode OLED. As a result, the diode OLED emits light with a luminance corresponding to the drive current Iel, and a display operation is performed. The diode OLED maintains the light emitting state after one frame period until the control signal of the first scanning line BG becomes the off potential again.

  The above-described source initialization operation, gate initialization operation, offset cancellation operation, video signal writing operation, and display operation are sequentially performed on each pixel PX in the kth and subsequent rows, thereby displaying a desired image.

  By the way, a parasitic capacitance Cp is generated between the gate electrode of the driving transistor DRT and the wiring to which the high potential voltage or the low potential voltage is supplied. The presence of such a parasitic capacitance Cp may cause an undesirable capacitance coupling when the gate of the drive transistor DRT is changed to a desired potential in the offset cancel operation and the video signal write operation described above.

  Here, the configuration of the circuit component in the present embodiment will be specifically described.

  FIG. 4 is a plan view of the pixel structure in the present embodiment.

  FIG. 4 shows a planar configuration of sub-pixels in the present embodiment. In the present embodiment, one main pixel is configured by four sub-pixels. As shown in the figure, a first scanning line BG, a second scanning line SG laid in the X direction, a video signal line Data laid in the Y direction, and a power supply line PL are arranged.

  In the sub-pixel of FIG. 4, a double-gate structure driving transistor DRT is disposed at a location on the right-hand II-II cross section, and a pixel switch SST is disposed at an upper left location. In the present embodiment, a metal layer (not shown in FIG. 4) covers an area of about three-quarters in the subpixel, and the gate electrode GT and the source electrode ST in the driving transistor DRT are arranged in the subpixel. In a relatively large area.

  Next, FIG. 5A corresponds to the II cross section, the II-II cross section, and the predetermined cross section outside the display area DP in FIG. In FIG. 4, the metal layer, the pixel electrode, and the configuration on the upper side thereof are omitted for convenience, but in the cross-sectional view of FIG. 5A, the metal layer MT and the like are displayed. As shown in these drawings, the II section corresponds to the contact portion between the source electrode ST and the pixel electrode AD of the drive transistor DRT, and the II-II section represents the position of the drive transistor DRT having a double gate structure. (See also FIG. 6).

  An organic layer (not shown) and a common electrode are disposed above the pixel electrode AD, and a light emitting element is configured by these. Further, the pixel electrode AD is individually arranged in each pixel and functions as an anode electrode (anode), and the common electrode functions as a cathode electrode (cathode) common to a plurality of pixels. In the present embodiment, the pixel electrode AD is configured to include a transparent conductive film (for example, ITO: Indium Tin Oxide) and a reflective conductive film made of a reflective metal such as aluminum or silver. Is constituted by a transparent conductive film.

  A driving transistor DRT composed of a top gate type thin film transistor is disposed below the pixel electrode AD. The drive transistor DRT includes a semiconductor layer AS formed on the substrate B1, a gate electrode GT, and a source electrode ST and a drain electrode DT connected to the semiconductor layer AS through contact holes.

  In the semiconductor layer AS, a portion overlapping in plan view with the gate electrode GT becomes a channel region, and a voltage is applied to the gate electrode GT so that a current input from the power supply line PL via the drain electrode DT can be controlled. Done. Further, in the semiconductor layer AS, a portion that does not overlap with the gate electrode GT in a plan view is doped with impurities, and a process of reducing electric resistance and functioning as a conductor is performed.

  A gate insulating film GI made of silicon oxide (SiOx) or silicon nitride (SiNy) is disposed between the semiconductor layer AS and the gate electrode GT, and the gate insulating film GI is made of silicon oxide (SiOx) or silicon nitride. It is covered with an interlayer insulating film SI (first insulating layer) made of an inorganic insulating film such as (SiNy). The source electrode ST and the drain electrode DT are connected to a region where the impurity of the semiconductor layer AS is implanted through a contact hole formed by the gate insulating film GI and the interlayer insulating film SI.

  Further, a planarization layer HR (second insulating layer) for reducing a step due to the drive transistor DRT or the like is disposed above the drive transistor DRT. The planarization layer HR is composed of an organic insulating film.

  In the display device according to the present embodiment, the metal layer MT is disposed on the planarization layer HR, and a passivation layer PA (which is formed of an inorganic insulating film such as silicon nitride) is provided between the metal layer MT and the pixel electrode AD. A third insulating layer) is disposed. A low potential voltage power supply Pvss is supplied to the metal layer MT from a power supply wiring PW arranged outside the display region DP, and an auxiliary capacitance Cad is formed between the pixel electrode AD and the metal layer MT. In the present embodiment, in order to secure a large auxiliary capacitance Cad, the overlapping area between the metal layer MT and the pixel electrode AD is as large as possible, and the portion excluding the contact portion between the pixel electrode AD and the source electrode ST is made of metal. The layer MT is formed to cover.

  Here, in particular, in the display device of the present embodiment, in the driving transistor DRT located below the metal layer MT, the source electrode ST extends above the channel region, and the gate electrode GT and the metal layer overlapping the channel region. It is designed to intervene with MT. FIG. 5B is a diagram showing a comparative example. As shown in FIG. 5B, when the source electrode ST does not extend above the channel region, the region between the gate electrode GT and the metal layer MT overlapping the channel region is shown. Parasitic capacitance Cp occurs. On the other hand, when the source electrode ST extends as in the present embodiment of FIG. 5A, the generation of the parasitic capacitance Cp is not only suppressed, but a new auxiliary is provided between the source electrode ST and the metal layer MT. The capacitance Cad is generated, and the storage capacitance Cs between the source electrode ST and the gate electrode GT is increased. Therefore, as shown in FIG. 5A, by adopting the drive transistor DRT in which the source electrode ST covers the channel region and the gate electrode GT on the upper side thereof, the auxiliary capacitance Cad and the holding capacitance Cs are reduced while suppressing the generation of the parasitic capacitance Cp. This can be further increased, thereby contributing to efficient arrangement and high definition of circuit components.

  FIG. 6 is a diagram for explaining in detail the planar shape of the constituent layers such as the drive transistor DRT in the pixel of the display device of the present embodiment. 6B to 6E show the planar shapes of the respective layers and the metal layer MT constituting the drive transistor DRT in FIG. 6A. Specifically, FIG. 6B shows a formation region of the semiconductor layer AS, FIG. 6C shows a formation region of the gate electrode GT formed above the semiconductor layer AS, and FIG. d) shows the formation region of the source electrode ST and drain electrode DT formed above the gate electrode GT, and FIG. 6E shows the metal layer MT formed above the source electrode ST and drain electrode DT. The formation region is shown.

  As shown in FIG. 6, in the display device of this embodiment, the channel region in the semiconductor layer AS (the formation region of the gate electrode GT overlapping the channel region) and the impurity region sandwiching the channel region are included in the source electrode ST. It overlaps with the formation region and the formation region of the metal layer MT. In other words, a region in which current flows in the semiconductor layer AS of the drive transistor DRT (region between the connection point with the source electrode ST and the connection point with the drain electrode DT) overlaps with the formation region of the metal layer MT in a plane. A region where the source electrode ST is formed extends between the channel region of the metal layer MT and the semiconductor layer AS.

  6B to 6D correspond to the connection points by the contact holes. The wiring layer disposed in the upper left part of FIG. 6D supplies a video signal from the pixel switch SST to the gate electrode GT, and the wiring layer connects the pixel switch SST via the contact hole. The semiconductor layer is connected to the gate electrode GT.

  In the display device of this embodiment, the driving transistor DRT has a double gate structure. However, the driving transistor DRT is not limited to such a mode, and may be a single gate thin film transistor or a triple gate thin film transistor. There may be. Further, as in the present embodiment, it is desirable that the two channel regions and the source electrode ST in the double gate structure overlap in a planar manner. However, as the source electrode ST, one channel region partially overlaps the other. Even if it does not overlap with the channel region, it is within the scope of the present invention. As shown in FIG. 5A, the source electrode ST desirably overlaps with three impurity regions sandwiching two channel regions in a planar manner. For example, the source electrode ST is planar with one of the three impurity regions. Even those that do not overlap with each other fall within the scope of the present invention.

  In the display device of this embodiment, the light emitting element is an organic electroluminescence element. However, the present invention is not limited to such an embodiment. For example, a quantum dot light emitting diode (QLED) is used. Such other self-luminous elements may be used. Further, although the common electrode functions as a cathode and the pixel electrode AD functions as an anode, the output switch BCT is connected to a low potential so that the common electrode functions as an anode and the pixel electrode AD functions as a cathode. The voltage power supply Pvss may be supplied.

  Further, the power supply wiring PW connected to the metal layer MT outside the display region DP may be formed of the same material in the same process as the source electrode ST or in the same process as the gate electrode GT. You may form with the same material. A high potential voltage power supply Pvdd may be input from the power supply wiring PW.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. In the scope of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. In addition, for example, those in which the person skilled in the art appropriately added, deleted, or changed the design of the above-described embodiments, or added the process, omitted, or changed the conditions are also included in the present invention. As long as the gist of the present invention is provided, it is included in the scope of the present invention.

  XDR video signal line drive circuit, Ydr1 first scan line drive circuit, Ydr2 second scan line drive circuit, BG first scan line, SG second scan line, PX pixel, SST pixel switch, DRT drive transistor, BCT output switch, RST reset switch, Cs holding capacitor, Cad auxiliary capacitor, Cel element capacitor, RG wiring, DT drain electrode, ST source electrode, GT gate electrode, AS semiconductor layer, PL power supply line, B1 substrate, AD pixel electrode, PA passivation layer GI gate insulation film, SI interlayer insulation film, HR planarization layer, MT metal layer, PW power supply wiring.

Claims (6)

A thin film transistor having a semiconductor layer and a gate electrode provided over an insulating surface;
A first electrode connected to an impurity-doped region of the semiconductor layer;
A pixel electrode connected to the first electrode;
A conductive layer disposed under the pixel electrode,
The display device, wherein the gate electrode, the first electrode, the conductive layer, and the pixel electrode overlap in this order from a side close to the insulating surface in a plan view. The display device according to claim 1,
A first insulating layer between the gate electrode and the first electrode;
Having a second insulating layer between the first electrode and the conductive layer;
A display device comprising a third insulating layer between the conductive layer and the pixel electrode. The display device according to claim 1 or 2,
A display device characterized in that a region where the impurity is added and the region where the first electrode is connected and a region where the first electrode and the pixel electrode are connected do not overlap in a plan view. . The display device according to any one of claims 1 to 3,
A light emitting element connected in series with the thin film transistor between a high potential voltage power source and a low potential voltage power source having a potential difference from each other;
The light emitting element has the pixel electrode, an organic layer provided on the pixel electrode, and a common electrode provided on the organic layer,
The display device, wherein the conductive layer and the common electrode are connected to the low potential voltage power source. The display device according to claim 4,
A display region in which a plurality of pixels including the pixel electrode are arranged;
The display device, wherein the conductive layer extends to the outside of the display region and is connected to the low potential voltage power source outside the display region. The display device according to claim 5,
The display device, wherein the conductive layer is continuously provided over at least two of the plurality of pixels in the display region.

Images