KR20220076173A - Electroluminescent display apparatus and manufacturing method of thereof - Google Patents

Abstract

The present specification relates to an electroluminescent display device and a method for manufacturing the same.
An electroluminescent display device according to the present specification includes a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area, a driving circuit for transmitting a driving signal to the display panel, and a high potential voltage to the display panel and a first layer electrically connected to the display panel and the power supply, and covering the light emitting area.

Description

Electroluminescent display apparatus and manufacturing method thereof

The present specification relates to an electroluminescent display device and a manufacturing method thereof, and an electroluminescent display capable of supplying high potential voltage to each pixel through a high potential voltage (ELVDD) front layer disposed to cover the entire surface of a display panel It relates to a device and a method for manufacturing the same.

An electroluminescent display device to which an organic light emitting diode (OLED), which is one of display devices, is applied has high luminance and low operating voltage characteristics.

Since such an electroluminescent display device is a self-luminous type that emits light by itself, the contrast ratio is large, it is possible to implement an ultra-thin display, and it is easy to implement a moving image with a response time of several microseconds, and the viewing angle is limited. It is stable even at low temperature, and it is driven with a low voltage of 5 to 15 V of DC, so it has the advantage of easy manufacturing and design of the driving circuit.

In addition, since deposition and encapsulation are all in the manufacturing process of the electroluminescent display device, the manufacturing process is very simple.

A plurality of thin film transistors such as a switching thin film transistor, a driving thin film transistor (D-TR), and a sensing thin film transistor are formed in each pixel region of the electroluminescent display device.

ELVDD wires supplying a high potential voltage (hereinafter referred to as ELVDD) are connected to the display panel of the electroluminescent display in the form of a vertical or horizontal and vertical mesh.

The ELVDD node is connected to the driving thin film transistor D-TFT, and when an ELVDD voltage drop occurs, the OLED current of the driving thin film transistor is affected.

Accordingly, the pixels of the vertical line to which the ELVDD wiring is connected are affected by the ELVDD voltage drop and have lower luminance than the pixels of the portion without the white box, and the larger the white box pattern is, the worse it is.

Accordingly, when the ELVDD wiring is connected only vertically to each pixel, crosstalk is generated more than that of the wiring having a horizontal pattern.

Accordingly, the inventors of the present specification set out to cover the front surface of the display panel in order to solve the problem that crosstalk occurs due to the influence of high potential voltage (ELVDD) wiring connected in a vertical pattern in the electroluminescent display device. An electroluminescent display device in which a first layer is disposed and a high potential voltage can be respectively supplied to each pixel through the first layer was invented.

In addition, the inventors of the present specification have formed a first film between a gate electrode and a source-drain electrode when manufacturing a display panel of an electroluminescent display device, insulate upper and lower portions of the first film by an insulating film, and contact holes of the insulating film A method for manufacturing an electroluminescent display device in which a high potential voltage is supplied to the source drain electrode of the thin film transistor by the first layer by electrically connecting the first layer and the source drain electrode by

The above-described objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned can be understood by the following description, and will be more clearly understood by the examples of the present invention. will be. It will also be readily apparent that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the appended claims.

An electroluminescent display device according to an embodiment of the present specification includes a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area, a driving circuit for transmitting a driving signal to the display panel, and a display panel A power supply unit for supplying a high potential voltage, and a first layer electrically connected to the display panel and the power supply unit and covering the light emitting area.

An electroluminescent display device according to an embodiment of the present specification includes a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area, a driving circuit for transmitting a driving signal to the display panel, and a display panel A power supply unit for supplying a high potential voltage, and a first layer electrically connected to the display panel and the power supply unit and covering the light emitting area and the non-emission area.

In addition, the method of manufacturing an electroluminescent display device according to an embodiment of the present specification includes the steps of (a) forming a first active layer and a second active layer on a substrate including a light emitting region and a non-emitting region, (b) a first forming a first insulating film on the active film and the second active film; (c) forming a first gate electrode and a second gate electrode on the first insulating film; (d) the first gate electrode and the second gate forming a second insulating film on the electrode, (e) forming a power supply wiring on the second insulating film, (f) forming the second insulating film and a third insulating film on the power supply wiring, (g) power supply forming a first film on the third insulating film in contact with the wiring by the first contact hole, (h) forming a fourth insulating film on the first film, (i) on the first film and on the second contact hole and forming a source-drain electrode in contact with the fourth insulating film on the fourth insulating film, and (j) forming a planarization film on the source-drain electrode.

According to an embodiment of the present specification, a transparent conductive material may be disposed on the entire surface of the high potential voltage line for applying the high potential voltage to the display panel.

Therefore, since the voltage drop of the high potential voltage wiring that occurs when a pattern with high power consumption is on a part of the screen can be uniformly applied to the entire panel, crosstalk can be achieved by reducing the luminance effect of a specific part of the display panel. It has the effect of reducing awareness.

In addition, according to the exemplary embodiment of the present specification, by disposing the first layer between the gate electrode and the source drain electrode on the high potential voltage line that applies the high potential voltage to the display panel, the resistance of the high potential voltage line is reduced and thus a crosstalk phenomenon occurs. This can be improved.

In addition, according to the embodiment of the present specification, a pattern with high power consumption, such as a white pattern, is displayed on the screen by disposing a first layer for applying a high potential voltage to each pixel of the display panel between the gate electrode and the source and drain electrode. The voltage drop of the high-potential voltage wiring that occurs when providing to a portion can be uniformly applied to the entire panel.

Accordingly, according to the embodiment of the present specification, by applying the high potential voltage wiring to the entire panel using the transparent conductive layer, the luminance effect of a specific portion of the display panel can be enjoyed, and crosstalk caused by the voltage drop of the high potential voltage wiring It has the effect of reducing awareness.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

In addition to the above-described effects, the specific effects of the present invention will be described together while describing specific details for carrying out the invention below.

1 is a view showing an electroluminescent display device according to an embodiment of the present specification.
FIG. 2 is a circuit diagram illustrating an embodiment of the pixel shown in FIG. 1 in the electroluminescent display device according to the embodiment of the present specification.
3 is a diagram illustrating a pixel arrangement of an electroluminescence display according to an exemplary embodiment of the present specification.
4 is a plan view of a structure of a first layer, a power supply wiring, and a source/drain wiring according to an exemplary embodiment of the present specification as viewed from above.
FIG. 5 is a cross-sectional view taken along line AA′ of FIG. 1 .
6A to 6C are diagrams illustrating a method of manufacturing an electroluminescent display device according to an exemplary embodiment of the present specification.
7 to 17 are cross-sectional views illustrating a process of manufacturing an electroluminescent display device according to an exemplary embodiment of the present specification.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and the text It should not be construed as being limited to the embodiments described in

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

The above-described objects, features and advantages will be described below in detail with reference to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention.

In describing the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Hereinafter, an embodiment according to the present specification will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

In addition, when it is described that a component is “connected”, “coupled” or “connected” to another component, the components may be directly connected or connected to each other, but other components are “interposed” between each component. It should be understood that “or, each component may be “connected,” “coupled,” or “connected,” through another component. On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that there is no other element in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this application, terms such as "comprises" or "having" are intended to designate that the disclosed feature, number, step, action, component, part, or combination thereof exists, but includes one or more other features or numbers, It should be understood that the possibility of the presence or addition of steps, operations, components, parts or combinations thereof is not precluded in advance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

On the other hand, when a certain embodiment can be implemented differently, functions or operations specified in a specific block may occur in a different order from that specified in the flowchart. For example, two consecutive blocks may be performed substantially simultaneously, or the blocks may be performed in reverse according to a related function or operation.

Reference to an element or layer to another element or “on” or “on” includes not only directly on the other element or layer, but also with other layers or other elements interposed therebetween. do. On the other hand, reference to an element "directly on" or "directly on" indicates that there are no intervening elements or layers.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, if an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the scope where the configuration of the present invention can function functionally. It may mean having a direction.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

Hereinafter, an electroluminescent display device and a manufacturing method thereof according to an embodiment of the present specification will be described.

1 is a view showing an electroluminescent display device according to an embodiment of the present specification.

Referring to FIG. 1 , the electroluminescent display device 100 according to the embodiment of the present specification includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply unit 40 , and a display panel 50 . ) and a high potential voltage front layer 60 .

The timing controller 10 controls the gate driver 20 and the data driver 30 . The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

The timing controller 10 implements the image signal RGB and the control signal CS to suit the operating conditions of the display panel 50 , so that the image data DATA, the gate driving control signal CONT1, and the data driving control signal are implemented. (CONT2) and power supply control signal (CONT3) can be generated and output.

The timing controller 10 may control the gate driver 20 and the data driver 30 by supplying a control signal to the gate driver 20 and the data driver 30 . The timing controller 10 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to match the data signal format used by the data driver 30, and outputs the converted image data, , it is possible to control the data operation at an appropriate time according to the scan.

A driving circuit that transmits a driving signal to the display panel 50 may include a gate driver 20 and a data driver 30 .

The gate driver 20 may drive a plurality of gate lines GL1 to GLn. For example, the gate driver 20 may sequentially drive the plurality of gate lines by sequentially supplying scan signals to the plurality of gate lines. The data driver 30 may drive a plurality of data lines by supplying a data voltage to the plurality of data lines.

The gate driver 20 sequentially supplies a scan signal of an on voltage or an off voltage to the plurality of gate lines GL1 to GLn under the control of the timing controller 10 to the plurality of gate lines GL1 . ~GLn) can be driven sequentially. Also, as shown in FIG. 1 , the gate driver 20 may be located on only one side of the display panel 150 , or on both sides in some cases, depending on a driving method or a design of the display panel.

The gate driver 20 may be connected to the pixels PX of the display panel 50 through the plurality of gate lines GL1 to GLn. The gate driver 20 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 10 . The gate driver 20 may provide the generated gate signals to the pixels PX through the plurality of gate lines GL1 to GLn.

Also, the gate driver 20 may include one or more gate driver integrated circuits. Each gate driver integrated circuit is connected to a bonding pad of the display panel 50 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or a gate in panel (GIP) type. , and may be directly disposed on the display panel 50 . As another example, the display panel 50 may be integrated and disposed.

In addition, each gate driver integrated circuit may be implemented in a Chip On Film (COF) method. A gate driving chip corresponding to each gate driver integrated circuit may be mounted on a flexible film, and one side of the flexible film may be bonded to the display panel 50 .

The data driver 30 may drive a plurality of data lines DL1 to DLm. For example, when a specific gate line is opened, the data driver 30 converts the image data received from the timing controller 10 into an analog data voltage and supplies it to the plurality of data lines, thereby driving the plurality of data lines. have.

The data driver 30 may be connected to the pixels PX of the display panel 50 through a plurality of data lines DL1 to DLm. The data driver 30 may generate data signals based on the image data DATA output from the timing controller 10 and the data driving control signal CONT2 . The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

The data driver 30 may include at least one source driver integrated circuit to drive a plurality of data lines.

Each source driver integrated circuit is connected to a bonding pad of the display panel 50 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or directly to the display panel 50 . may be placed. As another example, the display panel 50 may be integrated and disposed.

In addition, each source driver integrated circuit may be implemented in a chip on film (COF) method. A source driving chip corresponding to each source driver integrated circuit is mounted on a flexible film, one side of the flexible film is bonded to at least one source printed circuit board, and the other side is to be bonded to the display panel 50 . can

The source printed circuit board may be connected to the control printed circuit board through a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC). The timing controller 10 may be disposed on the control printed circuit board.

In addition, a power controller (not shown) for supplying voltage or current to the display panel 50 , the data driver 30 , and the gate driver 20 or controlling the voltage or current to be supplied may be further disposed on the control printed circuit board have. The above-mentioned source printed circuit board and control printed circuit board may be configured as a single printed circuit board.

The power supply unit 40 may be connected to the pixels PX of the display panel 50 through a plurality of power lines PL1 and PL2 . The power supply unit 40 may generate a driving voltage to be provided to the display panel 50 based on the power supply control signal CONT3 . The driving voltage may include, for example, a high potential driving voltage ELVDD and a low potential driving voltage ELVSS. The power supply unit 40 may provide the generated driving voltages ELVDD and ELVSS to the pixels PX through the corresponding power lines PL1 and PL2 .

The display panel 50 may include a light-emitting area AA and a non-emission area NA, and may include a plurality of pixels PX (or referred to as sub-pixels) disposed in the light-emitting area. have. The pixels PX may be arranged, for example, in a matrix form on the display panel 50 . The sub-pixel PX may be a unit in which a specific color filter is formed or a color filter is not formed and the organic light emitting device can emit a special color. The color defined by the sub-pixel may include red (R), green (G), blue (B), and optionally white (W), but is not limited thereto.

The display panel 50 may include a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn. Each pixel PX may be electrically connected to a corresponding gate line GL1 to GLn and a data line DL1 to DLm. The pixels PX may emit light with luminance corresponding to the gate signal and the data signal supplied through the gate lines GL1 to GLn and the data lines DL1 to DLm.

Each pixel PX may display any one of the first to third colors. In the exemplary embodiment of the present specification, each pixel PX may display any one color of red (R), green (G), and blue (B). In another embodiment, each pixel PX may display one or more colors of cyan, magenta, and yellow. In various embodiments, the pixels PX may be configured to display any one or more of four or more colors. For example, each pixel PX may display one or more colors of red (R), green (G), blue (B), and white (W).

In addition, a switching thin film transistor Tsw, a driving thin film transistor Tdr, a sensing thin film transistor Tse, a storage capacitor Cst, and a light emitting diode Del may be formed in each pixel PX.

The switching thin film transistor Tsw, the driving thin film transistor Tdr, and the sensing thin film transistor Tse each include an active layer ACT, a gate electrode GE, a source electrode SE and a drain electrode DE, The light emitting diode Del includes an anode electrode AE, a light emitting layer OLE, and a cathode electrode CE.

The gate electrode GE, the source electrode SE, and the drain electrode DE of the switching thin film transistor Tsw are the gate line GL, the data line DL, and the gate electrode GE of the driving thin film transistor Tdr, respectively. can be connected to The gate electrode GE, the source electrode SE, and the drain electrode DE of the driving thin film transistor Tdr are respectively the drain electrode of the switching thin film transistor Tsw, the anode of the light emitting diode Del, and the power wiring PL ) can be connected to The anode and the cathode of the light emitting diode Del may be respectively connected to the source electrode and the low potential voltage Vss of the driving thin film transistor Tdr.

In addition, the electrode connected to the thin film transistor for controlling light emission of each sub-pixel area of the display panel 50 may be a first electrode, and the electrode disposed on the front surface of the display panel 50 or disposed to include two or more pixel areas may be the second electrode. When the first electrode is the anode electrode AE, the second electrode becomes the cathode electrode CE, and vice versa. Hereinafter, an anode electrode as an embodiment of the first electrode and a cathode electrode as an embodiment of the second electrode will be described, but the present specification is not limited thereto.

The timing controller 10 , the gate driver 20 , the data driver 30 , and the power supply unit 40 are each composed of a separate integrated circuit (IC) or at least a part of an integrated circuit. . For example, at least one of the data driver 30 and the power supply unit 40 may be configured as an integrated circuit integrated with the timing controller 10 .

Also, although the gate driver 20 and the data driver 30 are illustrated as separate components from the display panel 50 in FIG. 1 , the present invention is not limited thereto. For example, at least one of the gate driver 20 and the data driver 30 may be configured as an in-panel method integrally formed with the display panel 50 . For example, the gate driver 20 may be integrally formed with the display panel 50 according to a gate in panel (GIP) method.

The first layer 60 may be electrically connected to the display panel 50 and the power supply unit 40 , and may cover or cover the emission area AA. Accordingly, the first layer 60 may overlap the light emitting area AA and may have an area equal to or smaller than the area of the light emitting area AA. As another example, the first layer 60 may have an area larger than the area of the light emitting area AA. The first layer 60 may be a high potential voltage front layer, but is not limited thereto.

Also, the first layer 60 may have an area covering both the light emitting area AA and the non-emission area NA. For example, the first layer 60 may have an area covering the display panel 50 . Accordingly, the first layer 60 may overlap the display panel 50 and may have an area equal to or smaller than that of the display panel 150 . As another example, the first layer 60 may have a larger area than that of the display panel 150 .

Also, in the first layer 60 , a contact hole 620 is formed at a position corresponding to each pixel, and may be electrically connected to each pixel through the contact hole 62 .

In addition, the first layer 60 may be positioned in an inner layer of the display panel 50 , and insulating layers may be respectively disposed on the upper and lower portions of the first layer 60 .

Also, the first layer 60 may be positioned on the uppermost layer of the display panel 50 , and an insulating layer may be disposed between the first layer 60 and the display panel 50 .

The power supply unit 40 may supply the high potential voltage ELVDD to the plurality of pixels PX through the first layer 60 . For example, since the first film 60 disposed on the front surface of the display panel 50 is respectively connected to each other by the contact hole 60 in each pixel, the power supply unit 40 is connected to the first film 60 . The supplied high potential voltage ELVDD may be supplied to each pixel PX through each contact hole 60 .

The present specification may be applied to a bottom-emission type electroluminescence display device, but is not limited thereto. As another example, it may be applied to an electroluminescent display device of a top-emission or dual-emission type.

FIG. 2 is a circuit diagram illustrating an embodiment of the pixel shown in FIG. 1 in the electroluminescent display device according to the embodiment of the present specification.

FIG. 2 illustrates the pixel PX ij connected to the i-th gate line GL i and the j-th data line DL j as an example.

Referring to FIG. 2 , one pixel PX may include a switching transistor S-TFT, a driving transistor D-TFT, a storage capacitor Cst, and a light emitting device LD. A first layer 60 may be formed on the display panel 50 to cover the switching transistor S-TFT, the driving transistor D-TFT, the storage capacitor Cst, and the light emitting device LD. The first layer 60 may be electrically connected to the switching transistor S-TFT and the storage capacitor Cst through a contact hole 62 .

A first electrode (eg, a source electrode) of the switching transistor S-TFT is electrically connected to the j-th data line DLj, and a second electrode (eg, a drain electrode) of the switching transistor S-TFT is connected to the first node N1 . ) can be electrically connected to. The gate electrode of the switching transistor S-TFT may be electrically connected to the i-th gate line GLi.

The switching transistor S-TFT is turned on when the gate signal of the gate-on level is applied to the i-th gate line GLi, and the data signal applied to the j-th data line DLj ( V_data) may be transferred to the first node N1 .

A first electrode of the storage capacitor Cst may be electrically connected to the first node N1 , and a second electrode may be connected to the contact hole 62 of the first layer 60 to receive the high potential voltage ELVDD. have. The storage capacitor Cst may be charged with a voltage corresponding to a difference between the voltage V_data applied to the first node N1 and the high potential voltage ELVDD applied from the first layer 60 .

A first electrode (eg, a source electrode) of the driving transistor D-TFT is connected to the contact hole 62 of the first layer 60 to receive the high potential voltage ELVDD, and a second electrode (eg, a second electrode) For example, the drain electrode) may be electrically connected to a first electrode (eg, an anode electrode) of the light emitting device LD. A gate electrode of the driving transistor D-TFT may be electrically connected to the first node N1 .

The driving transistor D-TFT is turned on when a gate-on level voltage is applied through the first node N1 , and a driving current flowing through the light emitting device LD in response to the voltage applied to the gate electrode The amount of (IOLED) can be controlled.

The amount of the driving current I _OLED flowing through the light emitting element LD is expressed in Equation 1 below.

For example, the amount of the driving current I _OLED flowing through the light emitting device LD is provided to the high potential voltage ELVDD of the first electrode (eg, the source electrode) of the driving transistor D-TFT and the gate electrode. It may be controlled according to the magnitude of V_GS, which is the difference value of the voltage V_data.

The light emitting device LD may output light corresponding to the driving current. The light emitting device LD may output light corresponding to any one of red, green, and blue. The light emitting device LD may be an organic light emitting diode (OLED) or a micro-inorganic light emitting diode having a size ranging from micro to nano scale, but the present specification is not limited thereto. Hereinafter, the light emitting device LD will be described with reference to an embodiment in which the organic light emitting diode is configured.

In the present specification, the structure of the pixels PX is not limited to that illustrated in FIG. 2 . According to an exemplary embodiment, the pixels PX compensate the threshold voltage VTH of the driving transistor D-TFT, or the voltage of the gate electrode of the driving transistor D-TFT and/or the anode electrode of the light emitting device LD. It may further include at least one device for initializing the voltage of .

2 illustrates an example in which the switching transistor S-TFT and the driving transistor D-TFT are NMOS transistors, but the present specification is not limited thereto. For example, at least some or all of the transistors constituting each pixel PX may be configured as PMOS transistors. In various embodiments, each of the switching transistor (S-TFT) and the driving transistor (D-TFT) is a Low Temperature Poly Silicon (LTPS) thin film transistor, an oxide thin film transistor, or a Low Temperature Polycrystalline Oxide (LTPO). ) can be implemented as a thin film transistor.

3 is a diagram illustrating a pixel arrangement of an electroluminescence display according to an exemplary embodiment of the present specification.

In FIG. 3 , the sub-pixels sP are arranged in a 4×4 matrix for convenience of description. Also, in FIG. 3 , it is assumed that the image data input to the display device has a large variation in the input image data.

Referring to FIG. 3 , one sub-pixel sP may be connected to gate lines GL1 to GLn, data lines DL1 to DLm, and power lines PL11 to PL1x and PL21 to PL2x.

Here, the high potential voltage line ELVDD is connected to the first layer 60 , and the first layer 60 is electrically connected to each sub-pixel sP11 , sP12 , sP44 by each contact hole 62 . can

Accordingly, the high potential voltage ELVDD may be applied to each of the sub-pixels sP11 , sP12 , sP44 through each contact hole 62 of the first layer 60 .

As a display device having a high resolution and a high pixel density is developed, a constraint on a pixel arrangement space is increasing. One way to solve the constraint is that a specific element, for example, the power line PL22 may be shared by multiple pixels. Thereby, the space occupied by the signal wiring can be saved by reducing the number of signal lines for supplying a common signal to each pixel. For example, as shown in FIG. 3 , a so-called flip structure in which two adjacent pixels (columns) share the low potential power lines PL21 to PL2x may be used.

The low potential power lines PL21 to PL2x may be arranged in a direction parallel to each other, but according to an embodiment, some are arranged in a first direction (eg, a horizontal direction), and others are arranged in a second direction (eg, a vertical direction) direction) and may be arranged to cross each other.

3 shows that the low potential power lines PL21 to PL2x are vertically arranged in parallel with each other, and the high potential power line ELVDD is arranged to cover each of the sub-pixels sP11, sP12, sP44, and sP44. It may be connected to the voltage front layer 60 .

Accordingly, the high potential power line ELVDD and the low potential power line PL21 to PL2x have the first layer 60 disposed on the front surface in a flat plate shape, and the low potential power lines PL21 to PL2x are vertically arranged. , there is an advantage of reducing signal interference between the high potential voltage signal ELVDD and the low potential voltage signal ELVSS.

In FIG. 3 , the gray level gl of the gray level voltage of the sub-pixels sP11 to sP41 and sP12 to sP42 in the first and second columns is 10, and the gray level gl of the sub-pixels in the third and fourth columns sP13 to sP43 and sP14 to sP44 is the gray level. The gray level gl of the voltage may be 255. The first and second column sub-pixels sP11 to sP41 and sP12 to sP42 may receive the high potential voltage ELVDD by the first layer 60 . In addition, the third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44 may also receive the high potential voltage ELVDD by the first layer 60 .

In the first and second column sub-pixels sP11 to sP41 and sP12 to sP42, the gray level gl of the grayscale voltage may be 10. In addition, in the third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44, the gray level gl of the grayscale voltage may be 255, which is the maximum gray level gl. Accordingly, the amount of the driving current IOLED flowing through the light emitting element LD of the third and fourth sub-pixels sP13 to sP43 and sP14 to sP44 rather than the first and second sub-pixels sP11 to sP41 and sP12 to sP42 This could be bigger.

The first and second column sub-pixels sP11 to sP41 and sP12 to sP42 may receive the high potential voltage ELVDD by the first layer 60 . Also, since the third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44 are also supplied with the high potential voltage ELVDD by the first layer 60 , the value of the current IR_11 flowing through PL11 is the current flowing through PL12 . It may be the same as IR_12.

Since the power line has a resistance component, a voltage drop IR-Drop may occur in the high potential voltage ELVDD supplied to each sub-pixel sP through the high potential power line due to the resistance component of the power line.

However, in the present specification, as the high potential voltage ELVDD is supplied to each of the sub-pixels sP11, sP12, , and sP44 by the first layer 60 , the voltage drop (IR-Drop) due to the resistance component of the power line can be made smaller.

For example, according to the present specification, due to the resistance component of the first layer 60 , the high potential voltage ELVDD supplied to each sub-pixel sP is substantially constantly supplied, and the image pattern input to the display device and the The voltage drop of the high potential voltage ELVDD may be almost insignificant depending on the arrangement of the high potential power line and the sub-pixel sP.

Accordingly, when the fluctuation of the input image data is large, the high potential voltage ELVDD supplied from the power supply unit 40 to the display panel 50 may be supplied as a substantially constant voltage. Accordingly, there may be no variation in the high potential voltage ELVDD, and accordingly, there may be no variation in the driving current IOLED of the driving transistor D-TFT for each pixel PX, which is the pixel PX. There may be no luminance difference. Accordingly, since the influence of luminance of a specific portion of the display panel can be reduced, the crosstalk recognition rate can be reduced, thereby reducing image quality defects of the display device.

4 is a plan view of a structure of a first layer, a power supply wiring, and a source/drain wiring according to an exemplary embodiment of the present specification as viewed from above.

Referring to FIG. 4 , the first layer 60 according to the embodiment of the present specification may be disposed to cover the ELVDD wiring 70 , the power supply wiring TM1 , and the source-drain wiring SD2 .

The first layer 60 according to the present specification may overlap the ELVDD wiring 70 , the power supply wiring TM1 , and the source-drain wiring SD2 .

The power wiring TM1 may be electrically connected to the gate electrode TM1 in contact with it.

The ELVDD wiring 70 may be electrically connected to the power wiring TM1 by the ELVDD contact hole 72 .

The ELVDD wiring 70 and the power wiring TM1 may be disposed to cross each other. For example, when the ELVDD wirings 70 are arranged in a vertical direction, the power wirings TM1 can cross each other by being arranged in a horizontal direction.

In the first layer 60 according to the present specification, an additional ELVDD contact hole 62 is formed at a position overlapping the ELVDD wiring 70 , and each ELVDD wiring 70 is formed by the ELVDD contact hole 62 . can be electrically connected to.

FIG. 5 is a cross-sectional view taken along line A-A' of FIG. 1 .

Referring to FIG. 5 , in the display panel 60 of the electroluminescent display device 100 according to the embodiment of the present specification, a buffer layer 102 is disposed on a substrate 101 , and a first buffer layer 102 is disposed on the buffer layer 102 . An active layer 103 and a second active layer 103 may be disposed, and a first insulating layer 104 may be disposed on the first active layer 103 and the second active layer 103 .

For example, the first insulating layer 104 may be the gate insulating layer 104 .

In the display panel 60 , a first gate electrode 105 and a second gate electrode 105 are disposed on a first insulating layer 104 , and a second gate electrode 105 and a second gate electrode 105 are disposed on the first gate electrode 105 and the second gate electrode 105 . An insulating layer 106 may be disposed, and a power supply line TM1 107 and a third insulating layer 108 may be disposed on the second insulating layer 106 .

In the display panel 60 , the first layer 109 is disposed on the power wiring 107 and the third insulating layer 108 , the fourth insulating layer 110 is disposed on the first layer 109 , and the fourth insulating layer ( A first planarization layer 111 may be disposed on the 110 , and a source drain electrode 112 may be disposed on the first planarization layer 111 .

The first layer 109 may be electrically connected to the power wiring 107 through a first contact hole, and the source drain electrode 112 may be electrically connected to the first layer 109 through a second contact hole.

In the display panel 60 , a second planarization layer 113 is disposed on the source and drain electrodes 112 , an anode electrode 114 is disposed on the second planarization layer 113 , and a portion of the second planarization layer 113 is disposed. And a bank layer 115 may be disposed on a portion of the anode electrode 114 , and a spacer 116 may be disposed on the bank layer 115 .

In the display panel 60 , an emission layer OLED may be disposed on the anode electrode 114 , and a cathode electrode CE may be disposed on the emission layer.

6A to 6C are views illustrating a method of manufacturing an electroluminescent display according to an embodiment of the present specification, and FIGS. 7 to 17 are cross-sectional views illustrating a process of manufacturing an electroluminescent display according to an embodiment of the present specification. .

A manufacturing process of an electroluminescent display device according to an exemplary embodiment of the present specification will be described with reference to FIGS. 6A to 17 .

6A and 7 , the buffer layer 102 is formed on the substrate 101 including the light emitting area AA and the non-emission area NA ( S602 ).

In the exemplary embodiment of the present specification, the light emitting area AA may be a display area, and the non-emission area NA may be a non-display area.

A light shield layer (LS) may be disposed on the substrate 101 in the non-emission area NA.

The light blocking layer LS can prevent leakage current by blocking light incident to the active layer ACT of the driving thin film transistor Tdr, and is connected to the source electrode SE of the driving thin film transistor Tdr for electrical stability. can be connected

A buffer layer 102 may be disposed on the substrate 101 in the light emitting area AA and the non-emission area NA. A polarization layer POL may be disposed under the substrate 101 in the emission area AA.

For example, a light-shielding metal layer is formed on the substrate 101 , and a photoresist PR is formed on the light-shielding metal layer. Thereafter, a photoresist pattern is formed by an exposure and development process using a mask including a transmission part and a blocking part. The light blocking metal layer is etched using the photoresist pattern as a mask to form the light blocking layer LS. The light blocking layer LS is formed on the substrate 101 of the non-emission area NA. The light blocking layer LS and the buffer layer 102 may be formed by one mask process.

The substrate 101 is an insulating substrate and may be made of glass or plastic. The light blocking layer LS may be formed of an opaque metal material. For example, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molytungsten (MoW), molithanium (MoTi), and copper/motitanium It may be formed of at least one selected from a group of conductive metals including (Cu/MoTi). The light blocking layer LS is not limited thereto, and may be made of a material capable of blocking light.

A color filter layer CF may be formed on the buffer layer 102 of the emission area AA.

Next, as shown in FIGS. 6A and 8 , a first active layer 103 and a second active layer 103 are formed on the buffer layer 102 ( S604 ).

The first active layer 103 may be formed on the substrate 101 or on the buffer layer 102 in an area corresponding to the emission area AA. Also, the second active layer 103 may be formed on the substrate 101 or on the buffer layer 102 in an area corresponding to the non-emission area NA.

Next, as shown in FIGS. 6A and 9 , a first insulating layer 104 is formed on the first active layer 103 and the second active layer 103 ( S606 ).

Next, as shown in FIGS. 6A and 10 , a first gate electrode 105 and a second gate electrode 105 are formed on the first insulating layer 104 ( S608 ), and the first gate electrode 105 . and a second insulating layer 106 is formed on the second gate electrode 105 ( S610 ).

The first gate electrode 105 may be formed on the first insulating layer 104 in a region corresponding to the first active layer 103 . Also, the second gate electrode 105 may be formed in a region corresponding to the second active layer 103 on the first insulating layer 104 .

Next, as shown in FIGS. 6A and 11 , a first metal layer ML is formed on the second insulating layer 106 ( S612 ), and the first metal layer is etched to expose the second insulating layer 106 . The power supply wiring 107 is formed ( S614 ), and a third insulating film 108 is formed on the second insulating film 106 and the power supply wiring 107 ( S616 ).

Next, as shown in FIGS. 6B and 12 , a first contact hole 62 is formed through the third insulating layer 108 ( S618 ), and is formed on the third insulating layer by the first contact hole 62 . First films 60 and 109 are formed so as to contact the power wiring 107 (S620).

The first layer 109 is formed on the third insulating layer 108 to have an area overlapping the emission area AA, or has an area overlapping both the emission area AA and the non-light emission area NA. to be formed on the third insulating layer 108 .

Next, as shown in FIGS. 6B and 12 , a fourth insulating layer 110 is formed on the first layer 109 ( S622 ).

Next, as shown in FIGS. 6B and 13 , a first planarization film 111 is formed on the fourth insulating film 110 ( S624 ), and the fourth insulating film 110 and the first planarization film 111 are formed thereon. A second contact hole is formed therethrough ( S626 ), and a source drain electrode 112 is formed on the first planarization layer 111 to contact the first layer 109 through the second contact hole ( S628 ).

For example, through the mask process M, the source electrode SE and the drain electrode DE may be formed in the non-emission area NA. For example, the source electrode SE is formed on the first layer 109 of the non-emission area NA and the drain electrode DE is formed on the first layer 109 of the light emitting area AA. can

For example, a source-drain electrode material layer is formed on the first layer 109 , and a photoresist PR is formed on the source-drain electrode material layer. Thereafter, a photoresist pattern is formed by an exposure and development process using a mask including a transmission part and a blocking part. The source electrode SE and the drain electrode DE may be formed by etching the source drain electrode material layer using the photoresist pattern as a mask.

The source-drain electrode material layer may include any one of an alloy formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), and combinations thereof. One or more may be formed. In addition, a transparent conductive material such as Indium Tin Oxide (ITO) may be used. However, the present invention is not limited thereto, and may be formed of a material that can be used as an electrode in general.

Both sides of the active layer 103 may be a source region and/or a drain region. For example, in the source-drain electrode 112 on the first layer 109 , a region corresponding to the first active layer 103 of the non-emission area NA becomes the source electrode SE, and the light-emitting area NA becomes the source electrode SE. A region corresponding to the second active layer 103 may be the drain electrode DE. For example, since a corresponding configuration may be used as a source or a drain depending on the characteristics of the active layer 103 , it may be a “source/drain electrode”, but may be used as a source electrode according to the characteristics of the active layer 103 , respectively. may be used or may be used as a drain electrode. Accordingly, the nomenclature of the electrode does not limit the use of the structure herein.

Next, as shown in FIGS. 6C and 14 , a second planarization layer 113 is formed on the first planarization layer 111 and the source-drain electrode 112 ( S630 ).

Next, as shown in FIGS. 6C and 15 , a third contact hole is formed through the second planarization layer 113 ( S632 ), and a source is formed on the second planarization layer 113 by the third contact hole. The anode electrode 114 is formed to contact the drain electrode 112 (S634).

Next, as shown in FIGS. 6C and 16 , a bank film 115 is formed on the second planarization film 113 and the anode electrode 114 , and a light emitting layer 117 is formed on the anode electrode 114 . and a cathode electrode 118 is formed on the emission layer 117 (S636).

The light emitting layer 117 may be formed through a thermal evaporation process using a shadow mask or a soluble process such as inkjet.

The light emitting layer 117 includes a hole injecting layer (HIL), a hole transporting layer (HTL), an emitting material layer (EML), an electron transporting layer (ETL), and electron injection. It may include an electron injecting layer (EIL), but is not limited thereto.

The cathode electrode 118 may be formed over the entire area of the emission layer 117 in the light emitting area AA and the non-emission area NA through the mask process M.

Next, as shown in FIGS. 6C and 17 , a spacer 116 is formed on the bank layer 115 ( S640 ).

A passivation layer PAS may be formed over the entire area of the light emitting area AA and the non-emission area NA through the mask process M on the cathode electrode 118 .

As described above, according to the present specification, an electroluminescent display device capable of supplying a high potential voltage to each pixel by the first film disposed to cover the entire surface of the display panel in the electroluminescent display device is provided. can

And, according to the present specification, a first film is formed between the gate electrode and the source-drain electrode when the display panel of the electroluminescent display is manufactured, the upper and lower portions of the first film are insulated by an insulating film, and the contact hole of the insulating film is formed. By electrically connecting the first layer and the source-drain electrode by the first layer, a high potential voltage can be supplied to the source-drain electrode of the thin film transistor by the first layer, thereby providing a method of manufacturing an electroluminescence display.

An electroluminescent display device and a manufacturing method thereof according to an embodiment of the present specification may be described as follows.

An electroluminescent display device according to an embodiment of the present specification includes a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area, a driving circuit for transmitting a driving signal to the display panel, and a display panel A power supply unit for supplying a high potential voltage, and a first layer electrically connected to the display panel and the power supply unit and covering the light emitting area.

An electroluminescent display device according to an embodiment of the present specification includes a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area, a driving circuit for transmitting a driving signal to the display panel, and a display panel A power supply unit for supplying a high potential voltage, and a first layer electrically connected to the display panel and the power supply unit and covering the light emitting area and the non-emission area.

According to some embodiments herein. The power supply may supply a high potential voltage to the plurality of pixels by the first layer.

According to some embodiments of the present specification, the first layer may be electrically connected to each pixel of the display panel through respective contact holes.

According to some embodiments herein. The first layer may be disposed on an inner layer of the display panel, and an insulating layer may be disposed above and below the first layer, respectively.

According to some embodiments herein. The display panel includes a substrate, an active layer over the substrate, a first insulating layer over the active layer, a gate electrode over the first insulating layer, a second insulating layer over the gate electrode, a power line and a third insulating layer over the second insulating layer, a power line, and a first layer over the third insulating layer, a fourth insulating layer over the first layer, and a source drain electrode over the fourth insulating layer.

According to some embodiments herein. The first layer may be disposed on an uppermost layer of the display panel, and an insulating layer may be further disposed between the first layer and the display panel.

According to some embodiments herein. The first layer may overlap the light emitting area and have an area equal to or smaller than the area of the light emitting area.

According to some embodiments of the present specification, the first layer may overlap the display panel and may have an area equal to or smaller than the area of the display panel.

According to some embodiments of the present specification, the first layer may have a thickness smaller than a thickness of the display panel.

According to some embodiments of the present specification, the first layer may be formed of a transparent conductive material.

According to some embodiments of the present specification, the first layer may be formed of one of indium tin oxide, indium zinc oxide, and silicon oxide-added indium tin oxide.

A method of manufacturing an electroluminescent display device according to an embodiment of the present specification includes the steps of (a) forming a first active film and a second active film on a substrate including a light emitting region and a non-light emitting region, (b) the first active film and forming a first insulating film on the second active film, (c) forming a first gate electrode and a second gate electrode on the first insulating film, (d) on the first gate electrode and the second gate electrode forming a second insulating film, (e) forming a power supply wiring on the second insulating film, (f) forming the second insulating film and a third insulating film on the power supply wiring; (g) forming a second insulating film on the power supply wiring Forming a first film in contact with the first contact hole on the third insulating film, (h) forming a fourth insulating film on the first film, (i) in contact with the first film by a second contact hole forming a source drain electrode on the fourth insulating film; and (j) forming a planarization film on the source drain electrode.

According to some embodiments of the present specification, in the step (a), the first active film and the second active film may be formed on a buffer film on a substrate and on the buffer film, respectively.

According to some embodiments of the present specification, in step (a), the first active film is formed on the substrate or on the buffer film in a region corresponding to the light emitting region, and the second active film corresponds to the non-emission region on the substrate or on the buffer film. It can be formed in an area where

According to some embodiments of the present specification, in step (c), the first gate electrode is formed on the first insulating film in a region corresponding to the first active film, and the second gate electrode is formed on the first insulating film on the second active film. It may be formed in a corresponding area.

According to some embodiments of the present specification, in step (g), the first film is formed on the third insulating film to have an area overlapping the light emitting region, or to have an area overlapping both of the light emitting region and the non-light emitting region. 3 may be formed on the insulating layer.

As described above, the present invention has been described with reference to the illustrated drawings, but the present invention is not limited by the embodiments and drawings disclosed in this specification, and a variety of It is obvious that variations can be made. In addition, although the effects of the configuration of the present invention are not explicitly described and described while describing the embodiments of the present invention, it is natural that the effects predictable by the configuration should also be recognized.

10: timing controller 20: gate driver
30: data driver 40: power supply
50: display panel 60: first film
62: first contact hole 70: ELVDD wiring
72: ELVDD contact hole 100: electroluminescence display device
101: substrate 102: buffer film
103: active film 104: first insulating film
105: gate electrode 106: second insulating film
107: power wiring 108: third insulating film
109: first film 110: fourth insulating film
111: first planarization film 112: source drain electrode
113: second planarization film 114: anode electrode
115: bank film 116: spacer
117: light emitting layer 118: cathode electrode
S-TFT : Switching Transistor D-TFT : Driving Transistor
GL1 to GLn : Gate line DL1 to DLm : Data line
PX: Pixel AA: Emission Area
NA: non-emission area ELVDD: high potential voltage
ELVSS: low potential voltage sP: sub-pixel
SD2: source drain wiring CE: cathode electrode
Tsw: switching thin film transistor Tdr: driving thin film transistor
Tse: sensing thin film transistor Cst: storage capacitor

Claims (17)

a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area;
a driving circuit for transmitting a driving signal to the display panel;
a power supply supplying a high potential voltage to the display panel; and
and a first layer electrically connected to the display panel and the power supply unit and covering the emission area. a display panel including a light emitting area and a non-emission area, the display panel including a plurality of pixels disposed in the light emitting area;
a driving circuit for transmitting a driving signal to the display panel;
a power supply supplying a high potential voltage to the display panel; and
and a first layer electrically connected to the display panel and the power supply and covering the light emitting area and the non-emission area. 3. The method of claim 1 or 2,
and the power supply unit supplies the high potential voltage to the plurality of pixels by the first layer. 3. The method of claim 1 or 2,
and the first layer is electrically connected to each pixel of the display panel by respective contact holes. 3. The method according to claim 1 or 2,
The first layer is located in an inner layer of the display panel, and insulating layers are respectively disposed on an upper portion and a lower portion of the first layer. 3. The method according to claim 1 or 2,
The first layer is disposed on an uppermost layer of the display panel, and an insulating layer is further disposed between the first layer and the display panel. 3. The method of claim 1 or 2,
The display panel is
Board;
an active film on the substrate;
a first insulating film over the active film;
a gate electrode over the first insulating layer;
a second insulating film over the gate electrode;
a power supply line and a third insulating film on the second insulating film;
the first film over the power wiring and the third insulating film;
a fourth insulating film over the first film;
and a source drain electrode disposed on the fourth insulating layer. The method of claim 1,
The first layer overlaps the light emitting region and has an area equal to or smaller than an area of the light emitting region. 3. The method of claim 2,
The first layer overlaps the display panel and has an area equal to or smaller than an area of the display panel. 3. The method of claim 1 or 2,
and the first layer has a thickness smaller than a thickness of the display panel. 3. The method of claim 1 or 2,
The first layer is made of a transparent conductive material. 3. The method of claim 1 or 2,
The first layer is made of one of indium tin oxide, indium zinc oxide, and silicon oxide-doped indium tin oxide. (a) forming a first active film and a second active film on a substrate including a light emitting region and a non-light emitting region;
(b) forming a first insulating film on the first active film and the second active film;
(c) forming a first gate electrode and a second gate electrode on the first insulating layer;
(d) forming a second insulating layer on the first gate electrode and the second gate electrode;
(e) forming a power wiring on the second insulating film;
(f) forming a third insulating film on the second insulating film and the power wiring;
(g) forming a first layer in contact with the power wiring through a first contact hole on the third insulating layer;
(h) forming a fourth insulating film on the first film;
(i) forming a source-drain electrode contacting the first layer through a second contact hole on the fourth insulating layer; and
(j) forming a planarization layer on the source and drain electrodes. 14. The method of claim 13,
In the step (a), the first active film and the second active film, a buffer film is formed on the substrate and is formed on the buffer film, respectively. 15. The method according to claim 13 or 14,
In step (a), the first active film is formed on the substrate or on the buffer film in a region corresponding to the light emitting region, and the second active film corresponds to the non-emission region on the substrate or on the buffer film. A method of manufacturing an electroluminescent display device, which is formed in a region to be 14. The method of claim 13,
In step (c), the first gate electrode is formed on the first insulating layer in a region corresponding to the first active layer, and the second gate electrode is formed on the first insulating layer corresponding to the second active layer. A method of manufacturing an electroluminescent display device, which is formed in the region. 14. The method of claim 13,
In step (g), the first layer is formed on the third insulating layer to have an area overlapping the light emitting region, or the third insulating layer to have an area overlapping both of the light emitting region and the non-light emitting region A method of manufacturing an electroluminescent display device formed on the

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