JP2005198872A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure the space for a board, to prevent forgery, and to generate random numbers with high randomness in a game machine. <P>SOLUTION: When a second random number updating method is selected among first and second random number updating methods in a random number circuit 103 built in a game controlling micro-processor together with a CPU, a selector 128 selects a random number generating clock signal S1 outputted from a clock signal output circuit 124 and outputs the signal to a counter 121. A delay circuit 132 outputs a delay clock signal S2 generated by delaying the random number generating clock signal S1 by the period different from a period which is an integral number of times of the cycle. A latch signal generating circuit 133 synchronizes a random number value reading signal inputted from a random number value reading signal output circuit 139 with the leading edge of the delay clock signal S2, and outputs the synchronized signal to a random number value storing circuit 131 as a latch signal SL. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko machine or a slot machine. The present invention relates to a gaming machine that includes a variable display device that variably displays identification information, and that controls a specific gaming state advantageous to a player when the display result of the variable display becomes a predetermined specific display result.

  In gaming machines such as pachinko machines and slot machines, multiple types of identification information (hereinafter referred to as display symbols) are variably displayed on multiple rows of display units in a variable display device, and given game values are given based on the display results. There is a game that has been enhanced by a so-called variable display game that determines whether or not to do so. In the variable display game, for example, when a predetermined condition such as detection of a game ball passing through a predetermined area or detection of an operation of a start lever is satisfied, variable display of display symbols is started. Then, when the stop symbol mode when the variable display of the display symbol is completely stopped is the specific display mode, the specific game state (big hit game state) advantageous to the player is obtained. For example, a pachinko gaming machine that has become a big hit game state has a special electric accessory called a big prize opening or an attacker opened, and a state where a player can easily win a game ball for a certain period of time continuously. provide.

In such gaming machines, it is known that a random number used for determining whether or not to make a “big hit” (a big hit determination random number) is generated by a microprocessor executing a predetermined application program ( For example, Patent Document 1).
JP 2002-282457 A

  However, in the technique disclosed in Patent Document 1, since a random number is generated by a program, the processing load on the microprocessor is large. In particular, since random number update processing is performed during execution of timer interrupt processing for game control, it is necessary to develop a program similar to that for game control, and within a limited interrupt processing time. There was a problem that processing for generating a random number had to be started and ended, increasing the processing load on the microprocessor.

Therefore, a latch signal in which the count value updated by the clock count circuit in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is synchronized with the rising edge of the inverted clock pulse (or clock pulse). Based on the above, a gaming machine or the like that can generate a random number by hardware by storing it in a count value storage circuit as a random value has been proposed (for example, Patent Document 2).
JP 2003-190483 A

In the technique disclosed in Patent Document 2, no consideration is given to the arrangement of a main control unit that executes control of a gaming machine or the like and a random number generation device that generates random numbers regardless of the control of the main control unit. Not. With respect to this point, from the viewpoint of facilitating inspection by a third-party organization, there has been proposed one that generates random numbers using a random number circuit externally attached to a game control microprocessor (for example, Patent Document 3).
JP 2000-300183 A

  In the technique disclosed in Patent Document 3, a circuit for generating random numbers must be arranged separately from the microprocessor, which increases the amount of hardware and occupies a lot of board space. Further, there has been a problem that it is difficult to prevent forgery, for example, numerical data indicating a random number value generated by a random number circuit is illegally rewritten due to installation of an illegal substrate or the like. In addition, the random number circuit of Patent Document 3 counts up the output from the pulse generator that continuously outputs pulses at a constant frequency one by one in a predetermined range, for example, 0 to 1023, and reaches the maximum value. Since only counting up from 0 (minimum value) is performed again, there is a possibility that the randomness may be lowered due to the occurrence of periodicity in the generated random numbers.

  In addition, in the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gentle, the rising edge of the inverted clock pulse also becomes gentle. Therefore, the latch signal synchronized with the rising edge of the inverted clock pulse The output timing becomes unstable, and there is a possibility that acquisition of a random number value cannot be performed reliably and stably.

  The present invention has been made in view of the above circumstances, and provides a gaming machine capable of reliably and stably obtaining a random value with high randomness while ensuring board space and preventing forgery. The purpose is to do.

  In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (for example, a pachinko gaming machine 1) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of variable display becomes a predetermined specific display result. Thus, the power supply means (for example, the power supply board 10) for supplying power to the gaming machine, the random number circuit (for example, the random number circuit 103) for generating random numbers (for example, the random R), and the progress of the game are controlled. A microprocessor (for example, a CPU 106 mounted on the main board 11) that operates using electric power supplied from the power supply means, and a predetermined period Generating a reference clock signal (for example, a reference clock signal CLK) and outputting it to the random number circuit and a start signal (for example, a start prize) based on the fact that the execution condition is satisfied Start signal output means (for example, start winning port switch 70) for outputting the signal SS) to the random number circuit and the game control means, and variable display of the identification information on the variable display device based on the control signal from the microprocessor Variable display control means (for example, display control board 12) for controlling the random number circuit, Using a reference clock signal input from the clock signal generation means, a preceding clock signal generation means (for example, a clock signal S1) for generating a preceding clock signal (for example, a random number generation clock signal S1) having a predetermined period and outputting the preceding clock signal. A delayed clock signal (for example, delayed clock signal S2) is generated by delaying the preceding clock signal input from the signal output circuit 124) and the preceding clock signal generating means by a period different from an integer multiple of the predetermined period. And a clock signal delay means (for example, delay circuit 132) for outputting the delayed clock signal, and a preceding clock signal output from the preceding clock signal generating means is changed in a predetermined manner every predetermined period. The timing and the delayed clock signal output from the clock signal delaying means are set at predetermined intervals. Numerical data (for example, timing T11, T12,..., For example, when the random number generation clock signal S1 rises from a low level to a high level) is selected from any one of the second timings that change in a fixed manner. Numerical value updating means (for example, counter 121) for updating the count value C), and timing (for example, timing) different from the timing at which numerical data is updated by the numerical value updating means among the first timing and the second timing. T23, etc.), a latch signal output means (for example, a latch signal generation circuit 133) that outputs a start signal input from the start signal output means as a latch signal (for example, a latch signal SL), and an input from the latch signal output means Updated by the numerical value updating means in response to the latch signal Random value storage means (for example, random value storage circuit 131) for storing value data as random value (for example, random R value), and the game control means, after the start of power supply by the power supply means, Random number circuit setting means (for example, a portion where the CPU 106 executes the random number circuit setting process in step S10) for setting the random number circuit to update the random number value, and the random number circuit setting means performs the setting on the random number circuit. Timer interrupt process execution permission means (for example, the part where the CPU 106 executes the process in step S14) that permits execution of a timer interrupt process that occurs periodically (for example, every 2 milliseconds), and the timer During the execution of the interrupt process (for example, during the execution of the game control interrupt process by the CPU 106), the start signal is input from the start signal output means. Subsequently, the random number value is read from the random number storage means, and it is determined whether or not the read random number value matches predetermined determination value data (for example, “3”, etc.). Display result determining means for determining whether or not the result is a specific display result (for example, a portion where the CPU 106 executes a winning process in step S142, a special symbol normal process in step S150, and a jackpot determination process in step S151). .

  3. The gaming machine according to claim 2, wherein the random number circuit includes random number maximum value setting data (for example, random number maximum value setting data “00FFh”) that specifies a maximum value (for example, “255”) of a random number generated by the random number circuit. A random number maximum value setting register (for example, random number maximum value setting register 135) and the like, and an update range by the numerical value updating means according to the random number maximum value setting data stored in the random number maximum value setting register (for example, “ Update range restriction means (for example, the comparator 122) for restricting a range from 1 ”to“ 255 ”, etc., and the random number circuit setting means writes a random number maximum value setting data to the random number maximum value setting register. Maximum value setting data writing means (for example, a portion where the CPU 106 executes the process of step S21) is included.

  4. The gaming machine according to claim 3, wherein the game control means has a predetermined maximum value of the random number specified by the random number maximum value setting data written by the random number maximum value setting means in the random number maximum value setting register. When the value is smaller than a lower limit value (for example, “4”, etc.) (for example, when the maximum value of the random number specified by the random number maximum value setting data is “0” to “3”), a predetermined value (for example, greater than the predetermined lower limit value) Random number maximum value setting data (such as “random number maximum value setting data“ 0FFFh ”) specifying“ 4095 ”or the like is stored in the random number maximum value setting register.

  5. The gaming machine according to claim 4, wherein the numerical value updating means cyclically updates the numerical data from a predetermined initial value (for example, “1”) to a predetermined maximum value (for example, “4095”), and the random number. When the numerical value data is updated to the predetermined maximum value by the numerical value updating means, the circuit outputs a notification signal (for example, a notification signal shown in FIG. 4) for notifying that effect. The game control means is a numerical data updated by the numerical value updating means in response to the notification signal input from the notification signal output means during execution of the timer interrupt process. Initial value changing means for changing the predetermined initial value (for example, a portion where the CPU 106 executes the initial value changing process in step S104).

  6. The gaming machine according to claim 5, wherein the initial value changing means is when the changed initial value is larger than the maximum value (for example, “255”) of the random number (for example, when the changed initial value is “256”). Etc.) means for changing the changed initial value again (for example, in the count value update operation in the counter 121 and the comparator 122 shown in FIG. 121 outputs the count value of the changed initial value to the comparator 122, and the comparator 122 outputs the count value update signal to the counter 121 to continuously count up to “4095” and the notification signal is output. In response to this, the CPU 106 further executes the initial value changing process in step S104 to change the changed initial value again. Including that part).

  7. The gaming machine according to claim 6, wherein the random number circuit requests numerical permutation change data (for example, count value permutation change data “01h”) for requesting a change in permutation that is an update order of the numerical data updated by the numerical value updating means. ) For storing a numerical permutation change register (for example, count value permutation change register 136), and when the numerical permutation change data is stored in the numerical permutation change register, the permutation when the numerical permutation change data is not stored Numerical value permutation changing means (for example, count value permutation changing circuit 123) for changing to a different permutation of the update order, and the game control means stores the numerical value in the numerical permutation change register during execution of the timer interrupt process. Numerical permutation change data writing means for writing permutation change data (for example, the CPU 106 changes the count value permutation in step S105) It includes a portion) to perform management.

8. The gaming machine according to claim 7, wherein the random number circuit stores a numerical value update register (for example, a count value) that stores numerical value update data (for example, count value update data “01h”) that requests the numerical value updating means to update the numerical data. Update register 138) and numerical value acquisition data (for example, count value acquisition data “01h”) for instructing to store the numerical data updated by the numerical value update means as a random value in the random value storage means. Random number update method selection data for designating a random number update method selected from a numerical value acquisition register (for example, a random number value acquisition register 139) and a first and second random number update method that is a method for updating a random value. For example, a random number update method selection data “01b”, “10b”) is stored. And the random number update method selection data (for example, random number update method selection data “01b”) for designating the first random number update method is stored in the random number value update method selection register. In place of the preceding clock signal output from the means or the delayed clock signal output from the delayed clock signal generation means, the numerical value data is updated in response to the numerical value update data being written to the numerical value update register. A numerical value update instruction signal (for example, count value update signal S3) is output to the numerical value update means, and a random number update method selection data (for example, random number update) for specifying a second random number update method in the random number value update method selection register is output. When the method selection data “10b”) is stored, it is output from the preceding clock signal generation means Update signal selection means (for example, selector 128) for outputting one of a row clock signal and a delay clock signal output from the delay clock signal generation means to the numerical value update means, and the random number circuit setting means The random number update method selection data for specifying a random number update method selected from at least the first and second random number update methods as a setting for causing the random number circuit to update the random number value, Update method setting means for writing into the random number update method selection register (for example, a portion where the CPU 106 executes the process of step S22 or step S32), and the game control means is configured to execute the first random number during the timer interrupt process. When the update method is selected, the numerical value update data to be written to the numerical value update register is written. Data writing means (for example, the part where the CPU 106 executes the random number value updating process of step S196), and the start signal output means writes the numerical value acquisition data into the numerical value acquisition register when outputting the start signal. The numerical value updating means is selected and inputted by the update signal selecting means when the random number update method selection data for specifying the first random number update method is stored in the random number value update method selection register. Numerical data is updated at a timing when the instruction signal changes in the predetermined manner (for example, timing T32), and random number update method selection data for specifying a second random number update method is stored in the random value update method selection register. When the update signal selection means selects and inputs the preceding clock signal and the delayed clock signal. The numerical data is updated at a timing at which one of the deviations changes in the predetermined manner every predetermined cycle (for example, timings T11, T12,...), And the latch signal output means stores a second value in the random value update method selection register. When random number update method selection data designating one random number update method is stored, the preceding clock signal output from the preceding clock signal generating unit and the delayed clock signal output from the delayed clock signal generating unit Either one is output as a latch signal (for example, the latch signal SL shown in FIG. 36D), and random number update method selection data for specifying the second random number update method is stored in the random value update method selection register. When the preceding clock signal is generated in response to the numerical value acquisition data being written to the numerical value acquisition register. Of the preceding clock signal output from the stage and the delayed clock signal output from the delayed clock signal generating means, a signal different from the signal selected by the update signal selecting means is the predetermined mode every predetermined period. A latch signal (for example, a latch signal SL shown in FIG. 29E) is output at a timing (for example, a timing T23) that changes at (1).
The update signal selection means responds to the fact that the numerical value change data is written to the numerical value change register when the random number update method selection data for designating the first random number update method is stored in the random number value update method selection register. Then, a numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal output from the random number generation clock signal generation means may be output to the numerical value update means.

  9. The gaming machine according to claim 8, wherein the random number circuit stores a cycle setting data (for example, a cycle setting data “0Fh”) for specifying a cycle for updating numeric data by the numerical value updating means (for example, a cycle). The random number circuit setting means includes a setting register 137), and the random number circuit setting means writes the frequency setting data for designating a preset update period to the period setting register (for example, a portion where the CPU 106 executes the process of step S23). And the preceding clock signal generating means changes the period of the reference clock signal output from the clock signal generating means in accordance with the period setting data stored in the period setting register and outputs it as the preceding clock signal To do.

  10. The gaming machine according to claim 9, wherein the game control means sets the update period specified by the period setting data written by the period setting means to the period setting register to a predetermined lower limit value (for example, “system clock signal”). The period of the clock signal specified by the period setting data is “0” to “the period of the system clock signal × 128 × 6”, etc.) Is stored in the cycle setting register (for example, cycle setting data “07h”, etc.).

  11. The gaming machine according to claim 10, wherein the random number circuit stores random number circuit activation data (for example, random number circuit activation data “80h”) for requesting activation of the random number circuit (for example, random number circuit activation register). 141) and random number circuit starting means (for example, random number circuit starting signal output circuit 130) for starting the random number circuit in response to the random number circuit starting data being written in the random number circuit starting register, The random number circuit setting means includes random number circuit activation setting means (for example, a portion where the CPU 106 executes the process of step S24) that writes the random number circuit activation data into the random number circuit activation register.

  12. The gaming machine according to claim 11, wherein the microprocessor includes a system reset unit (for example, a reset controller 102) for system resetting the microprocessor, and the random number circuit activation setting unit is configured by the system reset unit. When the system is reset (for example, when it is determined No in step S6 or step S7), the random number circuit activation data is rewritten in the random number circuit activation register to activate the random number circuit (for example, the CPU 106 activates step S9). Step S24 is executed in the random number circuit setting process in Step S10.

  13. The gaming machine according to claim 12, wherein the random number circuit measures a time during which a start signal is input from the start signal output means, and the measured time becomes a predetermined time (for example, 3 milliseconds). A timer means (for example, a timer circuit 134) for outputting the start signal to the latch signal output means,

  14. The gaming machine according to claim 13, wherein the display result determination unit is configured to output the start signal output unit until the number of executions of the timer interrupt process reaches a predetermined number (for example, 2 times) (for example, 4 milliseconds). The random number value is read out from the random value storage means based on the continuous input of the start signal from the timer means, and the timer means is configured to execute the timer interruption process more frequently than the predetermined time. Including setting means for setting a short time as the predetermined time (for example, a part in which the timer circuit 134 sets 3 milliseconds as a time shorter than 4 milliseconds which is the execution time of two game control interruption processes) When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.

  15. The gaming machine according to claim 14, wherein the game control means outputs an output control signal (for example, an output control signal SC) to the random value storage means before the display result determination means reads a random value from the random value storage means. ) To output the output control signal to the random value storage means after the display result determination means reads the random value from the random value storage means. It includes a read control means (for example, a portion where the CPU 106 executes the processing of step S172 and step S175) that stops and controls the random number value storage means to an unreadable state.

  16. The gaming machine according to claim 15, wherein when the latch signal is input from the latch signal output means, the random value storage means is in a state incapable of receiving the output control signal output from the read control means. Output control signal reception control means for controlling (for example, an AND circuit 203) is included.

  17. The gaming machine according to claim 16, wherein when the output control signal is input from the read control means, the random value storage means is in a state incapable of receiving the latch signal output from the latch signal output means. Latch signal reception control means (for example, AND circuit 201 etc.) to be controlled is included.

  The gaming machine according to claim 17 is a variable display start condition (for example, the previous variable display and jackpot game in the variable display device 4 after a variable display execution condition (for example, winning in the normal variable winning ball device 6) is established). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the establishment of (end of state). A gaming machine (for example, a pachinko gaming machine 1) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when a predetermined specific display result is obtained, and supplies power to the gaming machine Power supply means (eg, power supply board 10), random number circuit (eg, random number circuit 103) that generates random numbers (eg, random R), and game control means (eg, C) that controls the progress of the game U106) and a microprocessor (for example, a game control microprocessor 100 mounted on the main board 11) that operates using power supplied from the power supply means, and a reference clock signal (for example, U106). A clock signal generating means (for example, the clock circuit 101) for generating a reference clock signal (CLK) and outputting it to the random number circuit, and a start signal (for example, a start winning signal SS) as the random number based on the execution condition being satisfied. Start signal output means (for example, start winning port switch 70) for outputting to the circuit and the game control means, and variable display control for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor Means (for example, display control board 12), and the random number circuit is the clock signal generation means. A preceding clock signal generating means (for example, a clock signal output circuit 124) for generating a preceding clock signal (for example, a random number generating clock signal S1) having a predetermined period using the inputted reference clock signal and outputting the preceding clock signal; The first timing at which the preceding clock signal input from the preceding clock signal generating means changes in a predetermined manner every predetermined cycle (for example, the timing when the random number generating clock signal S1 rises from the low level to the high level) T11, T12,..., And the like, numerical value updating means (for example, counter 121) for updating numerical data (for example, count value C), and a start signal input from the start signal output means at the first timing are latched. Latch signal output means for outputting as a signal (for example, latch signal SL) (for example, FIG. 38) The latch signal generation circuit 133) and the latch signal input from the latch signal output means are delayed by a period different from an integer multiple of the predetermined period to generate a delayed latch signal (for example, a delayed latch signal SD). A latch signal delay means (for example, a delay circuit 232 shown in FIG. 38) that generates and outputs the delay latch signal, and a second timing at which the delay latch signal input from the latch signal delay means changes in the predetermined manner. Random number storage means (for example, random value storage circuit 131) for storing the numerical data updated by the numerical value update means (for example, a value of random R) at (for example, timing T71), the game control The means is a random number for setting the random number circuit to update the random number value after the power supply by the power supply means is started. Generated periodically (for example, every 2 milliseconds) after the setting is performed on the random number circuit by the path setting unit (for example, the part where the CPU 106 executes the random number circuit setting process of step S10) and the random number circuit setting unit. Timer interrupt process execution permission means for permitting execution of the timer interrupt process to be performed (for example, the part where the CPU 106 executes the process in step S14) and during execution of the timer interrupt process (for example, the game control interrupt process by the CPU 106) ), The random number value is read out from the random value storage means based on the input of the start signal from the start signal output means, and the read random number value is set to predetermined determination value data (for example, “3”). Display result determining means for determining whether or not the display result in the variable display is set as the specific display result ( If example CPU106 includes portions) and to perform a jackpot determination processing of special symbol normal processing steps S151 winning process and step S150 of step S142.

  The gaming machine according to claim 18 is the variable display start condition (for example, the previous variable display and jackpot game in the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball device 6) is established). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the establishment of (end of state). A gaming machine (for example, a pachinko gaming machine 1) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when a predetermined specific display result is obtained, and supplies power to the gaming machine Power supply means (eg, power supply board 10), random number circuit (eg, random number circuit 103) that generates random numbers (eg, random R), and game control means (eg, C) that controls the progress of the game U106) and a microprocessor (for example, a game control microprocessor 100 mounted on the main board 11) that operates using power supplied from the power supply means, and a reference clock signal (for example, U106). A clock signal generating means (for example, the clock circuit 101) for generating a reference clock signal (CLK) and outputting it to the random number circuit, and a start signal (for example, a start winning signal SS) based on the fact that the execution condition is satisfied. Start signal output means (for example, a start winning a prize opening switch 70) that outputs to the control means, and variable display control means (for example, display control) that controls variable display of identification information in the variable display device based on a control signal from the microprocessor. A board 12), the game control means after the start of power supply by the power supply means The random number circuit setting means (for example, the part where the CPU 106 executes the random number circuit setting process of step S10) for setting the random number circuit to update the random number value, and the random number circuit setting means, the setting is made to the random number circuit. Timer interrupt process execution permission means (for example, the part where the CPU 106 executes the process in step S14) that permits execution of the timer interrupt process that occurs periodically (for example, every 2 milliseconds) after being performed, While the timer interrupt process is being executed (for example, while the game control interrupt process is being executed by the CPU 106), the display result in the variable display is set as the specific display result based on the start signal input from the start signal output means. Display result determining means (for example, the CPU 106 performs special symbol normal processing in step S150 and jackpot judgment in step S151). A latch start signal (for example, a latch start winning signal SN) based on the start signal input from the start signal output means during execution of the timer interrupt process. And a start signal output means for latching that outputs to the random number circuit (for example, a portion where the CPU executes the process of step S254), and the random number circuit receives the reference clock signal input from the clock signal generation means A preceding clock signal generating means (for example, a clock signal output circuit 124) for generating a preceding clock signal (for example, a random number generating clock signal S1) with a predetermined period and outputting the preceding clock signal, and the preceding clock signal generating The preceding clock signal input from the means is delayed by a period different from a period that is an integral multiple of the predetermined period to delay the clock. A clock signal delay means (for example, delay circuit 132) that generates a signal (for example, delayed clock signal S2) and outputs the delayed clock signal, and a preceding clock signal output from the preceding clock signal generating means has a predetermined cycle. Any one of a first timing that changes in a predetermined manner and a second timing in which the delayed clock signal output from the clock signal delay means changes in a predetermined manner every predetermined period ( For example, at a timing T51, T52,... When the random number generating clock signal S1 rises from a low level to a high level, numerical value updating means (for example, a counter 121) for updating numerical data (for example, a count value C), The numerical data is updated by the numerical value updating means between the timing of 1 and the second timing. Latch signal output means for outputting a latch start signal input from the latch start signal output means as a latch signal (eg, latch signal SL) at a timing different from the timing of the latch signal (eg, timing T62), and the latch signal Random value storage means (for example, a random value storage circuit 131) for storing numerical data updated by the numerical value updating means as a random value (for example, a random R value) in response to a latch signal input from the output means The display result determining means reads a random number value from the random number storage circuit (for example, the CPU 106 executes the processing of steps S256 to S262), and the read random number value is converted into predetermined determination value data (for example, “ 3 ”etc.) to identify the display result in the variable display Decide whether to use the display result.

  The gaming machine according to claim 19 is a variable display start condition (for example, the previous variable display and jackpot game in the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball device 6) is established). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the establishment of (end of state). A gaming machine (for example, a pachinko gaming machine 1) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when a predetermined specific display result is obtained, and supplies power to the gaming machine Power supply means (eg, power supply board 10), random number circuit (eg, random number circuit 103) that generates random numbers (eg, random R), and game control means (eg, C) that controls the progress of the game U106) and a microprocessor (for example, a game control microprocessor 100 mounted on the main board 11) that operates using power supplied from the power supply means, and a reference clock signal (for example, U106). A clock signal generating means (for example, the clock circuit 101) for generating a reference clock signal (CLK) and outputting it to the random number circuit, and a start signal (for example, a start winning signal SS) based on the fact that the execution condition is satisfied. Start signal output means (for example, a start winning a prize opening switch 70) that outputs to the control means, and variable display control means (for example, display control) that controls variable display of identification information in the variable display device based on a control signal from the microprocessor. A board 12), the game control means after the start of power supply by the power supply means The random number circuit setting means (for example, the part where the CPU 106 executes the random number circuit setting process of step S10) for setting the random number circuit to update the random number value, and the random number circuit setting means, the setting is made to the random number circuit. Timer interrupt process execution permission means (for example, the part where the CPU 106 executes the process in step S14) that permits execution of the timer interrupt process that occurs periodically (for example, every 2 milliseconds) after being performed, While the timer interrupt process is being executed (for example, while the game control interrupt process is being executed by the CPU 106), the display result in the variable display is set as the specific display result based on the start signal input from the start signal output means. Display result determining means (for example, the CPU 106 performs special symbol normal processing in step S150 and jackpot judgment in step S151). A latch start signal (for example, a latch start winning signal SN) based on the start signal input from the start signal output means during execution of the timer interrupt process. And a start signal output means for latching that outputs to the random number circuit (for example, a portion where the CPU executes the process of step S254), and the random number circuit receives the reference clock signal input from the clock signal generation means A preceding clock signal generating means (for example, a clock signal output circuit 124) for generating a preceding clock signal (for example, a random number generating clock signal S1) with a predetermined period and outputting the preceding clock signal, and the preceding clock signal generating A first timing at which the preceding clock signal input from the means changes in a predetermined manner every predetermined period (for example, a random number) Numerical value updating means (for example, counter 121) for updating numerical data (for example, count value C) at the timing T51, T52,..., When the raw clock signal S1 rises from low level to high level, and the first Latch signal output means (for example, a latch signal generation circuit 133 shown in FIG. 38) for outputting a latch start signal input from the latch start signal output means as a latch signal (for example, latch signal SL) at the timing, and the latch A latch signal that delays a latch signal input from the signal output means by a period different from an integral multiple of the predetermined period to generate a delayed latch signal (for example, delayed latch signal SD), and outputs the delayed latch signal Delay means (for example, the delay circuit 232 shown in FIG. 38) and the latch signal delay means are input. Random value storage means for storing numerical data updated by the numerical value updating means as a random value (for example, a value of random R) at the second timing (for example, timing T81) when the delayed latch signal changes in the predetermined manner. (For example, the random value storage circuit 131), and the display result determining means reads the random number value from the random number storage circuit (for example, the CPU 106 executes the processing of steps S256 to S262), and the read random value Is determined to match a predetermined determination value data (for example, “3” or the like), thereby determining whether or not the display result in the variable display is a specific display result.

  The present invention has the following effects.

  According to the configuration of the first aspect, since the random number circuit is built in the microprocessor together with the game control means, a board space can be secured. In addition, by incorporating the random number circuit in the microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit due to the installation of an illegal board or the like from the outside, and forgery can be prevented. . Further, since the microprocessor can control the update operation of the random number value stored in the random value storage unit according to the setting by the random number circuit setting unit, for example, by performing a different setting for each gaming machine, the microprocessor reads the random value from the random value storage unit. Thus, the randomness of the random number used for determining whether or not the display result in the variable display is the specific display result can be improved. In addition, the random number circuit generates the preceding clock signal by the preceding clock signal generating unit without inverting the reference clock signal output from the clock signal generating unit, and the preceding clock signal is generated in a predetermined mode every predetermined period. At any one of the changing first timing and the second timing at which the delayed clock signal output from the delayed clock signal generating means changes in a predetermined manner every predetermined period, the numerical value updating means The numerical data is updated, and the start signal input from the start signal output means is output as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means in the first timing and the second timing. The signal is output as a latch signal by the means. Thereby, the update timing of the numerical data and the output timing (latch timing) of the latch signal can be reliably made different, so that the random value can be acquired reliably and stably. Further, according to this configuration, since the display result determination unit reads the random number value from the random value storage unit based on the input of the start signal, useless processing can be omitted.

  According to the configuration of claim 2, since the random number value stored in the random value updating means can be updated up to the preset maximum value of the random number as an upper limit, a random number different for each gaming machine can be updated. By setting the maximum value, it is possible to improve the randomness of the random number that is read from the random value storage means and used to determine whether or not the display result in variable display is the specific display result.

  According to the configuration of the third aspect, it is possible to prevent a value equal to or smaller than the predetermined lower limit value from being set in the random number circuit as the maximum value of the random number.

  According to the configuration of the fourth aspect, the predetermined initial value in the numerical data updated by the numerical value updating means is changed, and detection of a cycle in which the numerical data is updated from the predetermined initial value to the predetermined final value is detected. By making it difficult, it is possible to prevent an illegal act such as outputting a predetermined signal at a timing when the random number value read from the random number storage means coincides with the predetermined determination value data, and causing frequent occurrence of a specific gaming state.

  According to the configuration described in claim 5, when the initial value changed by the initial value changing means is larger than the maximum value of the random number set in the random number circuit, the initial value can be further changed, so that the random value value is stored. It is possible to prevent the numerical data output to the means from becoming larger than the maximum random number.

  According to the configuration of the sixth aspect, the permutation, which is the update order of the numerical data input to the random value storage means, is changed to read out from the random value storage means and specify the display result in the variable display. The randomness of the random numbers used to determine whether or not the result can be increased.

  According to the configuration of claim 7, since the random number value can be stored in the random value storage unit by the selected random number update method, the random value storage unit can be selected by selecting a different random number update method for each gaming machine. Thus, the randomness of the random number used to determine whether or not the display result in the variable display is used as the specific display result can be improved. In addition, since it is possible to specify the timing at which the numerical value updating means updates the numerical data and the timing at which the numerical value data is stored in the random value storage means as random numbers, it is possible to prevent reading of random numbers that have not been updated. Can do.

  According to the configuration of claim 8, the numerical data is updated by the numerical value updating means for each preset period, and the updated numerical data is stored as a random value in the random value storage means to update the random value. By setting a different period for each gaming machine, the random number read out from the random value storage means and used to determine whether or not the display result in the variable display is the specific display result is used. Randomness can be improved.

  According to the structure of Claim 9, it can prevent that the value below a predetermined | prescribed lower limit is set to a random number circuit as an update period.

  According to the configuration of the tenth aspect, since the random number circuit can be activated after setting the random number circuit to update the random number value, before the random number circuit is set after the power supply is started. In addition, the problem that the random number circuit starts generating random numbers can be prevented.

  According to the configuration of the eleventh aspect, even when the system is reset by the system reset means, the random number circuit can be activated again.

  According to the structure of claim 12, the random number circuit does not directly output the start signal input from the start signal output means to the latch signal output means, but measures the input time of the start signal by the timer means, When the measurement time reaches a preset time, a start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting the latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration of the thirteenth aspect, the timer means is set with a time shorter than the time until the number of executions of the timer interrupt processing reaches a predetermined time as the predetermined time. It is possible to prevent the random value read by the means from the random value storage means from being the same as the previously read random value.

  According to the configuration of the fourteenth aspect, the game control means can make the random value storage means readable only when the display result determination means reads the random number value. It can be performed stably.

  According to the configuration of the fifteenth aspect, in the random number circuit, when the random number value stored in the random value storage unit is updated, the random number value is read from the random value storage unit by the display result determination unit. Therefore, the random number value can be updated reliably and stably.

  According to the configuration of the sixteenth aspect, the random number circuit updates the random number value stored in the random value storage unit when the display result determination unit reads the random value from the random number storage unit. Therefore, it is possible to reliably and stably acquire a random value.

  According to the configuration of the seventeenth aspect, since the random number circuit is built in the microprocessor together with the game control means, a board space can be secured. In addition, by incorporating the random number circuit in the microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit due to the installation of an illegal board or the like from the outside, and forgery can be prevented. . Further, since the microprocessor can control the update operation of the random number value stored in the random value storage unit according to the setting by the random number circuit setting unit, for example, by performing a different setting for each gaming machine, the microprocessor reads the random value from the random value storage unit. Thus, the randomness of the random number used for determining whether or not the display result in the variable display is the specific display result can be improved. In addition, the random number circuit generates the preceding clock signal by the preceding clock signal generating unit without inverting the reference clock signal output from the clock signal generating unit, and the preceding clock signal is generated in a predetermined mode every predetermined period. At the first changing timing, the numerical data is updated by the numerical value updating means, the start signal input from the start signal output means is output as a latch signal by the latch signal output means, and the latch signal is predetermined by the latch signal delay means. A delayed latch signal is generated and output after being delayed by a period different from an integral multiple of the period. The random value storage means stores the numerical data updated by the numerical value updating means as a random value at the second timing when the delayed latch signal input from the latch signal delay means changes in a predetermined manner. Thereby, the update timing of the numerical data and the latch timing of the numerical data can be reliably made different, so that the random value can be acquired reliably and stably. Further, according to this configuration, since the display result determination unit reads the random number value from the random value storage unit based on the input of the start signal, useless processing can be omitted.

  According to the configuration of the eighteenth aspect, since the random number circuit is built in the microprocessor together with the game control means, a board space can be secured. In addition, by incorporating the random number circuit in the microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit due to the installation of an illegal board or the like from the outside, and forgery can be prevented. . Further, since the microprocessor can control the update operation of the random number value stored in the random value storage unit according to the setting by the random number circuit setting unit, for example, by performing a different setting for each gaming machine, the microprocessor reads the random value from the random value storage unit. Thus, the randomness of the random number used for determining whether or not the display result in the variable display is the specific display result can be improved. In addition, the random number circuit generates the preceding clock signal by the preceding clock signal generating unit without inverting the clock signal output from the clock signal generating unit, and the preceding clock signal changes in a predetermined manner every predetermined cycle. Numerical data is updated by the numerical value updating means at any one timing of the first timing and the second timing at which the delayed clock signal output from the delayed clock signal generating means changes in a predetermined manner every predetermined period. And the latch input from the game control means (latch start signal output means) at a timing different from the timing at which the numerical data is updated by the numerical value updating means of the first timing and the second timing. Output start signal as a latch signal. Thereby, the update timing of the numerical data and the output timing (latch timing) of the latch signal can be reliably made different, so that the random value can be acquired reliably and stably. Further, according to this configuration, since the display result determination unit reads the random number value from the random value storage unit based on the input of the start signal, useless processing can be omitted. Further, the latch start signal output means outputs the latch start signal to the latch signal output means based on the input of the start signal from the start signal output means, so that the start signal is sent from the start signal output means to the random number circuit. There is no need to provide a route for supplying the water. For this reason, the hardware configuration of the gaming machine can be simplified.

  According to the structure of the nineteenth aspect, since the random number circuit is built in the microprocessor together with the game control means, a board space can be secured. In addition, by incorporating the random number circuit in the microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit due to the installation of an illegal board or the like from the outside, and forgery can be prevented. . Further, since the microprocessor can control the update operation of the random number value stored in the random value storage unit according to the setting by the random number circuit setting unit, for example, by performing a different setting for each gaming machine, the microprocessor reads the random value from the random value storage unit. Thus, the randomness of the random number used for determining whether or not the display result in the variable display is the specific display result can be improved. In addition, the random number circuit generates the preceding clock signal by the preceding clock signal generating unit without inverting the reference clock signal output from the clock signal generating unit, and the preceding clock signal is generated in a predetermined manner every predetermined cycle. At the first changing timing, the latch start signal input from the game control means (latch start signal output means) is output as a latch signal, and the latch signal is set to an integral multiple of a predetermined period by the latch signal delay means. Creates a delayed latch signal with a delay of a different period and outputs it. The random value storage means stores the numerical data updated by the numerical value updating means as a random value at the second timing when the delayed latch signal input from the latch signal delay means changes in a predetermined manner. Thereby, the update timing of the numerical data and the latch timing of the numerical data can be reliably made different, so that the random value can be acquired reliably and stably. Further, according to this configuration, since the display result determination unit reads the random number value from the random value storage unit based on the input of the start signal, useless processing can be omitted. Further, the latch start signal output means outputs the latch start signal to the latch signal output means based on the input of the start signal from the start signal output means, so that the start signal is sent from the start signal output means to the random number circuit. There is no need to provide a route for supplying the water. For this reason, the hardware configuration of the gaming machine can be simplified.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) that has not yet been derived and displayed when it constitutes a part of a jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).
The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is arranged. On the lower side of the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus (large winning opening) 7, an ordinary symbol display 40, and the like are provided.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information in a plurality of display areas. For example, a game ball may win a normal variable winning ball device 6. In the special figure game, which is an execution condition, variable display of three display symbols (special symbols) consisting of numbers, letters, symbols, etc. is started. After a certain period of time, the symbols are displayed in the order of left, right, and middle. Confirm. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. Here, in the special figure game by the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, The pachinko gaming machine 1 enters a special gaming state (probability improvement state) following the end of the jackpot gaming state, and thereafter, the probability that the display result in the special figure game becomes a jackpot combination is improved until a predetermined condition is satisfied. In the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 is configured to include a light emitting diode (LED) or the like, and is lit, blinked, or flashed in a normal diagram game in which a game ball passes through a predetermined pass gate provided in the game area. Color development is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normally variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 3). (Community). The variable display of the special symbol based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in a special figure holding memory 170 (FIG. 25) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 3). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to the detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2) which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10 that functions as power supply means, a main board 11, a display control board 12, a voice control board 13, a lamp control board 14, and a payout control board 15. And an information terminal board 16 are disposed at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  The control command transmitted from the main board 11 to the display control board 12 is a display control command. FIG. 3 is a block diagram showing a circuit configuration of the main board 11 and signal lines of display control commands transmitted from the main board 11 to the display control board 12. As shown in FIG. 3, in this embodiment, a display control command is sent from the main board 11 to the display control board 12 through eight signal lines of display control signals CD0 to CD7. A signal line for a display control INT signal for transmitting and receiving a strobe signal is also wired between the main board 11 and the display control board 12.

  As shown in FIG. 3, the main board 11 is connected with wiring from the start winning a prize opening switch 70. The main board 11 is also connected with wiring from a special variable winning ball apparatus 7 which is a big winning opening and various switches for detecting winning of a game ball to other winning openings. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The main board 11 includes a game control microprocessor 100, a switch circuit 109, a solenoid circuit 110, and the like. The game control microprocessor 100 is, for example, a one-chip microprocessor, and includes a clock circuit 101, a reset controller 102 that functions as a system reset means, a random number circuit 103, a ROM (Read Only Memory) 104 that stores a game control program, and the like. A RAM (Random Access Memory) 105 used as a work memory, a CPU (Central Processing Unit) 106 that performs a control operation, a CTC (Counter Timer Circuit) 107 that sends an interrupt request signal to the CPU, and an I / O (Input / Input) Output) port 108 is built-in.

The clock circuit 101 outputs a system clock signal to the CPU 106, and outputs a reference clock signal CLK having a predetermined cycle generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuit 103. When a low level signal is input for a certain period, the reset controller 102 outputs a predetermined initialization signal to the CPU 106, the random number circuit 103, and the like, thereby resetting the game control microprocessor 100 as a system.

  FIG. 4 is a block diagram illustrating a configuration example of the random number circuit 103. As shown in FIG. 4, the random number circuit 103 includes a counter 121 functioning as a numerical value updating unit, a comparator 122 functioning as an update range regulating unit, a count value permutation changing circuit 123 functioning as a numerical value permutation changing unit, and a random number Clock signal output circuit 124 that functions as a generation clock signal generation unit, count value update signal output circuit 125, random number read signal output circuit 126, random number update method selection signal output circuit 127, and function as update signal selection unit Selector 128, random number circuit activation signal output circuit 130, random value storage circuit 131 functioning as random value storage means, delay circuit 132 functioning as clock signal delay means, and latch signal generation functioning as latch signal output means Circuit 133 and timer circuit 134 functioning as a timer means. To have. For example, the random number circuit 103 generates a random R that is a random number for jackpot determination that determines whether or not the pachinko gaming machine 1 is put into a jackpot gaming state by generating a jackpot.

  In response to the signal selected and input by the selector 128, the counter 121 cyclically updates the output count value C from the initial value to the final value according to a certain rule. When the counter 121 updates the count value C to the final value, the counter 121 outputs a notification signal to that effect to the CPU 106, and the CPU 106 responding to the notification signal changes the initial value. In this embodiment, every time the rising edge in the signal from the selector 128 is input, the counter 121 counts up the count value C from “1” to “4095” by one and counts up to “4095”. When it is up, a notification signal to that effect is output to the CPU 106. Then, the CPU 106 responding to this notification signal changes the initial value, and the counter 121 counts up again from this changed initial value to “4095”.

  The count value permutation change circuit 123 includes a count value permutation change register (RSC) 136 that stores count value permutation change data “01h” for requesting change of the permutation that is the update order of count values, and an update rule selection register (RRC). 142 and an update rule memory 143. When the count value permutation change data “01h” is stored in the count value permutation change register 136, the count value permutation change circuit 123 sets the permutation different from the permutation when the count value permutation change data “01h” is not stored. change.

  FIG. 5 is a block diagram illustrating a configuration example of the update rule selection register 142. As shown in FIG. 5, the update rule selection register 142 is an 8-bit register, and its initial value is set to “0 (= 00h)”. The update rule selection register 142 is configured such that bits 0 to 3 are writable and readable, and bits 4 to 7 are not writable and readable. Therefore, even if a value is written in bit 4 to bit 7 of the update rule selection register 142, the value is invalid, and all the values read from bit 4 to bit 7 are “0 (= 0000b)”.

  In response to the count value permutation change data “01h” being written in the count value permutation change register 136, the value (register value) of the update rule selection register 142 is changed from “0 (= 00h)” to “15 (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 136, the register value is incremented by “1” from “0”, and when it becomes “15”, it returns to “0” again.

  FIG. 6 is a block diagram illustrating a configuration example of the update rule memory 143. As shown in FIG. 6, the update rule memory 143 stores the count value update rule and the value of the update rule selection register 142 in association with each other. In the update rule memory 143, the update rule A that is the same as the update rule of the counter 121 is stored in correspondence with the register value “0”, and the update rules B to P different from the update rule of the counter 121 are the register value “1”. To "15".

  When the count value permutation change data “01h” is written in the count value permutation change register 136, the count value permutation change circuit 123 shown in FIG. 4 receives the final count value “4095” from the counter 121. Based on the updated register value, the update rule of the count value to be output is switched by selecting and setting the update rule from the update rule memory 143. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count value according to the switched update rule.

  In this manner, the count value permutation changing circuit 123 switches the update rule in response to the count value permutation change data “01h” being written in the count value permutation change register 136, thereby outputting the permutation of the count values to be output. To change.

  FIG. 7 is an explanatory diagram of the operation of changing the count value permutation in the count value permutation changing circuit 123. As shown in FIG. 7, when the count value permutation change data “01h” is written to the count value permutation change register 136 at a predetermined timing by the CPU 106, the register value is incremented by 1, for example, from “0” to “1”. Updated. Thereafter, the count value permutation changing circuit 123 updates the count value according to the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 121. Output. At this time, the permutation of count values output from the count value permutation changing circuit 123 is “1 → 2 →... → 4095”.

  When the final value “4095” of the count value is input from the counter 121, the count value permutation changing circuit 123 stores “update rule B” corresponding to the updated register value “1” from the update rule memory 143. Select and set. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count value according to the “update rule B” set and set. Thereby, the permutation of the count values output from the count value permutation changing circuit 123 is changed from “1 → 2 →... → 4095” to “4095 → 4094 →.

  Thereafter, the count value permutation change register 136 is initialized as described later, and the permutation of count values output from the count value permutation change circuit 123 remains “4095 → 4094 →... → 1”.

  When the count value permutation change data “01h” is written again to the count value permutation change register 136 by the CPU 106, the register value is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 121, the count value permutation changing circuit 123 selects “update rule C” corresponding to the register value “2” from the update rule memory 143. Set. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count values according to the “update rule C” selected and set, thereby further changing the permutation of the count values, "1 → 3 → ... → 4095 → 2 ... → 4094".

  As described above, after the count value permutation change register 136 is initialized, the count value permutation data “01h” is written again in the count value permutation change register 136, whereby the permutation of the changed count value can be further changed. .

  FIG. 8 is a diagram illustrating a configuration example of the count value permutation change register 136. As shown in FIG. 8, the count value permutation change register 136 is a readable 8-bit register, and its initial value is set to “0 (= 00h)”. The count value permutation change register 136 is configured so that only bit 0 is writable and writable. Therefore, even if a value is written to bit 1 to bit 7, the value is invalid, and bit 1 to bit 7 are written. All the values read from “0” are “0 (= 0000000b)”.

  In response to the count value permutation change circuit 123 starting the update operation of the count values according to the switched update rule, the CPU 106 counts the count value permutation change register 136 in which the count value permutation change data “01h” is written. Is initialized and the stored value is returned to the initial value “0 (= 00h)”.

  The comparator 122 shown in FIG. 4 includes a random number maximum value setting register (RMX) 135 that stores random number maximum value setting data for specifying the maximum value of random R (random number maximum value). The comparator 122 regulates the update range of the count value by the counter 121 according to the random number maximum value setting data stored in the random number maximum value setting register 135. In this embodiment, the random number maximum value (for example, “255”) designated by the count value input from the counter 121 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 135. When the input count value is less than or equal to the maximum random number value, the input count value is output to the random value storage circuit 131. When the input count value is greater than the maximum random number value, the count value update signal Is output to the counter 121.

  FIG. 9 is an explanatory diagram of a count value update operation in the counter 121 and the comparator 122. FIG. 9 illustrates an example in which the update rule A is selected in the count value permutation changing circuit 123 and the maximum random number is set to “255”.

  When the input count value is “1” to “255”, the comparator 122 outputs the input count value to the random value storage circuit 131 as it is. When the input count value becomes a value “256” larger than the random number maximum value “255”, the comparator 122 outputs a count value update signal to the counter 121 to update the count value to “257”. By repeating such an operation, the comparator 122 continuously counts up the input count value from “256” to “4095” by the counter 121. When the counter 121 counts up to “4095”, it outputs a notification signal to that effect to the CPU 106.

  When the initial value changed by the CPU 106 in response to the notification signal is larger than the random number maximum value “255” (for example, “256”), the counter 121 outputs the count value of the changed initial value to the comparator 122. The comparator 122 outputs a count value update signal to the counter 121 to update the count value. By repeating such an operation, the comparator 122 continuously counts up the input count value to “4095” by the counter 121 and causes the counter 121 to output a notification signal. Then, the initial value is further changed by the CPU 106 responding to the notification signal. In this way, the initial value is changed until it becomes a value equal to or less than the maximum random number. When the initial value changed by the CPU 106 in response to the notification signal becomes equal to or smaller than the random number maximum value “255” (for example, “15”), the counter 121 compares the count value of the changed initial value with a comparator. The comparator 122 outputs the input count value to the random value storage circuit 131 as it is.

  By the operation in the counter 121 and the comparator 122 described above, the random number circuit 103 outputs a random number value storage circuit 131 by outputting only the count value less than or equal to the random number maximum value stored in the random number maximum value setting register 135. It is possible to generate a random R whose upper limit is the random number maximum value “255” stored in the maximum value setting register 135. Further, by changing until the initial value becomes equal to or less than the random number maximum value, a value equal to or less than the random number maximum value “255” is input to the random value storage circuit 131 as the changed initial value.

  FIG. 10 is a block diagram illustrating a configuration example of the random number maximum value setting register 135. As shown in FIG. 10, the random number maximum value setting register 135 is a 16-bit register, and its initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 135 is configured so that bits 0 to 11 are writable and readable, and bits 12 to 15 are not writable and readable. Therefore, even if a value is written in bit 12 to bit 15 of the random number maximum value setting register 135, the value is invalid, and all the values read from bit 12 to bit 15 are “0 (= 0000b)”.

  When random number maximum value setting data “0000h” to “0003h” for designating a value smaller than the lower limit “4” is written in the random number maximum value setting register 135, the random number maximum value setting register 135 is stored in the random number maximum value setting register 135 by the CPU 106. The random number maximum value setting data “0FFFh” designating the initial value “4095” is stored. That is, the maximum random number values that can be set in the random number maximum value setting register 135 are “4” to “4095”. The CPU 106 controls the random number maximum value setting register 135 in which the random number maximum value setting data is written to be unwritable until the game controller microprocessor 100 is system-reset by the reset controller 102.

  The clock signal output circuit 124 illustrated in FIG. 4 includes a cycle setting register (RPS) 137 that stores cycle setting data that specifies the cycle of the clock signal output to the selector 128 and the delay circuit 132 (count value update cycle). The clock signal output circuit 124 divides the reference clock signal CLK input from the clock circuit 101 outside the random number circuit 103 based on the period setting data stored in the period setting register 137, A clock signal (random number generation clock signal S1) used to generate a random number value is generated, and the generated random number generation clock signal S1 is output to the selector 128 and the delay circuit 132. For example, when the cycle setting data written in the cycle setting register 137 is “0Fh (= 16)”, the clock signal output circuit 124 divides the reference clock signal CLK input from the clock circuit 101 by 16 to generate a random number. A clock signal S1 is generated. The cycle of the random number generating clock signal S1 generated at this time is “system clock signal cycle × 128 × 16”.

  FIG. 11 is a block diagram illustrating a configuration example of the period setting register 137. As shown in FIG. 11, the period setting register 137 is a writable and readable 8-bit register, and its initial value is set to “256 (= FFh)”.

  When the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 137, the CPU 106 sets the lower limit value in the cycle setting register 137. Cycle setting data “07h” for designating “cycle of system clock signal × 128 × 7” is stored. That is, the period that can be set in the period setting register 137 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. The CPU 106 controls the period setting register 137 in which the period setting data is written to be unwritable until the game controller microprocessor 100 is system reset by the reset controller 102.

  The count value update signal output circuit 125 shown in FIG. 4 includes a count value update register (RGN) 138 that stores count value update data “01h” for requesting update of the count value. In response to the count value update data “01h” being written in the count value update register 138, the count value update signal output circuit 125 outputs the count value update signal S3 to the selector 128.

  FIG. 12 is a block diagram illustrating a configuration example of the count value update register 138. As shown in FIG. 12, the count value update register 138 is an 8-bit register that cannot be read. Only the bit 0 is writable, and even if a value is written to the bits 1 to 7, the value is invalid. is there.

  The random value read signal output circuit 126 shown in FIG. 4 includes a random value acquisition register (RLT) 139 that stores random value acquisition data “01h” for requesting acquisition of the count value to the random value storage circuit 131. . The random value read signal output circuit 126 outputs a random value read signal to the latch signal generation circuit 133 in response to the random value fetch data “01h” being written in the random value fetch register 139.

  FIG. 13 is a block diagram illustrating a configuration example of the random value acquisition register 139. As shown in FIG. 13, the random value fetch register 139 is an unreadable 8-bit register and is configured so that only bit 0 can be written. Even if a value is written in bits 1 to 7, the value is invalid. It is.

  The random number update method selection signal output circuit 127 shown in FIG. 4 is a random number update method selection data that designates a random number update method selected from the first and second random number update methods that are methods for updating the value of the random R. Random number update method selection register (RTS) 140 is stored. The random number update method selection signal output circuit 127 responds to the writing of the random number update method selection data in the random number update method selection register 140 and corresponds to the random number update method specified by the written random number update method selection data. The random number update method selection signal to be output is output to the selector 128 and the latch signal generation circuit 133.

  FIG. 14A is a block diagram illustrating a configuration example of the random number update method selection register 140. As shown in FIG. 14A, the random number update method selection register 140 is an 8-bit register, and its initial value is set to “00h”. The random number update method selection register 140 is configured such that bits 0 to 1 are writable and readable, and bits 2 to 7 are not writable and readable. Therefore, even if a value is written in bits 2 to 7 of the random number update method selection register 140, the value is invalid, and all values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 14B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 140. As shown in FIG. 14B, the random number update method selection data is composed of 2-bit data, “01b” is data specifying the first random number update method, and “10b” is the second This data specifies the random number update method. When the random number update method selection data “00b” or “11b” is written in the random number update method selection register 140, the random number circuit 103 cannot be activated.

  When the random number update method selection signal output circuit 127 receives a random number update method selection signal (first random number update method selection signal) corresponding to the first random number update method, the selector 128 shown in FIG. The count value update signal S3 output from the signal output circuit 125 is selected and output to the counter 121. On the other hand, when the random number update method selection signal (second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 127, the selector 128 receives the clock signal output circuit 124. The random number generation clock signal S1 output from the above is selected and output to the counter 121. Note that the selector 128 receives a clock signal in response to the count value update signal S3 output from the count value update signal output circuit 125 when the first update method selection signal is input from the random number update method selection signal output circuit 127. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal S 1 output from the signal output circuit 124 may be output to the counter 121.

  The random number circuit activation signal output circuit 130 includes a random number circuit activation register (RST) 141 that stores random number circuit activation data “80h” for requesting activation of the random number circuit 103. The random number circuit activation signal output circuit 130 outputs a predetermined random number circuit activation signal in response to the random number circuit activation data “80h” being written in the random number circuit activation register 141, and the counter 121 and the clock signal output circuit 124. And the random number circuit 103 is activated by starting the update operation of the count value by the counter 121 and the output operation of the internal clock signal by the clock signal output circuit 124.

  FIG. 15 is a block diagram illustrating a configuration example of the random number circuit activation register 141. As shown in FIG. 15, the random number circuit activation register 141 is an 8-bit register, and its initial value is set to “00h”. The random number circuit start register 141 is configured so that only bit 7 can be read and read. Even if a value is written in bits 0 to 6, the value is invalid, and all the values read from bit 0 to bit 6 are “ 0 (= 0000b) ".

  The random value storage circuit 131 shown in FIG. 4 is an 8-bit register, for example, and stores a random R value extracted in a winning process in step S142 described later. In response to the latch signal SL output from the latch signal generation circuit 133, the random value storage circuit 131 stores the count value C output from the counter 121 via the comparator 122 as a random R value. Update the value of random R.

  FIG. 16 is a circuit diagram showing a configuration example of the random value storage circuit 131. As shown in FIG. 16, the random value storage circuit 131 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, eight flip-flop circuits 211 to 218, and eight OR circuits. 221 to 228.

  The input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 133 and the output terminal of the NOT circuit 204, and the output terminals are the input terminal of the NOT circuit 202 and the clock terminals Clk1 to Clk1 of the flip-flop circuits 211 to 218. It is connected to Clk8. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 106 built in the game control microprocessor 100, and the output terminal is connected to the input terminal of the NOT circuit 204. An input terminal of the NOT circuit 204 is connected to an output terminal of the AND circuit 203, and an output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 221 to 228.

  The input terminals D1 to D8 of the flip-flop circuits 211 to 218 are connected to the output terminal of the comparator 122. The clock terminals Clk1 to Clk8 of the flip-flop circuits 211 to 218 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q8 are connected to the other input terminals of the OR circuits 221 to 228, respectively.

  The input terminals of the OR circuits 221 to 228 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 211 to 218, and the output terminal is connected to the CPU 106 built in the game control microprocessor 100. Yes.

  The operation of the random value storage circuit 131 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the CPU 106 built in the gaming control microprocessor 100 (when one input of the AND circuit 203 is low level), the latch signal generation circuit 133 When the latch signal SL is input from (in the example shown in FIG. 17, at the timings T1, T2, and T7), the inputs of the AND circuit 201 are both at a high level, and the signal SR output from the output terminal is Become high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk8 of the flip-flop circuits 211 to 218.

  The flip-flop circuits 211 to 218 respond to the rising edges of the signal SR input from the clock terminals Clk1 to Clk8, and receive bit data C1 to the count value C input from the comparator 122 via the input terminals D1 to D8. C8 is latched and stored as bit data R1 to R8 of random values, and the stored random R bit data R1 to R8 is output from the output terminals Q1 to Q8.

  When the output control signal SC is not input (in the example shown in FIG. 17, in the period up to the timing T3, the period after the timing T6), one of the inputs of the AND circuit 203 is at the low level, so that the output is output from the output terminal. The signal SG to be output becomes low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one input terminal of the OR circuits 221 to 228.

  Thus, since one input of the OR circuits 221 to 228 is at the high level, regardless of whether the signal input to the other input terminal is at the high level or the low level, that is, the input random R Regardless of whether the values of the bit data R1 to R8 are “0” or “1”, the signals SO1 to SO8 output from the OR circuits 221 to 228 are all at a high level (“1”). . As a result, the value output from the random value storage circuit 131 is always “255 (= 11111111b)”, and the random R cannot be read from the random value storage circuit 131. That is, when the output control signal SC is not input, the random value storage circuit 131 is in a non-readable (disabled) state.

  When the latch signal SL is not input from the latch signal generation circuit 133 and the output control signal SC is input from the CPU 106 (in the example shown in FIG. 17, the period from the timing T4 to the timing T6), the AND circuit Since both inputs 203 are at a high level, the signal SG output from the output terminal thereof is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminals of the OR circuits 221 to 228.

  Since one input of the OR circuits 221 to 228 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the values of the random R bit data R1 to R8 input to the other input terminals of the OR circuits 221 to 228 are directly from the output terminals of the OR circuits 221 to 228 (the values of the bit data R1 to R8 are “1”). "1" and "0" when "0") are output. Thereby, the random R can be read from the random value storage circuit 131. That is, when the output control signal SC is input, the random value storage circuit 131 is in a readable (enable) state.

  However, when the latch signal SL is input from the latch signal generation circuit 133 before the output control signal SC is input from the CPU 106, one input of the AND circuit 203 is at a low level. Even when the output control signal SC is input (in the example shown in FIG. 17, the period from the timing T3 to the timing T4), the signal SG output from the output terminal is low level. Will remain. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 221 to 228.

  Thus, since one input of the OR circuits 221 to 228 is at a high level, the output from the OR circuits 221 to 228 is output regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO8 are all at a high level and remain in a state where the random R cannot be read from the random value storage circuit 131 in spite of the input of the output control signal SC. That is, when the latch signal SL is input, the random value storage circuit 131 becomes incapable of receiving the output control signal SC.

  In addition, when the output control signal SC is input from the CPU 106 before the latch signal SL is input from the latch signal generation circuit 133, one input of the AND circuit 201 becomes low level. Even if the latch signal SL is input while SC is being input (timing T5 in the example shown in FIG. 17), the signal SR output from the output terminal remains at the low level. For this reason, the signal SR input to the clock terminals Clk1 to Clk8 of the flip-flop circuits 211 to 218 does not rise from the low level to the high level, and the random R bit data R1 to R1 stored in the flip-flop circuits 211 to 218. R8 is not updated despite the latch signal SL being input. That is, when the output control signal SC is input, the random value storage circuit 131 becomes incapable of receiving the latch signal SL.

  The delay circuit 132 shown in FIG. 4 delays the random number generation clock signal S1 input from the clock signal output circuit 124 by a period different from a period that is an integral multiple of the period of the random number generation clock signal S1. A clock signal S2 is generated. The delay circuit 132 outputs the generated delayed clock signal S2 to the latch signal generation circuit 133.

  The latch signal generation circuit 133 is configured by using a selector, a flip-flop circuit, and the like. The latch signal SL is output in accordance with the random value update method designated by the random number update method selection signal from the selection signal output circuit 127. That is, when the first random number update method selection signal output circuit 127 receives the first random number update method selection signal output circuit 127, the latch signal generation circuit 133 selects the delay clock signal S2 output from the delay circuit 132, and the latch signal SL. Is output to the random value storage circuit 131. On the other hand, the latch signal generation circuit 133 delays the random value read signal output from the random value read signal output circuit 126 when the second random number update method selection signal is input from the random number update method selection signal output circuit 127. In synchronization with the rising edge of the delayed clock signal S2 output from the circuit 132, it is output to the random value storage circuit 131 as a latch signal SL.

  The timer circuit 134 measures the time during which the start winning signal SS is input from the start winning opening switch 70, and when the measured time reaches a predetermined time (for example, 3 milliseconds), the random value read signal output circuit 126 The random value fetch data “01h” is written in the random number fetch register 139. For example, the timer circuit 134 is configured by an up counter or a down counter that starts in response to the input of a high level signal, and a reference that is sequentially input from the clock circuit 101 while the input is at a high level. The clock signal CLK is counted up or down. When the count value obtained by counting up or down reaches a value corresponding to 3 milliseconds, it is determined that the input signal is the start winning signal SS, and the random number value corresponding to the start winning signal SS is fetched. The data “01h” is written into the random value fetch register 139.

  FIG. 18 is a diagram showing an example of an address map in the gaming control microprocessor 100 shown in FIG. As shown in FIG. 18, the area from address 0000h to 1FFFh is allocated to the ROM 104, the area from address 7E00h to 7FFFh is allocated to the RAM 105, and the area from address FD00h to FE00h is the random number maximum value setting register 135. Etc. are assigned to built-in registers.

  A program (user program) 150 created in advance by the user is stored in the user program area in the area from 0000h to 1F7Fh in the ROM 104, and the CPU 106 is used by the user in the user program management area in the area from 1F80h to 1FFFh. Data necessary for executing the program 150 (user program execution data) is stored. Further, the area from 7E00h to 7EFFh in the RAM 105 is not used, and the 7EFFh to 7FFFh addresses are used as work areas.

  FIG. 19 is a diagram showing an example of an address map in the user program management area shown in FIG. As shown in FIG. 19, in the area of address 1F97h, an initial value changing method selected by the user from the first, second, and third initial value changing methods, which are methods for changing the initial value, is designated. Value change method setting data is stored. In the area of address 1F98h, RAM address data for specifying an address in RAM 105 (designated RAM address) designated in advance by the user from among addresses 7EFFh to 7FFFh assigned to RAM 105 is stored as a lower value. . In the area of address 1F99h, the RAM address data at the address next to the designated RAM address is stored as a higher value.

  FIG. 20 is an explanatory diagram of an example of initial value change method setting data selected by the user. As shown in FIG. 20, the initial value change data is composed of 8-bit data, “00h” is data specifying that the initial value is not changed, and “01h” is the first initial value change. This data specifies the method. “02h” is data specifying the second initial value changing method, and “03h” is data specifying the third initial value changing method.

  FIG. 21 is a diagram illustrating a configuration example of the user program 150. In this embodiment, as shown in FIG. 21, the user program 150 includes a random number circuit setting program 151 composed of a plurality of types of program modules, a display result determination program 152, an initial value change program 153, a count value, A permutation change program 154 and a random value update program 155 are included.

  The random number circuit setting program 151 is a program for executing a random number circuit setting process for setting the random number circuit 103 to update the random R value. The CPU 106 executes the random number circuit setting program 151 by executing the random number circuit setting program 151. , Function as random number circuit setting means.

  FIG. 22 is a diagram illustrating a configuration example of the random number circuit setting program 151. As shown in FIG. 22, the random number circuit setting program 151 includes a random number maximum value setting module 151a, a random number update method selection module 151b, a cycle setting module 151c, and a random number circuit activation module 151d as the above-described plural types of program modules. And.

  The random number maximum value setting module 151 a is a program module for setting a random R maximum value preset by the user in the random number circuit 103. The CPU 106 executes the random number maximum value setting module 151a and writes the random number maximum value setting data designating the maximum value of the random R preset by the user, thereby obtaining the preset maximum value of the random R. The random number circuit 103 is set. For example, when the maximum value of the random R preset by the user is “255”, the CPU 106 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 135 and the random R maximum value “255”. Is set in the random number circuit 103.

  The random number update method selection module 151 b is a program module for setting a random number update method selected by the user from the first and second random number update methods in the random number circuit 103. The CPU 106 executes the random number update method selection module 151b and writes the random number update method selection data “01b” or “10b” for designating the random number update method selected by the user into the random number update method selection register 140, thereby The selected random number update method is set in the random number circuit 103. Accordingly, the game control microprocessor 100 can exhibit a function of selecting a random number update method set in the random number circuit 103 from the first and second random number update methods.

  The cycle setting module 151 c is a program module for setting the cycle of the internal clock signal preset by the user in the random number circuit 103. The CPU 106 executes the cycle setting module 151c and writes cycle setting data for designating the cycle of the internal clock signal preset by the user in the cycle setting register 137, thereby setting the cycle of the preset internal clock signal. Is set in the random number circuit 103. For example, when the period of the internal clock signal preset by the user is “system clock signal period × 128 × 16”, the CPU 106 writes the period setting data “0Fh” in the period setting register 137 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 103.

  The random number circuit activation module 151 d is a program module for activating the random number circuit 103. The CPU 106 activates the random number circuit 103 by executing the random number circuit activation module 151 d and writing the random number circuit activation data “80h” in the random number circuit activation register 141.

  The random value update program 155 is a program for updating the random R value stored in the random value storage circuit 131 when the first random number update method is selected. The CPU 106 functions as a random value updating unit by executing the random value updating program 155. The CPU 106 executes this random number update program 155 and writes the count value update data “01h” to the count value update register 138 to update the random R value stored in the random value storage circuit 131.

  The display result determination program 152 is a program for determining whether or not the display result in the special figure game is a big hit, and the CPU 106 functions as a display result determination means by executing the display result determination program 152. To do.

  The CPU 106 displays the display result determination program 152 in response to the fact that a condition (execution condition) for executing a variable symbol display (special game) for a game ball to win the normal variable winning ball device 6 is established. Is executed to read out the updated random R value from the random value storage circuit 131 and determine whether or not the display result of the special figure game by the variable display device 4 is a big hit.

  FIG. 23 is an explanatory diagram of a random R value update operation and a read operation performed by the CPU 106 when the first random number update method is selected. As shown in FIG. 23, when the first random number update method is selected, the CPU 106 writes the count value update data “01h” into the count value update register 138, thereby storing the random number value storage circuit 131. The value of random R (for example, “2”) is updated. Then, the CPU 106 determines whether the game ball has won the normal variable winning ball device 6 and the condition (execution condition) for executing the special symbol variable display (special game) is established. A random R value (eg, “2”) is read from 131. In the case of further updating the random R value stored in the random value storage circuit 131, an interval equal to or longer than the period of the system clock signal output by the clock circuit 101 from when the previous random R value was updated. The count value update data “01h” must be written to the count value update register 138. This is to secure time for reading the updated random R value from the random value storage circuit 131.

  FIG. 24 is an explanatory diagram of a random R value update operation and a read operation performed by the CPU 106 when the second random number update method is selected. As shown in FIG. 24, when the second random number update method is selected, the CPU 106 writes the random number value acquisition command “01h” into the random number value acquisition register 139 to output the count output from the counter 121. A value (for example, “2”) is taken into the random value storage circuit 131 and the value of the random R stored in the random value storage circuit 131 is updated. Then, the updated random R value (for example, “2”) is read from the random value storage circuit 131.

  Note that when the second random number update method is selected, the count value output from the counter 121 is updated unless the CPU 106 writes the random value capture command “01h” in the random value capture register 139. However, the random value stored in the random value storage circuit 131 is not updated. For example, the CPU 106 writes a random number value capture command “01h” into the random number value capture register 139, causes the count value “3” output from the counter 121 to be captured in the random value storage circuit 131, and When the stored random R value “3” is updated, if the CPU 106 does not subsequently write the random value fetch command “01h” in the random value fetch register 139, the count value output from the counter 121 is Even if “3” is updated to “4” or “5”, the random value stored in the random value storage circuit 131 is not updated, and the random value read from the random value storage circuit 131 is “3”. Will remain.

  The initial value changing program 153 shown in FIG. 21 is a program for changing the initial value of the count value updated by the counter 121, and the CPU 106 executes the initial value changing program 153 to thereby change the initial value changing means. Function as. The CPU 106 executes the initial value change program 153, and uses the initial value change method selected by the user from the first, second, and third initial value change methods to initialize the count value updated by the counter 121. Change the value. Thereby, the microprocessor 100 for game control can exhibit the function which selects the system which changes an initial value from the 1st, 2nd and 3rd initial value change system.

  More specifically, when initial value change method setting data “01h” for specifying the first initial value change method is stored in the area of address 1F97h in the user program management area shown in FIG. The initial value is changed to a value set based on an ID (Identification) number unique to the game control microprocessor 100.

  When initial value change method setting data “02h” for designating the second initial value change method is stored in the area of the user program execution data area at address 1F97h, the CPU 106 addresses address 1F97h in the user program execution data area. The designated RAM address is specified from the address data stored in the area, the value stored in the area of the specified designated RAM address is read, and the initial value is changed to the read value.

  When initial value change method setting data “03h” for designating the third initial value change method is stored in the area of address 1F97h in the user program execution data area, the CPU 106 stores the values stored in the respective addresses of the RAM 105. And the read value is added. Then, the CPU 106 changes the initial value to this added value.

  The count value permutation change program 154 writes count value permutation change data “01h” into the count value permutation change register 136 and performs count value permutation change processing for changing the permutation of the count values stored in the random value storage circuit 131. The CPU 106 functions as numerical data permutation changing means by executing the count value permutation changing program 154. The CPU 106 executes the count value permutation change program 154 and writes the count value permutation change data “01h” in the count value permutation change register 136, so that the CPU 106 outputs the random number value storage circuit 131. The permutation of the count values input to is changed.

  Further, as shown in FIG. 25, the gaming control microprocessor 100 shown in FIG. 3 includes a special figure holding memory 170, a jackpot determination table memory 171, a flag memory 172, a start winning port switch timer memory 173, It has.

  In the special figure holding memory 170, the condition (execution condition) for executing the variable display (special game) of the special symbol when the game ball wins the normal variable winning ball apparatus 6 is established, but the previous variable display is displayed. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 170 includes four entries, and each entry has a holding number and a random R value read from the random value storage circuit 131 according to the winning order in the winning order to the ordinary variable winning ball apparatus 6. Are stored in association with each other. A special symbol confirmation command is sent from the main board 11 to the display control board 12 to instruct the variable display device 4 to end the variable symbol variable display, and the special symbol variable display is terminated once or the jackpot gaming state is terminated. Each time a variable display start condition is established based on the highest level information, variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball newly wins the normal variable winning ball apparatus 6 during variable display of a special symbol or the like, the random R value read from the random value storage circuit 131 based on the winning is the highest value. Registered in an empty entry.

  The jackpot determination table memory 171 shown in FIG. 25 stores a plurality of jackpot determination tables set in order for the CPU 106 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 171 stores a normal big hit determination table 171a shown in FIG. 26A and a probable change big hit determination table 171b shown in FIG.

  In the flag memory 172 shown in FIG. 25, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 172 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a timer interrupt flag, an initial value change flag, and the like.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (described later) (FIG. 32). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

  The input state flag is a flag composed of a plurality of bits that are set or cleared according to the state of various signals input to the I / O port 108, the state of the detection signal input from the start winning award opening switch 70, and the like. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated. The initial value change flag is set to an on state in response to the notification signal output from the random number circuit 103, and is cleared to an off state when the initial value is changed.

  The start winning port switch timer memory 173 stores a timer value that is added or cleared in accordance with the start winning signal SS input from the start winning port switch 70.

  The switch circuit 109 shown in FIG. 3 takes in a detection signal from each winning port switch such as the starting winning port switch 70 and transmits it to the game control microprocessor 100. The solenoid circuit 110 drives the solenoids 21 and 22 in accordance with a command from the game control microprocessor 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The start winning opening switch 70 sends a start winning signal (high level signal) SS via the switch circuit 109 based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. To the random number circuit 103 and the CPU 106.

  The display control board 12 is for performing effect control according to the control command received from the main board 11. Specifically, the display control board 12 performs display control of the variable display device 4 and lighting control of the game effect lamp 9 and the normal symbol display 40.

  The audio control board 13 and the lamp control board 14 are sub-side control boards that execute audio output control and lamp output control independently of the main board 11 based on control commands transmitted from the main board 11. is there. The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 27 is a flowchart showing a game control main process executed by the game control microprocessor 100 mounted on the main board 11. In the main board 11, when power from the power supply board 10 is supplied, the game control microprocessor 100 is activated, and the CPU 106 first executes a game control main process shown in the flowchart of FIG. When the game control main process is started, first, the CPU 106 sets the interrupt prohibition (step S1), and then sets the interrupt mode to mode 2 (step S2).

  Thereafter, the CPU 106 sets a stack pointer designation address in the stack pointer (step S3). Then, register setting is performed for the CTC 107, which is a built-in device of the game control microprocessor 100 (step S4). For example, an interrupt vector is set for the CTC 107.

  Subsequent to step S4, the CPU 106 checks, for example, a backup flag area provided in the RAM 105 (step S5), and all or part of the RAM 105 is backed up by a predetermined data protection process when the power is last turned off. It is determined whether or not (step S6). In the pachinko gaming machine 1, when an unexpected power failure occurs, a data protection process for protecting all or a part of the data stored in the RAM 105 is performed. If such data protection processing has been performed, it is determined that there is a backup.

  When it is determined in step S6 that there is a backup (step S6; Yes), the CPU 106 performs a parity check as a backup data check, and determines whether the check result is normal (step S7). If the check result is normal (step S7; Yes), the internal state of the main board 11 and the control boards on the sub side (display control board 12, voice control board 13, lamp control board 14, and payout control board 15). A game state restoration process for returning the control state to the state at the time of power-off is executed (step S8). Then, it progresses to step S10.

  When it is determined in step S6 that there is no backup (step S6; No), or when the check result is not normal in step S7 (step S7; No), the CPU 106 clears the RAM 105 or performs a predetermined work area. Initialization processing such as initial setting is performed (step S9).

  FIG. 28 is a flowchart showing the random number circuit setting process in step S10. In this random number circuit setting process, the CPU 106 first executes a random number maximum value setting module 151a included in the random number circuit setting program 151, and sets random number maximum value setting data for specifying a random number maximum value preset by the user as a random number. By writing in the maximum value setting register 135, the preset maximum value of the random R is set in the random number circuit 103 (step S21).

  Next, the CPU 106 executes the random number update method selection module 151b included in the random number circuit setting program 151 and writes the random number update method selection data “10b” in the random number update method selection register 140, thereby performing the second random number update. The method is set in the random number circuit 103 (step S22).

  Subsequently, the CPU 106 executes the period setting module 151c included in the random number circuit setting program 151, and writes the period setting data specifying the period of the random number generation clock signal S1 preset by the user in the period setting register 137. Thus, the preset cycle of the random number generating clock signal S1 is set in the random number circuit 103 (step S23).

  Thereafter, the CPU 106 executes the random number circuit starting module 151d included in the random number circuit setting program 151, and writes the random number circuit starting data “80h” in the random number circuit starting register 141, thereby starting the random number circuit 103 (step). S24).

  By executing the random number circuit setting process as shown in FIG. 28 in this way, the random number circuit 103 operates according to a timing chart as shown in FIG. 29, for example.

  In the operation example shown in FIG. 29, the reference clock signal CLK shown in FIG. 29A is supplied from the clock circuit 101 to the random number circuit 103.

  The clock signal output circuit 124 divides the reference clock signal CLK supplied from the clock circuit 101 and is shown in FIG. 29B, for example, at a period T that rises from a low level to a high level at timings T11, T12,. A random number generating clock signal S1 is generated. In the example of operation shown in FIG. 29, for the sake of explanation, the clock signal output circuit 124 divides the reference clock signal CLK by two to generate the random number generating clock signal S1. However, in practice, the period that can be set in the period setting register 137 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. By dividing the reference clock signal CLK by a frequency dividing ratio corresponding to the cycle setting data “07h” to “FFh” set in the setting register 137, the random number generating clock signal S1 is generated. The random number generating clock signal S 1 generated by the clock signal output circuit 124 is output to the selector 128 and the delay circuit 132.

  The selector 128 selects the random number generating clock signal S1 output from the clock signal output circuit 124 in response to the second random number update method selection signal output from the random number update method selection signal output circuit 127. Output to the counter 121. The counter 121 updates the count value C and outputs it to the count value permutation change circuit 123 every time the rising edge of the random number generation clock signal S1 supplied from the selector 128 is input.

  The delay circuit 132 delays the random number generating clock signal S1 output from the clock signal output circuit 124 by ΔT (≠ nT: n is an integer), and rises from a low level to a high level at timings T21, T22,. A delayed clock signal S2 having a period T shown in FIG. The delayed clock signal S2 generated by the delay circuit 132 is output to the latch signal generation circuit 133.

  The latch signal generation circuit 133 outputs a random number read signal when the elapsed time after the start winning signal SS shown in FIG. 29D is input to the timer circuit 134 reaches a predetermined time (for example, 3 milliseconds). The random number read signal from the circuit 126 rises from a low level to a high level. In response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127, the latch signal generation circuit 133 receives the random number value read signal input from the random number value read signal output circuit 126. In synchronization with the rising edge of the delayed clock signal S2 supplied from the delay circuit 132, the latch signal SL shown in FIG.

  Accordingly, the random number circuit 103 updates the count value C at timings T11, T12, T13,... Among timings T11, T21, T12, T22, T13, T23. At T23, the latch signal SL can be output.

  In the game control main process shown in FIG. 27, following the random number circuit setting process in step S10, the CPU 106 performs setting for timer interruption by the CTC 107 (step S11). Specifically, the timer mode is set by giving interrupt permission to one of a plurality of channels included in the CTC 107 (specifically, the third channel from the 0th channel to the third channel) of the CTC 107. And specify the initial count value for the channel. Thereby, thereafter, an interrupt request signal is sent from the CTC 107 to the CPU 106 every predetermined time (for example, 2 milliseconds), and the CPU 106 can periodically execute a timer interrupt process.

  Thereafter, the CPU 106 proceeds to a loop process for monitoring whether or not a timer interrupt has occurred due to an interrupt request signal from the CTC 107. In this loop process, after setting the interrupt prohibition (step S12), the display random number update process (step S13) is executed, and when the display random number update process is completed, the interrupt permission is set (step S14).

  When the CPU 106 that has executed the game control main process shown in FIG. 27 receives the interrupt request signal from the CTC 107 and receives the interrupt request, the CPU 106 starts executing the game control interrupt process shown in FIG.

  When the game control interrupt process is started, the CPU 106 executes a predetermined power-off process, thereby making it possible to execute a predetermined data protection process or the like when the power supplied from the power supply board 10 is reduced (step) S101). Subsequently, by executing a predetermined switch process, the state of the detection signal input from each winning a prize opening switch such as the starting winning a prize opening switch 70 is determined (step S102). In the switch process, it is determined whether or not the start winning signal SS input from the start winning port switch 70 via the switch circuit 109 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the start winning port switch timer memory 173. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Next, the CPU 106 executes a display random number update process (step S103). Subsequently, the CPU 106 executes the initial value change program 153 to perform an initial value change process (step S104).

  FIG. 31 is a flowchart showing the initial value changing process in step S104. In this initial value change process, the CPU 106 first checks an initial value change flag provided in the flag memory 172 to determine whether or not a notification signal is output from the random number circuit 103 (step S121). When the initial value flag is in the off state (step S121; No), it is determined that the count value of the counter 121 has not been counted up to the final value, and the initial value change process is terminated. On the other hand, when the initial value flag is in the ON state (step S121; Yes), the initial value change method selected by the user is read by reading the initial value change method setting data stored in the area 1F97h in the user program execution data area A method is specified (steps S122, S123, and S124).

  When initial value change method setting data “01h” for designating the first initial value change method is stored (step S122; Yes), the CPU 106 sets the initial value as an ID (Identification) unique to the gaming control microprocessor 100. The value is changed to a value set based on the number (step S125).

  When initial value change method setting data “02h” for designating the second initial value change method is stored (step S122; No, step S123; Yes), the CPU 106 stores the area 1F97h in the user program execution data area. The specified RAM address is specified from the RAM address data stored in the memory, and the value stored in the area of the specified specified RAM address is read (step S126). Then, the CPU 106 changes the initial value to the read value (step S127).

  When initial value change method setting data “03h” for designating the third initial value change method is stored (step S122; No, step S123; No, step S124; Yes), the CPU 106 at each address of the RAM 105. The stored value is read (step S128), and the read value is added (step S129). Then, the CPU 106 changes the initial value to this added value (step S130).

  If it is determined No in step S122, step S123, and step S124, the initial value change method setting data stored in the area 1F97h in the user program execution data area is determined as “00h”, and the initial value is set. The process proceeds to step S131 without change.

  Thereafter, the CPU 106 clears the initial value change flag to turn it off (step S131), and ends the initial value change process.

  After the initial value change process is completed in this way, the CPU 106 executes the count value permutation change program 154 to perform the count value permutation change process (step S105). In this count value permutation update process, the CPU 106 changes the permutation of the count values C input to the random value storage circuit 131 by writing the count value permutation change data “01h” into the count value permutation change register 136.

  Subsequently, the CPU 106 executes special symbol process processing (step S106). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 106 executes normal symbol process processing (step S107). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the normal symbol display 40 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the special symbol command control process (step S108) and the normal symbol command control process (step S109) are sequentially executed. Thus, the CPU 106 sends a display control command from the main board 11 to the display control board 12 to instruct display control of the variable display device 4 and lighting control of the normal symbol display 40.

  Subsequently, the CPU 106 executes predetermined information output processing to output various output data to each output port included in the I / O port 108 (step S110). In this information output process, a command for outputting jackpot information, starting information, probability variable information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Further, the CPU 106 performs predetermined prize ball processing to set the number of prize balls based on the detection signal input from each prize opening switch such as the start prize opening switch 70 and the like, and to the payout control board 15. The payout control command can be output (step S111). Further, the CPU 106 performs a predetermined solenoid output process to open and close the movable wing piece in the normal variable winning ball device 6 and the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied ( Step S112).

  FIG. 32 is a flowchart showing the special symbol process executed in step S106. When the special symbol process is started, the CPU 106 first executes the display result determination program 152 and stores in the start winning opening switch timer memory 173 whether or not the game ball has won the normal variable winning ball device 6. A determination is made by checking the timer value (step S141). In step S141, the CPU 106 loads the timer value stored in the start winning a prize opening switch timer memory 173, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of executions of the game control interrupt process (for example, “2”). Thereby, the CPU 106 continuously receives the start winning signal SS from the start winning port switch 70 while the game control interruption process is executed a predetermined number of times (for example, twice) (for example, 4 milliseconds). It can be determined whether or not.

  Based on the comparison result, the CPU 106 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won (Step S141; Yes), and the winning process is executed (Step S142). clear. On the other hand, when the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S141; No), and the winning process is skipped.

  FIG. 33 is a flowchart showing the winning process in step S142. In this winning process, the CPU 106 first determines whether or not the starting winning memory number stored in the special figure reservation memory 170 is a predetermined maximum value (for example, “4”) (step S171). Here, in the special figure holding memory 170, for example, when a random R corresponding to the start winning storage number “4” is stored, it is determined that the start winning storage number is the maximum value.

  When the start winning memory number is the maximum value (step S171; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memorized number is not the maximum value (step S171; No), an output control signal SC is sent to the random value memory circuit 131 to control the random value memory circuit 131 to a readable (enable) state ( Step S172).

  Subsequently, the CPU 106 reads a random R value stored as a random value from the random value storage circuit 131 (step S173), and stores the read random R value in a predetermined buffer area provided in the RAM 105, for example. After the storage (step S174), the transmission of the output control signal SC to the random value storage circuit 131 is stopped, and the random value storage circuit 131 is controlled to be unreadable (disabled) (step S175). Then, the CPU 106 adds “1” to the start winning memory number (step S176), and sets the random R value stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 170 (step S177).

  Thereafter, the CPU 106 selects one of the nine processes of steps S150 to S158 shown in FIG. 32 based on the value of the special symbol process flag stored in the flag memory 172. Below, each process of step S150-S158 is demonstrated.

  The special symbol normal process of step S150 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 106 determines whether or not the number of reserved memories stored in the special figure reservation memory 170 is “0”. Here, when various data such as random R corresponding to the hold number “1” is not stored in the special figure hold memory 170, it is determined that the hold storage number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S151 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 34, the CPU 106 first reads the random R value stored in correspondence with the hold number “1” from the special figure hold memory 170 (step S181). At this time, 1 is subtracted from the reserved storage number, and the value of the random R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure holding memory 170 is increased by one entry. Shift (step S182).

  Subsequently, the CPU 106 determines whether or not the probability improvement state (probability change is in progress) (step S183). If the probability change is not in progress (step S183; No), the CPU 106 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table 171a as shown in FIG. 26A is set (step S184). On the other hand, if the probability change is in progress (step S183; Yes), a probability change big hit determination table 171b as shown in FIG. 26B is set (step S185).

  Based on the random R value read in step S181, the CPU 106 uses the jackpot determination table 171a or 171b set in step S184 or S185 to determine whether or not to display the special game display result as a jackpot ( Step S186). If it is determined to be a big hit (step S186; Yes), the big hit state flag provided in the flag memory 172 is set to the on state (step S187), and if it is determined to be lost. (Step S186; No), the big hit state flag is cleared and turned off (Step S188). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S189).

  The confirmed symbol determination process in step S152 shown in FIG. 32 is a process executed when the value of the special symbol process flag is “2”. In this processing, the CPU 106 determines whether or not the big hit state flag provided in the flag memory 172 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S153 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 106 first determines whether or not the big hit state flag provided in the flag memory 172 is turned on, and whether or not it is determined to reach in the determined symbol determination process in step S152. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in this special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 106 updates the value of the special symbol process flag to “4”, which is a value corresponding to the variable display command process.

  The variable display command process of step S154 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 106 controls the variable display device 4 so that all the special symbols start variable display. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S152 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S153 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S155 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 106 performs settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether or not to return from the probability improved state to the normal gaming state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S156 is a process executed when the value of the special symbol process flag is “6”. In this process, the CPU 106 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S157 is a process executed when the value of the special symbol process flag is “7”. In this processing, the CPU 106 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S158 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 106 ends the jackpot gaming state by making settings for sending a predetermined jackpot end command to the display control board 12. Further, the CPU 106 clears the big hit state flag provided in the flag memory 172 and sets it to the off state. Then, the value of the special symbol process flag is updated to “0”.

  As described above, in this embodiment, the selector 128 is output from the clock signal output circuit 124 in response to the second random number update method selection signal output circuit 127 receiving the second random number update method selection signal input. The random number generating clock signal S 1 is selected and output to the counter 121. Accordingly, the counter 121 is supplied with a random number generating clock signal S1 that rises from a low level to a high level at timings T11, T12, T13,. The random number generation clock signal S1 output from the clock signal output circuit 124 is input to the delay circuit 132, delayed by ΔT (≠ nT), and then output to the latch signal generation circuit 133 as the delayed clock signal S2. The The latch signal generation circuit 133 responds to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127 and outputs the random value read signal output from the random value read signal output circuit 126. Is synchronized with the delayed clock signal S2 input from the delay circuit 132, and is output to the random value storage circuit 131 as the latch signal SL rising from the low level to the high level at the timing T23.

  In this way, the random number circuit 103 updates the count value C at the timings T11, T12, T13,... At which the random number generation clock signal S1 output from the clock signal output circuit 124 rises from the low level to the high level. The latch signal SL can be output at timings T21, T22, T23,... Different from the timings T11, T12, T13,. The random value storage circuit 131 stores the updated count value C as a random R in response to the rising edge of the latch signal SL.

  For this reason, the random number circuit 103 can reliably change the update timing of the count value C by the counter 121 and the output timing (latch timing) of the latch signal SL by the latch signal generation circuit 133. Since the random number circuit 103 updates the count value C and outputs the latch signal SL without inverting the random number generation clock signal S1, the random number generation clock signal S1 falls slowly. However, the update timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In addition, after the power is supplied to the pachinko gaming machine 1 and the game control main process is started, the CPU 106 executes the random number circuit setting program 151 before allowing the timer interrupt process to be executed and proceeding to the loop process. Since the random number circuit setting process is performed, it is not necessary to start / end the random number generation process within a limited interrupt processing time (for example, 2 milliseconds), and the processing load of the game control microprocessor 100 is reduced. An increase can be prevented. Further, since the random number circuit 103 is built in the game control microprocessor 100 together with the CPU 106, a space for the main board 11 can be secured, and counterfeiting such as installation of an unauthorized board can be made difficult.

  Preferably, the random number circuit setting process permits the timer interrupt process to be executed after the game state restoration process is executed or after the RAM 105 is cleared or an initialization process such as an initial setting for a predetermined work area is executed. It is desirable to be executed before the loop process is entered.

  Further, since the CPU 106 determines whether or not the display result in the special game is to be a big hit using the value of the random R generated by the random number circuit 103, the capacity of the program stored in the ROM 104 or the like can be reduced. .

  Furthermore, since the value of the random R is updated by the random number circuit 103, the capacity of the program stored in the ROM 104 or the like can be reduced as compared with that updated by software.

  Further, since the value of random R stored in the random value storage circuit 131 can be updated according to the setting made by executing the random number circuit setting program 151, different settings are made for each pachinko gaming machine 1. Thus, the randomness of the random number value read from the random value storage circuit 131 and used to determine whether or not the display result in the special figure game is a big hit can be improved.

  More specifically, the CPU 106 executes the random number maximum value setting module 151a, the random number update method selection module 151b, and the period setting module 151c included in the random number circuit setting program 151, and the user appropriately sets for each pachinko gaming machine 1. The maximum value of the random R, the random number update method, and the cycle of the random number generating clock signal S1 are set in the random number circuit 103, and then the random number circuit activation module 151d is executed to activate the random number circuit 103. By updating the value of the random R stored in the random value storage circuit 131 in accordance with the maximum value of the random R, the random number update method, and the cycle of the random number generating clock signal S1 set in the random number circuit 103 in this way. Thus, the randomness of the random number value read from the random value storage circuit 131 and used to determine whether or not the display result in the special figure game is a big hit can be improved.

  Further, by executing the count value permutation change program 154 and changing the permutation that is the update order of the count values, the randomness of the count values input to the random value storage circuit 131 is increased. As a result, the random value storage circuit 131 Thus, the randomness of the random number value used for determining whether or not the display result in the special figure game is a big hit can be improved.

  Further, in response to the count value permutation change circuit 123 starting the update operation of the count value according to the switched update rule, the CPU 106 counts the count value permutation change register 136 in which the count value permutation change data “01h” is written. Can be prevented from being continuously changed in the permutation of count values output from the count value permutation changing circuit 123 and input to the random value storage circuit 131.

  Further, after the count value permutation change register 136 is initialized, the CPU 106 can further change the permutation of the changed count value by rewriting the count value permutation data “01h” in the count value permutation change register 136. it can.

  Further, by changing the initial value of the count value updated by the counter 121, it is possible to make it difficult to detect the cycle in which the count value is counted up from the initial value to the final value. This prevents a fraudulent act such as outputting a predetermined signal at the timing when the random R value read from the random value storage circuit 131 matches the jackpot determination value in step S173 and causing frequent jackpots. it can.

  Further, the CPU 106 writes the random number maximum value setting register 135 in which the random number maximum value setting data is written, the cycle setting register 137 in which the cycle setting data is written, and the random number update method selection data until the system is reset by the reset controller 102. The random number update method selection register 140 is controlled to be unwritable so that the random number maximum value, the cycle of the random number generation clock signal S1 and the random number update method set in the random number circuit 103 cannot be changed. As a result, the malicious player changes the random number maximum value, the cycle of the random number generation clock signal S1 and the random number update method, and the timing at which the random R value read from the random value storage circuit 131 matches the jackpot determination value. It can be set freely and fraudulent actions such as frequent hits can be prevented.

  Further, in order to change the initial value of the count value by the initial value changing method appropriately selected by the user for each pachinko gaming machine 1, whether or not the display result in the special game is read out from the random value storage circuit 131 It is possible to improve the randomness of the random number value used to determine whether or not.

  Further, when random number maximum value setting data “0000h” to “0003h” designating a value equal to or lower than the lower limit value “4” is written in the random number maximum value setting register 135, the CPU 106 stores the random number maximum value setting register 135 in this random number maximum value setting register 135. Since “0FFFh” is stored, a value of “4” or less can be prevented from being set in the random number circuit 103 as the maximum random number.

  When the initial value changed by the CPU 106 is larger than the random number maximum value, the comparator 122 sequentially outputs a count value update signal and continuously outputs the count value to the counter 121 from the changed initial value to the final value. The updated initial value can be further changed by the CPU 106 by outputting the notification signal. Thereby, it is possible to prevent the count value output to the random value storage circuit 131 from becoming larger than the random number maximum value.

  Further, when a cycle setting command “00h” to “06h” for designating a value less than or equal to the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 137, the CPU 106 Since “07h” is stored in 137, it is possible to prevent a value smaller than “system clock signal cycle × 128 × 7” from being set in the random number circuit 103 as the cycle of the internal clock signal.

  In addition, the CPU 106 sets the maximum value of the random number, the random number update method, and the cycle of the random number generation clock signal S1 in the random number circuit 103, and then starts the random number circuit 103. It is possible to prevent a problem that random numbers are generated from the random number circuit 103 before setting the random number update method and the cycle of the random number generating clock signal S1.

  When the system is reset by the reset controller 102, the random number circuit 103 can be restarted by writing the random number circuit starting data “80h” into the random number circuit starting register 141.

  The start winning opening switch 70 outputs a start winning signal SS to the random number circuit 103 and the CPU 106 based on the fact that the game ball has won the normal variable winning ball apparatus 6 which is the start winning opening. The CPU 106 is based on the fact that the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 milliseconds). The winning process is executed. In this winning process, the CPU 106 sends an output control signal SC to the random value storage circuit 131 to control the random value storage circuit 131 to a readable state (enable), and then obtains a random R value from the random value storage circuit 131. read out. Then, after the CPU 106 stops sending the output control signal SC to the random value storage circuit 131 and controls the random value storage circuit 131 to the unreadable state, the read random R value is set to a predetermined determination value. By determining whether or not it matches “3” or the like, it is determined whether or not the display result of the special figure game by the variable display device 4 is a big hit gaming state.

  In this way, the pachinko gaming machine 1 acquires the random number value more reliably and stably by controlling the random value storage circuit 131 to the readable state only when the CPU 106 reads the random R value. be able to. Further, since the CPU 106 reads out the random R value from the random value storage circuit 131 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. can do.

  The random number circuit 103 does not directly input the start prize signal SS output from the start prize port switch 70 to the latch signal generation circuit 133 but temporarily inputs it to the timer circuit 134 to input the start prize signal SS. When the measured time reaches a preset time (3 milliseconds), the random value read signal is latched by setting the random value fetch data “01h” in the random value fetch register 139 The signal is input to the signal generation circuit 133. For this reason, the pachinko gaming machine 1 can prevent the latch signal generation circuit 133 from erroneously outputting the latch signal SL to the random value storage circuit 131 due to the influence of noise or the like. Since the timer circuit 134 is set to “3 milliseconds” shorter than “4 milliseconds” between the executions of the two timer interrupt processes, the random R value read out from the random value storage circuit 131 by the CPU 106 is set. Can be prevented from becoming the same value as the random R value read at the time of the previous winning.

  In addition, when the latch signal SL is input from the latch signal generation circuit 133, the random value storage circuit 131 converts the output control signal (high level signal) SC input from the game control microprocessor 100 to a low level signal. By converting to, the output control signal SC is controlled so as not to be received. This prevents the CPU 106 from reading the random R value from the random value storage circuit 131 when the random R value stored in the random value storage circuit 131 is updated. The gaming machine 1 can reliably and stably update the random number value.

  Further, when the output control signal SC is input from the game control microprocessor 100, the random value storage circuit 131 uses the latch signal (high level signal) SL input from the latch signal generation circuit 133 as a low level signal. By converting to, the latch signal SL is controlled so as not to be received. This prevents the random R value stored in the random value storage circuit 131 from being updated when the gaming control microprocessor 100 reads the random R value from the random value storage circuit 131. Therefore, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In the above-described embodiment, the case where the second random number update method is selected by the user has been described. On the other hand, when the first random number update method is selected, the process shown in the flowchart of FIG. 35 is executed as the random number circuit setting process of step S10 shown in FIG.

  In the random number circuit setting process shown in FIG. 35, the CPU 106 first executes the random number maximum value setting module 151a included in the random number circuit setting program 151, and sets a random number maximum value setting that specifies a random number maximum value preset by the user. By writing data into the random number maximum value setting register 135, the preset maximum value of the random R is set in the random number circuit 103 (step S31). Next, the CPU 106 executes the random number update method selection module 151b included in the random number circuit setting program 151, and writes the random number update method selection data “01b” in the random number update method selection register 140, whereby the first random number update method is selected. The method is set in the random number circuit 103 (step S32). Thereafter, the CPU 106 executes the random number circuit starting module 151d included in the random number circuit setting program 151, and writes the random number circuit starting data “80h” in the random number circuit starting register 141, thereby starting the random number circuit 103 (step). S33).

  By executing the random number circuit setting process as shown in FIG. 35 in this way, the random number circuit 103 operates according to a timing chart as shown in FIG. 36, for example.

  In the operation example shown in FIG. 36, the reference clock signal CLK shown in FIG. 36A is supplied from the clock circuit 101 to the random number circuit 103.

  The clock signal output circuit 124 divides the reference clock signal CLK supplied from the clock circuit 101 to generate a random number generation clock signal S 1, and outputs it to the selector 128 and the delay circuit 132. The selector 128 selects the count value update signal S3 output from the count value update signal output circuit 125 in response to the input of the first random number update method selection signal from the random number update method selection signal output circuit 127. To the counter 121. The counter 121 updates the count value C and outputs it to the count value permutation change circuit 123 at the timing when the rising edge of the count value update signal S3 supplied from the selector 128 is input. Here, the selector 128 responds to the count value update signal S3 output from the count value update signal output circuit 125 when the first random number update method selection signal output circuit 127 receives the first random number update method selection signal. Thus, a numerical value update instruction signal for instructing the update of numerical data synchronized with the random number generation clock signal S1 output from the clock signal output circuit 124 may be output to the counter 121.

  The delay circuit 132 delays the random number generation clock signal S1 output from the clock signal output circuit 124 by ΔT (≠ nT: n is an integer), and rises from a low level to a high level at timings T41, T42,. A delayed clock signal S2 having a period T shown in FIG. The delayed clock signal S2 generated by the delay circuit 132 is output to the latch signal generation circuit 133.

  In response to the input of the first random number update method selection signal output circuit 127 from the random number update method selection signal output circuit 127, the latch signal generation circuit 133 generates the delayed clock signal S2 supplied from the delay circuit 132 as shown in FIG. D) is output as a latch signal SL shown in FIG. When such a first random number update method is selected, the timing at which the CPU 106 writes the count value update data “01h” to the count value update register 138 is changed, for example, the random number generation clock signal S1 is changed from the low level to the high level. Control to be the timing to start up. When the selector 128 can output a numerical value update instruction signal synchronized with the random number generation clock signal S1 output from the clock signal output circuit 124, the random number generation clock can be output even if such control is not performed. A numerical value update instruction signal for switching the signal level at the timing when the signal S1 rises from the low level to the high level is output to the counter 121. As a result, the random number circuit 103 updates the count value C at the timing when the random number generating clock signal S1 rises from the low level to the high level, and outputs the latch signal SL at timings T41, T42, T43,. Can be output. That is, even when the first random number update method is selected, the random number circuit 103 determines the update timing of the count value C by the counter 121 and the output timing (latch timing) of the latch signal SL by the latch signal generation circuit 133. It is possible to reliably make the difference, and it is possible to reliably and stably acquire the random value.

  When the first random number update method is selected, the CPU 106 executes the process shown in FIG. 37 instead of the game control interrupt process shown in the flowchart of FIG.

  In the game control interrupt process shown in FIG. 37, the CPU 106 can execute a predetermined data protection process or the like when the power supplied from the power supply board 10 decreases by first executing a predetermined power-off process. (Step S191). Subsequently, by executing a predetermined switch process, the state of the detection signal input from each winning a prize port switch such as the starting winning a prize port switch 70 is determined (step S192). Next, the CPU 106 executes display random number update processing (step S193). Subsequently, the CPU 106 executes the initial value changing program 153 to perform the initial value changing process shown in FIG. 31 (step S194). Further, the CPU 106 executes the count value permutation change program 154 to perform a count value permutation change process (step S195).

  Then, the CPU 106 executes the random value update program 155 to perform a random value update process (step S196). In this random number value update process, the CPU 106 writes the count value update data “01h” in the count value update register 138 in synchronization with the rising edge of the random number generation clock signal S 1 output from the clock signal output circuit 124. The count value C counted by the counter 121 is updated. The count value C in the counter 121 is taken in and stored in the random value storage circuit 131 in synchronization with the rising edge of the delayed clock signal S2 output as the latch signal SL from the latch signal generation circuit 133.

  Subsequently, special symbol process processing is executed (step S197). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, the CPU 106 executes normal symbol process processing (step S198). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the normal symbol display 40 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the special symbol command control process (step S199) and the normal symbol command control process (step S200) are sequentially executed. Thus, the CPU 106 sends a display control command from the main board 11 to the display control board 12 to instruct display control of the variable display device 4 and lighting control of the normal symbol display 40. Subsequently, the CPU 106 executes predetermined information output processing to output various output data to each output port included in the I / O port 108 (step S201). In this information output process, a command for outputting jackpot information, starting information, probability variable information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16. Further, the CPU 106 performs predetermined prize ball processing to set the number of prize balls based on the detection signal input from each prize opening switch such as the start prize opening switch 70 and the like, and to the payout control board 15. The payout control command can be output (step S202). Further, the CPU 106 performs a predetermined solenoid output process to open and close the movable wing piece in the normal variable winning ball device 6 and the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied ( Step S203).

  In this way, either the first or second random number update method is selected according to the user setting, and the random value storage circuit 131 can store the value of the random R by the selected random number update method. For this reason, by selecting a different random number update method for each pachinko gaming machine 1, the randomness of the value of random R read from the random value storage circuit 131 can be improved. Further, the timing at which the counter 121 updates the count value C and the timing at which the count value C is taken into the random value storage circuit 131 and the value of the random R are updated can be designated, so that a random value that has not been updated is read out. Can be prevented.

  In the above embodiment, the random number generating clock signal S1 output from the clock signal output circuit 124 is input to the counter 121 via the selector 128 and input to the delay circuit 132 to generate the delayed clock signal S2. By inputting the generated delay clock signal S2 to the latch signal generation circuit 133, the update timing of the count value C and the latch timing are made different. On the other hand, the random number generating clock signal S 1 may be input to the latch signal generating circuit 133 and the delayed clock signal S 2 may be input to the counter 121.

  Further, by inputting the random number generating clock signal S1 to the counter 121 and the latch signal generating circuit 133, the count value C is updated and the latch signal SL is output at the same timing, and then the latch signal SL is transmitted to the delay circuit. The update timing of the count value C and the latch timing may be made different from each other by delaying the input to. FIG. 38 is a block diagram illustrating a configuration example of the random number circuit 103 when the latch signal SL is input to the delay circuit to be delayed. In FIG. 38, the same components as those in FIG. 4 are denoted by the same reference numerals. 38 shows a comparator 122, a count value permutation change circuit 123, a count value update signal output circuit 125, a random number update method selection signal output circuit 127, and a random number circuit start signal output circuit 130 for the sake of simplicity. Although not done, each of these components and their operations are the same as those in the random number circuit 103 shown in FIG.

  In the random number circuit 103 shown in FIG. 38, a clock signal output circuit 124 and a latch signal generation circuit 133 are connected, and a delay circuit 232 is interposed between the latch signal generation circuit 133 and the random number value storage circuit 131. . The latch signal generation circuit 133 generates a random number read signal input from the random value read signal output circuit 126 and generates a random number input from the clock signal output circuit 124 when the second random number update method is selected. It is output as a latch signal SL in synchronization with the rising edge of the clock signal S1.

  The delay circuit 232 delays the latch signal SL output from the latch signal generation circuit 133 by a period ΔT that is different from a period that is an integral multiple of the period T of the random number generation clock signal S1, thereby generating a delayed latch signal SD. . The delay circuit 232 outputs the generated delay latch signal SD to the random value storage circuit 131.

  FIG. 39 is a timing chart for explaining the operation of the random number circuit 103 shown in FIG.

  The clock signal output circuit 124 divides the reference clock signal CLK shown in FIG. 39A supplied from the clock circuit 101, and shows a period T rising from the low level to the high level at timings T11, T12,. The random number generating clock signal S 1 shown in 39 (B) is output to the selector 128 and the latch signal generating circuit 133. When the second random number update method is selected, the selector 128 selects the random number generation clock signal S 1 output from the clock signal output circuit 124 and outputs it to the counter 121.

  Each time the rising edge of the random number generating clock signal S1 is input, the counter 121 updates the count value C and outputs it to the random value storage circuit 131. Further, the latch signal generation circuit 133 reads the random number value when the elapsed time after the start winning signal SS shown in FIG. 39C is input to the timer circuit 134 reaches a predetermined time (for example, 3 milliseconds). The random number read signal from the signal output circuit 126 rises from a low level to a high level. In response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127, the latch signal generation circuit 133 receives the random number value read signal input from the random number value read signal output circuit 126. The latch signal SL shown in FIG. 39D is output to the delay circuit 232 in synchronization with the rising edge of the random number generating clock signal S 1 supplied from the clock signal output circuit 124.

  The delay circuit 232 delays the latch signal SL input from the latch signal generation circuit 133 by ΔT (≠ nT: n is an integer), and rises from the low level to the high level at timing T71, as shown in FIG. A delayed latch signal SD is generated and output to the random value storage circuit 131. The random value storage circuit 131 stores the count value C input from the counter 121 as a random R in response to the delay latch signal SD input from the delay circuit 232.

  Thus, the random number circuit 103 shown in FIG. 38 updates the count value C at timings T11, T12, T13,..., And outputs a delayed latch signal SD at timing T71 different from the timings T11, T12, T13,. can do. As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In the random number circuit 103 shown in FIGS. 4 and 38, the count value C is updated by inputting the random number generation clock signal S1 to the counter 121. On the other hand, the random number circuit 103 may update the count value C by inputting the divided clock signal generated by dividing the random number generating clock signal S1 to the counter 121, for example. The count value C may be updated by inputting to the counter 121 a clock signal obtained by performing an AND operation on CLK and the divided clock signal S4 divided by the clock signal output circuit 124. FIG. 40 is a block diagram showing a configuration example of the random number circuit 103 in the case where the random number generation clock signal S1 is generated by performing an AND operation on the reference clock signal CLK and the output signal from the clock signal output circuit 124. In FIG. 40, the same components as those in FIG. 4 are denoted by the same reference numerals. 40 shows a comparator 122, a count value permutation changing circuit 123, a count value update signal output circuit 125, a random number update method selection signal output circuit 127, and a random number circuit activation signal output circuit 130 for the sake of simplicity. Although not done, each of these components and their operations are the same as those in the random number circuit 103 shown in FIG.

  In the random number circuit 103 shown in FIG. 40, the clock signal output circuit 124 divides the reference clock signal CLK input from the clock circuit 101 to generate a divided clock signal S4, and the generated divided clock signal S4 is ANDed. Output to the circuit 145. The AND circuit 145 generates a random number generating clock signal S1 by performing an AND operation on the reference clock signal CLK supplied from the clock circuit 101 and the divided clock signal S4 input from the clock signal output circuit 124. The random number generating clock signal S 1 is output to the selector 128 and the delay circuit 132.

  The delay circuit 132 delays the random number generating clock signal S1 input from the AND circuit 145 by a period ΔT that is different from a period that is an integral multiple of the period T of the random number generating clock signal S1, thereby causing the delayed clock signal S5 to be delayed. Generate. The delay circuit 132 outputs the generated delayed clock signal S5 to the latch signal generation circuit 133.

  FIG. 41 is a timing chart for explaining the operation of the random number circuit 103 shown in FIG.

  The clock signal output circuit 124 divides the reference clock signal CLK shown in FIG. 41A supplied from the clock circuit 101, and shows a period T rising from the low level to the high level at timings T11, T12,. The frequency-divided clock signal S4 shown in 41 (B) is output to the AND circuit 145.

  The AND circuit 145 performs an AND operation on the reference clock signal CLK supplied from the clock circuit 101 and the divided clock signal S4 input from the clock signal output circuit 124, and generates a random number generating clock shown in FIG. A signal S 1 is generated and output to the selector 128 and the delay circuit 132. When the second random number update method is selected, the selector 128 selects the random number generation clock signal S 1 output from the AND circuit 145 and outputs it to the counter 121.

  The delay circuit 132 delays the random number generation clock signal S1 input from the AND circuit 145 by, for example, T / 2 to generate a delay clock signal S5 shown in FIG. Output.

  The counter 121 updates the count value C and outputs it to the random value storage circuit 131 each time the rising edge of the random number generation clock signal S1 input from the AND circuit 145 is input. Further, the latch signal generation circuit 133 reads the random number value when the elapsed time after the start winning signal SS shown in FIG. 41E is input to the timer circuit 134 reaches a predetermined time (for example, 3 milliseconds). The random number read signal from the signal output circuit 126 rises from a low level to a high level. In response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127, the latch signal generation circuit 133 receives the random number value read signal input from the random number value read signal output circuit 126. In synchronization with the rising edge of the delayed clock signal S5 supplied from the delay circuit 132, the latch signal SL shown in FIG.

  The random value storage circuit 131 stores the count value C input from the counter 121 as a random R in response to the latch signal SL input from the latch signal generation circuit 133.

  As a result, the random number circuit 103 shown in FIG. 40 updates the count value C at timings T11, T12, T13,..., And outputs the latch signal SL at timing T72 different from the timings T11, T12, T13,. be able to.

  Further, the reference clock signal CLK and the output signal from the clock signal output circuit 124 are ANDed to generate a random number generation clock signal S1, and the count value C is updated and the latch signal SL is output at the same timing. After that, the update timing of the count value C and the latch timing may be made different by inputting the latch signal SL to the delay circuit and delaying it. FIG. 42 is a block diagram showing a configuration example of the random number circuit 103 that realizes such a function. In FIG. 42, the same components as those in FIG. 4 are denoted by the same reference numerals. 42 shows a comparator 122, a count value permutation change circuit 123, a count value update signal output circuit 125, a random number update method selection signal output circuit 127, and a random number circuit start signal output circuit 130 for the sake of simplicity. Although not done, each of these components and their operations are the same as those in the random number circuit 103 shown in FIG.

  In the random number circuit 103 shown in FIG. 42, the clock signal output circuit 124 divides the reference clock signal CLK input from the clock circuit 101 to generate a divided clock signal S4, and the generated divided clock signal S4 is ANDed. Output to the circuit 145. The AND circuit 145 generates a random number generating clock signal S1 by performing an AND operation on the reference clock signal CLK supplied from the clock circuit 101 and the divided clock signal S4 input from the clock signal output circuit 124. The random number generation clock signal S1 is output to the selector 128 and the latch signal generation circuit 133. A delay circuit 232 is interposed between the latch signal generation circuit 133 and the random value storage circuit 131. The latch signal generation circuit 133 uses the random number read signal input from the random value read signal output circuit 126 as the random number generation clock signal input from the AND circuit 145 when the second random number update method is selected. It is output as a latch signal SL in synchronization with the rising edge of S1.

  The delay circuit 232 delays the latch signal SL output from the latch signal generation circuit 133 by T / 2 as an example of a period different from an integer multiple of the period T of the random number generation clock signal S1. A signal SD is generated. The delay circuit 232 outputs the generated delay latch signal SD to the random value storage circuit 131.

  FIG. 43 is a timing chart for explaining the operation of the random number circuit 103 shown in FIG.

  The clock signal output circuit 124 divides the reference clock signal CLK shown in FIG. 43A supplied from the clock circuit 101, and shows a period T rising from the low level to the high level at timings T11, T12,. The frequency-divided clock signal S4 shown in 43 (B) is output to the AND circuit 145.

  The AND circuit 145 performs an AND operation on the reference clock signal CLK supplied from the clock circuit 101 and the divided clock signal S4 input from the clock signal output circuit 124, and generates a random number generating clock shown in FIG. The signal S1 is generated and output to the selector 128 and the latch signal generation circuit 133. When the second random number update method is selected, the selector 128 selects the random number generation clock signal S 1 output from the AND circuit 145 and outputs it to the counter 121.

  Each time the rising edge of the random number generating clock signal S1 is input, the counter 121 updates the count value C and outputs it to the random value storage circuit 131. Further, the latch signal generation circuit 133 reads the random number value when the elapsed time after the start winning signal SS shown in FIG. 43D is input to the timer circuit 134 reaches a predetermined time (for example, 3 milliseconds). The random number read signal from the signal output circuit 126 rises from a low level to a high level. In response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127, the latch signal generation circuit 133 receives the random number value read signal input from the random number value read signal output circuit 126. The latch signal SL shown in FIG. 43E is output to the delay circuit 232 in synchronization with the rising edge of the random number generating clock signal S1 supplied from the AND circuit 145.

  The delay circuit 232 delays the latch signal SL input from the latch signal generation circuit 133 by, for example, T / 2 and rises from the low level to the high level at the timing T73, and the delay latch signal SD shown in FIG. Is output to the random value storage circuit 131. The random value storage circuit 131 stores the count value C input from the counter 121 as a random R in response to the delay latch signal SD input from the delay circuit 232.

  42 updates the count value C at timings T11, T12, T13,..., And outputs a delayed latch signal SD at timing T73 different from the timings T11, T12, T13,. can do. As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In the random number circuit shown in FIG. 40 or FIG. 42, the difference between the update timing of the count value C and the latch timing can be increased as compared with the random number circuit shown in FIG. 4 or FIG. As a result, the pachinko gaming machine 1 can acquire the random value more reliably and stably.

  In the random number circuit 103, clock signals having different periods may be input to the counter 121 and the latch signal generation circuit 133, respectively. 44 and 45 are block diagrams illustrating a configuration example of the random number circuit 103 when clock signals having different periods are input to the counter 121 and the latch signal generation circuit 133, respectively. 44 and 45, the reference clock signal CLK supplied from the clock circuit 101 is frequency-divided by the counter 121, and the reference clock signal CLK is frequency-divided by the clock signal output circuit 124 and then thinned by the AND circuit 145. The random number generation clock signal S1 or the delayed clock signal S5 obtained by the operation is input to the latch signal generation circuit 133. In this case, since the value of the random R stored in the random value storage circuit 131 is only odd or even, the big hit determination table includes only the odd or even numbers according to this. Store the value.

  In the above embodiment, the case where the start winning signal SS from the start winning port switch 70 is input to the random number circuit 103 and the CPU 106 of the gaming control microprocessor 100 via the switch circuit 109 has been described. On the other hand, the start winning signal SS from the start winning port switch 70 may be input to the CPU 106 and not input to the random number circuit 103. In this case, the CPU 106 may generate the latch start winning signal SN and supply it to the random number circuit 103.

  FIG. 46 is a block diagram showing a configuration example of the random number circuit 103 when the CPU 106 generates the latch start winning signal SN and supplies it to the random number circuit 103. In FIG. 46, the same components as those in FIG. 4 are denoted by the same reference numerals.

  In the configuration shown in FIG. 46, random value fetch data “01h” is written in the random value fetch register 139 provided in the random value read signal output circuit 126 as the latch start winning signal SN from the CPU 106. The random value read signal output circuit 126 outputs a random value read signal to the latch signal generation circuit 133 in response to the random value fetch data “01h” being written in the random value fetch register 139.

  The game control microprocessor 100 includes a special figure holding memory 170 as shown in FIG. 25, a jackpot determination table memory 171, a flag memory 172, and a start winning opening switch timer memory 173. The memory 172 is provided with a random value read flag. The random value read flag is set to the on state when the CPU 106 sends the latch start winning signal SN to the random number circuit 103, and is cleared to the off state when the random R value is read from the random value storage circuit 131. .

  In the pachinko gaming machine 1 having the random number circuit 103 configured as shown in FIG. 46, when the second random number update method is selected, the CPU 106 performs the random number circuit setting process of step S10 shown in the flowchart of FIG. The processing shown in the flowchart of 28 is executed. Thereby, the random number circuit 103 operates according to a timing chart as shown in FIG. 47, for example.

  47, the reference clock signal CLK shown in FIG. 47A is supplied from the clock circuit 101 to the random number circuit 103.

  The clock signal output circuit 124 divides the reference clock signal CLK supplied from the clock circuit 101 and is shown in FIG. 47B, for example, at a period T that rises from a low level to a high level at timings T51, T52,. A random number generating clock signal S1 is generated. The random number generating clock signal S 1 generated by the clock signal output circuit 124 is output to the selector 128 and the delay circuit 132.

  The selector 128 selects the random number generating clock signal S1 output from the clock signal output circuit 124 in response to the second random number update method selection signal output from the random number update method selection signal output circuit 127. Output to the counter 121. The counter 121 updates the count value C and outputs it to the count value permutation change circuit 123 every time the rising edge of the random number generation clock signal S1 supplied from the selector 128 is input.

  The delay circuit 132 delays the random number generating clock signal S1 output from the clock signal output circuit 124 by ΔT (≠ nT: n is an integer), and rises from a low level to a high level at timings T61, T62,. A delayed clock signal S2 having a period T shown in FIG. The delayed clock signal S2 generated by the delay circuit 132 is output to the latch signal generation circuit 133.

  The latch signal generation circuit 133 responds to the input of the second random number update method selection signal output from the random number update method selection signal output circuit 127 and receives the start prize for latch shown in FIG. The signal SN is output as a latch signal SL shown in FIG. 47E in synchronization with the rising edge of the delayed clock signal S2 supplied from the delay circuit 132. More specifically, the latch signal generation circuit 133 uses the latch start winning signal SN as shown in FIG. 47D input from the CPU 106, and the rising edge timing of the delay clock signal S2 supplied from the delay circuit 132. At the same time, a latch signal SL as shown in FIG. 47 (E) is output corresponding to the signal level of the latch start winning signal SN that has been fetched.

  Thereby, the random number circuit 103 can update the count value C at the timings T51, T52, T53, and can output the latch signal SL at the timing T63 different from the timings T51, T52, T53.

  In addition, in the pachinko gaming machine 1 including the random number circuit 103 having the configuration shown in FIG. 46, when the second random number update method is selected, the CPU 106 starts the special symbol process process of step S106 shown in the flowchart of FIG. 48, the processes of steps S251 to S262 shown in FIG. 48 are executed.

  In the process shown in FIG. 48, the CPU 106 first determines whether or not the random number read flag provided in the flag memory 172 is on (step S251). When the random number read flag is off (step S251; No), the timer value stored in the start winning a prize opening switch timer memory 173 is checked to determine (step S252). In step S252, the CPU 106 loads the timer value stored in the start winning a prize opening switch timer memory 173, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of executions of the game control interrupt process (for example, “2”). Thereby, the CPU 106 continuously receives the start winning signal SS from the start winning port switch 70 while the game control interruption process is executed a predetermined number of times (for example, twice) (for example, 4 milliseconds). It can be determined whether or not.

  Then, based on the comparison result, the CPU 106 determines whether or not the timer value is greater than or equal to the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S252; Yes), and the number of start prizes stored in the special figure holding memory 170 is stored. Is a predetermined maximum value (for example, “4”) (step S253). Here, in the special figure holding memory 170, for example, when a random R corresponding to the start winning storage number “4” is stored, it is determined that the start winning storage number is the maximum value.

  When the start winning memorized number is the maximum value (step S253; Yes), the start detection by the current winning is invalidated, and nine processes of steps S150 to S158 shown in FIG. 32 are performed based on the value of the special symbol process flag. Select one of them and execute it. On the other hand, when the start winning memorized number is not the maximum value (step S253; No), the start winning signal SN for latch is sent to the random number circuit 103, and the random value reading register provided in the random number read signal output circuit 126 is sent. The random number fetch data “01h” is written in 139 (step S254). At this time, after setting the random number read flag to the ON state (step S255), the process corresponding to the value of the special symbol process flag is selected from the processes of steps S150 to S158 shown in FIG. 32 and executed.

  Thereafter, when the special symbol process is executed again, it is determined in step S251 that the random number read flag is on (step S251; Yes). At this time, the CPU 106 sends an output control signal SC to the random value storage circuit 131 to control the random value storage circuit 131 to a readable (enable) state (step S256). Subsequently, the CPU 106 reads a random R value stored as a random value from the random value storage circuit 131 (step S257), and stores the read random R value in a predetermined buffer area provided in the RAM 105, for example. After the storage (step S258), the transmission of the output control signal SC to the random value storage circuit 131 is stopped, and the random value storage circuit 131 is controlled to be unreadable (disabled) (step S259). Then, the CPU 106 adds “1” to the start winning memory number (step S260), and sets the random R value stored in the predetermined buffer area to the head of the empty entry in the special figure holding memory 170 (step S261). Thereafter, CPU 106 clears the random number read flag to turn it off (step S262), and proceeds to the process corresponding to the value of the special symbol process flag in the processes of steps S150 to S158 shown in FIG.

  As described above, in the pachinko gaming machine 1 including the random number circuit 103 configured as shown in FIG. 46, in response to the second random number update method selection signal input from the random number update method selection signal output circuit 127. Thus, the selector 128 selects the random number generating clock signal S 1 output from the clock signal output circuit 124 and outputs it to the counter 121. Accordingly, the counter 121 is supplied with a random number generating clock signal S1 that rises from a low level to a high level at timings T51, T52, T53,. The random number generation clock signal S1 output from the clock signal output circuit 124 is input to the delay circuit 132, delayed by ΔT (≠ nT), and then output to the latch signal generation circuit 133 as the delayed clock signal S2. The The latch signal generation circuit 133 responds to the input of the second random number update method selection signal from the random number update method selection signal output circuit 127 and outputs the random value read signal output from the random value read signal output circuit 126. Are synchronized with the delayed clock signal S2 input from the delay circuit 132, and are output to the random value storage circuit 131 as the latch signal SL rising from the low level to the high level at the timing T63.

  46 is counted at the timings T51, T52, T53,... At which the random number generating clock signal S1 output from the clock signal output circuit 124 rises from the low level to the high level. The value C is updated, and the latch signal SL can be output at timings T61, T62, T63,... Different from these timings T51, T52, T53,. The random value storage circuit 131 stores the updated count value C as a random R in response to the rising edge of the latch signal SL.

  Therefore, the random number circuit 103 illustrated in FIG. 46 can reliably make the update timing of the count value C by the counter 121 different from the output timing (latch timing) of the latch signal SL by the latch signal generation circuit 133. Since the random number circuit 103 updates the count value C and outputs the latch signal SL without inverting the random number generation clock signal S1, the random number generation clock signal S1 falls slowly. However, the update timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  Also, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the CPU 106 permits the execution of the timer interrupt process after power is supplied to the pachinko gaming machine 1 and the game control main process is started. Before shifting to the loop processing, the random number circuit setting program 151 is executed to perform random number circuit setting processing. For this reason, it is not necessary to start / end the processing for generating random numbers within a limited interrupt processing time (for example, 2 milliseconds), and an increase in processing load on the gaming control microprocessor 100 can be prevented. . Further, by incorporating the random number circuit 103 shown in FIG. 46 in the game control microprocessor 100 together with the CPU 106, the space of the main board 11 can be secured, and counterfeiting such as the installation of an illegal board is difficult. Can do.

  Preferably, the random number circuit setting process permits the timer interrupt process to be executed after the game state restoration process is executed or after the RAM 105 is cleared or an initialization process such as an initial setting for a predetermined work area is executed. It is desirable to be executed before the loop process is entered.

  In the pachinko gaming machine 1 provided with the random number circuit 103 shown in FIG. 46, when the CPU 106 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 106 sends a latch start winning signal SN to the random number circuit 103. Random value fetch data “01h” is written into the random value fetch register 139. For this reason, the pachinko gaming machine 1 does not need to provide a path for supplying the start winning signal SS from the start winning port switch 70 to the random number circuit 103, and can simplify the hardware configuration.

  Further, the CPU 106 determines whether or not the display result in the special figure game is a big hit using the value of the random R generated by the random number circuit 103 shown in FIG. Thereby, the capacity of the program stored in the ROM 104 or the like can be reduced.

  Furthermore, since the value of the random R is updated by the random number circuit 103 shown in FIG. 46, the capacity of the program stored in the ROM 104 or the like can be reduced compared to that updated by software.

  Also, the random R value stored in the random value storage circuit 131 included in the random number circuit 103 shown in FIG. 46 is updated according to the setting made by executing the random number circuit setting program 151. Thereby, different settings are made for each pachinko gaming machine 1, and the randomness in the value of the random R read from the random value storage circuit 131 is increased in order to determine whether or not the display result in the special figure game is a big hit. Can do.

  More specifically, the CPU 106 executes the random number maximum value setting module 151a, the random number update method selection module 151b, and the period setting module 151c included in the random number circuit setting program 151, and the user appropriately sets for each pachinko gaming machine 1. The maximum value of the random R, the random number update method, and the cycle of the random number generating clock signal S1 are set in the random number circuit 103 having the configuration shown in FIG. 46, and then the random number circuit starting module 151d is executed and the random number circuit shown in FIG. 103 is started. In this way, the random R value stored in the random value storage circuit 131 is updated in accordance with the maximum value of random R, the random number update method, and the cycle of the internal clock signal set in the random number circuit 103 shown in FIG. Thereby, the randomness of the random number value read from the random value storage circuit 131 and used to determine whether or not the display result in the special figure game is a big hit can be improved.

  The comparator 122 provided in the random number circuit 103 shown in FIG. 46 is provided with a random number maximum value setting register 135 in which random number maximum value setting data for specifying the maximum value of random R (random number maximum value) is stored. The comparator 122 regulates the update range of the count value by the counter 121 according to the random number maximum value setting data stored in the random number maximum value setting register 135. Thereby, the maximum value of different random numbers can be set for each pachinko gaming machine 1 provided with the random number circuit 103 shown in FIG. 46, and the random number value used for determining whether or not the display result in the variable display is the specific display result. Randomness can be improved.

  Further, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the CPU 106 executes the count value permutation change program 154 to change the permutation that is the update order of the count values. The count value permutation changing circuit 123 included in the random number circuit 103 shown in FIG. 46 is provided with a count value permutation changing register 136 for storing count value permutation change data “01h” for requesting permutation change. The count value permutation change circuit 123 stores the count value permutation change data “01h” by switching the update rule in response to the count value permutation change data “01h” being written in the count value permutation change register 136. Change to a permutation of the update order different from that when not. As a result, the randomness of the count value C input to the random value storage circuit 131 is increased, so that it is read out from the random value storage circuit 131 to determine whether or not the display result in the special figure game is a big hit. The randomness of the random number used can be improved.

  Also, in response to the count value permutation changing circuit 123 included in the random number circuit 103 shown in FIG. 46 having started the count value updating operation in accordance with the updated update rule, the CPU 106 receives the count value permutation change data “01h”. The written count value permutation change register 136 is initialized. For this reason, the trouble that the permutation of the count values output from the count value permutation changing circuit 123 and input to the random value storage circuit 131 is continuously changed can be prevented.

  Further, after the count value permutation change register 136 provided in the random number circuit 103 shown in FIG. 46 is initialized, the CPU 106 writes the count value permutation data “01h” again in the count value permutation change register 136. Thereby, the permutation of the changed count value can be further changed.

  Further, by changing the initial value of the count value updated by the counter 121 included in the random number circuit 103 shown in FIG. 46, it may be difficult to detect the cycle in which the count value is counted up from the initial value to the final value. it can. This prevents a fraudulent act such as outputting a predetermined signal at the timing when the random R value read from the random value storage circuit 131 matches the jackpot determination value in step S173 and causing frequent jackpots. it can.

  Further, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the CPU 106 stores the random number maximum value setting register 135 in which the random number maximum value setting data is written and the cycle setting data until the system is reset by the reset controller 102. The cycle setting register 137 and the random number update method selection register 140 in which the random number update method selection data is written are controlled to be unwritable, and the maximum random number set in the random number circuit 103 and the cycle of the random number generating clock signal S1. And make the random number update method unchangeable. As a result, the malicious player changes the random number maximum value, the cycle of the random number generation clock signal S1 and the random number update method, and the timing at which the random R value read from the random value storage circuit 131 matches the jackpot determination value. It can be set freely and fraudulent actions such as frequent hits can be prevented.

  In addition, the initial value of the count value is changed by an initial value changing method appropriately selected for each pachinko gaming machine 1 by the user of the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. For this reason, the randomness of the random number value read from the random value storage circuit 131 and used to determine whether or not the display result in the special figure game is a big hit can be improved.

  Furthermore, when random number maximum value setting data “0000h” to “0003h” for designating a value equal to or lower than the lower limit value “4” is written in the random number maximum value setting register 135 provided in the random number circuit 103 shown in FIG. The CPU 106 stores “0FFFh” in the random number maximum value setting register 135. For this reason, it is possible to prevent a value equal to or smaller than “4” from being set in the random number circuit 103 as the random number maximum value.

  In addition, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, when the initial value changed by the CPU 106 is larger than the maximum random number value, the comparator 122 sequentially outputs a count value update signal to the counter 121. The CPU 106 can further change the changed initial value by continuously updating the count value from the changed initial value to the final value and outputting a notification signal. Thereby, it is possible to prevent the count value output to the random value storage circuit 131 from becoming larger than the random number maximum value.

  Further, cycle setting commands “00h” to “06h” for designating a value less than or equal to the lower limit value “system clock signal cycle × 128 × 7” are written in the cycle setting register 137 provided in the random number circuit 103 shown in FIG. In this case, the CPU 106 stores “07h” in the period setting register 137. For this reason, it is possible to prevent a value smaller than “system clock signal cycle × 128 × 7” from being set in the random number circuit 103 as the cycle of the internal clock signal.

  In the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the CPU 106 sets the maximum value of the random number, the random number update method, and the cycle of the random number generation clock signal S1 in the random number circuit 103, Start. For this reason, after the start of power supply, before setting the maximum value of the random number, the random number update method, and the cycle of the random number generation clock signal S1, the problem that random numbers are generated from the random number circuit 103 is prevented. Can do.

  In addition, in the pachinko gaming machine 1 having the random number circuit 103 shown in FIG. 46, when the system is reset by the reset controller 102, the random number circuit activation data “80h” is written into the random number circuit activation register 141, thereby It can be started again.

  In the pachinko gaming machine 1 provided with the random number circuit 103 shown in FIG. 46, the start winning opening switch 70 sends the start winning signal SS to the CPU 106 based on the winning of the game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. Output to. The CPU 106 is based on the fact that the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 milliseconds). It is determined that the game ball has won the normal variable winning ball apparatus 6, a start winning signal SN for latch is sent to the random number circuit 103, and random number value fetch data “01h” is written in the random value fetch register 139.

  Thereafter, in the first game control interrupt process, the CPU 106 sends an output control signal SC to the random value storage circuit 131 to control the random value storage circuit 131 to a readable (enable) state, and then the random value The random R value is read from the storage circuit 131. Then, after the CPU 106 stops sending the output control signal SC to the random value storage circuit 131 and controls the random value storage circuit 131 to the unreadable state, the read random R value is set to a predetermined determination value. By determining whether or not it matches “3” or the like, it is determined whether or not the display result of the special figure game by the variable display device 4 is a big hit gaming state.

  As described above, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the CPU 106 continues the start winning signal SS while the game control interrupt process as the two timer interrupt processes is being executed. Based on the input, it is determined that the game ball has won the normal variable winning ball apparatus 6. For this reason, the pachinko gaming machine 1 can prevent the latch start winning signal SN from being erroneously output to the random number circuit 103 due to the influence of noise or the like.

  Furthermore, in the pachinko gaming machine 1 including the random number circuit 103 shown in FIG. 46, the random number value storage circuit 131 is controlled to be readable only when the CPU 106 reads the random R value. Thereby, the pachinko gaming machine 1 can more reliably and stably acquire the random number value. Further, since the CPU 106 reads out the random R value from the random value storage circuit 131 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. can do.

  The random number storage circuit 131 included in the random number circuit 103 shown in FIG. 46 has an output control signal (high level) input from the gaming control microprocessor 100 when the latch signal SL is input from the latch signal generation circuit 133. The signal SC) is converted into a low level signal, thereby controlling the output control signal SC so that it cannot be received. This prevents the CPU 106 from reading the random R value from the random value storage circuit 131 when the random R value stored in the random value storage circuit 131 is updated. The gaming machine 1 can reliably and stably update the random number value.

  Further, the random number value storage circuit 131 provided in the random number circuit 103 shown in FIG. 46 has a latch signal (high level) input from the latch signal generation circuit 133 when the output control signal SC is input from the game control microprocessor 100. The signal SL) is converted into a low level signal, thereby controlling the latch signal SL so that it cannot be received. This prevents the random R value stored in the random value storage circuit 131 from being updated when the gaming control microprocessor 100 reads the random R value from the random value storage circuit 131. Therefore, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In the pachinko gaming machine 1 having the random number circuit 103 shown in FIG. 46, when the first random number updating method is selected, the first random number updating method in the pachinko gaming machine 1 having the random number circuit 103 shown in FIG. As in the case of the selection, the process shown in the flowchart of FIG. 35 is executed as the random number circuit setting process of step S10 shown in FIG. When the random number circuit setting process as shown in FIG. 35 is executed, the random number circuit 103 shown in FIG. 46 operates according to a timing chart as shown in FIG. 36, for example. If the first random number update method is selected, the CPU 106 executes the process shown in FIG. 37 instead of the game control interrupt process shown in the flowchart of FIG. 30, and performs the random value update process in step S196. Do. In this random number value update process, the CPU 106 writes the count value update data “01h” into the count value update register 138 in synchronization with the rising edge of the random number generation clock signal S1 output from the clock signal output circuit 124. The count value C counted by the counter 121 is updated. The count value C in the counter 121 is taken in and stored in the random value storage circuit 131 in synchronization with the rising edge of the delayed clock signal S2 output as the latch signal SL from the latch signal generation circuit 133.

  As described above, also in the pachinko gaming machine 1 including the random number circuit 103 illustrated in FIG. 46, either the first random number update method or the second random number update method is selected according to the setting of the user, and the random number update method is selected. The value of random R can be stored in the numerical value storage circuit 131. For this reason, by selecting a different random number update method for each pachinko gaming machine 1, the randomness of the value of random R read from the random value storage circuit 131 can be improved. Further, the timing at which the counter 121 updates the count value C and the timing at which the count value C is taken into the random value storage circuit 131 and the value of the random R are updated can be designated, so that a random value that has not been updated is read out. Can be prevented.

  46, the random number generating clock signal S1 output from the clock signal output circuit 124 is input to the latch signal generating circuit 133, and the delayed clock signal S2 output from the delay circuit 132 is countered. The circuit configuration may be changed so as to be input to 121.

  In addition, the random number circuit 103 shown in FIG. 46 is changed in the same manner as the random number circuit 103 shown in FIG. 38, so that the random number generation clock signal S1 is input to the counter 121 and the latch signal generation circuit 133 and the count value C And updating the latch signal SL at the same timing, the latch signal SL may be input to the delay circuit 232 and delayed so that the update timing of the count value C and the latch timing are different. . In this case, the random number circuit 103 operates according to a timing chart shown in FIG. 49, for example.

  In the operation example shown in FIG. 49, the clock signal output circuit 124 divides the reference clock signal CLK shown in FIG. 49A supplied from the clock circuit 101, and at a low level at timings T51, T52, T53,. The clock signal S1 for generating random numbers shown in FIG. 49B is generated with the period T rising from high to low. The generated random number generation clock signal S1 is output to the selector 128 and the latch signal generation circuit 133. Here, when the second random number update method is selected, the selector 128 selects the random number generation clock signal S 1 output from the clock signal output circuit 124 and outputs it to the counter 121.

  Each time the rising edge of the random number generating clock signal S1 is input, the counter 121 updates the count value C and outputs it to the random value storage circuit 131. When the latch start winning signal SN shown in FIG. 49C is input from the CPU 103, the latch signal generation circuit 133 is synchronized with the rising edge of the random number generation clock signal S1 supplied from the clock signal output circuit 124. Thus, the latch signal SL shown in FIG. 49D is output to the delay circuit 232.

  The delay circuit 232 delays the latch signal SL input from the latch signal generation circuit 133 by ΔT (≠ nT: n is an integer), and rises from a low level to a high level at timing T81, as shown in FIG. A delayed latch signal SD is generated and output to the random value storage circuit 131. The random value storage circuit 131 stores the count value C input from the counter 121 as a random R in response to the delay latch signal SD input from the delay circuit 232. As a result, the random number circuit 103 can update the count value C at the timings T11, T12, T13,... And output the delayed latch signal SD at the timing T81 different from the timings T11, T12, T13,. . As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  In addition, in the random number circuit 103 shown in FIG. 46, the reference clock signal CLK supplied from the clock circuit 101 and the output signal from the clock signal output circuit 124 are changed by performing the same change as the random number circuit 103 shown in FIG. A random number generation clock signal S1 may be generated by performing an AND operation. Alternatively, in the random number circuit 103 shown in FIG. 46, for example, the divided clock signal generated by dividing the random number generating clock signal S1 may be input to the counter 121 to update the count value C.

  Further, in the random number circuit 103 shown in FIG. 46, a random number is generated by performing an AND operation on the reference clock signal CLK and the output signal from the clock signal output circuit 124 by performing the same change as the random number circuit 103 shown in FIG. The clock signal S1 is generated, the count value C is updated and the latch signal SL is output at the same timing, and then the latch signal SL is input to the delay circuit, whereby the count value C is updated and latched. May be different. In the random number circuit 103 shown in FIG. 46, when the same change as the random number circuit 103 shown in FIG. 40 or FIG. 42 is performed, in the case of the random number circuit shown in FIG. 46 or the same as the random number circuit shown in FIG. Compared to the case where the change is made, the difference between the update timing of the count value C and the latch timing can be increased. As a result, the pachinko gaming machine 1 can acquire the random value more reliably and stably.

  In addition, the random number circuit 103 shown in FIG. 46 is changed in the same way as the random number circuit 103 shown in FIG. 44 or 45 so that clock signals with different periods are input to the counter 121 and the latch signal generation circuit 133. May be. In these cases, since the value of the random R stored in the random value storage circuit 131 is only one of odd and even numbers, the big hit determination table includes a big hit consisting of only odd or even numbers accordingly. A judgment value may be stored.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  First, the counter 121 and the latch signal generation circuit 133 are not limited to those that update the count value C or output the latch signal SL in response to the rising edge of the random number generation clock signal S1 or the delay clock signal S2. The count value C may be updated or the latch signal SL may be output in response to the falling edge of each signal. That is, the counter 121 and the latch signal generation circuit 133 have a predetermined value such that the signal level in the random number generation clock signal S1 or the delayed clock signal S2 changes from a predetermined first signal level to a second signal level. Any device can be used as long as it can update the count value C and output the latch signal SL in response to the signal change in the embodiment.

  Next, in the above embodiment, the counter 121 counts up and updates the count value from “1” to “4095” one by one. However, the present invention is not limited to this, and the rule for updating the count value of the counter 121 is arbitrary. In the above embodiment, the counter 121 is an up counter, but may be a down counter. Furthermore, the numerical value updating means is not limited to the counter 121, and may be a pseudo random number generation circuit. Further, the randomness of the count value C input to the random value storage circuit 131 may be improved by switching the connection of each bit output terminal of the counter 121.

  Further, in the above-described embodiment, the update range restriction unit obtains the count value C input from the counter 121 and the random number maximum value specified by the random number maximum value setting data stored in the random number maximum value setting register 135. When the input count value C is less than or equal to the maximum random number value, the input count value C is output to the random value storage circuit 131, and when the input count value C is greater than the maximum random number value, the count value is updated. The comparator 122 outputs a signal to the counter 121. However, the present invention is not limited to this, and the update range restricting means performs a predetermined calculation in accordance with the random number maximum value setting data stored in the random number maximum value setting register 135 and sets the update range of the count value. Anything to regulate is optional.

  For example, as shown in FIG. 50, the update range restricting means uses the random number maximum value setting data stored in the random number maximum value setting register 135 in which the count value C input from the counter 121 is “0” to “99”. In the case of the designated random number maximum value “9”, the count value “0” is set when the input count value is “0” to “9”, the count value “1” is set when the input count value is “10” to “19”, ..., the count value update range may be restricted to "9" by outputting the count value "9" when the input count value is "90" to "99".

  In the above embodiment, the random R value read from the random value storage circuit 131 is used as a big hit determination random number for determining whether or not the pachinko gaming machine 1 is put into the big hit gaming state by generating a big hit. It was described as being used. However, the present invention is not limited to this, and the read random R value is arbitrarily used, and reach determination random numbers, special symbols, and decorations for determining whether or not to reach when lost. Random number for display to determine the variable display pattern used for variable display of the symbol, Random number for display to determine the fixed symbol of the special symbol at the time of big hit, To determine the fixed symbol of the special symbol at the time of loss Random numbers for display, random numbers for probability variation determination for determining whether or not a high probability state (special game state) in which the probability of generating a big hit is improved, and display results in a normal diagram game by the normal symbol display 40 It may be used as a random number for determining per normal drawing for determining whether or not to win. However, it is not necessary to update all the random numbers listed here using the random number circuit 103, and some random numbers may be updated without using the random number circuit 103. For example, a part of these random numbers may be updated by executing a predetermined program during the game control interrupt process, or a random number update method using a refresh register may be used in combination. Good. Furthermore, the value of the random R read from the random value storage circuit 131, the value of the random number updated by executing a predetermined program during the game control interrupt process, and / or the value of the random number updated using the refresh register, , May be used as a random number for determining jackpot, reach, variable pattern, etc.

  In the above embodiment, in the game control main process, the CPU 106 performs a random number circuit after setting the timer interrupt by the CTC 107 in step S11 after the game state restoration process in step S8 or the initialization process in S9. Although the setting process has been executed, the present invention is not limited to this, and is optional as long as the power supply is started and before the transition to the loop process. For example, the interrupt is prohibited in step S1. It may be performed immediately after setting, or may be performed immediately after setting the interrupt mode to mode 2 in step S2. Further, immediately after setting the stack pointer designation address to the stack pointer in step S3, immediately after setting the register such as CTC 107 in step S4, or immediately after setting for timer interruption in step S11. Good.

  Furthermore, in the above embodiment, the CPU 106 updates the random number value in step S196 after the count value permutation process in step S195 and before the special symbol process process in step S197 in the game control interrupt process shown in FIG. Although the process has been executed, the present invention is not limited to this, and is arbitrary as long as the game control interrupt process is in progress. For example, the random number value update process is performed before the display random number update process in step S193. May be executed. Further, the random value update process may be performed after the display random number update process in step S193 and before the initial value change process in step S194, and further after the initial value change process in step S194, step S195. It may be performed before the count value permutation change processing by.

  Further, in the above embodiment, the CPU 106 writes the random value capture data “01h” into the random value capture register 139 when winning, and updates the random R value stored in the random value storage circuit 131. It was. However, the present invention is not limited to this, and for each timer interrupt, the random number capture data “01h” is written in the random value capture register 139 and stored in the random value storage circuit 131. The value may be updated.

  Furthermore, in the above embodiment, when initial value change method setting data “03h” for designating the third initial value change method is stored in the area of address 1F97h in the user program execution data area, the CPU 106 The initial value of the count value C updated by 121 is changed to an addition value of the value stored in each address of the RAM 105. However, the present invention is not limited to this, and when the initial value change method setting data “03h” is stored, the value to be changed is based on the value stored at a predetermined address in the RAM 105. If it is a thing, it is arbitrary. For example, the CPU 106 may change the initial value of the count value C updated by the counter 121 to an integrated value or a multiplied value of a value stored in each address of the RAM 105.

  In the above embodiment, the random value storage circuit 131 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 221 to 228 to control the reception of the latch signal SL and the output control signal SC, and the output control of the random R. Enable / Disable control was performed. However, the present invention is not limited to this, and the random value storage circuit 131 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 108 and the latch signal generation circuit 133, and the latch signal SL. In response to the input of the output control signal SC, the path to the I / O port 108 and the latch signal generation circuit 133 is turned on and off to enable / disable the latch signal SL and the output control signal SC. Also good.

  In the above embodiment, the timer circuit 134 is activated in response to the input of the high level signal, and receives the reference clock signal CLK sequentially input from the clock circuit 101 while the input is at the high level. Up-counting or down-counting, and when the up-counting or down-counting value becomes a value corresponding to a predetermined time, the input signal is determined to be a high-level signal and is stored in the random value acquisition register 139 Random value capture data “01h” was written. However, the present invention is not limited to this, and the timer circuit 134 measures the time during which the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. It is optional as long as it outputs a winning signal SS. The timer circuit 134 may be configured using a dedicated or general-purpose circuit provided outside the random number circuit 103.

  Furthermore, in the above embodiment, the timer circuit 134 measures the signal input time using the reference clock signal CLK sequentially input from the clock circuit 101. However, the present invention is not limited to this, and the timer circuit 134 The circuit 134 may use a clock signal obtained by dividing the reference clock signal CLK or a clock signal output from a clock signal generation circuit different from the clock circuit 101. In the above embodiment, the timer circuit 134 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, but from the 4 ms which is the execution time of two timer interruption processes. Any time can be set as long as the time is short.

  In the above embodiment, the CPU 106 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 106 receives the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 134 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  Further, in the above-described embodiment, the gaming machine having the random number circuit 103 built therein has a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning to the normal variable winning ball device 6) is satisfied. 4 is provided with a variable display device (for example, a variable display device 4) that variably displays a plurality of types of identification information that can be identified based on the fact that the previous variable display in 4 and the end of the big hit gaming state have been established. When the display result is a predetermined specific display result, the gaming machine is controlled to a specific gaming state (for example, a big hit gaming state) advantageous to the player.

  However, the present invention is not limited to this. For example, a gaming machine having a built-in random number circuit 103 uses start detection means (for example, a start ball detector) that detects a game medium in a start area provided in the game area. A variable winning device having a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, a releasing operation) that changes from a second state unfavorable to the player to a first state advantageous to the player by detection. The variable winning device is set to the first state in a specific manner more advantageous to the player than the starting operation by detection of specific detection means (for example, a specific ball detector) that detects the game medium in a specific area provided in It may be a pachinko gaming machine that generates a specific gaming state to be controlled (for example, a big hit gaming state).

  In this case, the value of the random R read from the random value storage circuit 131 is opened in a specific manner advantageous to the player by a predetermined opening / closing member (for example, a predetermined opening / closing member) in a specific gaming state (for example, a big hit gaming state). It can be used as a determination random number relating to the determination of the upper limit number of times of operation) and the change in the internal structure of a variable winning device (for example, a variable winning ball device).

  In addition, the gaming machine incorporating the random number circuit 103 is provided on the condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special area (for example, a special device operation area). During the period in which the right is generated and the right is generated, start detection means (for example, an operation ball detection switch or a start port switch) provided in a start area (for example, an operation winning opening or a starting opening in a starting winning device) Based on the detection of the game ball, control is performed to change the special variable prize-winning device (for example, a big prize opening) from a state unfavorable for the player (for example, a closed state) to a state advantageous for the player (for example, an open state). It may be a pachinko gaming machine that can be used.

  When such a pachinko gaming machine is a gaming machine including a variable display device that displays a display result related to opening and closing of a winning device that generates a right generation state by winning a prize, a random number read from the random value storage circuit 131 is normally It can be used as a random number for design prior determination. In addition, when this type of pachinko gaming machine displays a specific display result on the variable display device, it generates a right generation state for the game medium that caused the variable display device to derive the specific display result. In the case of a gaming machine including a guidance device that guides a game ball to the specific detection device to be used, the random number read from the random value storage circuit 131 can be used as a random number for prior determination of the determination symbol.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 51, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. A slot machine 1000 shown in FIG. 51 uses a game control means (for example, a main board) or a random number generation means (for example, a main board) based on the start lever 1011 being operated by a player as a start signal output means of the present invention. For example, a start switch (not shown) for outputting to a random number generation circuit is provided. Note that the liquid crystal display 1001 shown in FIG. 51 functions as rendering means.

  In addition, if the gaming machine of the present invention has an image display device in a ball game machine such as a pachinko game machine, for example, a general electric machine or a ball game machine with a probability setting function called a Pachi-Con It does not matter. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. That is, any form of game machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information. In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

  1, 2 and 51, FIG. 3, FIG. 4, FIG. 25, FIG. 38, FIG. 40, FIG. 42, and block configurations shown in FIG. 15 to FIG. 15, the program configuration shown in FIGS. 21 and 22, the table configuration shown in FIGS. 6 and 26, the circuit configuration shown in FIG. 16, the address map shown in FIGS. 18 and 19, FIG. 27 and FIG. 30 to 35, FIG. 37, and FIG. 48, the timing chart configurations shown in FIGS. 29, 36, 39, 41, 43, 47, and 49, etc. Changes and modifications can be arbitrarily made without departing from the scope. In addition, “input” and “output” of each signal are relative concepts that change depending on which of the components included in the pachinko gaming machine 1 of the present invention is focused. Therefore, regardless of which term is used, it is only necessary that each signal can be transmitted and the above-described operations and processes can be realized without departing from the spirit of the present invention.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided on a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Further, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a removable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows one structural example of a random number circuit. It is a figure which shows the structural example of an update rule selection register. It is a figure which shows the structural example of an update rule memory. It is explanatory drawing of the change operation | movement of the permutation of count value by a count value permutation change circuit. It is a figure which shows the structural example of a count value permutation change register. It is explanatory drawing of the update operation of the count value by a counter and a comparator. It is a figure which shows the structural example of a random number maximum value setting register. It is a figure which shows the structural example of a period setting register. It is a figure which shows the structural example of a count value update register. It is a figure which shows the structural example of a random value taking-in register. (A) is a figure which shows the structural example of a random number update system selection register, (B) is explanatory drawing of random number update system selection data. It is a figure which shows the structural example of a random number circuit starting register. It is a figure which shows the structural example of a random value storage circuit. 3 is a timing chart for explaining the operation of a random value storage circuit. It is a figure which shows an example of the address map in the microprocessor for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing of initial value change system selection data. It is a figure which shows the structural example of a user program. It is a figure which shows the structural example of a random number circuit setting program. It is explanatory drawing of the update operation | movement of the random value by CPU when the 1st random number update system is selected. It is explanatory drawing of the update operation | movement of the random value by CPU when the 2nd random number update system is selected. It is a block diagram which shows the structural example of the microprocessor for game control. It is a figure which shows the structural example of a big hit determination table. It is a flowchart which shows a game control main process. It is a flowchart which shows a random circuit setting process. It is a timing chart for demonstrating operation | movement of a random number circuit. It is a flowchart which shows a game control interruption process. It is a flowchart of the initial value change process in FIG. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a flowchart which shows the modification of the random number circuit setting process in FIG. It is a timing chart for demonstrating operation | movement of a random number circuit. FIG. 31 is a flowchart showing a modification of the game control interrupt process in FIG. 30. FIG. It is a block diagram which shows the other structural example of a random number circuit. FIG. 39 is a timing chart for explaining the operation of the random number circuit shown in FIG. 38. FIG. It is a block diagram which shows the other structural example of a random number circuit. 41 is a timing chart for explaining the operation of the random number circuit shown in FIG. 40. It is a block diagram which shows the other structural example of a random number circuit. 43 is a timing chart for explaining the operation of the random number circuit shown in FIG. It is a block diagram which shows the other structural example of a random number circuit. It is a block diagram which shows the other structural example of a random number circuit. It is a block diagram which shows the other structural example of a random number circuit. 47 is a timing chart for explaining the operation of the random number circuit shown in FIG. 46. It is a flowchart which shows the modification of the special symbol process process in FIG. 47 is a timing chart for explaining the operation of the random number circuit shown in FIG. 46. It is explanatory drawing of the modification of the update operation | movement of the count value shown in FIG. It is a front view of a slot machine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Variable display device 6 ... Ordinary variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp 10 ... Power supply board 11 ... Main board 12 ... Display control board 13 ... Audio control board 14 ... Lamp control board 15 ... Dispensing control board 16 ... Information terminal boards 21, 22 ... Solenoid 40 ... Normal symbol display 70 ... Start winning port switch 100 ... Micro for game control Processor 101 ... Clock circuit 102 ... Reset controller 103 ... Random number circuit 104 ... ROM
105 ... RAM
106 ... CPU
107… CTC
DESCRIPTION OF SYMBOLS 108 ... I / O port 109 ... Switch circuit 110 ... Solenoid circuit 121 ... Counter 122 ... Comparator 123 ... Count value permutation change circuit 124 ... Clock signal output circuit 125 ... Count value update signal output circuit 126 ... Random value read signal output circuit 127: Random number update method selection signal output circuit 128 ... Selector 130 ... Random number circuit start signal output circuit 131 ... Random value storage circuit 132, 232 ... Delay circuit 133 ... Latch signal generation circuit 134 ... Timer circuit 135 ... Random number maximum value setting register 136 ... Count value permutation change register 137 ... Period setting register 138 ... Count value update register 139 ... Random value fetch register 140 ... Random number update method selection register 141 ... Random number circuit start register 142 ... Update rule selection register 143 ... update rule memory 145, 201, 203 ... AND circuit 150 ... user program 151 ... random number circuit setting program 151a ... random number maximum value setting module 151b ... random number update method selection module 151c ... cycle setting module 151d ... random number circuit starting module 152 ... Display result determination program 153 ... Initial value change program 154 ... Count value permutation change program 170 ... Special figure holding memory 171 ... Big hit determination table memory 171a ... Normal big hit determination table 171b ... Probability change big hit determination table 172 ... Flag memory 202, 204 ... NOT circuits 211 to 218 ... flip-flop circuits 221 to 228 ... OR circuit 1000 ... slot machine 1001 ... liquid crystal display 1002 ... variable display device 1011 ... start lever

Claims (19)

A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A microprocessor incorporating a random number circuit for generating a random number and a game control means for controlling the progress of the game, and operating using power supplied from the power supply means;
A clock signal generating means for generating a reference clock signal having a predetermined period and outputting the reference clock signal to the random number circuit;
A starting signal output means for outputting a starting signal to the random number circuit and the game control means based on the execution condition being satisfied;
Variable display control means for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor;
The random number circuit includes:
A preceding clock signal generating means for generating a preceding clock signal having a predetermined period using a reference clock signal input from the clock signal generating means, and outputting the preceding clock signal;
Clock signal delaying means for generating a delayed clock signal by delaying the preceding clock signal input from the preceding clock signal generating means by a period different from a period that is an integral multiple of the predetermined period, and outputting the delayed clock signal; ,
The first timing at which the preceding clock signal output from the preceding clock signal generating means changes in a predetermined manner at each predetermined period and the delayed clock signal output from the clock signal delaying means at each predetermined period. Numerical value updating means for updating numerical data at any one timing of the second timing that changes in a predetermined manner;
A latch for outputting a start signal input from the start signal output means as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means between the first timing and the second timing. Signal output means;
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Random number circuit setting means for setting the random number circuit to update the random number value after starting the supply of power by the power supply means;
Timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically after the setting is made to the random number circuit by the random number circuit setting means;
During execution of the timer interrupt process, based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and the read random value is the predetermined determination value data. Display result determination means for determining whether or not to make the display result in the variable display a specific display result by determining whether or not they match,
A gaming machine characterized by that. The random number circuit includes:
A random number maximum value setting register for storing random number maximum value setting data for specifying a maximum value of a random number generated by the random number circuit;
Update range restriction means for restricting the update range by the numerical value update means according to the random number maximum value setting data stored in the random number maximum value setting register,
The random number circuit setting means includes random number maximum value setting data writing means for writing random number maximum value setting data in the random number maximum value setting register.
The gaming machine according to claim 1. When the maximum value of the random number specified by the random number maximum value setting data written by the random number maximum value setting unit in the random number maximum value setting register is smaller than a predetermined lower limit value, the game control means The random number maximum value setting data for designating a predetermined value equal to or greater than the value is stored in the random number maximum value setting register.
The gaming machine according to claim 2, wherein: The numerical value updating means circularly updates the numerical data from a predetermined initial value to a predetermined maximum value,
The random number circuit includes notification signal output means for outputting a notification signal for notifying that when the numerical data is updated to the predetermined maximum value by the numerical value updating means,
The game control means is an initial stage for changing the predetermined initial value in the numerical data updated by the numerical value updating means in response to the notification signal input from the notification signal output means during execution of the timer interruption process. Including value change means,
The gaming machine according to claim 1, 2, or 3. The initial value changing means includes means for changing the changed initial value again when the changed initial value is larger than the maximum value of the random number.
The gaming machine according to claim 4, wherein: The random number circuit includes:
A numerical permutation change register for storing numerical permutation change data for requesting a change in the permutation, which is an update order of the numerical data updated by the numerical value updating means;
When the numerical permutation change data is stored in the numerical permutation change register, the numerical permutation change means for changing to a permutation of an update order different from the permutation when the numerical permutation change data is not stored,
The game control means includes numerical permutation change data writing means for writing the numerical permutation change data to the numerical permutation change register during execution of the timer interrupt process.
The gaming machine according to any one of claims 1 to 5, characterized in that: The random number circuit includes:
A numerical value update register for storing numerical value update data for requesting updating of numerical data by the numerical value update means;
A numerical value acquisition register for storing numerical value acquisition data instructing to store the numerical value data updated by the numerical value update means in the random value storage means as a random value;
A random value update method selection register for storing random number update method selection data for designating a random number update method selected from the first and second random number update methods which are methods for updating a random value;
When random number update method selection data for specifying a first random number update method is stored in the random value update method selection register, the preceding clock signal output from the preceding clock signal generation unit or the delayed clock signal generation unit Instead of the delayed clock signal that is output from the numerical value update instruction signal to instruct the update of the numerical data in response to the numerical value update data is written to the numerical value update register to the numerical value update means, When the random number update method selection data for designating the second random number update method is stored in the random value update method selection register, the preceding clock signal output from the preceding clock signal generating unit and the delayed clock signal generating unit One of the delayed clock signals output from the update signal for outputting to the numerical value updating means It includes a selection means,
The random number circuit setting means specifies the random number update method selected from at least the first and second random number update methods as a setting for causing the random number circuit to update the random number value. Update method setting means for writing selection data into the random number update method selection register;
The game control means includes numerical value update data writing means for writing the numerical value update data to the numerical value update register when the first random number update method is selected during execution of the timer interrupt process,
When the start signal output means outputs a start signal, the numerical value acquisition data is written in the numerical value acquisition register,
The numerical value update means is a numerical value update instruction selected and input by the update signal selection means when random number update method selection data designating a first random number update method is stored in the random number value update method selection register When the random number update method selection data specifying the second random number update method is stored in the random number value update method selection register when the numerical data is updated at a timing when the signal changes in the predetermined manner, the preceding clock signal Update the numerical data at a timing at which one of the delayed clock signal selected and input by the update signal selection means changes in the predetermined manner every predetermined cycle,
The latch signal output means includes a preceding clock signal output from the preceding clock signal generation means when random number update method selection data for designating a first random number update method is stored in the random number value update method selection register. Either one of the delayed clock signals output from the delayed clock signal generation means is output as a latch signal, and random number update method selection data for specifying a second random number update method is stored in the random value update method selection register. The preceding clock signal output from the preceding clock signal generator and the delay output from the delayed clock signal generator in response to the writing of the numerical data into the numerical register. A signal different from the signal selected by the update signal selection means among the clock signals is provided for each predetermined period. At a timing of varying the predetermined manner, and outputs the latched signal,
The gaming machine according to any one of claims 1 to 6, characterized in that: The random number circuit includes a cycle setting register for storing cycle setting data for designating an update cycle of numeric data by the numeric update unit,
The random number circuit setting means includes a period setting means for writing the frequency setting data for designating a preset update period to the period setting register,
The preceding clock signal generation means changes the period of the reference clock signal output from the clock signal generation means according to the period setting data stored in the period setting register, and outputs it as the preceding clock signal;
The gaming machine according to any one of claims 1 to 7, characterized in that: The game control means, when the update period specified by the period setting data written in the period setting register by the period setting means is smaller than a predetermined lower limit value, sets the period setting data for specifying the predetermined lower limit value. Store in the cycle setting register,
The gaming machine according to claim 8, wherein: The random number circuit includes:
A random number circuit activation register for storing random number circuit activation data for requesting activation of the random number circuit;
Random number circuit activation means for activating the random number circuit in response to the random number circuit activation data being written to the random number circuit activation register;
The random number circuit setting means includes random number circuit activation setting means for writing the random number circuit activation data into the random number circuit activation register.
The gaming machine according to any one of claims 1 to 9, wherein the gaming machine is characterized by that. The microprocessor includes system reset means for system resetting the microprocessor,
The random number circuit activation setting means, when the system is reset by the system reset means, rewrites the random number circuit activation data in the random number circuit activation register to activate the random number circuit.
The gaming machine according to claim 10. The random number circuit measures a time during which a start signal is input from the start signal output means, and outputs a start signal to the latch signal output means when the measured time reaches a predetermined time. including,
The gaming machine according to any one of claims 1 to 11, characterized in that: The display result determining means is based on the fact that the start signal is continuously input from the start signal output means until the number of executions of the timer interrupt process reaches a predetermined number. Read a random value,
The timer means includes
Including setting means for setting, as the predetermined time, a time shorter than the time until the number of executions of the timer interrupt process reaches the predetermined time, and the measured time is set as the predetermined time by the setting means When the time comes, the start signal is output to the latch signal output means.
The gaming machine according to claim 12, wherein: The game control means outputs an output control signal to the random value storage means so that the random number value storage means can be read before the display result determination means reads the random value from the random value storage means. Read control for stopping the output of the output control signal to the random value storage means and controlling the random value storage means to an unreadable state after the display result determination means reads the random value from the random value storage means Including means,
The gaming machine according to any one of claims 1 to 13, wherein the gaming machine is any one of the above. The random value storage means includes an output control signal reception control means for controlling the output control signal output from the read control means to an unreceivable state when a latch signal is input from the latch signal output means. ,
The gaming machine according to claim 14, wherein The random value storage means includes a latch signal reception control means for controlling the latch signal output from the latch signal output means in an unreceivable state when an output control signal is input from the read control means.
The gaming machine according to claim 14 or 15, characterized in that A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A microprocessor incorporating a random number circuit for generating a random number and a game control means for controlling the progress of the game, and operating using power supplied from the power supply means;
A clock signal generating means for generating a reference clock signal of a predetermined period and outputting it to the random number circuit;
A starting signal output means for outputting a starting signal to the random number circuit and the game control means based on the execution condition being satisfied;
Variable display control means for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor;
The random number circuit includes:
A preceding clock signal generating means for generating a preceding clock signal having a predetermined period using a reference clock signal input from the clock signal generating means, and outputting the preceding clock signal;
Numerical value updating means for updating numerical data at a first timing at which the preceding clock signal input from the preceding clock signal generating means changes in a predetermined manner every predetermined cycle;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at the first timing;
A latch signal delay means for delaying a latch signal input from the latch signal output means by a period different from an integer multiple of the predetermined period to generate a delayed latch signal, and outputting the delayed latch signal;
Random number value storage means for storing numerical data updated by the numerical value update means as a random value at a second timing when the delayed latch signal input from the latch signal delay means changes in the predetermined manner;
The game control means includes
Random number circuit setting means for setting the random number circuit to update the random number value after starting the supply of power by the power supply means;
Timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically after the setting is made to the random number circuit by the random number circuit setting means;
During execution of the timer interrupt process, based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and the read random value is the predetermined determination value data. Display result determination means for determining whether or not the display result in the variable display is set as a specific display result by determining whether or not they match,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A microprocessor incorporating a random number circuit for generating a random number and a game control means for controlling the progress of the game, and operating using power supplied from the power supply means;
A clock signal generating means for generating a reference clock signal of a predetermined period and outputting it to the random number circuit;
A start signal output means for outputting a start signal to the game control means based on the execution condition being satisfied;
Variable display control means for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor;
The game control means includes
Random number circuit setting means for setting the random number circuit to update the random number value after starting the supply of power by the power supply means;
Timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically after the setting is made to the random number circuit by the random number circuit setting means;
Display result determination means for determining whether or not to display the variable display as a specific display result based on the start signal being input from the start signal output means during execution of the timer interrupt process;
A latch start signal output means for generating a latch start signal and outputting it to the random number circuit based on the start signal input from the start signal output means during execution of the timer interrupt process;
The random number circuit includes:
A preceding clock signal generating means for generating a preceding clock signal having a predetermined period using a reference clock signal input from the clock signal generating means, and outputting the preceding clock signal;
Clock signal delaying means for generating a delayed clock signal by delaying the preceding clock signal input from the preceding clock signal generating means by a period different from a period that is an integral multiple of the predetermined period, and outputting the delayed clock signal; ,
The first timing at which the preceding clock signal output from the preceding clock signal generating means changes in a predetermined manner at each predetermined period and the delayed clock signal output from the clock signal delaying means at each predetermined period. Numerical value updating means for updating numerical data at any one timing of the second timing that changes in a predetermined manner;
The latch start signal input from the latch start signal output means is a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means between the first timing and the second timing. Latch signal output means for outputting as
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The display result determining means reads a random value from the random number storage circuit and determines whether or not the read random number value matches a predetermined determination value data, thereby specifying the display result in the variable display. Decide whether to make a result,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A microprocessor incorporating a random number circuit for generating a random number and a game control means for controlling the progress of the game, and operating using power supplied from the power supply means;
A clock signal generating means for generating a reference clock signal of a predetermined period and outputting it to the random number circuit;
A start signal output means for outputting a start signal to the game control means based on the execution condition being satisfied;
Variable display control means for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor;
The game control means includes
Random number circuit setting means for setting the random number circuit to update the random number value after starting the supply of power by the power supply means;
Timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically after the setting is made to the random number circuit by the random number circuit setting means;
Display result determination means for determining whether or not to display the variable display as a specific display result based on the start signal being input from the start signal output means during execution of the timer interrupt process;
A latch start signal output means for generating a latch start signal and outputting it to the random number circuit based on the start signal input from the start signal output means during execution of the timer interrupt process;
The random number circuit includes:
A preceding clock signal generating means for generating a preceding clock signal having a predetermined period using a reference clock signal input from the clock signal generating means, and outputting the preceding clock signal;
Numerical value updating means for updating numerical data at a first timing at which the preceding clock signal input from the preceding clock signal generating means changes in a predetermined manner every predetermined cycle;
Latch signal output means for outputting the latch start signal input from the latch start signal output means as a latch signal at the first timing;
A latch signal delay means for delaying a latch signal input from the latch signal output means by a period different from an integer multiple of the predetermined period to generate a delayed latch signal, and outputting the delayed latch signal;
Random number value storage means for storing numerical data updated by the numerical value update means as a random value at a second timing when the delayed latch signal input from the latch signal delay means changes in the predetermined manner;
The display result determining means reads a random value from the random number storage circuit and determines whether or not the read random number value matches a predetermined determination value data, thereby specifying the display result in the variable display. Decide whether to make a result,
A gaming machine characterized by that.

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