JP2005142524A - 半導体ウエハの接着前表面処理 - Google Patents
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02096—Cleaning only mechanical cleaning
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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Abstract
【解決手段】 二つの対応する接着表面で二枚のウエハを接着するプロセスであって、(a)少なくとも一つの接着表面を活性化させる工程と、(b)接着表面を接触させる工程とを備え、工程(a)は前記接触すべき表面をブラッシングすることにより行われるプロセス。さらにドナーウエハに起因する層を剥離するプロセスである。
【選択図】 図1
Description
別の方法としては、特定の化学的環境で行う場合は、Chemical Mechanical Planarization (CMP)のような機械化学的研磨が接着表面を活性化するのに用いられる。
(a)少なくとも一つの接着表面を活性化させる工程と、
(b)前記接着表面を接触させる工程とを備え、
工程(a)は前記接触表面をブラッシングすることにより行われることを特徴とするプロセスが提案される。
(a)薄い層の厚みにほぼ対応する前記ドナーウエハの所定深さに脆弱領域を形成する工程と、
(b)ブラッシングにより、前記ドナーウエハ且つ又は受入れウエハの表面を活性かさせる工程と、
(c)前記活性化された(複数の)表面において前記ドナーウエハと受入れウエハとを接着させる工程と、
(d)前記ドナーウエハから前記受入れウエハに接着された薄い層を剥離するためにエネルギを前記脆弱領域に供給する工程とを備えたことを特徴とするプロセスを提供する。
(2)ドライ・ケミカル洗浄
(3)プラズマ処理
(4)機械化学研磨
ウェト・ケミカル洗浄(1)は(水酸化アンモニウム(NH4OH、過酸化水素(H2O2)そして脱イオン水を含む溶液SC1を用いる処理とこれに続く塩化水素酸(HCL)と過酸化水素(H2O2)そして脱イオン水を含む溶液SC2を用いる処理とを含むRCA処理且つ又は一連のリンス且つ又はオゾン化ウェット処理且つ又はSPM処理且つ又は塩化水素酸処理、又は、接着表面を洗浄且つ又は活性化させるのに適する他の溶液でもよい。
図4、5を参照して、本出願人は、2枚のウエハの表面を一回のブラッシングを行った又は行わずに接触させ、そして最後にそれらを加熱した後の2枚のウエハの間の平均結合エネルギを測定した。
Claims (22)
- マイクロエレクトロニクス、光学又は光電子での応用のために、二つの対応する接着表面で二枚のウエハを接着するプロセスであって、
(a)少なくとも一つの接着表面を活性化させる工程と、
(b)前記接着表面を接触させる工程とを備え、
工程(a)は前記接触すべき表面をブラッシングすることにより行われることを特徴とするプロセス。 - 工程(a)の前に、前記二つの接着表面の少なくとも一つの上に接着層を形成する工程を備えることを特徴とする請求項1に記載の二枚のウエハを接着するプロセス。
- 工程(c)は結合鎖を増加させる加熱処理が工程(c)と共に又は工程(c)に続いて行われることを特徴とする請求項1又は2に記載の二枚のウエハを接着するプロセス。
- 工程(a)の前に、少なくとも一回の表面を洗浄且つ又は活性化させる工程を備えることを特徴とする請求項1乃至3いずれかに記載の二枚のウエハを接着するプロセス。
- 工程(a)の前に、ウエット洗浄工程が行われることを特徴とする請求項4に記載の二枚のウエハを接着するプロセス。
- ウエット洗浄は、オゾン、塩化水素酸、SC1、SC2,SPMの化学種の内の少なくとも一つを用いることを特徴とする請求項5に記載の二枚のウエハを接着するプロセス。
- 工程(a)の前に、ドライ洗浄工程が行われることを特徴とする請求項4乃至6いずれかに記載の二枚のウエハを接着するプロセス。
- ドライ洗浄はドライオゾンの基に行われることを特徴とする請求項7に記載の二枚のウエハを接着するプロセス。
- プラズマ処理表面活性化工程が工程(a)の前に行われることを特徴とする請求項4乃至8いずれかに記載の二枚のウエハを接着するプロセス。
- 化学機械研磨工程が工程(a)の前に行われることを特徴とする請求項4乃至9いずれかに記載の二枚のウエハを接着するプロセス。
- ドナーウエハに起因する半導体材料の層を剥離するプロセスであって、
(a)薄い層の厚みにほぼ対応する前記ドナーウエハの所定深さに脆化領域を形成する工程と、
(b)ブラッシングにより、前記ドナーウエハ且つ又は受入れウエハの表面を活性化させる工程と、
(c)前記活性化された(複数の)表面において前記ドナーウエハと受入れウエハとを接着させる工程と、
(d)前記ドナーウエハから前記受入れウエハに接着された薄い層を剥離するためにエネルギを前記脆化領域に供給する工程とを備えたことを特徴とするプロセス。 - 工程(a)は、前記脆弱領域の深さにほぼ等しい深さに原子種を注入する又は前記脆化領域における層を多孔性とするという二つの技術の一つを用いて行われることを特徴とする請求項11に記載の層を剥離するプロセス。
- 工程(b)の前に、接着層が前記二つの接着表面の少なくとも一つの上に形成されることを特徴とする請求項11又は12に記載の層を剥離するプロセス。
- 過熱処理が前記ドナーウエハと前記受入れウエハとの間の接着に伴い又は後で行われて前記2枚のウエハ間の結合鎖を増加することを特徴とする請求項11乃至13いずれかに記載の層を剥離するプロセス。
- 工程(a)と工程(b)との間に少なくとも一回の表面洗浄且つ又は活性化工程が行われることを特徴とする請求項11乃至14いずれかに記載の層を剥離するプロセス。
- 工程(a)と工程(b)との間にウエット洗浄工程が行われることを特徴とする請求項15に記載の層を剥離するプロセス。
- ウエット洗浄は、オゾン、塩化水素酸、SC1、SC2,SPMの化学種の内の少なくとも一つを用いることを特徴とする請求項16に記載の層を剥離するプロセス。
- 工程(a)と工程(b)との間にドライ洗浄工程が行われることを特徴とする請求項15乃至17いずれかに記載の層を剥離するプロセス。
- ドライ洗浄はドライオゾンの基に行われることを特徴とする請求項18に記載の層を剥離するプロセス。
- プラズマ処理による表面活性化工程が工程(a)と工程(b)との間に行われることを特徴とする請求項15乃至19いずれかに記載の層を剥離するプロセス。
- プラズマ処理による化学機械研磨工程が工程(a)と工程(b)との間に行われることを特徴とする請求項15乃至20いずれかに記載の層を剥離するプロセス。
- silicon-on-insulator構造を作る請求項11乃至21いずれかに記載の層を剥離するプロセスの応用。
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0305236A FR2854493B1 (fr) | 2003-04-29 | 2003-04-29 | Traitement par brossage d'une plaquette semiconductrice avant collage |
Publications (3)
Publication Number | Publication Date |
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JP2005142524A true JP2005142524A (ja) | 2005-06-02 |
JP2005142524A5 JP2005142524A5 (ja) | 2006-05-18 |
JP4549726B2 JP4549726B2 (ja) | 2010-09-22 |
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JP2004136254A Expired - Lifetime JP4549726B2 (ja) | 2003-04-29 | 2004-04-30 | 半導体ウエハの接着前表面処理 |
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JP (1) | JP4549726B2 (ja) |
FR (1) | FR2854493B1 (ja) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007091639A1 (ja) * | 2006-02-09 | 2007-08-16 | Shin-Etsu Chemical Co., Ltd. | Soi基板の製造方法 |
JP2007214478A (ja) * | 2006-02-13 | 2007-08-23 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
WO2007094233A1 (ja) * | 2006-02-15 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | Soi基板およびsoi基板の製造方法 |
WO2007094232A1 (ja) * | 2006-02-16 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | Soi基板の製造方法 |
WO2007094231A1 (ja) | 2006-02-16 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | 半導体基板の製造方法 |
JP2009536446A (ja) * | 2006-09-07 | 2009-10-08 | Necエレクトロニクス株式会社 | 半導体基板の製造方法及び半導体デバイスの製造方法 |
JP2011530826A (ja) * | 2008-08-14 | 2011-12-22 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | 埋め込み接地板を備えた半導体構造体の製造方法 |
US8821644B2 (en) | 2007-11-13 | 2014-09-02 | Tokyo Electron Limited | Bevel/backside polymer removing method and device, substrate processing apparatus and storage medium |
KR20220102764A (ko) * | 2021-01-14 | 2022-07-21 | (주)인터체크 | 스크러버를 이용한 레티클 세정장치 및 방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US7919391B2 (en) * | 2004-12-24 | 2011-04-05 | S.O.I.Tec Silicon On Insulator Technologies | Methods for preparing a bonding surface of a semiconductor wafer |
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JPH06302486A (ja) * | 1993-02-16 | 1994-10-28 | Nippondenso Co Ltd | 2つの材料の直接接合方法及び材料直接接合装置 |
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Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007214304A (ja) * | 2006-02-09 | 2007-08-23 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
WO2007091639A1 (ja) * | 2006-02-09 | 2007-08-16 | Shin-Etsu Chemical Co., Ltd. | Soi基板の製造方法 |
US7977209B2 (en) | 2006-02-09 | 2011-07-12 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing SOI substrate |
JP2007214478A (ja) * | 2006-02-13 | 2007-08-23 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
WO2007094230A1 (ja) * | 2006-02-13 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | Soi基板の製造方法 |
JP2007220782A (ja) * | 2006-02-15 | 2007-08-30 | Shin Etsu Chem Co Ltd | Soi基板およびsoi基板の製造方法 |
WO2007094233A1 (ja) * | 2006-02-15 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | Soi基板およびsoi基板の製造方法 |
WO2007094232A1 (ja) * | 2006-02-16 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | Soi基板の製造方法 |
JP2007220900A (ja) * | 2006-02-16 | 2007-08-30 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
US7833878B2 (en) | 2006-02-16 | 2010-11-16 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing SOI substrate |
WO2007094231A1 (ja) | 2006-02-16 | 2007-08-23 | Shin-Etsu Chemical Co., Ltd. | 半導体基板の製造方法 |
JP2009536446A (ja) * | 2006-09-07 | 2009-10-08 | Necエレクトロニクス株式会社 | 半導体基板の製造方法及び半導体デバイスの製造方法 |
US8821644B2 (en) | 2007-11-13 | 2014-09-02 | Tokyo Electron Limited | Bevel/backside polymer removing method and device, substrate processing apparatus and storage medium |
JP2011530826A (ja) * | 2008-08-14 | 2011-12-22 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | 埋め込み接地板を備えた半導体構造体の製造方法 |
US9214515B2 (en) | 2008-08-14 | 2015-12-15 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for making a semiconductor structure with a buried ground plane |
KR20220102764A (ko) * | 2021-01-14 | 2022-07-21 | (주)인터체크 | 스크러버를 이용한 레티클 세정장치 및 방법 |
KR102567863B1 (ko) | 2021-01-14 | 2023-08-18 | (주)인터체크 | 스크러버를 이용한 레티클 세정장치 |
Also Published As
Publication number | Publication date |
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JP4549726B2 (ja) | 2010-09-22 |
EP1473765A3 (fr) | 2005-12-28 |
FR2854493A1 (fr) | 2004-11-05 |
EP1473765A2 (fr) | 2004-11-03 |
EP1473765B1 (fr) | 2013-06-05 |
FR2854493B1 (fr) | 2005-08-19 |
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