JP2005125447A - Electronic component and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized electronic component securing a space excellent in air-tightness on the functional face of a chip. <P>SOLUTION: The electronic component has a silicon substrate 100, in which an MEMS is formed in the functional region of the main face, and a sealing member 200 for air-tightly sealing the functional region. The sealing member 200 is joined to the silicon substrate 100 in a state of being separated from the functional region and covering the functional region. Further, the joining with the silicon substrate 100 has a linear expansion coefficient capable of keeping the air-tight sealing in the functional region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic component and a manufacturing technique thereof, and more particularly to a technology effective when applied to an electronic component having a MEMS.

  In surface movable electronic components such as surface acoustic wave devices, piezoelectric thin film resonators (FBARs), and RF-MEMS switches (Radio Frequency Micro Electro Mechanical Systems), the device surface state has a significant effect on the device characteristics. In order to provide, space is required on the device surface.

  FIG. 16 is a schematic view of a conventional surface acoustic wave device. In the figure, 10 is a piezoelectric element, 11 is a comb-shaped electrode on the piezoelectric element 10, 12 is an electrode on the piezoelectric element 10, 13 is a bonding wire, 14 is an adhesive, 20 is a ceramic package, and 21 is a ceramic package. The internal electrodes 21 and 22 are through holes, 23 is an external extraction electrode, 24 is a sealing cap, and 25 is a sealing cap connecting portion. The piezoelectric element 10 is connected to the ceramic package 20 with an adhesive 14 or solder with the device surface as the upper surface, and is connected to the ceramic package internal electrode 21 with a bonding wire 13 to obtain electrical continuity. Since the surface acoustic wave element uses vibration on the device surface, a space is required on the device. As with surface acoustic wave elements, space is indispensable for surface movable electronic components such as piezoelectric thin film resonators and RF-MEMS switches.

  Japanese Laid-Open Patent Publication No. 8-330894 (Patent Document 1) also proposes a method in which a surface acoustic wave element and a concave glass substrate are connected by anodic bonding to secure a space in a comb electrode portion on a piezoelectric element. ing.

JP-A-8-330984

  However, in the conventional wire bonding method, it is necessary to cap the ceramic package in order to secure the space on the chip surface. By performing cap sealing, the package size increases. In addition, the use of a ceramic substrate with a cavity is expensive. These problems also occur in surface movable electronic components such as piezoelectric thin film resonators and FR-MEMS switches, and a smaller mounting method is required for cost reduction.

  In addition to the wire bonding method, there is a flip chip method in which the device surface is on the package side and the device is connected to the package with gold bumps, solder, or the like, but it has a problem of a large package size.

  Furthermore, since a chip cut into individual pieces is mounted on a ceramic package, it takes a long manufacturing time. The package height is also increased.

  The method described in JP-A-8-330984 can provide a chip size package, but the glass substrate must be formed into a concave shape, the through-hole cannot be formed unless it is a glass substrate, It is difficult and expensive to produce a glass substrate having a linear expansion coefficient equivalent to that of a piezoelectric element having a linear expansion coefficient.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
The electronic component of the present invention is
A silicon substrate having a functional region on a main surface, and a MEMS formed on the functional region;
The functional region is hermetically sealed by being bonded to the silicon substrate in a state of covering the functional region apart from the functional region, and the bonding with the silicon substrate further hermetically seals the functional region. And a sealing member having a linear expansion coefficient that can be maintained.
(2) In the electronic component of the means (1),
A through hole provided in the silicon substrate or the sealing member;
An electrode that is electrically connected to the MEMS through the through-hole and provided on the back surface opposite to the main surface of the silicon substrate or on the surface opposite to the surface facing the silicon substrate of the sealing member; Have.
(3) In the electronic component of the means (1),
The sealing member is bonded to the silicon substrate by anodic bonding or room temperature bonding.
(4) In the electronic component of the means (1),
The sealing member is bonded to the silicon substrate by an intermetallic compound (for example, a compound of gold and tin, a compound of silver and tin).
(5) In the electronic component of the means (1),
The sealing member is bonded to the silicon substrate with a metal material (for example, solder).
(6) In the electronic component of the means (1),
The sealing member is bonded to the silicon substrate with a conductive resin or an insulating resin.

  According to the above-described means, packaging of a chip size is possible, and the height can be reduced by reducing the thickness of the silicon substrate and the sealing member. Also, wafer batch manufacturing is possible. Furthermore, since there is no or very little difference in linear expansion coefficient between the silicon substrate and the sealing member, it is possible to suppress the stress generated at the connection part (joint part between the silicon substrate and the sealing member) even during expansion and contraction due to temperature changes. , Improve reliability.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, chip-size packaging is possible, and a low profile can be achieved by reducing the thickness of the substrate. Wafer batch manufacturing is also possible. Furthermore, since there is no or very little difference in linear expansion coefficient between the silicon substrate having the functional region and the sealing member that seals the functional region, the connection portion (between the silicon substrate and the sealing member) The stress generated in the joint portion) can be suppressed, and the reliability is improved.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of an electronic component in which an RF-MEMS switch formed on a silicon chip according to a first embodiment of the present invention is sealed with silicon and a glass film,
2 is a surface shape transmission diagram of the silicon chip side after sealing and bonding with a glass film,
FIG. 3 is a perspective view of the sealing member side surface shape after sealing and joining with a glass film,
FIG. 4 shows a process for manufacturing an individual part of an electronic component in which an RF-MEMS switch formed on a silicon chip is sealed with a silicon chip and a glass film.
FIG. 5 shows a wafer batch manufacturing process of electronic components in which an RF-MEMS switch formed on a silicon wafer is sealed with a silicon wafer and a glass film.

  1 to 5, 100 is a silicon chip (silicon substrate), 101 is an electrode on the chip, 102 is a through hole, 103 is metallized, 104 is solder, 105 is an anode junction, and 106 is formed on the chip electrode 101. The electrode pad, 200 is a sealing member, and 201 is a glass film.

  In the case of the present embodiment, as an example, the electronic component constitutes an RF-MEMS switch in which an on-chip electrode 101 including an RF switch portion is formed on a silicon chip 100.

  As shown in FIG. 1, the electronic component of this embodiment has a configuration including a silicon chip 100 and a sealing member 200. The silicon chip 100 has a sealing portion on its main surface and a functional region surrounded by the sealing portion, and an RF-MEMS including the on-chip electrode 101 is formed in the functional region. The sealing member 200 is joined to the sealing portion of the silicon chip 100 in a state of covering the functional area while being separated from the functional area of the silicon chip 100. The sealing member 200 is joined by joining the glass film 201 between the joint portion of the sealing member 200 and the joint portion of the silicon chip 100. The functional area of the silicon chip 100 is hermetically sealed in a space formed by joining the silicon chip 100 and the sealing member 200.

  In the case of the package structure in which the sealing member 200 is bonded to the silicon chip 100 having the functional region and the functional region is hermetically sealed as in the present embodiment, the silicon chip and the sealing are changed by the temperature change at the time of package formation or actual use. The stop member expands and contracts, and stress and strain due to the difference in the linear expansion coefficient between the silicon chip and the sealing member are concentrated at the joint between the two. A hermetic seal cannot be maintained. Therefore, in the case of such a structure, the sealing member having the same or similar linear expansion coefficient as that of the silicon chip, in other words, the linear expansion in which the bonding between the silicon chip and the sealing member can maintain the hermetic sealing in the functional region. A sealing member having a coefficient, and in other words, a sealing member having a linear expansion coefficient that does not cause damage to the silicon chip with respect to the linear expansion coefficient of the silicon chip, and the silicon chip and the sealing member It is effective to reduce the stress and strain concentrated on the joint. In this embodiment, a sealing member 200 made of, for example, a silicon plate is used.

  The silicon chip 100 is provided with a through hole (through hole) 102 from the main surface to the back surface opposite to the main surface, and is electrically connected to the MEMS in the functional region in the through hole 102. Solder 104 is embedded. The solder 104 protrudes from the back surface of the silicon chip 100, and an electrode (external connection terminal) made of the solder 104 is provided on the back surface of the silicon chip 100.

  FIGS. 4A and 4B show a manufacturing process for realizing the first embodiment of the electronic component according to the present invention. FIG. 4A shows the silicon chip 100 on which the on-chip electrode 101 is formed, and FIG. A silicon chip in which a through hole 102 for ensuring electrical continuity with the outside is formed on the silicon chip 100 on which the electrode 101 is formed, and (c) is a glass film 201 for anodic bonding formed on a sealing member 200 such as silicon. The silicon chip in which the metallization 103 is formed in the through hole 102 of the silicon chip 100 in which the sealing member 200 and the through hole 102 are formed, and (d) is the anode of the sealing member 200 and the silicon chip 100 formed in (c). (E) is an electronic part in which solder 104 is inserted into the through hole 102 in order to ensure electrical continuity with the outside. The, (f) shows the RF-MEMS switch which is sealed by a space of the device surface.

  In (a), wiring is formed on the silicon chip 100 using a metal such as aluminum or gold or a conductive material. Electrode pads 106 are provided for these wirings.

  In (b), the through hole 102 is formed on the back surface of the electrode pad 106 using silicon wet etching, dry etching, or the like. The silicon wet etching method will be briefly described below.

  A silicon dioxide film having a thickness of 0.2 μm is formed on the [100] surface of the single crystal silicon wafer by, for example, holding it in an oxygen atmosphere with an oxidation temperature of 1000 ° C. for 90 minutes. A photosensitive resist having a thickness of 3 μm is applied to the surface of the silicon dioxide film, and the resist in the region where the through hole is formed is removed by photolithography. The silicon dioxide film in the opening is etched by dipping in a mixture of hydrofluoric acid and ammonium fluoride. Next, the photosensitive resist is removed, and the exposed silicon surface is anisotropically etched with a potassium hydroxide aqueous solution heated to 90 ° C. using silicon dioxide as a mask to form a quadrangular through-hole 102. A silicon dioxide film having a thickness of 0.2 μm is formed by performing thermal oxidation again. The above is the same as the method described in JP-A-7-283280.

  In (c), in order to ensure conduction between the on-chip electrode pad 106 and the back surface of the chip, a metallization 103 is formed by electroless plating inside the through hole 102 in order to ensure solder wettability. The metallized material may be formed from nickel, gold, copper, chromium, titanium, etc., and electrical continuity may be obtained. Further, silicon similar to the chip material is used for the sealing member 200, and a glass film 201 such as Pyrex glass for anodic bonding is formed on the outer peripheral sealing portion by a method such as vapor deposition or sputtering. As a material of the sealing member 200, it is sufficient that the linear expansion coefficient is close to that of a chip material having a functional surface such as a ceramic substrate or a glass substrate. By making the linear expansion coefficient of the sealing material equal to that of the silicon chip 100, this occurs at the sealant / chip connection (joint) when expansion or contraction occurs due to temperature changes during package formation or actual use. Stress and strain can be reduced, and connection reliability is improved.

  In (d), the silicon chip 100 having the RF-MEMS switch part manufactured in (c) is opposed to the sealing part, and the chip-side anodic bonding part 105 and the sealing member-side glass film 201 are aligned. After alignment, the anodic bonding part 105 and the glass film 201 are connected by anodic bonding by applying a heating and pressing voltage. As a result, the on-chip electrode section is sealed with a space and is protected against dust from the outside air. Further, since it is sealed with silicon and the glass film 201, it is difficult for water to enter, and no characteristic abnormality due to moisture occurs. Moreover, since it is a connection (joining) by glass, there is no fear of remelting at the time of component mounting reflow. The joining may be performed by room temperature connection.

  In (e), solder 104 for connecting to another substrate is formed in the through hole 102. As a solder forming method, a solder paste is printed on the opening using a mask having an opening at a solder application portion, and solder is formed in the through hole 102 by performing reflow, or a mask having an opening at a solder mounting portion is used. For example, a method of forming a solder ball in each through hole 102 by reflowing a solder ball into each through hole 102 can be used. However, when the solder paste is printed on the substrate on which the electronic component is mounted, for example, the mother board, this step is not necessary.

  In (f), the electronic component having the solder 104 formed thereon is inverted to obtain an electronic component having a space on the chip functional surface.

  By this step, a chip-sized RF-MEMS switch having a space on the chip functional surface and capable of reducing the stress at the connecting portion and having high moisture resistance is realized.

  FIG. 5 shows a wafer batch manufacturing process of the RF-MEMS switch for realizing the first embodiment of the electronic component according to the present invention. Components similar to those in FIGS. 1 to 4 are denoted by the same numerals.

  In (a), a wiring 101 is formed on a silicon wafer (silicon substrate) 110 using a metal such as aluminum or gold or a conductive material. Electrode pads 106 are provided for these wirings.

  In (b), through-holes 102 are formed on the back surface of each electrode pad 106 in the wafer state using silicon wet etching, dry etching, or the like. The silicon wet etching method will be briefly described below. A silicon dioxide film having a thickness of 0.2 μm is formed on the [100] surface of the single crystal silicon wafer by, for example, holding it in an oxygen atmosphere with an oxidation temperature of 1000 ° C. for 90 minutes. A photosensitive resist having a thickness of 3 μm is applied to the surface of the silicon dioxide film, and the resist in the region where the through hole 102 is to be formed is removed by photolithography. The silicon dioxide film in the opening is etched by dipping in a mixture of hydrofluoric acid and ammonium fluoride. Next, the photosensitive resist is removed, and the exposed silicon surface is anisotropically etched with a potassium hydroxide aqueous solution heated to 90 ° C. using silicon dioxide as a mask to form a quadrangular through-hole 102. A silicon dioxide film having a thickness of 0.2 μm is formed by performing thermal oxidation again. The above is the same as the method described in JP-A-7-283080.

  In (c), in order to ensure conduction between the on-chip electrode pad 106 and the back surface of the chip, a metallization 103 is formed by electroless plating inside the through hole 102 in order to ensure solder wettability. The metallized material may be formed from nickel, gold, copper, chromium, titanium, etc., and electrical continuity may be obtained. Further, silicon similar to the chip material is used for the wafer-sized sealing member 210, and a glass film 201 such as Pyrex glass for anodic bonding is formed on the outer peripheral sealing portion by about 2 to 3 μm. As a material of the wafer size sealing member 210, a linear expansion coefficient may be close to that of a chip material having a functional surface such as a ceramic substrate or a glass substrate. By making the linear expansion coefficient of the wafer size sealing member 210 equal to that of the silicon wafer 110, the encapsulant / chip connection portion (joint portion) when expansion / contraction occurs due to a temperature change during package formation or actual use. ) Can be reduced, and connection reliability is improved.

  In (d), the silicon wafer 110 having the RF-MEMS switch part produced in (c) and the wafer size sealing member 210 are made to face each other, and the position of the chip-side anode bonding part and the sealing member-side glass film 201 in the wafer state. Combine. After alignment, by applying a heating and pressing voltage, the anodic bonding portion and the glass film 201 are connected by anodic bonding. As a result, the on-chip electrode 101 is sealed with a space, and has a structure protected against dust from the outside air. Further, since it is sealed with silicon and the glass film 201, it is difficult for water to enter, and no characteristic abnormality due to moisture occurs. Moreover, since the connection is made of glass, there is no fear of remelting during component mounting reflow. The joining may be performed by room temperature connection.

  In (e), solder 104 for connecting to another substrate is formed in the through hole 102. As a solder forming method, a method of forming solder 104 in the through hole 102 by printing solder paste on the opening using a mask having an opening on the solder application portion and performing reflow, or a mask having an opening on the solder 104 mounting portion. For example, a solder ball is transferred into each through-hole 102 using solder, and solder is formed in the through-hole 102 by reflow. However, when the solder paste is printed on the substrate on which the electronic component is mounted, for example, the mother board, this step is not necessary.

  In (f), the device after anodic bonding is inverted as the wafer size, and each RF-MEMS switch device is diced by sandblasting or a dicer to produce individual RF-MEMS switch devices. Thereby, an electronic component having a space on the chip functional surface is obtained.

  By this step, a chip-sized RF-MEMS switch having a space on the chip functional surface and capable of reducing the stress at the connecting portion and having high moisture resistance is realized. Furthermore, since it is a wafer batch process, the number of steps can be reduced and handling is easy.

FIG. 6 is a cross-sectional view of an electronic component in which an RF-MEMS switch formed on a silicon chip according to a second embodiment of the present invention is sealed with silicon.
FIG. 7 shows a process for manufacturing an individual part of an electronic component in which an RF-MEMS switch formed on a silicon chip is sealed with silicon and a glass film.
FIG. 8 shows a wafer batch manufacturing process of electronic components in which an RF-MEMS switch formed on a silicon chip is sealed with silicon and a glass film.

  6 to 8, 202 is a sealing member side through hole (through hole), 203 is a sealing member side metallization, and 204 is a sealing member side solder. Existing materials are indicated by the same numbers.

  In the case of the present embodiment, as an example, the electronic component constitutes an RF-MEMS switch in which an on-chip electrode 101 including an RF switch portion is formed on a silicon chip 100.

  FIG. 7 shows a manufacturing process for realizing a second embodiment of an electronic component according to the present invention. FIG. 7A shows a sealing member in which a glass film 201 for anodic bonding is formed on a sealing member 200 such as silicon. 200, (b) is the sealing member 200 in which the through-hole 202 is formed corresponding to the electrode pad 106, and the silicon chip 100 in which the on-chip electrode 101 is formed. (C) is produced in (b). An electronic component in which the sealing member 200 and the silicon chip 100 are connected by anodic bonding, (d) an electronic component in which the sealing member side metallized 203 is formed in the sealing member side through hole 202, and (e) an external An electronic component in which a sealing member side solder 204 is inserted into the through hole 202 on the sealing member side in order to ensure electrical continuity of the device, (f) is an RF-MEMS switch sealed with a device surface space secured Indicate

  In (a), silicon similar to the chip material is used for the sealing member 200, and a glass film 201 such as Pyrex glass for anodic bonding is formed on the outer peripheral sealing portion by vapor deposition or sputtering to about 2 to 20 μm. As a material of the sealing member 200, it is sufficient that the linear expansion coefficient is close to that of a chip material having a functional surface such as a ceramic substrate or a glass substrate. By making the linear expansion coefficient of the sealing material equal to that of the chip 100, the stress and strain generated in the sealing material / chip connection portion when expansion / contraction occurs due to temperature change during package formation or actual use. It can be reduced, and the connection reliability is improved.

  In (b), a through hole 202 is formed at a location corresponding to the electrode pad 106 using silicon wet etching, dry etching, or the like. The silicon wet etching method will be briefly described below. A silicon dioxide film having a thickness of 0.2 μm is formed on the [100] surface of the single crystal silicon wafer by, for example, holding it in an oxygen atmosphere with an oxidation temperature of 1000 ° C. for 90 minutes. A photosensitive resist having a thickness of 3 μm is applied to the surface of the silicon dioxide film, and the resist in the region where the through hole 202 is formed is removed by photolithography. The silicon dioxide film in the opening is etched by dipping in a mixture of hydrofluoric acid and ammonium fluoride. Next, the photosensitive resist is removed, and the exposed silicon surface is anisotropically etched with a potassium hydroxide aqueous solution heated to 90 ° C. using silicon dioxide as a mask to form a quadrangular through hole. A silicon dioxide film having a thickness of 0.2 μm is formed by performing thermal oxidation again. The above is the same as the method described in JP-A-7-283280. On the other hand, wiring is formed on a silicon chip using a metal such as aluminum or gold or a conductive material. These wirings are provided with electrode pads.

  In (c), the chip having the RF-MEMS switch part produced in (b) is opposed to the sealing part, and the chip-side anodic bonding part and the sealing member 200-side glass film 201 are aligned. At this time, the electrode pad and the through hole are also aligned. After alignment, the anodic bonding part and the glass film 201 are connected by anodic bonding by applying a heating and pressing voltage. As a result, the on-chip electrode section is sealed with a space and is protected against dust from the outside air. Further, since it is sealed with silicon and the glass film 201, it is difficult for water to enter, and no characteristic abnormality due to moisture occurs. In addition, since the connection is made of glass, there is no fear of remelting during component mounting reflow. The joining may be performed by room temperature connection.

  In (d), in order to ensure electrical connection between the on-chip electrode pad 106 and the sealing member 200, a metallized 203 is formed by electroless plating inside the sealing member side through hole 202 in order to ensure solder wettability. . The metallized material may be formed from nickel, gold, copper, chromium, titanium, etc., and electrical continuity may be obtained.

  In (e), the sealing member side solder 204 for connecting to another substrate is formed in the sealing member side through hole 202. As a solder forming method, a solder paste is printed on the opening using a mask having an opening in the solder application portion, and solder is formed in the through hole by performing reflow, or a mask having an opening in the solder mounting portion is used. For example, a method of forming solder in the through hole by reflowing a solder ball into each through hole may be used. However, when the solder paste is printed on the substrate on which the electronic component is mounted, for example, the mother board, this step is not necessary.

  In (f), the electronic component having the sealing member-side solder 204 formed thereon is reversed to obtain an electronic component having a space on the chip functional surface.

  By this step, in addition to the advantages of the first embodiment, the sealing member side through hole 202 is formed on the sealing member 200 side, so that the sealing member side through hole 202 can be easily formed, and a chip having a functional surface It is mentioned that no special processing is required on the 100 side.

  FIG. 8 shows a wafer batch manufacturing process of an RF-MEMS switch for realizing the second embodiment of the electronic component according to the present invention. The same numerals are given to the same members as those in FIGS.

  In (a), silicon similar to the material of the silicon wafer 110 is used for the wafer size sealing member 210, and a glass film 201 such as Pyrex glass for anodic bonding is deposited or sputtered on the outer peripheral sealing portion in the wafer state. To form about 2 to 20 μm. As a material of the wafer size sealing member 210, it is sufficient that the linear expansion coefficient is close to the silicon wafer 110 material having a functional surface such as a ceramic substrate or a glass substrate. By making the linear expansion coefficient of the wafer size sealing member 210 equal to that of the silicon wafer 110, it is generated in the sealing material / chip connection portion when expansion / contraction occurs due to a temperature change during package formation or actual use. Stress and strain can be reduced, and connection reliability is improved.

  In (b), a through hole is formed at a location corresponding to the electrode pad 106 using silicon wet etching, dry etching, or the like. The silicon wet etching method will be briefly described below. A silicon dioxide film having a thickness of 0.2 μm is formed on the [100] surface of the single crystal silicon wafer by, for example, holding it in an oxygen atmosphere with an oxidation temperature of 1000 ° C. for 90 minutes. A photosensitive resist having a thickness of 3 μm is applied to the surface of the silicon dioxide film, and the resist in the region where the through hole is formed is removed by photolithography. The silicon dioxide film in the opening is etched by dipping in a mixture of hydrofluoric acid and ammonium fluoride. Next, the photosensitive resist is removed, and using silicon dioxide as a mask, the exposed silicon surface is anisotropically etched with a potassium hydroxide aqueous solution heated to 90 ° C. to form a quadrangular pyramidal through hole 202. A silicon dioxide film having a thickness of 0.2 μm is formed by performing thermal oxidation again. The above is the same as the method described in JP-A-7-283280. On the other hand, wiring is formed on a silicon wafer with a metal such as aluminum or gold or a conductive material. These wirings are provided with electrode pads.

  In (c), the silicon wafer 110 having the RF-MEMS switch part manufactured in (b) and the wafer size sealing member 210 are opposed to each other, and the position of the chip-side anode bonding part and the wafer size sealing member 210 side glass film 201 is determined. Combine. At this time, the electrode pad 106 and the sealing member side through hole 202 are also aligned. After alignment, by applying a heating and pressing voltage, the anodic bonding portion and the glass film 201 are connected by anodic bonding. As a result, the on-chip electrode portion is sealed with a space and has a structure protected against dust from the outside air. Further, since it is sealed with silicon and the glass film 201, it is difficult for water to enter, and no characteristic abnormality due to moisture occurs. Moreover, since the connection is made of glass, there is no fear of remelting during component mounting reflow. The joining may be performed by room temperature connection.

  In (d), in order to ensure electrical connection between the on-chip electrode pad 106 and the wafer size sealing member 210, the sealing member is sealed by electroless plating inside the sealing member side through-hole 202 in order to ensure solder wettability. Side metallization 203 is formed. The metallized material may be formed from nickel, gold, copper, chromium, titanium, etc., and electrical continuity may be obtained.

  In (e), the sealing member side solder 204 for connecting to another substrate is formed in the sealing member side through hole 202. As a method for forming the solder 204 on the sealing member side, a method of forming solder in the through hole by printing solder paste on the opening using a mask having an opening on the solder application portion and performing reflow, or a solder mounting portion For example, a method of forming solder in the through holes by reflowing solder balls into each through hole using an opened mask can be used. However, when the solder paste is printed on the substrate on which the electronic component is mounted, for example, the mother board, this step is not necessary.

  In (f), the device after anodic bonding is inverted as the wafer size, and each RF-MEMS switch device is diced by sandblasting or a dicer to produce individual RF-MEMS switch devices. Thereby, an electronic component having a space on the chip functional surface is obtained.

  By this step, a chip-sized RF-MEMS switch having a space on the chip functional surface and capable of reducing the stress at the connecting portion and having high moisture resistance is realized. Furthermore, since it is a wafer batch process, the number of steps can be reduced and handling is easy.

  By this step, in addition to the advantages of the first embodiment, since the sealing member side through hole 202 is formed on the wafer size sealing member 210 side, the sealing member side through hole 202 is easily formed and has a functional surface. A special processing is not necessary on the wafer side.

  FIG. 9 shows a schematic sectional view of a third embodiment of the present invention. In this embodiment, the connection portion of the silicon chip 100 / sealing member 200 subjected to the anodic bonding of the first embodiment is a gold-tin connection. By using a gold-tin connection, it is possible to manufacture at a lower cost than anodic bonding. Moreover, since it is a metal connection, stress relaxation is also expected. In order to realize this embodiment, both the chip piece manufacturing process and the wafer batch manufacturing process are possible as in the first and second embodiments. Only the steps that are different from the individual piece manufacturing process during anodic bonding shown in FIG. 4 will be described below.

  Similar to the steps of FIGS. 4A and 4B, the on-chip electrode 101 and the through hole 102 are formed on the silicon chip 100.

  About (c), about 5-30 micrometers of gold protrusions 205 are formed in the outer periphery sealing part of the sealing member 200 by plating. Nickel / gold plating or the like to be formed in the conduction port is also formed on the outer peripheral sealing portion on the chip outer peripheral sealing portion facing, and tin is formed on the outer peripheral sealing portion by about 1 to 10 μm by plating or the like. In forming the tin plating, a base metallization such as nickel, chromium, or titanium may be used. Tin may be formed by a printing method. Further, a structure in which tin plating is formed on the gold protrusion 205 on the sealing member 200 and only metallization is formed on the chip side may be employed.

  As for (d), the sealing member 200 and the silicon chip 100 formed as described above are aligned, and heated and pressurized. When the tin plating is simple tin, the heating temperature is not lower than the melting point of tin (232 ° C.), and only tin is melted at the contact interface. At the interface between the outer periphery sealing gold protrusion 205 and the tin plating, tin melts and reacts with gold to form the gold-tin intermetallic compound 107. When tin reacts, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed with the tin plating are metal-bonded. Since the melting point of the gold-tin-based intermetallic compound 107 formed thereby is higher than 232 ° C. which is the melting point of tin, even if secondary reflow is performed to mount other parts, the reflow temperature is the gold-tin-based intermetallic compound. When the melting point is 107 or less, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed by tin plating are kept connected without being remelted. Further, since the outer periphery is surrounded by the outer periphery sealing gold protrusion 205 and the gold-tin intermetallic compound 107, the on-chip electrode (on-chip wiring) 101 is maintained in a space and hermetically sealed. Note that the outer peripheral sealing portion may be used as a ground.

  In the steps (e) and (f), a space is maintained on the chip electrode and an RF-MEMS switch hermetically sealed is obtained.

  Next, the wafer collective manufacturing process by the gold-tin connection will be described only in steps different from those in FIG.

  The on-chip electrode 101 and the through hole 102 are formed on the silicon wafer 110 in the same manner as in the steps of FIGS.

  About (c), the outer periphery sealing gold protrusion 205 is formed on the outer periphery sealing portion of the wafer size sealing member 210 by plating or the like to about 5 to 30 μm. Nickel / gold plating or the like to be formed in the through hole 102 is also formed on the outer peripheral sealing portion on the chip outer peripheral sealing portion facing, and tin is formed on the outer peripheral sealing portion by about 1 to 10 μm plating or the like. In forming the tin plating, a base metallization such as nickel, chromium, or titanium may be used. Tin may be formed by a printing method. Further, a configuration in which tin plating is formed on the outer peripheral sealing gold protrusion 205 on the sealing member 200 and only metallization is formed on the chip side may be employed.

  As for (d), the wafer size sealing member 210 and the silicon wafer 110 formed as described above are aligned, and heated and pressurized. When the tin plating is simple tin, the heating temperature is not lower than the melting point of tin (232 ° C.), and only tin is melted at the contact interface. At the interface between the outer periphery sealing gold protrusion 205 and the tin plating, tin melts and reacts with gold to form the gold-tin intermetallic compound 107. When tin reacts, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed with the tin plating are metal-bonded. Since the melting point of the gold-tin-based intermetallic compound 107 formed thereby is higher than 232 ° C. which is the melting point of tin, even if secondary reflow is performed to mount other parts, the reflow temperature is the gold-tin-based intermetallic compound. When the melting point is 107 or less, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed by tin plating are kept connected without being remelted. Further, since the outer periphery is surrounded by the outer periphery sealing gold protrusion 205 and the gold-tin intermetallic compound 107, the space on the on-chip electrode is maintained and hermetically sealed. Note that the outer peripheral sealing portion may be used as a ground.

  After the through holes 102 are filled with the solder 104 in the steps (e) and (f), they are divided into individual pieces. As a result, an RF-MEMS switch that maintains a space on the chip electrode 101 and is hermetically sealed is obtained. Since it is a wafer batch process, the process can be simplified compared to the chip piece process.

  FIG. 10 is a cross-sectional view of an electronic component in which an RF-MEMS switch formed on a silicon chip 100 according to a fourth embodiment of the present invention is sealed with silicon. In this embodiment, the connection portion of the silicon chip 100 / sealing member 200 subjected to the anodic bonding of the second embodiment is a gold-tin connection. By using a gold-tin connection, it is possible to manufacture at a lower cost compared to anodic bonding. Moreover, since it is a metal connection, stress relaxation is also expected. In order to realize this embodiment, both the chip piece manufacturing process and the wafer batch manufacturing process are possible as in the second embodiment. Only the steps that are different from the individual piece manufacturing process during anodic bonding shown in FIG. 7 will be described below.

  As for (a), silicon similar to the material of the silicon chip 100 is used for the sealing member 200, and the sealing member side outer periphery sealing gold protrusion 205 is formed on the outer periphery sealing portion by about 5 to 30 μm by plating or the like. . FIG. 11 shows a pattern example of the outer peripheral sealing portion. As long as there is no electrical connection between the on-chip electrode 101 and the outer peripheral sealing portion as shown in FIG. 11, any pattern may be used. Similarly to the step (b), the sealing member side through hole 202 is formed on the sealing member 200 side, and the on-chip electrode 101 is formed on the silicon chip 100. The opposing chip outer periphery sealing portion 108 is also formed with nickel / gold plating or the like formed in the sealing member side through-hole 202 on the outer periphery sealing portion 108, and tin is plated on the outer periphery sealing portion 108 by about 1 to 10 μm. And so on. In forming the tin plating, a base metallization such as nickel, chromium, or titanium may be used. Tin may be formed by a printing method. Further, a configuration in which tin plating is formed on the outer peripheral sealing gold protrusion 205 on the sealing member 200 and only metallization is formed on the silicon chip 100 side may be employed.

  As for (c), the sealing member 200 and the chip formed as described above are aligned, and heated and pressurized. When the tin plating is simple tin, the heating temperature is not lower than the melting point of tin (232 ° C.), and only tin is melted at the contact interface. At the interface between the outer periphery sealing gold protrusion 205 and the tin plating, tin melts and reacts with gold to form the gold-tin intermetallic compound 107. When tin reacts, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed with the tin plating are metal-bonded. Since the melting point of the gold-tin-based intermetallic compound 107 formed thereby is higher than the tin melting point of 232 ° C., the reflow temperature remains the gold-tin-based intermetallic compound even when secondary reflow is performed to mount other components. When the melting point is 107 or less, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed by tin plating are kept connected without being remelted. Further, since the outer periphery is surrounded by the outer periphery sealing gold protrusion 205 and the gold-tin intermetallic compound 107, the space on the chip electrode 101 is maintained and hermetically sealed. Note that the outer peripheral sealing portion may be used as a ground.

  In the steps (d), (e), and (f), a space is maintained on the chip electrode and an RF-MEMS switch that is hermetically sealed is obtained.

  Next, the wafer collective manufacturing process by the gold-tin connection will be described only in steps different from those in FIG.

  As for (a), silicon similar to the material of the silicon wafer 110 is used for the wafer size sealing member 210, and the outer periphery sealing gold protrusion 205 is formed on the outer periphery sealing portion by about 5 to 30 μm by plating or the like. FIG. 11 shows a pattern example of the outer peripheral sealing portion. As shown in FIG. 11, any pattern may be used as long as the on-chip electrode 101 and the outer peripheral sealing portion 108 are not electrically connected. As in the step (b), the sealing member side through hole 202 is formed on the wafer size sealing member 210 side, and the on-chip electrode 101 is formed on the silicon wafer 110. Nickel / gold plating formed in the sealing member side through-hole 202 is also formed on the outer peripheral sealing portion on the outer peripheral sealing portion on the opposing chip outer peripheral sealing portion, and tin is plated on the outer peripheral sealing portion by about 1 to 10 μm. And so on. In forming the tin plating, a base metallization such as nickel, chromium, or titanium may be used. Tin may be formed by a printing method. Further, a configuration in which tin plating is formed on the outer periphery sealing gold protrusion 205 on the wafer size sealing member 210 and only metallization is formed on the silicon wafer 110 side may be employed.

  For (c), the wafer size sealing member 210 and the silicon wafer 110 formed as described above are aligned, and heated and pressurized. When the tin plating is simple tin, the heating temperature is not lower than the melting point of tin (232 ° C.), and only tin is melted at the contact interface. At the interface between the outer periphery sealing gold protrusion 205 and the tin plating, tin melts and reacts with gold to form the gold-tin intermetallic compound 107. When tin reacts, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed with the tin plating are metal-bonded. Since the melting point of the gold-tin based intermetallic compound 107 formed thereby is higher than the tin melting point of 232 ° C., the reflow temperature is maintained even after secondary reflow mounting other components. When the melting point is 107 or less, the outer peripheral sealing gold protrusion 205 and the outer peripheral sealing portion formed by tin plating are kept connected without being remelted. Further, since the outer periphery is surrounded by the outer peripheral sealing gold protrusion 205 and the gold-tin intermetallic compound 107, the space on the chip electrode 101 is maintained and hermetically sealed. Note that the outer peripheral sealing portion may be used as a ground.

  In steps (d) and (e), the sealing member side metallization 203 and the sealing member side solder 204 are formed in the sealing member side through-hole 202 so that a space is maintained on the chip electrode 101 and hermetically sealed. A wafer-like RF-MEMS switch is obtained.

  As in (f), it is divided into individual pieces to obtain an RF-MEMS switch.

  By this step, a chip-sized RF-MEMS switch having a space on the chip functional surface and capable of reducing the stress at the connecting portion and having high moisture resistance is realized. Furthermore, since it is a wafer batch process, the number of steps can be reduced and handling is easy.

  By this step, in addition to the advantages of the third embodiment, since the sealing member side through hole 202 is formed on the wafer size sealing member 210 side, the sealing member side through hole 202 is easily formed and has a functional surface. It can be mentioned that no special processing is required on the silicon wafer 110 side.

  In the third and fourth embodiments, the outer peripheral sealing portion may be connected to a metal that reacts with tin, such as silver-tin or nickel-tin.

  FIG. 12 shows a fifth embodiment according to the present invention. In the present embodiment, the outer peripheral sealing portion connection portion is changed from the gold-tin connection to the solder connection in the third embodiment shown in FIG. In addition to the advantages of the third embodiment, the solder 206 is melted at the time of connection to absorb the unevenness in the height of the outer peripheral sealing portion and the warp of the chip and the sealing material by making the connecting portion a solder connection. it can. Self-alignment is also possible.

  Also in this embodiment, both the individual piece manufacturing process and the wafer batch process are possible.

  FIG. 13 shows a sixth embodiment according to the present invention. In this embodiment, the outer peripheral sealing portion connection portion is changed from the gold-tin connection to the solder connection in the fourth embodiment in FIG. In addition to the advantages of the fourth embodiment, the solder 206 is melted at the time of connection to absorb the variation in the height of the outer peripheral sealing portion and the warp of the silicon chip 100 and the sealing member 200 by making the connecting portion a solder connection. can do. Self-alignment is also possible.

  Also in this embodiment, both the individual piece manufacturing process and the wafer batch process are possible.

  FIG. 14 shows a seventh embodiment according to the present invention. In the present embodiment, the outer peripheral sealing portion connection portion is changed from the gold-tin connection to the resin connection in the third embodiment shown in FIG. By connecting with the resin 207, the metallization process performed for ensuring wettability becomes unnecessary, and the resin can absorb the height variation of the outer peripheral sealing portion and the warp of the silicon chip 100 and the sealing member 200. By using an insulating resin, it is not necessary to consider a short circuit between the outer peripheral sealing portion 111 and the on-chip electrode 101 as shown in FIG. In the case of using a conductive resin, the outer peripheral sealing portion can be used as a ground in addition to the height variation and the absorption of the warp of the silicon chip 100 and the sealing member 200.

  Also in this embodiment, both the individual piece manufacturing process and the wafer batch process are possible.

  FIG. 15 shows an eighth embodiment according to the present invention. In the fourth embodiment, the outer peripheral sealing portion connection portion is changed from the gold-tin connection to the resin connection in the fourth embodiment shown in FIG. By connecting with the resin 207, the metallization process performed for ensuring wettability becomes unnecessary, and the resin can absorb the height variation of the outer peripheral sealing portion and the warp of the silicon wafer 110 and the wafer size sealing member 210. . By using an insulating resin, it is not necessary to consider a short circuit between the outer peripheral sealing portion 111 and the on-chip electrode 101 as shown in FIG. In the case of using a conductive resin, the outer peripheral sealing portion can be used as a ground in addition to the height variation and the absorption of the warp of the silicon wafer 110 and the wafer size sealing member 210.

  Also in this embodiment, both the individual piece manufacturing process and the wafer batch process are possible.

1 is a schematic cross-sectional view of a first embodiment of the present invention. 1 is a schematic view of a device surface on a chip according to a first embodiment of the present invention. The sealing member upper surface schematic of the 1st Example in this invention. FIG. 4 is a schematic diagram of a process for producing an individual piece according to the first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The wafer batch preparation process schematic of the 1st Example in this invention. Sectional schematic of the 2nd Example in this invention. Schematic diagram of individual piece manufacturing process of the second embodiment of the present invention. The wafer batch production process schematic of the 2nd Example in this invention. Sectional schematic of the 3rd Example in this invention. Sectional schematic of the 4th Example in this invention. The device surface schematic diagram of the 4th example in the present invention. Sectional schematic of the 5th Example in this invention. Sectional schematic of the 6th Example in this invention. Sectional schematic of the 7th Example in this invention. Sectional schematic of the 8th Example in this invention. Schematic which shows the conventional surface acoustic wave package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Piezoelectric element 11 ... Comb-shaped electrode 12 ... Electrode 13 ... Bonding wire 14 ... Adhesive 20 ... Ceramic package 21 ... Ceramic package internal electrode 22 ... Through hole 23 ... External extraction electrode 24 ... Sealing cap 25 ... Sealing Stop cap connecting part 100 ... Silicon chip 101 ... on-chip electrode 102 ... through hole 103 ... metallized 104 ... solder 105 ... anodic bonding part 106 ... electrode pad 107 ... gold-tin based intermetallic compound 108 ... periphery sealing part 109 ... conduction Mouth opening contact part 110 ... silicon wafer 111 ... outer periphery sealing part 200 ... sealing member 201 ... glass film 202 ... sealing member side through hole 203 ... sealing member side metallized 204 ... sealing member side solder 205 ... outer periphery sealing Gold protrusion 206 ... solder 207 ... resin 210 ... wafer size sealing member

Claims (13)

A silicon substrate having a functional region on a main surface, and a MEMS formed on the functional region;
The functional region is hermetically sealed by being bonded to the silicon substrate in a state of being separated from the functional region and covering the functional region, and the bonding with the silicon substrate can keep the hermetic seal of the functional region. An electronic component comprising a sealing member having a linear expansion coefficient. The electronic component according to claim 1,
The electronic component is characterized in that the functional region is hermetically sealed in a space formed by joining the silicon substrate and the sealing member. The electronic component according to claim 1,
The electronic component is characterized in that the sealing member is made of silicon. The electronic component according to claim 1,
A through hole provided in the silicon substrate or the sealing member;
An electrode that is electrically connected to the MEMS through the through-hole and provided on the back surface opposite to the main surface of the silicon substrate or on the surface opposite to the surface facing the silicon substrate of the sealing member; An electronic component comprising: The electronic component according to claim 1,
The electronic component is characterized in that the sealing member is bonded to the silicon substrate by anodic bonding or room temperature bonding. The electronic component according to claim 1,
The electronic component, wherein the sealing member is bonded to the silicon substrate by an intermetallic compound. The electronic component according to claim 1,
The electronic component, wherein the sealing member is bonded to the silicon substrate with a metal material. The electronic component according to claim 1,
The electronic component is characterized in that the sealing member is bonded to the silicon substrate by a conductive resin or an insulating resin. The electronic component according to claim 1,
The electronic component is characterized in that the sealing member is bonded to the silicon substrate by glass. A silicon substrate having a functional region on a main surface, and a MEMS formed on the functional region;
The functional region is hermetically sealed by being bonded to the silicon substrate in a state of being separated from the functional region and covering the functional region, and the bonding with the silicon substrate can keep the hermetic seal of the functional region. A sealing member having a linear expansion coefficient;
A through hole provided in the silicon substrate or the sealing member;
It is electrically connected to the MEMS through the through hole, and has an electrode provided on the back surface opposite to the main surface of the silicon substrate, or on the surface opposite to the surface facing the silicon substrate of the sealing member. An electronic component characterized by that. A step of preparing a silicon substrate on which MEMS is formed in the functional region of the main surface and a sealing member;
A step of hermetically sealing the functional region by bonding the sealing member to the silicon substrate in a state of covering the functional region apart from the functional region,
The method for manufacturing an electronic component according to claim 1, wherein the sealing member has a linear expansion coefficient that allows a joint portion with the silicon substrate to maintain hermetic sealing of the functional region. In the manufacturing method of the electronic component of Claim 11,
The silicon substrate or the sealing member has a through hole,
After the step of bonding the sealing member to the silicon substrate, it is electrically connected to the MEMS through the through hole, and the back surface opposite to the main surface of the silicon substrate, or the silicon substrate of the sealing member A method of manufacturing an electronic component, further comprising a step of forming an electrode disposed on a surface opposite to the facing surface. A step of preparing a silicon substrate having a plurality of functional regions on the main surface, each of which has a MEMS formed thereon, and a plate member made of silicon;
Bonding the plate member to the silicon substrate in a state of covering the plurality of functional regions apart from the plurality of functional regions, and individually sealing the plurality of functional regions;
And a step of dividing the silicon substrate and the plate member into a plurality of pieces.

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