JP2005084907A - メモリ帯域制御装置 - Google Patents

メモリ帯域制御装置 Download PDF

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Publication number
JP2005084907A
JP2005084907A JP2003315731A JP2003315731A JP2005084907A JP 2005084907 A JP2005084907 A JP 2005084907A JP 2003315731 A JP2003315731 A JP 2003315731A JP 2003315731 A JP2003315731 A JP 2003315731A JP 2005084907 A JP2005084907 A JP 2005084907A
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JP
Japan
Prior art keywords
memory
data
buffer
port
data transfer
Prior art date
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Pending
Application number
JP2003315731A
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English (en)
Japanese (ja)
Other versions
JP2005084907A5 (enExample
Inventor
Kenichi Okuno
健一 奥野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2003315731A priority Critical patent/JP2005084907A/ja
Priority to EP04255414A priority patent/EP1513071B1/en
Priority to DE602004008712T priority patent/DE602004008712T2/de
Priority to US10/935,608 priority patent/US7657711B2/en
Priority to CNB2004100921756A priority patent/CN100397374C/zh
Publication of JP2005084907A publication Critical patent/JP2005084907A/ja
Publication of JP2005084907A5 publication Critical patent/JP2005084907A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Memory System (AREA)
JP2003315731A 2003-09-08 2003-09-08 メモリ帯域制御装置 Pending JP2005084907A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003315731A JP2005084907A (ja) 2003-09-08 2003-09-08 メモリ帯域制御装置
EP04255414A EP1513071B1 (en) 2003-09-08 2004-09-07 Memory bandwidth control device
DE602004008712T DE602004008712T2 (de) 2003-09-08 2004-09-07 Speicherbandbreiten-Steuereinrichtung
US10/935,608 US7657711B2 (en) 2003-09-08 2004-09-07 Dynamic memory bandwidth allocation
CNB2004100921756A CN100397374C (zh) 2003-09-08 2004-09-08 存储器带宽控制装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003315731A JP2005084907A (ja) 2003-09-08 2003-09-08 メモリ帯域制御装置

Publications (2)

Publication Number Publication Date
JP2005084907A true JP2005084907A (ja) 2005-03-31
JP2005084907A5 JP2005084907A5 (enExample) 2005-06-30

Family

ID=34131940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003315731A Pending JP2005084907A (ja) 2003-09-08 2003-09-08 メモリ帯域制御装置

Country Status (5)

Country Link
US (1) US7657711B2 (enExample)
EP (1) EP1513071B1 (enExample)
JP (1) JP2005084907A (enExample)
CN (1) CN100397374C (enExample)
DE (1) DE602004008712T2 (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008032711A1 (en) * 2006-09-13 2008-03-20 Panasonic Corporation Memory controller, nonvolatile storage device, access device and nonvolatile storage system
JP2008129932A (ja) * 2006-11-22 2008-06-05 Nec System Technologies Ltd ディスクアレイ装置システム、ディスクアレイ装置制御方法、および、プログラム
JP2012525662A (ja) * 2009-04-29 2012-10-22 マイクロン テクノロジー， インク． マルチポートメモリデバイスおよび方法
US9166933B2 (en) 2011-07-11 2015-10-20 Ricoh Company, Limited Memory control apparatus, information processing apparatus, and memory control method
WO2016038710A1 (ja) * 2014-09-11 2016-03-17 株式会社日立製作所 ストレージシステム

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4135747B2 (ja) * 2006-04-06 2008-08-20 ソニー株式会社 データ処理装置及びフラッシュメモリへのアクセス方法
JP5045229B2 (ja) * 2007-05-14 2012-10-10 富士ゼロックス株式会社 ストレージシステム及びストレージ装置
US20120066471A1 (en) * 2010-09-14 2012-03-15 Advanced Micro Devices, Inc. Allocation of memory buffers based on preferred memory performance
US20120066444A1 (en) * 2010-09-14 2012-03-15 Advanced Micro Devices, Inc. Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation
US10095422B2 (en) * 2016-10-28 2018-10-09 Veritas Technologies, LLC Systems and methods for allocating input/output bandwidth in storage systems
US11258877B2 (en) 2018-07-26 2022-02-22 Netapp, Inc. Methods for managing workloads in a storage system and devices thereof
US11983164B1 (en) 2022-11-17 2024-05-14 Bank Of America Corporation System and method for data community detection via data network telemetry
US12021731B1 (en) 2023-01-05 2024-06-25 Bank Of America Corporation System and method for evaluating compliance of transmitted object data via data efficiency mapping

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63132369A (ja) 1986-11-21 1988-06-04 Oki Electric Ind Co Ltd メモリ情報転送方式
JPH03273353A (ja) 1990-03-22 1991-12-04 Hitachi Ltd 通信制御装置
JP3273191B2 (ja) 1991-11-29 2002-04-08 日本電気エンジニアリング株式会社 データ転送装置
JP3364751B2 (ja) 1992-02-20 2003-01-08 日本電気エンジニアリング株式会社 データ転送システム
KR960706657A (ko) * 1993-11-30 1996-12-09 토마스 씨. 토코스 공유 메모리 시스템에서의 병행 동작을 가능하게 하고 최대화하는 방법 및 장치(method and apparatus for providing and maximizing concurrent operations in a shared memory system)
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade
US5634004A (en) * 1994-05-16 1997-05-27 Network Programs, Inc. Directly programmable distribution element
JPH11511313A (ja) * 1995-08-16 1999-09-28 スターガイド デジタル ネットワークス，インコーポレイティド 音声信号および映像信号伝送用の帯域幅の動的割当て方法
JP3273353B2 (ja) 1995-12-21 2002-04-08 日立造船株式会社 硫酸プラント排ガスの乾式脱硫方法
US6098123A (en) 1997-05-08 2000-08-01 International Business Machines Corporation Method and apparatus for dynamic allocation of bandwidth to/from network adapter memory amongst active input/output ports
JPH10340243A (ja) 1997-06-06 1998-12-22 Hitachi Ltd 入出力データ転送システム
US6903733B1 (en) * 1997-11-24 2005-06-07 Pixelworks, Inc. Ultra-high bandwidth multi-port memory system for image scaling applications
US6339434B1 (en) * 1997-11-24 2002-01-15 Pixelworks Image scaling circuit for fixed pixed resolution display
JP2000330923A (ja) 1999-05-19 2000-11-30 Nec Corp データ転送システム及び転送方法並びに記録媒体
US6501734B1 (en) * 1999-05-24 2002-12-31 Advanced Micro Devices, Inc. Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port
KR100724438B1 (ko) * 2001-12-26 2007-06-04 엘지전자 주식회사 기지국 모뎀의 메모리 제어장치

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008032711A1 (en) * 2006-09-13 2008-03-20 Panasonic Corporation Memory controller, nonvolatile storage device, access device and nonvolatile storage system
JP2008129932A (ja) * 2006-11-22 2008-06-05 Nec System Technologies Ltd ディスクアレイ装置システム、ディスクアレイ装置制御方法、および、プログラム
JP2012525662A (ja) * 2009-04-29 2012-10-22 マイクロン テクノロジー， インク． マルチポートメモリデバイスおよび方法
US8930642B2 (en) 2009-04-29 2015-01-06 Micron Technology, Inc. Configurable multi-port memory device and method thereof
US9166933B2 (en) 2011-07-11 2015-10-20 Ricoh Company, Limited Memory control apparatus, information processing apparatus, and memory control method
WO2016038710A1 (ja) * 2014-09-11 2016-03-17 株式会社日立製作所 ストレージシステム
US10216448B2 (en) 2014-09-11 2019-02-26 Hitachi, Ltd. Storage system with read request accelerator having dynamic internal data memory allocation

Also Published As

Publication number Publication date
US7657711B2 (en) 2010-02-02
EP1513071A3 (en) 2005-12-14
CN1601501A (zh) 2005-03-30
US20050086425A1 (en) 2005-04-21
DE602004008712T2 (de) 2008-06-12
DE602004008712D1 (de) 2007-10-18
EP1513071A2 (en) 2005-03-09
EP1513071B1 (en) 2007-09-05
CN100397374C (zh) 2008-06-25

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