JP2004528707A - Ｓｏｉを形成する方法 - Google Patents

Ｓｏｉを形成する方法 Download PDF

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Publication number
JP2004528707A
JP2004528707A JP2002560178A JP2002560178A JP2004528707A JP 2004528707 A JP2004528707 A JP 2004528707A JP 2002560178 A JP2002560178 A JP 2002560178A JP 2002560178 A JP2002560178 A JP 2002560178A JP 2004528707 A JP2004528707 A JP 2004528707A
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Japan
Prior art keywords
substrate
layer
silicon
soi
insulating layer
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Pending
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JP2002560178A
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English (en)
Japanese (ja)
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JP2004528707A5 (enExample
Inventor
ファング，ツィウェイ
Original Assignee
バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド
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Application filed by バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド filed Critical バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド
Publication of JP2004528707A publication Critical patent/JP2004528707A/ja
Publication of JP2004528707A5 publication Critical patent/JP2004528707A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP2002560178A 2001-01-23 2002-01-10 Ｓｏｉを形成する方法 Pending JP2004528707A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/767,787 US20020098664A1 (en) 2001-01-23 2001-01-23 Method of producing SOI materials
PCT/US2002/000802 WO2002059946A2 (en) 2001-01-23 2002-01-10 Method of producing soi materials

Publications (2)

Publication Number Publication Date
JP2004528707A true JP2004528707A (ja) 2004-09-16
JP2004528707A5 JP2004528707A5 (enExample) 2005-12-22

Family

ID=25080577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002560178A Pending JP2004528707A (ja) 2001-01-23 2002-01-10 Ｓｏｉを形成する方法

Country Status (6)

Country Link
US (1) US20020098664A1 (enExample)
EP (1) EP1354339A2 (enExample)
JP (1) JP2004528707A (enExample)
KR (1) KR20030076627A (enExample)
CN (1) CN1528010A (enExample)
WO (1) WO2002059946A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005333052A (ja) * 2004-05-21 2005-12-02 Sony Corp Ｓｉｍｏｘ基板及びその製造方法及びｓｉｍｏｘ基板を用いた半導体装置及びｓｉｍｏｘ基板を用いた電気光学表示装置の製造方法
CN100454483C (zh) * 2007-04-20 2009-01-21 中国电子科技集团公司第四十八研究所 一种离子注入厚膜soi晶片材料的制备方法
US7619283B2 (en) * 2007-04-20 2009-11-17 Corning Incorporated Methods of fabricating glass-based substrates and apparatus employing same
CN102386123B (zh) * 2011-07-29 2013-11-13 上海新傲科技股份有限公司 制备具有均匀厚度器件层的衬底的方法
US8575694B2 (en) 2012-02-13 2013-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Insulated gate bipolar transistor structure having low substrate leakage
JP2016224045A (ja) * 2015-05-29 2016-12-28 セイコーエプソン株式会社 抵抗素子の製造方法、圧力センサー素子の製造方法、圧力センサー素子、圧力センサー、高度計、電子機器および移動体

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0845920A (ja) * 1994-07-25 1996-02-16 Hewlett Packard Co <Hp> 半導体基板に絶縁物層を形成する方法
US5710057A (en) * 1996-07-12 1998-01-20 Kenney; Donald M. SOI fabrication method
JPH11307455A (ja) * 1998-04-20 1999-11-05 Sony Corp 基板およびその製造方法
JP2000294513A (ja) * 1999-04-06 2000-10-20 Nec Corp Ｓｉ基板の酸化膜形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0845920A (ja) * 1994-07-25 1996-02-16 Hewlett Packard Co <Hp> 半導体基板に絶縁物層を形成する方法
US5710057A (en) * 1996-07-12 1998-01-20 Kenney; Donald M. SOI fabrication method
JPH11307455A (ja) * 1998-04-20 1999-11-05 Sony Corp 基板およびその製造方法
JP2000294513A (ja) * 1999-04-06 2000-10-20 Nec Corp Ｓｉ基板の酸化膜形成方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
H. W. LAM, ET. AL.: ""SILICON-ON-INSULATOR BY OXGEN ION IMPLANTATION"", JOURNAL OF CRYSTAL GROWTH, vol. 63, JPNX007010370, 1983, pages 554 - 558, ISSN: 0000824332 *
前田和夫著, 「最新ＬＳＩプロセス技術」, JPNX007010371, 20 April 1988 (1988-04-20), ISSN: 0000824333 *

Also Published As

Publication number Publication date
WO2002059946A8 (en) 2003-10-09
KR20030076627A (ko) 2003-09-26
WO2002059946A3 (en) 2003-02-20
CN1528010A (zh) 2004-09-08
WO2002059946A2 (en) 2002-08-01
US20020098664A1 (en) 2002-07-25
EP1354339A2 (en) 2003-10-22

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