JP2004236311A - 集積回路デバイス間で伝送される出力信号の電圧ピーキングを制御するマルチデバイスシステム及び方法 - Google Patents

集積回路デバイス間で伝送される出力信号の電圧ピーキングを制御するマルチデバイスシステム及び方法 Download PDF

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Publication number
JP2004236311A
JP2004236311A JP2004012760A JP2004012760A JP2004236311A JP 2004236311 A JP2004236311 A JP 2004236311A JP 2004012760 A JP2004012760 A JP 2004012760A JP 2004012760 A JP2004012760 A JP 2004012760A JP 2004236311 A JP2004236311 A JP 2004236311A
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Japan
Prior art keywords
adjustable
transistor
output
circuit
resistance
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Pending
Application number
JP2004012760A
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English (en)
Japanese (ja)
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JP2004236311A5 (enExample
Inventor
Bernd Wuppermann
ベルント・ヴッパーマン
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Agilent Technologies Inc
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Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2004236311A publication Critical patent/JP2004236311A/ja
Publication of JP2004236311A5 publication Critical patent/JP2004236311A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
JP2004012760A 2003-01-30 2004-01-21 集積回路デバイス間で伝送される出力信号の電圧ピーキングを制御するマルチデバイスシステム及び方法 Pending JP2004236311A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/354,400 US6956402B2 (en) 2003-01-30 2003-01-30 Multi-device system and method for controlling voltage peaking of an output signal transmitted between integrated circuit devices

Publications (2)

Publication Number Publication Date
JP2004236311A true JP2004236311A (ja) 2004-08-19
JP2004236311A5 JP2004236311A5 (enExample) 2007-03-08

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ID=32655545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004012760A Pending JP2004236311A (ja) 2003-01-30 2004-01-21 集積回路デバイス間で伝送される出力信号の電圧ピーキングを制御するマルチデバイスシステム及び方法

Country Status (3)

Country Link
US (1) US6956402B2 (enExample)
EP (1) EP1443651A1 (enExample)
JP (1) JP2004236311A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303668A (ja) * 2005-04-18 2006-11-02 Matsushita Electric Ind Co Ltd 出力インピーダンス可変回路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4652703B2 (ja) * 2004-03-10 2011-03-16 ルネサスエレクトロニクス株式会社 半導体回路装置及びマルチ・チップ・パッケージ
KR100773746B1 (ko) * 2006-01-31 2007-11-09 삼성전자주식회사 채널부하에 따라 송신신호레벨을 조절하는 장치
KR102573219B1 (ko) 2018-09-14 2023-09-01 삼성전자주식회사 임피던스를 조절할 수 있는 집적 회로 및 이를 포함하는 전자 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008419A (ja) * 2001-06-25 2003-01-10 Nec Corp 半導体ｉｃの出力インピーダンス整合方式

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016481A (en) * 1975-11-26 1977-04-05 Gte Automatic Electric Laboratories Incorporated Unmatched field effect transistors providing matched voltage-controlled resistances
DE2950584C2 (de) * 1979-12-15 1984-07-12 Robert Bosch Gmbh, 7000 Stuttgart Schaltungsanordnung mit steuerbarem Widerstand
US4390851A (en) * 1980-11-25 1983-06-28 Rockwell International Corporation Monolithic microwave amplifier having active impedance matching
US4813045A (en) * 1986-07-28 1989-03-14 Tektronix, Inc. Laser driver
US5852540A (en) * 1997-09-24 1998-12-22 Intel Corporation Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels
US6198309B1 (en) * 1999-03-31 2001-03-06 Applied Micro Circuits Corporation Emitter follower output with programmable current
US6114876A (en) * 1999-05-20 2000-09-05 Pericom Semiconductor Corp. Translator switch transistor with output voltage adjusted to match a reference by controlling gate and substrate charge pumps
US6781415B2 (en) * 2001-11-27 2004-08-24 Fairchild Semiconductor Corporation Active voltage level bus switch (or pass gate) translator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008419A (ja) * 2001-06-25 2003-01-10 Nec Corp 半導体ｉｃの出力インピーダンス整合方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303668A (ja) * 2005-04-18 2006-11-02 Matsushita Electric Ind Co Ltd 出力インピーダンス可変回路

Also Published As

Publication number Publication date
US6956402B2 (en) 2005-10-18
US20040150424A1 (en) 2004-08-05
EP1443651A1 (en) 2004-08-04

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