JP2004207452A - Thin-film transistor and its manufacturing method, and flat-panel display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress degrading of characteristic of a TFT due to hot carriers generated at the edge of the drain area of the TFT. <P>SOLUTION: The TFT is provided with a polysilicon layer 3 as a semiconductor layer formed on an insulative substrate 1, a gate electrode 5 formed on the polysilicon layer 3 with a gate insulation film 4 in between, a channel area 31 in the semiconductor layer 3 under the gate electrode 5, and a source area 32 and a drain area 33 formed in the polysilicon layer 3 on both sides of the channel area 31. The thicknesses T<SB>1</SB>of the polysilicon layer 3 on both sides of the source area 32 side or the drain area 33 side are made larger than that T<SB>2</SB>of the polysilicon layer 3 under the central part of the gate electrode 5, and a boundary B where the polysilicon layer 3 becomes large in thickness is located under the gate electrode 5. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a thin film transistor, a method for manufacturing the same, and a flat display device including the thin film transistor.
[0002]
[Prior art]
[Patent Document] JP-A-5-47788
A flat display device using a light-emitting diode, a liquid crystal, or the like can reduce the thickness of a display portion, and is increasingly required for use in display devices such as office equipment and computers, or special display devices.
[0003]
In particular, a thin film transistor (hereinafter, referred to as a TFT (Thin Film Transistor)) using an amorphous silicon layer or a polysilicon layer (polycrystalline silicon layer) which is amorphous is used as a switching element of the pixel in a matrix with the pixel. 2. Description of the Related Art Flat display devices which are arranged and connected to a display element to perform display have high display quality and low power consumption.
[0004]
Among them, a TFT using a polysilicon layer has a mobility about 100 to 1000 times higher than a TFT using an amorphous silicon layer. The switching element and the switching element can be integrally formed on the same substrate, whereby a low-cost and high-performance flat display device can be realized.
[0005]
[Problems to be solved by the invention]
The TFT has a problem in that a high electric field is generated at the end of the drain region during circuit operation, and hot carriers generated at the end of the drain region damage the polysilicon layer, thereby deteriorating the characteristics of the TFT.
[0006]
As a conventional technique for suppressing the problem of TFT characteristic deterioration caused by hot carriers generated at the end of the drain region and ensuring the reliability of the TFT, a TFT having an LDD (Lightly Doped Drain) structure is typical. In addition, TFTs having a GOLD (Gate Overlapped Drain) structure and the like have been proposed from the viewpoint of relaxing the electric field at the drain end.
[0007]
In view of the above technical problems, the present invention provides a TFT and a method for manufacturing the same, which can suppress the problem of deterioration of the characteristics of the TFT due to hot carriers generated at the end of the drain region. It is an object to provide a flat panel display device which is also used as a part of a driving circuit.
[0008]
[Means for Solving the Problems]
Conventionally, it has been considered that hot carriers are generated in a region of the polysilicon layer where a channel is formed, that is, in the gate electrode side of the polysilicon layer, that is, near the interface with the gate insulating film. Therefore, measures to suppress the generation of hot carriers at the end of the drain region have been proposed.
[0009]
However, the present inventors have examined the inside of the TFT during high-speed operation in consideration of a signal that is actually input to a circuit, and found that hot carriers are present in a portion other than the gate electrode side in the polysilicon layer. It was also confirmed that this occurred on the opposite side of the polysilicon layer from the gate electrode. Until now, no suppression plan has been proposed that specifically considers the generation of hot carriers on the side of the polysilicon layer opposite to the gate electrode. In other words, in the existing hot carrier suppression technology, the weight that is generated on the gate electrode side in the polysilicon layer is emphasized, so that the hot carrier generated on the side opposite to the gate electrode in the polysilicon layer is not much. Probably not.
[0010]
FIG. 4A shows the ON state of the TFT (gate voltage V _g > Threshold voltage V _th FIG. 4B is a schematic sectional view showing the TFT in the off state (V _g It is an outline sectional view showing a situation in the middle of changing to <0).
[0011]
3 is a semiconductor layer, for example, a polysilicon layer, 4 is a gate insulating film, 5 is a gate electrode, 31 is a channel region, 32 is a source region, 33 is a drain region, and 8 is an electron.
[0012]
When the TFT is turned off from on, hot carriers are generated on the side opposite to the gate electrode 5 in the polysilicon layer 3, as shown in FIG. This is because it takes time for 8 to pass through to the source region 32 or the drain region 33 as indicated by the arrow. That is, in FIG. 4B, the electrons 8 at the end of the channel region 31 immediately escape to the lateral source region 32 or the drain region 33, but most of the electrons 8 near the center of the channel region 31 Move to the lower side (the side opposite to the gate electrode 5).
[0013]
FIG. 4C is a schematic cross-sectional view showing the ON state of the TFT when the crystallinity of the channel region 31 is good, and FIG. 4D is a schematic cross-sectional view showing the OFF state of the TFT.
[0014]
Originally, if the crystallinity of the channel region 31 is improved, the electrons 8 in the channel region 31 will be generated before the high electric field region is generated in the source region 32 or the drain region 33 as shown by an arrow in FIG. Since it is quickly removed in a short time, no hot carriers are generated and such a problem does not occur. However, since there is a trap in the polysilicon layer 3 due to a crystal grain boundary, crystal distortion, or the like, a hot carrier generation phenomenon is inevitable.
[0015]
Therefore, a method other than improving the crystallinity is required, in which carriers in the channel region 31 easily escape to the source region 32 or the drain region 33.
[0016]
One means in the present invention for solving the above problem is to increase the junction area between the channel region 31 and the source region 32 or the drain region 33 so that carriers can easily escape to the source region 32 or the drain region 33. is there.
[0017]
However, as shown in FIG. 5B, simply increasing the junction area also increases the area of the channel region 31, which also increases the number of carriers. This is not the case (FIG. 5A shows a conventional structure).
[0018]
Therefore, the present inventors have considered increasing the thickness of the polysilicon layer 3 on at least one side of the source region 32 or the drain region 33 as shown in FIG. 5D. In this case, it is necessary that the boundary where the thickness of the polysilicon layer 3 becomes thicker be located below the gate electrode 5 in order to obtain an effect (FIG. 5C shows a conventional structure).
[0019]
According to this configuration, although the area of the channel region 31 does not increase, the junction area between the channel region 31 and the source region 32 or the drain region 33 increases, so that carriers can relatively easily escape.
[0020]
As another means in the present invention for solving the above-mentioned problem, as shown in FIG. 6B, the present inventors, as shown in FIG. It was considered that an impurity region 30 having a conductivity type opposite to the conductivity type of the source region 32 and the drain region 33 was provided in the layer 3 (FIG. 6A shows a conventional structure).
[0021]
For example, in the case of an n-channel TFT, a p-type impurity region 30 is provided in a part of the polysilicon layer 3 on the n-type source region 32 side or the n-type drain region 33 side.
[0022]
According to this configuration, the carriers disappear by recombination near the junction surface between the p-type impurity region 30 and the channel region 31 below the gate electrode 5, so that the carriers can relatively easily escape.
[0023]
According to the above two means according to the present invention, when the gate voltage is sufficiently turned off and a high electric field is generated near the junction surface between the channel region 31 and the source region 32 or the drain region 33, the channel voltage increases. Since almost no carriers are present in the region 31, even if a high electric field is generated, almost no carriers pass therethrough, so that almost no hot carriers are generated.
[0024]
Therefore, since the polysilicon layer 3 constituting the channel region 31 is hardly damaged by hot carriers, the TFT according to the present invention having such a structure hardly changes in characteristics even when driven for a long time. Thus, according to the present invention, a TFT having high reliability can be provided.
[0025]
That is, in order to solve the above problems, the present invention employs a configuration as described in the claims.
[0026]
That is, the thin film transistor according to claim 1 includes a semiconductor layer provided on an insulating substrate, a gate electrode provided on the semiconductor layer via a gate insulating film, and a semiconductor layer provided under the gate electrode. In a thin film transistor having a channel region provided and a source region and a drain region provided in the semiconductor layer on both sides of the channel region, the thickness of the semiconductor layer on at least one side of the source region or the drain region is reduced. The thickness of the semiconductor layer below the central portion of the gate electrode is greater than the thickness of the semiconductor layer, and the boundary where the thickness of the semiconductor layer increases is located below the gate electrode.
[0027]
Further, the thin film transistor according to claim 2 includes a semiconductor layer provided on an insulating substrate, a gate electrode provided on the semiconductor layer via a gate insulating film, and a semiconductor layer provided under the gate electrode. In the thin film transistor having a channel region provided and a source region and a drain region provided in the semiconductor layer on both sides of the channel region, the semiconductor layer on at least one side of the source region side or the drain region side includes: An impurity region having a conductivity type opposite to the conductivity type of the source region and the drain region is provided.
[0028]
Further, the method for manufacturing a thin film transistor according to claim 3 includes a first step of providing a semiconductor layer on an insulating substrate;
A second step of providing a gate electrode on the semiconductor layer via a gate insulating film, and a third step of providing a source region and a drain region in the semiconductor layer on both sides of the channel region, In the first step, the semiconductor layer has a thickness on at least one side on the source region side or the drain region side which is greater than a thickness of the semiconductor layer below a central portion of the gate electrode, and The boundary where the thickness is increased is provided so as to be located below the gate electrode.
[0029]
Further, in the method of manufacturing a thin film transistor according to claim 4, in the method of manufacturing a thin film transistor according to claim 3, the first step includes a step of providing a first semiconductor layer; Providing a mask layer having an opening; etching the first semiconductor layer in the opening by a thickness smaller than the total thickness of the first semiconductor layer; A step of oxidizing the layer to provide an insulating film; and a step of providing a second semiconductor layer over the first semiconductor layer and the insulating film.
[0030]
According to a fifth aspect of the present invention, in the method of manufacturing a thin film transistor according to the third aspect, the first step includes a step of providing an insulating film on the insulating substrate; The method is characterized by comprising a step of etching the insulating film on at least one side on the drain region side by a thickness smaller than the entire thickness of the insulating film, and a step of providing the semiconductor layer on the insulating film.
[0031]
The method of manufacturing a thin film transistor according to claim 6 includes a first step of providing a semiconductor layer on an insulating substrate, and a second step of providing a gate electrode on the semiconductor layer via a gate insulating film. A third step of providing a source region and a drain region in the semiconductor layer on both sides of the channel region; and providing at least one of the source region side and the drain region side with a conductivity type opposite to that of the source region and the drain region. And a fourth step of providing a conductive type impurity region.
[0032]
According to a seventh aspect of the present invention, there is provided a flat panel display device comprising: pixels arranged in a matrix on the insulating substrate; switching elements of the pixels; and a peripheral driving circuit integrally provided on the insulating substrate. In a display device, the switching element and the peripheral driving circuit are configured using the thin film transistor according to claim 1 or 2.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0034]
Embodiment 1
《TFT structure》
FIG. 1 is a schematic sectional view of the TFT according to the first embodiment of the present invention.
[0035]
1 is an insulating substrate, 2 is a base insulating film, 21 is an insulating film, 3 is a polysilicon layer, 34 is a first polysilicon layer, 35 is a second polysilicon layer, 31 is a channel region, and 32 is a source region. , 33 are drain regions, 4 is a gate insulating film, 41 and 42 are contact holes, 5 is a gate electrode, 6 is a source electrode, 7 is a drain electrode, 8 is an electron, T ₁ , T ₂ Is a thickness of the polysilicon layer 3 and B is a boundary where the thickness of the polysilicon layer 3 is increased.
[0036]
The TFT according to the first embodiment includes a polysilicon layer 3 which is a semiconductor layer provided on an insulating substrate 1, a gate electrode 5 provided on the polysilicon layer 3 via a gate insulating film 4, 5, a TFT having a channel region 31 provided in the semiconductor layer 3 below the semiconductor region 3 and a source region 32 and a drain region 33 provided in the polysilicon layer 3 on both sides of the channel region 31. 33, the thickness T of the polysilicon layer 3 on at least one side, here both sides. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker than that of the polysilicon layer 3 and is thicker, is located below the gate electrode 5.
[0037]
As described above, in the TFT of the first embodiment, the thickness T of the polysilicon layer 3 on the source region 32 side or the drain region 33 side. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker than the polysilicon layer 3 and has a larger thickness, is formed under the gate electrode 5, and the junction area between the channel region 31 and the source region 32 or the drain region 33 increases. The carrier is easy to escape. When the TFT is turned off from on and the current flowing through the channel region 31 is sufficiently turned off and a high electric field is generated near the junction between the channel region 31 and the source region 32 or the drain region 33, the channel region 31 Since almost no carriers are present, even if a high electric field is generated, almost no carriers pass therethrough, and thus almost no hot carriers are generated. Therefore, since the polysilicon layer 3 forming the channel region 31 is hardly damaged by hot carriers, the characteristics of the TFT hardly change even when the TFT is driven for a long time. As a result, a highly reliable TFT can be provided.
[0038]
《TFT manufacturing method》
Hereinafter, a method of manufacturing the TFT according to the first embodiment will be described with reference to FIG.
First, for example, SiO 2 is placed on an insulating substrate 1 such as a glass substrate. ₂ Is formed.
[0039]
Next, on the base insulating film 2, a first amorphous silicon film (not shown; see the first polysilicon layer 34) is formed in an island shape to form the first polysilicon layer 34.
[0040]
Next, a material that does not react with the underlying silicon layer or has an oxygen blocking effect, for example, Si ₃ N ₄ Forming a mask layer made of a nitride film, etc., etching a portion of the amorphous silicon film that is not covered by the mask layer, for example, a half thickness, and then oxidizing the etched portion of the amorphous silicon film, SiO ₂ The insulating film 21 made of is formed. After that, the mask layer is removed. At this time, it is preferable that the heights of the surfaces of the amorphous silicon film and the insulating film 21 are substantially equal. This can be achieved by optimizing process conditions such as the thickness of the amorphous silicon film to be etched and the oxidation time of the amorphous silicon film to be oxidized. For example, at least one surface of the amorphous silicon film and the insulating film 21 Can be mechanically polished to be planarized.
[0041]
Next, a second amorphous silicon layer is formed on the amorphous silicon thin film 3 and the insulating film 21 to form a second polysilicon layer 35 (not shown; see the second polysilicon layer 35). ). After that, the first amorphous silicon film and the second amorphous silicon film are changed into a first polysilicon layer 34 and a second polysilicon layer 35 by ELA (excimer laser annealing) irradiation. After that, the polysilicon layer 3 including the first polysilicon layer 34 and the second polysilicon layer 35 is processed into an island shape.
[0042]
Next, a gate insulating film 4 is formed thereon, and then a gate electrode 5 is formed. At this time, both ends of the gate electrode 5 in the gate width direction need to protrude outside the gate insulating film 4.
[0043]
Next, impurity doping is performed through the gate insulating film 4 using the gate electrode 5 as a mask to form a source region 32 and a drain region 33 on both sides of the channel region 31.
[0044]
Next, part of the gate insulating film 4 is dry-etched or wet-etched to form contact holes 41 and 42.
[0045]
Next, a source electrode 6 and a drain electrode 7 are formed. Subsequent processes, such as formation of an interlayer insulating film and formation of wiring, may be performed by the same method as in the related art.
[0046]
As described above, the TFT manufacturing method according to the first embodiment includes the first step of providing the polysilicon layer 3 on the insulating substrate 1 and the step of forming the gate on the polysilicon layer 3 with the gate insulating film 4 interposed therebetween. A second step of providing an electrode 5; and a third step of providing a source region 32 and a drain region 33 in the polysilicon layer 3 on both sides of the channel region 31. In the first step, the polysilicon The layer 3 has a thickness of at least one side on the source region 32 side or the drain region 33 side, here the thickness T on both sides. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker and thicker, is provided so as to be located below the gate electrode 5.
[0047]
The first step is a step of providing the first amorphous silicon layer as a first semiconductor layer, and a step of providing a mask layer (not shown) having an opening on the first amorphous silicon layer. Etching the first amorphous silicon layer in the opening by a thickness smaller than the total thickness of the first amorphous silicon layer; and oxidizing the first amorphous silicon layer in the etched portion. It is characterized by comprising a step of providing an insulating film 21 and a step of providing the second amorphous silicon layer on the first amorphous silicon layer and the insulating film 21.
[0048]
According to the method of manufacturing the TFT of the first embodiment having such a configuration, the TFT of the first embodiment shown in FIG. 1 can be easily manufactured using a simple process.
[0049]
Embodiment 2
《TFT structure》
FIG. 2 is a schematic sectional view of a TFT according to the second embodiment of the present invention.
[0050]
1 is an insulating substrate, 2 is a base insulating film, 3 is a polysilicon layer, 31 is a channel region, 32 is a source region, 33 is a drain region, 4 is a gate insulating film, 41 and 42 are contact holes, 5 is a gate electrode. , 6 is a source electrode, 7 is a drain electrode, and 8 is an electron.
[0051]
The TFT according to the second embodiment includes a polysilicon layer 3 which is a semiconductor layer provided on an insulating substrate 1, a gate electrode 5 provided on the polysilicon layer 3 via a gate insulating film 4, 5, a TFT having a channel region 31 provided in the semiconductor layer 3 below the semiconductor region 3 and a source region 32 and a drain region 33 provided in the polysilicon layer 3 on both sides of the channel region 31. 33, the thickness T of the polysilicon layer 3 on at least one side, here both sides. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker than that of the polysilicon layer 3 and is thicker, is located below the gate electrode 5.
[0052]
As described above, in the TFT according to the second embodiment, the thickness T of the polysilicon layer 3 on the source region 32 side or the drain region 33 side. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker than the polysilicon layer 3 and has a larger thickness, is formed under the gate electrode 5, and the junction area between the channel region 31 and the source region 32 or the drain region 33 increases. The carrier is easy to escape. When the TFT is turned off from on and the current flowing through the channel region 31 is sufficiently turned off and a high electric field is generated near the junction between the channel region 31 and the source region 32 or the drain region 33, the channel region 31 Since almost no carriers are present, even if a high electric field is generated, almost no carriers pass therethrough, and thus almost no hot carriers are generated. Therefore, since the polysilicon layer 3 forming the channel region 31 is hardly damaged by hot carriers, the characteristics of the TFT hardly change even when the TFT is driven for a long time. As a result, a highly reliable TFT can be provided.
[0053]
《TFT manufacturing method》
Hereinafter, a method of manufacturing the TFT according to the second embodiment will be described with reference to FIG.
First, a base insulating film 2 is formed on an insulating substrate 1.
[0054]
Next, a part of the base insulating film 2 (a part corresponding to a part where the polysilicon layer 3 is formed thick) is removed by etching.
[0055]
Next, an amorphous silicon layer is deposited on the portion removed by the previous etching to form the polysilicon layer 3. Here, when the surface flatness of the amorphous silicon layer is not good, the surface is flattened using, for example, a method such as mechanical polishing.
[0056]
Next, the amorphous silicon layer is changed to the polysilicon layer 3 by ELA irradiation.
[0057]
Next, a gate insulating film 6 is deposited on the polysilicon layer 3, and subsequently, a gate electrode 5 is formed. At this time, both ends of the gate electrode 5 in the gate width direction need to protrude from both ends of the protruding portion of the insulating layer 2.
[0058]
Next, impurity doping is performed using the gate electrode 5 as a mask to form a source region 32 and a drain region 33 on both sides of the channel region 31.
[0059]
Next, part of the gate insulating film 4 is dry-etched or wet-etched to form contact holes 41 and 42.
[0060]
Next, a source electrode 6 and a drain electrode 7 are formed. Subsequent processes, such as formation of an interlayer insulating film and formation of wiring, may be performed by the same method as in the related art.
[0061]
As described above, the manufacturing method of the TFT according to the second embodiment includes the first step of providing the polysilicon layer 3 on the insulating substrate 1 and the step of forming the gate on the polysilicon layer 3 with the gate insulating film 4 interposed therebetween. A second step of providing an electrode 5; and a third step of providing a source region 32 and a drain region 33 in the polysilicon layer 3 on both sides of the channel region 31. In the first step, the polysilicon The layer 3 has a thickness of at least one side on the source region 32 side or the drain region 33 side, here the thickness T on both sides. ₁ Is the thickness T of the polysilicon layer 3 below the central portion of the gate electrode 5. ₂ The boundary B, which is thicker and thicker, is provided so as to be located below the gate electrode 5.
[0062]
Further, the first step includes a step of providing the insulating film 2 on the insulating substrate 1 and a step of forming at least one side, here both sides of the insulating film 2 on the source region 32 side or the drain region 33 side. It is characterized by comprising a step of etching by a thickness smaller than the entire thickness and a step of providing a polysilicon layer 3 on the insulating film 2.
[0063]
According to the method of manufacturing the TFT of the second embodiment having such a configuration, the TFT of the second embodiment shown in FIG. 2 can be easily manufactured by using a simple process.
[0064]
Embodiment 3
《TFT structure》
FIG. 3A is a schematic cross-sectional view of the TFT according to the third embodiment of the present invention (cross-sectional view taken along the line AA in FIG. 3D), and FIG. FIG. 3D is a schematic cross-sectional view (cross-sectional view taken along the line BB in FIG. 3D), FIG. 3C is a schematic plan view in the middle of the manufacturing process of the TFT of the first embodiment, and FIG. FIG. 3 is a schematic plan view of a TFT.
[0065]
1 is an insulating substrate, 2 is a base insulating film, 3 is a polysilicon layer, 31 is a channel region, 32 is a source region, 33 is a drain region, 4 is a gate insulating film, 41 and 42 are contact holes, 5 is a gate electrode. , 6 are source electrodes, 7 is a drain electrode, 8 is electrons, and 10 is a p-type impurity region.
[0066]
The TFT according to the third embodiment includes a polysilicon layer 3 provided on an insulating substrate 1, a gate electrode 5 provided on the polysilicon layer 3 via a gate insulating film 4, and a gate electrode 5 on both sides of a channel region 31. In the TFT having the source region 32 and the drain region 33 provided in the polysilicon layer 3, at least one side of the source region 32 side or the drain region 33 side, here, the n-type source region 32 And a p-type impurity region 30 of a conductivity type opposite to the conductivity type of the n-type drain region is provided.
[0067]
As described above, in the TFT according to the third embodiment, the carriers disappear by recombination near the junction surface between the p-type impurity region 30 and the channel region 31 under the gate electrode 5, so that the carriers are relatively easy to escape. Become. When the TFT is turned off from on and the current flowing through the channel region 31 is sufficiently turned off and a high electric field is generated near the junction between the channel region 31 and the source region 32 or the drain region 33, the channel region 31 Since almost no carriers are present, even if a high electric field is generated, almost no carriers pass therethrough, and thus almost no hot carriers are generated. Therefore, since the polysilicon layer 3 forming the channel region 31 is hardly damaged by hot carriers, the characteristics of the TFT hardly change even when the TFT is driven for a long time. As a result, a highly reliable TFT can be provided.
[0068]
《TFT manufacturing method》
Hereinafter, a method of manufacturing the TFT according to the third embodiment will be described with reference to FIG.
First, a base insulating film 2 is formed on an insulating substrate 1.
[0069]
Next, an amorphous silicon layer is deposited on a part of the insulating film 2 to form the polysilicon layer 3. After that, the amorphous silicon layer is changed to a polysilicon layer 3 by ELA irradiation. After that, the polysilicon layer 3 is processed into an island shape, a gate insulating film 4 is formed thereon, and then a gate electrode 5 is formed.
[0070]
Next, a p-type impurity is implanted later on a part of the gate electrode 5 and a part of the gate insulating film 4 to form a resist film 36 on a region where the p-type impurity region 30 is to be formed. Then, using the gate electrode 5 and the resist film 36 as a mask, n-type impurity doping is performed to form a source region 32 and a drain region 33 on both sides of the channel region 31.
[0071]
Next, after removing the resist film 36, a p-type impurity is implanted, and a resist film (not shown) is applied except for a region where the p-type impurity region 30 is to be formed, and the resist film is used as a mask. A p-type impurity is implanted to form a p-type impurity region 30, and then the resist film is removed.
[0072]
Next, part of the gate insulating film 4 is dry-etched or wet-etched to form contact holes 41 and 42.
[0073]
Next, a source electrode 6 and a drain electrode 7 are formed. Subsequent processes, such as formation of an interlayer insulating film and formation of wiring, may be performed by the same method as in the related art.
[0074]
As described above, the TFT manufacturing method according to the third embodiment includes the first step of providing the polysilicon layer 3 on the insulating substrate 1 and the step of forming the gate on the polysilicon layer 3 with the gate insulating film 4 interposed therebetween. A second step of providing the electrode 5, a third step of providing the source region 32 and the drain region 33 in the polysilicon layer 3 on both sides of the channel region 31, and at least one side of the source region 32 or the drain region 33 side The fourth step is to provide a p-type impurity region 30 having a conductivity type opposite to that of the source region 32 and the drain region 33 on both sides.
[0075]
According to the TFT manufacturing method of the third embodiment having such a configuration, the TFT of the third embodiment shown in FIG. 3 can be easily manufactured by using a simple process.
[0076]
In the third embodiment, one p-type impurity region 30 is provided in each of the source region 32 and the drain region 33 as shown in FIG. It may be provided on at least one side of the region 33 side. However, when the p-type impurity region 30 is provided at one position, it is preferable to provide the p-type impurity region 30 on the drain side in consideration of the operating conditions of the TFT. Further, for example, as shown in FIG. 7, a boundary B of the p-type impurity ₂ May be provided below the gate electrode 5.
[0077]
Although not shown, in a flat display device having pixels arranged in a matrix on the insulating substrate 1, switching elements of the pixels, and a peripheral driving circuit integrally provided on the insulating substrate 1, When the switching element and the peripheral driving circuit are configured using the TFTs of Embodiments 1 to 3, not only the TFT is used as the pixel switching element, but also the peripheral driving circuit is integrated on the same substrate as the pixel switching element. Thus, a low-cost, high-performance flat display device can be provided.
[0078]
Although the present invention has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.
[0079]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress the semiconductor layer forming the channel layer of the TFT from being damaged by hot carriers, and it is possible to obtain a highly reliable semiconductor device in which characteristics do not easily change even when driven for a long time. TFT having properties, a manufacturing method thereof, and a flat display device can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a structure of a TFT according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view showing a structure of a TFT according to a second embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view and a plan view illustrating a structure of a TFT according to a third embodiment of the present invention.
FIG. 4 is a schematic sectional view for explaining the principle of the present invention.
FIG. 5 is a schematic plan view and a sectional view for explaining the principle of the present invention.
FIG. 6 is a schematic plan view for explaining the principle of the present invention.
FIG. 7 is a schematic plan view showing another structure of the TFT according to the third embodiment of the present invention.
[Explanation of symbols]
1 .... insulating substrate
2. Base insulating film
3 ... Polysilicon layer
4: Gate insulating film
5 ... Gate electrode
6 ... Source electrode
7 ... Drain electrode
8 ... Electronics
21 ... Insulating film
30 ... p-type impurity region
31 ... Channel area
32: Source area
33 ... Drain region
34 first polysilicon layer
35 ... second polysilicon layer
36 ... Resist film
41, 42 ... contact hole
T ₁ , T ₂ … Polysilicon layer thickness
B: boundary where the thickness of the polysilicon layer becomes thicker

Claims (7)

A semiconductor layer provided on an insulating substrate,
A gate electrode provided on the semiconductor layer via a gate insulating film;
A channel region provided in the semiconductor layer below the gate electrode;
In a thin film transistor having a source region and a drain region provided in the semiconductor layer on both sides of the channel region,
The thickness of the semiconductor layer on at least one side of the source region side or the drain region side is thicker than the thickness of the semiconductor layer below a central portion of the gate electrode,
A thin film transistor, wherein the boundary where the thickness of the semiconductor layer is increased is located below the gate electrode. A semiconductor layer provided on an insulating substrate,
A gate electrode provided on the semiconductor layer via a gate insulating film;
A channel region provided in the semiconductor layer below the gate electrode;
In a thin film transistor having a source region and a drain region provided in the semiconductor layer on both sides of the channel region,
A thin film transistor, wherein an impurity region of a conductivity type opposite to a conductivity type of the source region and the drain region is provided in at least one of the semiconductor layers on the source region side or the drain region side. A first step of providing a semiconductor layer on an insulating substrate;
A second step of providing a gate electrode on the semiconductor layer via a gate insulating film, and a third step of providing a source region and a drain region in the semiconductor layer on both sides of the channel region;
In the first step, the semiconductor layer includes:
The thickness of at least one side of the source region side or the drain region side is larger than the thickness of the semiconductor layer below the center of the gate electrode, and the boundary where the thickness becomes thicker is below the gate electrode. A method for manufacturing a thin film transistor. The first step includes:
Providing a first semiconductor layer;
Providing a mask layer having an opening on the first semiconductor layer;
Etching the first semiconductor layer in the opening by a thickness smaller than the total thickness of the first semiconductor layer;
A step of oxidizing the etched portion of the first semiconductor layer to provide an insulating film; and a step of providing a second semiconductor layer on the first semiconductor layer and the insulating film. The method for manufacturing a thin film transistor according to claim 3. The first step includes:
Providing an insulating film on the insulating substrate;
Etching the insulating film on at least one side of the source region side or the drain region side by a thickness smaller than the total thickness of the insulating film;
4. The method according to claim 3, further comprising the step of providing the semiconductor layer on the insulating film. A first step of providing a semiconductor layer on an insulating substrate;
A second step of providing a gate electrode on the semiconductor layer via a gate insulating film, and a third step of providing a source region and a drain region in the semiconductor layer on both sides of the channel region;
A fourth step of providing an impurity region of a conductivity type opposite to that of the source region and the drain region on at least one of the source region side and the drain region side. In a flat display device having pixels arranged in a matrix on the insulating substrate and switching elements of the pixels, and a peripheral driving circuit integrally provided on the insulating substrate,
A flat display device, wherein at least one of the switching element and the peripheral drive circuit is configured using the thin film transistor according to claim 1.

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