JP2004199677A - キャッシュを動作させるためのシステム及び方法 - Google Patents

キャッシュを動作させるためのシステム及び方法 Download PDF

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Publication number
JP2004199677A
JP2004199677A JP2003415025A JP2003415025A JP2004199677A JP 2004199677 A JP2004199677 A JP 2004199677A JP 2003415025 A JP2003415025 A JP 2003415025A JP 2003415025 A JP2003415025 A JP 2003415025A JP 2004199677 A JP2004199677 A JP 2004199677A
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JP
Japan
Prior art keywords
information
cache
tag
tag memory
memory
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Pending
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JP2003415025A
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English (en)
Japanese (ja)
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JP2004199677A5 (enExample
Inventor
Robert F Krick
ロバート・エフ・クリック
Duane A Wiens
デュアン・エイ・ウィーンズ
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Hewlett Packard Development Co LP
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Hewlett Packard Development Co LP
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Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of JP2004199677A publication Critical patent/JP2004199677A/ja
Publication of JP2004199677A5 publication Critical patent/JP2004199677A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2003415025A 2002-12-13 2003-12-12 キャッシュを動作させるためのシステム及び方法 Pending JP2004199677A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/319,205 US6950906B2 (en) 2002-12-13 2002-12-13 System for and method of operating a cache

Publications (2)

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JP2004199677A true JP2004199677A (ja) 2004-07-15
JP2004199677A5 JP2004199677A5 (enExample) 2006-11-16

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ID=32506599

Family Applications (1)

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JP2003415025A Pending JP2004199677A (ja) 2002-12-13 2003-12-12 キャッシュを動作させるためのシステム及び方法

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US (1) US6950906B2 (enExample)
JP (1) JP2004199677A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10037278B2 (en) 2015-08-17 2018-07-31 Fujitsu Limited Operation processing device having hierarchical cache memory and method for controlling operation processing device having hierarchical cache memory

Families Citing this family (14)

* Cited by examiner, † Cited by third party
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US20040250027A1 (en) * 2003-06-04 2004-12-09 Heflinger Kenneth A. Method and system for comparing multiple bytes of data to stored string segments
EP1717708B1 (en) * 2005-04-29 2010-09-01 STMicroelectronics Srl An improved cache memory system
US7581068B2 (en) * 2006-06-29 2009-08-25 Intel Corporation Exclusive ownership snoop filter
JP5011885B2 (ja) * 2006-08-18 2012-08-29 富士通株式会社 スヌープタグの制御装置
US7840874B2 (en) * 2006-12-27 2010-11-23 Mips Technologies, Inc. Speculative cache tag evaluation
JP4388557B2 (ja) * 2007-01-11 2009-12-24 株式会社日立製作所 画像処理システム
US9251069B2 (en) * 2012-12-21 2016-02-02 Advanced Micro Devices, Inc. Mechanisms to bound the presence of cache blocks with specific properties in caches
JP6432450B2 (ja) * 2015-06-04 2018-12-05 富士通株式会社 並列計算装置、コンパイル装置、並列処理方法、コンパイル方法、並列処理プログラムおよびコンパイルプログラム
US11010165B2 (en) 2019-03-12 2021-05-18 Marvell Asia Pte, Ltd. Buffer allocation with memory-based configuration
US11093405B1 (en) 2019-05-29 2021-08-17 Marvell Asia Pte, Ltd. Shared mid-level data cache
US11036643B1 (en) 2019-05-29 2021-06-15 Marvell Asia Pte, Ltd. Mid-level instruction cache
US11327890B1 (en) 2019-05-29 2022-05-10 Marvell Asia Pte, Ltd. Partitioning in a processor cache
US11513958B1 (en) 2019-05-29 2022-11-29 Marvell Asia Pte, Ltd. Shared mid-level data cache
US11379368B1 (en) 2019-12-05 2022-07-05 Marvell Asia Pte, Ltd. External way allocation circuitry for processor cores

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224042A (ja) * 1988-10-28 1990-09-06 Apollo Computer Inc キャッシュデータアクセス方法及び装置
JPH05282203A (ja) * 1992-01-31 1993-10-29 Motorola Inc キャッシュ・コントローラ
JPH06318178A (ja) * 1992-05-18 1994-11-15 Sun Microsyst Inc キャッシュタグメモリ用キャッシュタグ制御装置及び制御方法
JPH08153039A (ja) * 1994-11-30 1996-06-11 Hitachi Ltd 半導体メモリ装置、及び、それを用いた情報処理装置

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Publication number Priority date Publication date Assignee Title
US118801A (en) * 1871-09-12 Improvement in head-blocks for saw-mills
US853738A (en) * 1905-06-26 1907-05-14 Edwin Ruud Storage water-heater.
US852951A (en) * 1906-04-25 1907-05-07 August A Harnischfeger Suspension-clamp for bacon.
JPH06318174A (ja) * 1992-04-29 1994-11-15 Sun Microsyst Inc キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法
KR960006484B1 (ko) * 1992-09-24 1996-05-16 마쯔시다 덴기 산교 가부시끼가이샤 캐쉬메모리장치
US5835929A (en) * 1996-05-20 1998-11-10 Integrated Device Technology, Inc. Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of a line fill
US6289420B1 (en) * 1999-05-06 2001-09-11 Sun Microsystems, Inc. System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem
US6385696B1 (en) * 1999-06-25 2002-05-07 Intel Corporation Embedded cache with way size bigger than page size

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224042A (ja) * 1988-10-28 1990-09-06 Apollo Computer Inc キャッシュデータアクセス方法及び装置
JPH05282203A (ja) * 1992-01-31 1993-10-29 Motorola Inc キャッシュ・コントローラ
JPH06318178A (ja) * 1992-05-18 1994-11-15 Sun Microsyst Inc キャッシュタグメモリ用キャッシュタグ制御装置及び制御方法
JPH08153039A (ja) * 1994-11-30 1996-06-11 Hitachi Ltd 半導体メモリ装置、及び、それを用いた情報処理装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10037278B2 (en) 2015-08-17 2018-07-31 Fujitsu Limited Operation processing device having hierarchical cache memory and method for controlling operation processing device having hierarchical cache memory

Also Published As

Publication number Publication date
US6950906B2 (en) 2005-09-27
US20040117558A1 (en) 2004-06-17

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