JP2004063996A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2004063996A
JP2004063996A JP2002223484A JP2002223484A JP2004063996A JP 2004063996 A JP2004063996 A JP 2004063996A JP 2002223484 A JP2002223484 A JP 2002223484A JP 2002223484 A JP2002223484 A JP 2002223484A JP 2004063996 A JP2004063996 A JP 2004063996A
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Japan
Prior art keywords
wiring
semiconductor device
insulating film
conductive film
manufacturing
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JP2002223484A
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Japanese (ja)
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JP2004063996A5 (enExample
Inventor
Muneyuki Matsumoto
宗之 松本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002223484A priority Critical patent/JP2004063996A/ja
Publication of JP2004063996A publication Critical patent/JP2004063996A/ja
Publication of JP2004063996A5 publication Critical patent/JP2004063996A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05006—Dual damascene structure
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01073—Tantalum [Ta]
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    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002223484A 2002-07-31 2002-07-31 半導体装置及びその製造方法 Pending JP2004063996A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002223484A JP2004063996A (ja) 2002-07-31 2002-07-31 半導体装置及びその製造方法

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JP2002223484A JP2004063996A (ja) 2002-07-31 2002-07-31 半導体装置及びその製造方法

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JP2004063996A true JP2004063996A (ja) 2004-02-26
JP2004063996A5 JP2004063996A5 (enExample) 2005-10-20

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842614B2 (en) 2007-01-04 2010-11-30 Fujitsu Limited Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device
CN108511350A (zh) * 2018-05-14 2018-09-07 深圳市欧科力科技有限公司 一种功率器件的封装方法及功率器件
CN108520871A (zh) * 2018-04-20 2018-09-11 北京智芯微电子科技有限公司 晶圆级芯片中的嵌入式焊盘及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140564A (ja) * 1997-07-18 1999-02-12 Nec Corp 半導体装置およびその製造方法
JPH11251321A (ja) * 1998-01-05 1999-09-17 Texas Instr Inc <Ti> 集積回路内の電子部品間の導通パス製作方法および集積回路
JP2000340569A (ja) * 1999-03-19 2000-12-08 Toshiba Corp 半導体装置の配線構造及びその形成方法
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP2002198491A (ja) * 2000-12-27 2002-07-12 Toshiba Corp 半導体装置
JP2002368085A (ja) * 2001-06-12 2002-12-20 Oki Electric Ind Co Ltd 半導体素子およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140564A (ja) * 1997-07-18 1999-02-12 Nec Corp 半導体装置およびその製造方法
JPH11251321A (ja) * 1998-01-05 1999-09-17 Texas Instr Inc <Ti> 集積回路内の電子部品間の導通パス製作方法および集積回路
JP2000340569A (ja) * 1999-03-19 2000-12-08 Toshiba Corp 半導体装置の配線構造及びその形成方法
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP2002198491A (ja) * 2000-12-27 2002-07-12 Toshiba Corp 半導体装置
JP2002368085A (ja) * 2001-06-12 2002-12-20 Oki Electric Ind Co Ltd 半導体素子およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842614B2 (en) 2007-01-04 2010-11-30 Fujitsu Limited Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device
CN108520871A (zh) * 2018-04-20 2018-09-11 北京智芯微电子科技有限公司 晶圆级芯片中的嵌入式焊盘及其制作方法
CN108511350A (zh) * 2018-05-14 2018-09-07 深圳市欧科力科技有限公司 一种功率器件的封装方法及功率器件
CN108511350B (zh) * 2018-05-14 2020-09-01 南京溧水高新创业投资管理有限公司 一种功率器件的封装方法及功率器件

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