JP2004046201A - Driving circuit, electrooptic device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device for a liquid crystal display device which can surely prevent deterioration in display quality such as ghosts with simple constitution even when an image signal is written in the line sequence of data lines. <P>SOLUTION: A buffer circuit 402 comprising a selecting circuit 403 composed of a 3-input NAND circuit and an inverter is provided between each output stage of a shift register 401 and a sampling circuit 301, and an output signal line of each output stage of the shift register, an output signal line of an output stage adjacent to the output stage, and an enable signal ENB outputted from an image control means are connected to an input terminal of the 3-input NAND circuit. Then this enable signal ENB is a signal which is common to all 3-input NAND circuits, the output timing is within a period output signals of adjacent output stage overlap, and the pulse width is narrower than the period. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit of an electro-optical device of an active matrix driving system by driving a thin film transistor (hereinafter, appropriately referred to as TFT), an electro-optical device including the driving circuit, and an electro-optical device provided with the driving circuit on a substrate. The present invention belongs to the technical field of a device or an electronic device using the electro-optical device, and particularly to the technical field of a drive circuit including a sampling circuit, an electro-optical device, and an electronic device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a liquid crystal device of an active matrix driving system by TFT driving, a large number of scanning lines and data lines arranged vertically and horizontally and a large number of pixel electrodes corresponding to respective intersections of the scanning lines and data lines are formed on a TFT array substrate. It is provided in. In addition, in addition to these, various peripheral circuits including a TFT as a component, such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit, may be provided on such a TFT array substrate.
[0003]
The scan line drive circuit and the data line drive circuit each include a shift register, and a drive signal for writing an image signal or a scan signal for each data line or scan line is provided by the scan line drive circuit and the drive signal. It is configured to sequentially output from each output stage of the data line drive circuit.
[0004]
FIG. 22 shows an example of a conventional data line drive circuit. In the circuit shown in FIG. 22, a shift register 401 'is constituted by a clocked inverter circuit and an inverter, and output signals Q1 to Qn are sequentially transferred from each output stage of the shift register 401' as shown in FIG. Is output. Therefore, by controlling the conduction timing of the switching elements SH1 to SHn of the sampling circuit 301 using the output signals Q1 to Qn, the write timing of the image signal VID supplied to the image signal line 304 to each data line can be scanned. This can be synchronized with the timing of writing a signal to a scanning line.
[0005]
However, the pulse width of these output signals Q1 to Qn is equal to the pulse width of start signal SPX as shown in FIG. 23, and transfer of output signals Q1 to Qn is performed by clock signal CLX and inverted clock signal CLX of the clock signal. _INV 23, the output signals (Q1 and Q2, Q2 and Q3, etc.) from adjacent output stages overlap during a period corresponding to a half cycle of the clock signal CLX as shown in FIG. Become. Therefore, when the output signals Q1 to Qn are supplied as they are to the switching elements SH1 to SHn of the sampling circuit 301, the adjacent switching elements SH1 to SHn are simultaneously turned on during the overlapping period, and a ghost of the image signal occurs on the data line. Would.
[0006]
Therefore, conventionally, a selection circuit 403 'as shown in FIG. 22 is provided. The selection circuit 403 ′ includes a two-input NAND circuit 500, and an output signal of an adjacent output stage of the shift register 401 ′ is input to an input terminal of the two-input NAND circuit 500. As a result of this configuration, as shown in the timing chart of FIG. 23, the output signals Q1 to Qn are output from the output signals (Q1 and Q2, Q2 and Q3 to Qn-1 of the output stage adjacent to the shift register 401 '). Qn) is selected only during the period when both are at the high level, and supplied to the switching elements SH1 to SHn of the sampling circuit 301 as the sampling circuit drive signals S1 to Sn. Images can be displayed.
[0007]
[Problems to be solved by the invention]
However, in such a conventional configuration, when a delay occurs in the output signals Q1 to Qn of the shift register 401 ′, the sampling circuit drive signals S1 to Sn, which are the output signals of the buffer circuit 402 ′, are as shown by dotted lines in FIG. For example, the first-stage sampling circuit drive signal S1 and the second-stage sampling circuit drive signal S2 overlap in a period indicated by T1 in FIG.
[0008]
When such duplication occurs, for example, as shown in FIG. 24, the image signal to be written to the fifth data line is also written to the sixth data line, and then the image signal is written to the next data line one by one. Therefore, there is a problem that a ghost image is generated as shown by oblique lines in FIG.
[0009]
Particularly, when an image signal output as a serial signal is phase-expanded into a parallel image signal, a plurality of previous image signals are written, so that a ghost image occurs more remarkably in a wider area. Become. For example, in a display mode such as XGA or EWS, the dot frequency becomes high, and if the phase expansion of the image signal is not performed, as shown in FIG. 25, the high level of the sampling circuit drive signals S1, S2, S3,. Cannot be sufficiently secured, and it becomes impossible to write a sufficient image signal to each data line. Therefore, conventionally, as shown in FIG. 26, for example, each of parallel image signals VID1 to VID6 expanded into six phases is connected to a sampling circuit 301, and one buffer circuit 402 'and a plurality of adjacent The switching element of the sampling circuit 301 to be connected is connected, and a plurality of switching elements are turned on at a time. With this configuration, as shown in FIG. 27, a high-level period of the sampling circuit drive signals S1 to Sm can be sufficiently secured, and a favorable display can be performed.
[0010]
However, even in such a configuration, as shown in FIG. 27, when the transistor characteristics of the NAND circuit 500 and the buffer circuit 402 ′ are deteriorated, or when the output signal of the shift register 401 ′ is delayed. 27, the sampling circuit drive signals S1 to Sm are delayed, and in the period indicated by T2 in FIG. 27, the conduction periods of the switching elements SH1 to SHm overlap. In the period T2 shown in FIG. 27, the sampling circuit drive signals S1 to S6 that make the switching elements SH1 to SH6 of the sampling circuit 301 conductive are high in order to write an image signal to the first to sixth data lines. And at the same time, the sampling circuit drive signals S7 to S12 that make the switching elements SH7 to SH12 conductive to write image signals to the seventh to twelfth data lines become high level signals. I have. Accordingly, for example, the image signal for the fifth data line is VID5, and this VID5 is supplied not only to the switching element SH5 but also to the switching element SH11 for the sixth data line. The image signal VID6 for the sixth data line is supplied not only to the switching element SH6, but also to the switching element S12 for the sixth data line. As a result, as shown in FIG. 28, the image signals for the fifth to tenth data lines are written to the eleventh to sixteenth data lines, and a ghost image as indicated by oblique lines occurs.
[0011]
The occurrence of such a ghost image becomes more remarkable as the number of switching elements of the sampling circuit driven at a time is larger. For example, as shown in FIG. In the case of a configuration in which the elements are driven at the same time, as shown in FIG. 30, the image signals written to the first to twelfth data lines are written to the thirteenth to twenty-fourth data lines after twelve. As a result, a ghost image as indicated by oblique lines is generated.
[0012]
When a ghost image occurs, the contrast of the image decreases, and a clear image cannot be displayed. In particular, when a moving image is displayed, the ghost image moves and is displayed following the original image, so that the image becomes extremely hard to see. In addition, when performing gradation display, it is necessary to set the voltage value to be written to a value corresponding to the gradation level, not only to simply turn on / off the writing of the image signal to the pixel. The value cannot be obtained, and accurate gradation display cannot be performed. In addition, even when the resolution of a display image is increased by miniaturization of pixels or the like, when a ghost image as described above occurs, the definition of the image is substantially lost and the display quality is deteriorated. Become.
[0013]
In order to remove the ghost image, the output signals Q1 to Qn of the shift register 401 need only be shifted by one period of the CLX of the clock signal so that the overlapping period of the output signals Q1 to Qn can be eliminated. However, in order to shift the output signals Q1 to Qn by one cycle of the clock signal CLX, it is necessary to use a shift register having an extremely complicated configuration, which increases the cost and the size of the liquid crystal device based on an increase in the area occupied by the shift register. This leads to problems such as
[0014]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides an electro-optical device that can reliably prevent deterioration of display quality such as ghosts with a simple configuration even when image signals are written line-by-line with data lines. It is an object to provide a driving circuit, an electro-optical device, and an electronic device.
[0015]
[Means for Solving the Problems]
2. The driving circuit for an electro-optical device according to claim 1, wherein: a plurality of data lines to which an image signal is supplied; a plurality of scanning lines to which a scanning signal is supplied; A driving circuit for an electro-optical device, comprising: a switching circuit connected to each of the scanning lines; a sampling circuit that samples the image signal and supplies the data signal to the data line; and supplies a driving signal to the sampling circuit. And a selector provided corresponding to each output stage of the shift register and controlling a selection period of the drive signal to the sampling circuit, wherein each of the selectors is A three-input logic in which an output of one output stage, an output of an output stage adjacent to one output stage, and an output from a control signal line common to each selection means are supplied to input terminals. Characterized by comprising the road.
[0016]
According to the driving circuit of the electro-optical device according to the first aspect, when the writing period of the image signal in one horizontal scanning period ends and a transfer start signal is input to the shift register, the drive circuit is configured based on the transfer start signal. Drive signals are generated and output from each output stage of the shift register and output as input signals in the next stage of the shift register. Similarly, a drive signal is generated in the next stage, output as a drive signal in this stage, and further output as an input signal in the next stage.
[0017]
Hereinafter, similarly, the drive signals are sequentially output by the respective stages of the shift register and output as the output signals of the respective stages, and are provided in the sampling circuits corresponding to the respective data lines in correspondence with the respective output stages. Supplied via the selection means.
[0018]
Each of the selection means includes an output terminal of one output stage of the corresponding shift register, an output of one output stage adjacent to the one output stage, and an output of a control signal line output from the outside at an input terminal. The period during which the signals are supplied and each signal is valid is selected as the valid period of the drive signal. Further, the control signal line is connected as a control signal line common to each selection unit. Therefore, even when the switching characteristic of each output stage of the shift register is deteriorated and the signal to be transferred is delayed, the effective period of the drive signal can be forcibly determined by the control signal from the outside. It is possible to prevent the driving signals from being overlapped between adjacent sampling circuits, and to reliably prevent deterioration of display quality such as a ghost phenomenon.
[0019]
That is, the sampling circuit is non-overlapping and is made conductive by the drive signal set for a sufficiently long period, and supplies the image signal supplied from the supply line of the image signal line-sequentially to each data line. , Image signals are written.
[0020]
According to a second aspect of the present invention, there is provided a drive circuit for an electro-optical device according to the first aspect, wherein the selection unit includes a three-input NAND circuit at each stage. Means.
[0021]
According to the drive circuit of the electro-optical device according to claim 2, each of the three-input NAND circuits has an output of one output stage of the shift register and an output of one output stage adjacent to the one output stage. , And an output of a control signal line output from the outside. Therefore, only when each signal becomes valid with a positive polarity, the output of the negative polarity is performed, and the adjustment of the valid period can be performed by a control signal input through the control signal line. .
[0022]
According to a third aspect of the present invention, in the driving circuit for an electro-optical device according to the first aspect, the selection unit includes a three-input OR circuit in each stage. Means.
[0023]
According to the driving circuit of the electro-optical device according to claim 3, each of the three-input OR circuits includes an output of one output stage of the shift register and an output of one output stage adjacent to the one output stage. , And an output from a control signal line output from the outside. Therefore, only when each signal becomes valid with a negative polarity, a negative polarity output is performed, and the validity period can be adjusted by a control signal input through the control signal line. .
[0024]
According to a fourth aspect of the present invention, in the electro-optical device driving circuit according to any one of the first to third aspects, the shift register includes: It is a bidirectional shift register further provided with a transfer direction control unit for limiting a signal transfer direction to a predetermined direction based on a direction control signal supplied from the outside.
[0025]
According to the drive circuit of the electro-optical device, when a direction control signal for determining a signal transfer direction is externally supplied to the shift register, the shift register transfers the signal. The transfer direction is limited by the direction control unit to a predetermined direction based on the direction control signal. Therefore, the output signal to be supplied to the selection means is appropriately transferred in a desired direction, and a reverse display without a ghost image is enabled.
[0026]
The drive circuit of the electro-optical device according to claim 5, in order to solve the problem, in the drive circuit of the electro-optical device according to any one of claims 1 to 4, wherein the sampling circuit includes: The image forming apparatus is connected to a supply line of an image signal output in a phase-expanded manner, and the selection unit is connected to supply the drive signal to a plurality of stages of the sampling circuit at a time. I do.
[0027]
According to the drive circuit of the electro-optical device according to the fifth aspect, the image signal is phase-expanded and output by an external control unit and supplied to a sampling circuit. On the other hand, the driving signal of the sampling circuit is supplied to the plurality of stages of the sampling circuit at once by the selection means. Therefore, even when the dot frequency is high, a sufficient sampling period is ensured, and an appropriate valid period is selected by the control signal input via the control signal line, so that a ghost image is not generated.
[0028]
According to a sixth aspect of the present invention, in order to solve the above-described problem, the electro-optical device according to any one of the first to fifth aspects has a drive circuit for reversing an optical characteristic by an electric signal. Image display means provided with an electro-optical member for changing the image quality in the pixel portion.
[0029]
According to the electro-optical device of the sixth aspect, the driving circuit of the electro-optical device according to any one of the first to fifth aspects, and an electro-optical device that reversibly changes an optical characteristic by an electric signal. Since the image display means including the member in the pixel portion is provided, a sufficient sampling period is secured, and an appropriate valid period is selected by a control signal input through the control line, and a ghost The present invention provides a small-sized electro-optical device capable of displaying a good image without a defect.
[0030]
According to a seventh aspect of the invention, there is provided an electronic apparatus including the electro-optical device according to the sixth aspect, in order to solve the above problem.
[0031]
According to the electronic device of the present invention, the electronic device includes the above-described electro-optical device of the present invention, and a sufficient sampling period is ensured, and the control input through the control signal line is performed. An appropriate valid period is selected by a signal, and a high-quality image is displayed by an electro-optical device capable of displaying a good image without ghost. Further, since the size of the electro-optical device can be reduced, the size of the electronic device can be reduced.
[0032]
The operation and other advantages of the present invention will become more apparent from the embodiments explained below.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0034]
(Configuration of electro-optical device)
A liquid crystal device as an example of the electro-optical device will be described.
[0035]
First, the overall configuration of the liquid crystal device will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of various wirings, peripheral circuits, and the like provided on a TFT array substrate in an embodiment of a liquid crystal device.
[0036]
In FIG. 1, a plurality of liquid crystal devices 10 are arranged in a matrix on a TFT array substrate made of, for example, a quartz substrate, hard glass, a silicon substrate, or the like, and a plurality of pixel electrodes 11 are arranged in the X direction. A data line 35 extending along the Y direction, a plurality of scanning lines 31 arranged in the Y direction, each extending along the X direction, and a data line 35 interposed between each data line 35 and the pixel electrode 11, respectively. And a plurality of TFTs 30 as an example of a pixel driving means for controlling the conduction state and the non-conduction state in accordance with the scanning signals supplied via the scanning lines 31, respectively. Although not shown, on the TFT array substrate, a capacitance line, which is a wiring for a storage capacitor, is formed substantially in parallel along the scanning line 31 or by using a lower part of the preceding scanning line. Have been.
[0037]
On the TFT array substrate, there are formed a sampling circuit 301 for sampling an image signal and supplying each to the plurality of data lines 35, a data line driving circuit 101, and a scanning line driving circuit 104.
[0038]
The data line driving circuit 101 includes a shift register circuit 401, and includes a reference clock signal CLX supplied from an external control circuit (not shown) and its inverted clock signal CLX. _INV , The sampling drive signals S1 to Sn are sequentially supplied to the sampling drive signal line 306 based on the start signal SPX and the like.
[0039]
The scanning line driving circuit 104 has substantially the same configuration as the data line driving circuit 101, includes a shift register circuit in the scanning line driving circuit 104, and includes a start signal SPY, a reference clock signal CLY, and its inverted clock signal CLY. _INV Based on the above, the scanning signals Y1 to Yp are applied to the scanning line 31 at predetermined timing in a pulsed manner in a line-sequential manner.
[0040]
The sampling circuit 301 includes switching elements SH1 to SHn each composed of a TFT for each data line 35. An image signal line 304 is electrically connected to source electrodes of the switching elements SH1 to SHn, and a sampling circuit drive signal line 306 is electrically connected to gate electrodes of the switching elements SH1 to SHn. Therefore, when the sampling circuit drive signals S1 to Sn are input from the data line drive circuit 101 via the sampling circuit drive signal line 306, an image supplied from an external control circuit (not shown) via the image signal line 304 is provided. The signals D1 to Dn are sampled and sequentially supplied to the data line 35. If the dot frequency of the image signal is high, the image signal VID may be phase-developed to reduce the frequency. Although there is no restriction on the number of phase expansions of the image signal, in the case of video display, since the signal lines are required for each of RGB, an external control circuit can be relatively easily configured by using a multiple of three. Needless to say, the image signal lines 304 are required at least for the number of phase expansions of the image signal.
[0041]
(First Embodiment of Drive Circuit)
Next, a first embodiment of the drive circuit in the liquid crystal device 10 of the present embodiment will be described with reference to FIGS. Note that, in the following description, a data line driving circuit is described as an example, but a configuration similar to that of the data line driving circuit can be applied to a scanning line driving circuit.
[0042]
As shown in FIG. 1, the data line driving circuit 101 includes a shift register 401, a buffer circuit 402, and a selection circuit 403 for removing a ghost.
[0043]
In this embodiment mode, the shift register 401 has a function of sequentially outputting output signals Q1 to Qn from each stage of the shift register 401 in the transfer direction from A to B shown in FIG. These output signals Q1 to Qn are supplied to the sampling circuit 301 as sampling circuit drive signals S1 to Sn via the selection circuit 403 or the buffer circuit 402.
[0044]
Next, a configuration example of the shift register 401 will be described with reference to FIGS.
[0045]
As shown in FIG. 2, each stage of the shift register 401 includes two clocked inverters 130 and 132 and one inverter 131. When the start signal SPX is supplied to the shift register 401 configured as described above as shown in FIG. 3, the start signal SPX becomes the first stage of the clocked inverter 130 at the rise of the clock signal CLX indicated by the timing t0. The falling edge of the clock signal CLX at the timing t1, that is, the inverted signal CLX _INV From the rising edge of the clock signal CLX, feedback is performed by the inverter 131 and the clocked inverter 132 to obtain a first-stage output signal Q1 which is a pulse signal having the same width as one cycle of the clock signal CLX as shown in FIG.
[0046]
Next, in the second stage, an inverted signal CLX of the clock signal CLX _INV At the rising edge of the clock signal CLX, the feedback is performed at the rising edge of the clock signal CLX, so that an output signal Q2 delayed by a half cycle of the clock signal CLX from the output signal Q1 is obtained.
[0047]
Thereafter, in each stage, the capture and feedback of the signal are performed one after another at a timing shifted by a half cycle of the clock signal CLX, and output signals Q1 to Qn sequentially shifted by a half cycle of the clock signal CLX are obtained.
[0048]
As described above, according to the shift register 401 of the present embodiment, the output signals Q1 to Qn of each output stage of the shift register 401 are transferred to the next stage while being shifted by a half cycle of the clock signal CLX. When the switching elements SH1 to SHn of the sampling circuit 301 are driven using the output signals Q1 to Qn, the image signals can be written to the data lines 35 in a line-sequential manner.
[0049]
In the present embodiment, a selection circuit 403 as shown in FIG. 1 is further provided. More specifically, a selection circuit including a three-input NAND circuit 404 is provided. Each of the three-input NAND circuits 404 receives an output signal of one output stage of the shift register circuit 401 and an enable signal ENB, and also receives an output signal of an output stage adjacent to the one output stage. Is configured. In the present embodiment, the valid period of the output signal of each output stage of the shift register circuit 401 is set such that the enable signal ENB is made valid within a period in which both output signals of the adjacent output stages are at a high level. The choice is made by With this configuration, the enable signal ENB can be commonly used for all the three-input NAND circuits 404 included in the selection circuit 403, and one enable signal line for supplying the enable signal ENB is provided. Only needs to be done. Therefore, it is easy to route the wiring on the substrate, and the selection circuit can be easily built in the substrate.
[0050]
Further, in the present embodiment, the pulse width of the enable signal ENB is set to be shorter than a half cycle of the clock signal CLK as shown in FIG. With this configuration, the sampling circuit drive signals S1 to Sn output via the selection circuit 403 and the buffer circuit 402 always have a margin of time tm with respect to the sampling circuit drive signals S1 to Sn of the adjacent stage. Therefore, even when the output signal is delayed in the shift register 401, the writing of the duplicated image signal due to the signal delay as in the related art does not occur. That is, if the output signals Q1 to Qn are supplied to the respective switching elements SH1 to SHn as they are, the adjacent switching elements SH1 to SHn are simultaneously turned on for a half cycle of the clock signal CLX, and the overlapping image signals are written. However, according to the present embodiment, such a problem can be avoided.
[0051]
As described above, according to the present embodiment, a selection circuit can be built in a substrate with a simple configuration while using a shift register with a simple configuration, and a ghost image can be reliably removed by the selection circuit. Therefore, it is possible to provide a liquid crystal device capable of displaying a high-quality image at low cost.
[0052]
(Embodiment of sampling circuit)
Next, an embodiment of the sampling circuit 301 to which the drive signals S1 to Sn shaped as described above are supplied will be described.
[0053]
FIG. 4 is a circuit diagram showing various TFTs forming the switching elements SH1 to SHn of the sampling circuit 301.
[0054]
As shown in FIG. 4A, the switching elements SH1 to SHn (see FIG. 1) of the sampling circuit 301 can be formed of, for example, an N-channel TFT 302a. Further, as shown in FIG. 4B, it may be composed of a P-channel TFT 302b, or as shown in FIG. 4C, a complementary TFT 302c composed of an N-channel TFT and a P-channel TFT. May be configured. 4 (1) to 4 (3), the image signal VID input via the image signal line 304 shown in FIG. 1 is input to each of the TFTs 302a to 302c as a source or drain voltage. The sampling circuit drive signals 306a and 306b input from the data line drive circuit 101 shown in FIG. 1 via the sampling circuit drive signal line 306 are input to the TFTs 302a to 302c as gate voltages.
[0055]
In the sampling circuit 301, a sampling circuit drive signal 306a applied as a gate voltage to the N-channel TFT 302a via the sampling circuit drive signal line 306, and a P-channel TFT 302b via the sampling circuit drive signal line 306. The sampling circuit drive signal 306b applied as a gate voltage is a mutually inverted signal. Therefore, when the sampling circuit 301 is constituted by the complementary TFTs 302c, at least two or more sampling circuit drive signal lines 306 for sampling circuit drive signals which are inverted signals are required.
[0056]
(Second embodiment of drive circuit)
Next, a second embodiment of the drive circuit of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description is omitted.
[0057]
This embodiment is different from the first embodiment in that a bidirectional shift register 405 is used as a shift register of the data line driving circuit 101.
[0058]
In the bidirectional shift register 405, as shown in FIGS. 5 and 6, all the shift registers are constituted by clocked inverters.
[0059]
In this case, although not shown, the scanning line driving circuit 104 can also be configured to include the same bidirectional shift register and buffer circuit as the data line driving circuit 101.
[0060]
As shown in FIG. 5, the bidirectional shift register 405 is configured such that all stages of the shift register described in the first embodiment are configured by clocked inverters, and each of the shift registers described in the first embodiment. One clocked inverter is further added to the stage, and each stage is constituted by a total of four clocked inverters 130, 132, 133, and 134. Then, the clock signal CLX and its inverted clock signal CLX _INV Are input to the clocked inverters 133 and 134 other than the clocked inverters 130 and 132 for inputting the transfer direction control signal DX and the inverted transfer direction control signal DX, respectively. _INV Enter
[0061]
In such a configuration, when the transfer direction control signal DX is a high level signal, the transfer is performed in the direction from A to B, as in the shift register 401 of the first embodiment. The timing chart at this time is as shown in FIG. However, an inverted signal DX of the transfer direction control signal DX _INV Are high-level signals, the output signals Qn to Q1 are transferred in the direction from B to A. The timing chart at this time is as shown in FIG. The output signal transfer mechanism in each transfer direction is the same as that of the shift register 401 described in the first embodiment.
[0062]
Even when such a bidirectional shift register 405 is used as the shift register, the configuration of the selection circuit 403 and the configuration of the enable signal ENB can be applied as in the first embodiment.
[0063]
That is, since the enable signal ENB is a signal commonly input to each of the three-input NAND circuits 404 of the selection circuit 403, as shown in FIG. Even when the output signals are transferred in the order of the output signal Qn-1 of the stage and the output signal Qn-2 of the (n-2) th stage, each output signal is output during a period in which the output signals of the adjacent output stages are both at the high level. The valid period of the signal can be selected, and the sampling circuit driving signals Sn to S1 having a margin of the period tm are output.
[0064]
As described above, it is not necessary to invert the polarity of the signal in accordance with the transfer direction, and the sampling circuit drive signal transferred bidirectionally can be generated by one system of the enable signal ENB, which is advantageous in wiring routing. Thus, the drive circuit can be easily built on the substrate.
[0065]
When the above-described bidirectional shift register 405 is used in a liquid crystal device as a light valve of a liquid crystal projector, three colorless liquid crystal devices (that is, no color filters are formed) are used for each of RGB. A double-plate system can be adopted, and the display screen is brightened to obtain high-quality image quality. According to this double-plate system, three-color lights separately modulated by three liquid crystal devices are combined into one projection light by a prism or a dichroic mirror, and then projected on a screen. In this way, when combined with a prism or the like, as shown in FIG. 7, the G light is compared with the R light and the B light reflected by the prism 502 after being modulated by the three light valves 500R, 500G and 500B for RGB. Is not reflected by the prism 502. That is, the number of times of light inversion is reduced once for G light. This phenomenon is, of course, the same even if the optical system is configured so that the R light or the B light is not reflected by the prism instead of the G light, and the same applies to the case where three-color light is combined using a dichroic mirror or the like. Happens. Therefore, in such a case, it is necessary to turn the image signal for the G light up and down in some form.
[0066]
Therefore, if a liquid crystal device having a bidirectional shift register as in the present embodiment is used, the image signal can be turned right and left, and the double-panel liquid crystal projector as described above can be configured.
[0067]
The liquid crystal projector having the light valve includes a single-panel system using only one colored liquid crystal device (that is, a color filter formed on a counter substrate). If the scanning line driving circuit 104 is also constituted by the bidirectional shift register 405, the image signal can be turned upside down, left and right, and such a single-panel type liquid crystal projector or the above-mentioned double-panel type liquid crystal projector can be used. It can be configured so that it can be used as a floor-standing type that is normally installed on the floor, or as a ceiling-hanging type that is installed upside down on the ceiling. In addition, a liquid crystal monitor, which is a single-panel type liquid crystal device, such as a liquid crystal monitor of a portable video camera, can be turned over at a fulcrum, for example, on a fulcrum according to the shooting posture of the user. Is also possible. Further, even in a liquid crystal monitor capable of such display, deterioration of display quality such as ghost can be reliably prevented.
[0068]
(Third Embodiment of Drive Circuit)
Next, a third embodiment of the drive circuit of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description is omitted.
[0069]
This embodiment is different from the first embodiment in that the selection circuit 403 is constituted by a three-input NOR circuit 406 as shown in FIG.
[0070]
When the three-input NOR circuit 406 is used, the start signal SPX and the enable signal ENB need to be set to low active. Accordingly, the output stage of the three-input NOR circuit 406 has a relation with the buffer circuit 402. Thus, an inverter circuit 407 is required. That is, this means that an OR circuit is configured.
[0071]
In such a configuration, as shown in FIG. 9, when all of the output signals Q1 to Qn of the shift register 401 and the enable signal ENB become low level signals, the output of the three-input NOR circuit 406 becomes high level, This output is inverted by the inverter 407 and supplied to the sampling circuit 301 via the buffer circuit 402.
[0072]
Also in the present embodiment, it is possible to reliably prevent display quality degradation such as a ghost without complicating the wiring.
[0073]
(Fourth embodiment of drive circuit)
Next, a fourth embodiment of the drive circuit of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description is omitted.
[0074]
In the present embodiment, as shown in FIG. 10, a display information processing circuit (external IC) applies, for example, a phase-developing image signal VIDEO, which is output as a serial signal, to parallel image signals VID <b> 1 to VID <b> 6. This is an application of the present invention.
[0075]
Also in the present embodiment, as shown in FIG. 11, the waveform is adjusted by using a single external enable signal ENB using a selection circuit 403 having the same configuration as that described in the first embodiment. Configured.
[0076]
With this configuration, even when the phase expansion is performed, as shown in FIG. 12, even when the sampling circuit drive signals S1 to Sm are delayed, it is ensured that the sampling circuit drive signals S1 to Sm overlap. Ghost image as described in the related art can be reliably prevented.
[0077]
Therefore, by configuring to perform phase expansion, it is possible to reduce the driving frequency of the shift register even in a high-speed display mode such as XGA or EWS, and not only can the load on the external control circuit be reduced. Thus, high-quality image display without a ghost image can be performed.
[0078]
Further, when the driving frequency of the shift register is reduced, not only the current consumption can be reduced, but also the life of the TFT constituting the shift register can be extended, and a highly reliable liquid crystal device can be provided. it can.
[0079]
The number of phase expansions and the number of sampling circuits driven at a time need not be the same. That is, even when the number of sampling circuits to be driven at one time is reduced and the output period of the sampling circuit drive signal is shortened, good display can be performed if the driving performance of the transistors included in the sampling circuit is good. .
[0080]
(Fifth Embodiment of Drive Circuit)
Next, a fifth embodiment of the drive circuit of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description is omitted.
[0081]
This embodiment is an example in which a bidirectional shift register is configured using a transmission gate.
[0082]
The bidirectional shift register 405 shown in FIG. 13 includes a transfer direction control signal DX and an inverted signal DX. _INV A transfer direction control unit whose transfer direction is fixed in accordance with the clock signal CLX and the inverted signal CLX _INV And a feedback unit configured to capture a signal based on the clocked inverters 130 and 131.
[0083]
Further, the bidirectional shift register 405 shown in FIG. 14 is an example in which not only the transfer direction control unit but also a signal capturing unit and a feedback unit are configured by the transmission gate 410.
[0084]
The transmission gate 410 has an N-channel TFT and a P-channel TFT according to a potential difference between a direction control signal DX or a clock signal CLX applied to a gate electrode and a transfer signal applied to an input electrode or an output electrode of the transfer signal. Do not need to be supplied with the positive power supply VDD and the negative power supply VSS unlike the clocked inverter. Therefore, it is not necessary to route these power supply patterns, the interval between adjacent stages of the bidirectional shift register can be narrowed as compared with the related art, and the size of the liquid crystal device can be reduced.
[0085]
Further, as shown in FIG. 14, the bidirectional shift register 405 is entirely composed of the transmission gate 410, and the selection circuit 403 for removing a ghost according to the present invention further reduces the size of the liquid crystal device. It is possible to do.
[0086]
(Sixth embodiment of drive circuit)
Next, a sixth embodiment of the drive circuit of the present invention will be described with reference to FIG. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description is omitted.
[0087]
This embodiment shows another configuration example of the buffer circuit 402 and the sampling circuit 301.
[0088]
For example, as shown in FIG. 15A, this is an example in which the inverters of the buffer circuit 402 are stacked in multiple stages. With such a configuration, signal deterioration can be reliably prevented, and the sampling circuit 301 can be driven more accurately.
[0089]
Further, as shown in FIG. 15B, this is an example in which the sampling circuit 301 is configured by a transmission gate 410 having a complementary TFT structure including a P-channel TFT and an N-channel TFT. In this case, since it is necessary to input a signal of both positive and negative polarities to the transmission gate 410, an inverted signal is generated by an inverter in the buffer circuit 402. When an inverted signal is generated by the inverter, a signal delay occurs. Therefore, as shown in FIG. 15B, a bistable circuit 411 having a positive feedback unit is provided to eliminate the signal delay. You can do it. With such a configuration, even when the transistor characteristics are slightly deteriorated, more reliable operation can be guaranteed, and data line drive control can be performed at accurate timing.
[0090]
The embodiments of the driving circuits have been described above. However, the bidirectional shift register, the sampling circuit, or the scanning line driving circuit of the data line driving circuit can be formed by the same thin film forming process as that of the TFT 30 in the pixel region. It is possible and advantageous in manufacturing.
[0091]
In each of the above-described embodiments, a case has been described where an external control circuit that outputs a clock signal, an image signal, or the like is provided outside the liquid crystal device with respect to the data line driving circuit and the scanning line driving circuit. The present invention is not limited to this, and the control circuit may be provided in the liquid crystal device.
[0092]
(Other components of the liquid crystal device 10)
Further, the liquid crystal device 10 of the present embodiment as described above includes the following units.
[0093]
16 and 17, on the TFT array substrate 1, a screen display area defined by a plurality of pixel electrodes 11 (that is, an area of the liquid crystal device where an image is actually displayed due to a change in the alignment state of the liquid crystal layer 50). A seal member 52 made of a photocurable resin is provided along the screen display area as an example of a seal member that surrounds the liquid crystal layer 50 by bonding the two substrates together around (). A light-shielding peripheral partition 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.
[0094]
When the TFT array substrate 1 is put in a light-shielding case having an opening corresponding to the screen display area later, the peripheral display 53 is formed by an edge of the opening of the case due to a manufacturing error or the like. Formed from a strip-shaped light-shielding material having a width of at least 500 μm or more around the screen display area so as not to be hidden by, for example, to allow a shift of about several hundred μm with respect to the case of the TFT array substrate 1. It was done. Such a light-shielding peripheral partition 53 is formed on the counter substrate 2 by, for example, sputtering, photolithography, and etching using a metal material such as Cr (chromium) or Ni (nickel). Alternatively, it is formed from a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist. Needless to say, the light-shielding peripheral partition 53 may be provided on the TFT array substrate 1. Further, if the sampling circuit 301 is provided below the peripheral partition 53, the area occupied by the data line driving circuit 101 can be reduced, and thus there is an advantage that the size of the liquid crystal device 10 can be reduced.
[0095]
A data line driving circuit 101 and a mounting terminal 102 are provided along the lower side of the screen display area in a region outside the sealing material 52, and a scanning line driving circuit 104 is provided along two left and right sides of the screen display area. It is provided on both sides of the screen display area. Here, when the scanning signal delay of the scanning line 31 does not matter, the scanning line driving circuit 104 may be formed on only one side of the scanning line 103. Further, a plurality of wires 105 are provided on the upper side of the screen display area. At least one corner of the opposing substrate 2 is provided with an upper / lower conducting member 106 for establishing electric conduction between the TFT array substrate 1 and the opposing substrate 2. The opposite substrate 2 having substantially the same contour as the sealing material 52 is fixed to the TFT array substrate 1 by the sealing material 52.
[0096]
Since the liquid crystal device 10 described above is applied to a color liquid crystal projector, three liquid crystal devices 10 are respectively used as light valves for RGB, and each panel is separated via a dichroic mirror for RGB color separation. The light of each color is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal device 10 as well, an RGB color filter may be formed on the counter substrate 2 together with the protective film in a predetermined region facing the pixel electrode 11 where the light shielding film 23 is not formed. In this way, the liquid crystal device of the present embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector.
[0097]
Further, the switching element of the liquid crystal device 10 may be a normal stagger type or coplanar type polysilicon TFT, and the present embodiment is applicable to other types of TFTs such as an inverse stagger type TFT and an amorphous silicon TFT. It is valid.
[0098]
The data line driving circuit 101 and the scanning line driving circuit 104 are provided on the driving LSI mounted on, for example, TAB (tape automated bonding substrate) instead of being provided on the TFT array substrate 1. The connection may be made electrically and mechanically via an anisotropic conductive film provided in the peripheral portion.
[0099]
(Electronics)
Next, an embodiment of an electronic apparatus including the liquid crystal device 10 described in detail above will be described with reference to FIGS.
[0100]
First, FIG. 18 shows a schematic configuration of an electronic apparatus including the liquid crystal device 10 as described above.
[0101]
In FIG. 18, an electronic apparatus includes a display information output source 1000, a display drive circuit 1004 including the above-described external display information processing circuit 1002, the above-described scan line drive circuit 104 and the data line drive circuit 101, a liquid crystal device 10, a clock generation circuit. 1008 and a power supply circuit 1010. The display information output source 1000 is configured to include a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit for tuning and outputting a television signal, and the like. Display information such as an image signal in a predetermined format is output to the display information processing circuit 1002 based on the clock signal. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. Digital signals are sequentially generated from the input display information based on the display information and output to the display drive circuit 1004 together with the clock signal CLK. The display driving circuit 1004 drives the liquid crystal device 10 by the scanning line driving circuit 104 and the data line driving circuit 101 by the driving method described above. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the display drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 10, and in addition, the display information processing circuit 1002 may be mounted.
[0102]
As the electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 19, a personal computer (PC) and an engineering workstation (EWS) for multimedia shown in FIG. 20, or a mobile phone, a word processor, a television, a viewfinder type or Examples include a monitor direct-view video table recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.
[0103]
19 to 21 show specific examples of the electronic device configured as described above.
[0104]
In FIG. 19, a liquid crystal projector 1100, which is an example of an electronic apparatus, is a projection type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113, 1114, reflection mirrors 1115, 1116, 1117, an incident lens 1118, a relay lens 1119, It comprises an emission lens 1120, liquid crystal light valves 1122, 1123, 1124, a cross dichroic prism 1125, and a projection lens 1126. The liquid crystal light valves 1122, 1123, and 1124 are prepared by preparing three liquid crystal display modules each including the liquid crystal device 10 in which the above-described drive circuit 1004 is mounted on a TFT array substrate, and using each of them as a liquid crystal light valve. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects light from the lamp 1111.
[0105]
In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits red light of the white light flux from the light source 1110 and reflects blue light and green light. . The transmitted red light is reflected by the reflection mirror 1117 and is incident on the liquid crystal light valve 1122 for red light. On the other hand, among the color lights reflected by the dichroic mirror 1113, green light is reflected by the dichroic mirror 1114 that reflects green light, and is incident on the liquid crystal light valve 1123 for green light. The blue light also passes through the second dichroic mirror 1114. For blue light, in order to prevent light loss due to a long optical path, light guiding means 1121 composed of a relay lens system including an entrance lens 1118, a relay lens 1119, and an exit lens 1120 is provided. The light enters the liquid crystal light valve for light 1124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. This prism is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The synthesized light is projected on a screen 1127 by a projection lens 1126 which is a projection optical system, and an image is enlarged and displayed.
[0106]
In FIG. 20, a laptop personal computer 1200 as another example of the electronic apparatus includes a liquid crystal display 1206 in which the above-described liquid crystal device 10 is provided in a top cover case, a CPU, a memory, a modem, and the like. And a main body 1204 in which the main body 1202 is incorporated.
[0107]
Alternatively, as shown in FIG. 21, an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed on one of two transparent substrates 1304a and 1304b constituting the liquid crystal device 10. A TCP (Tape Carrier Package) 1320 can be connected to produce, sell, and use a liquid crystal device as one component of an electronic device.
[0108]
As described above, in addition to the electronic devices described with reference to FIGS. 19 to 21, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, a workstation, and a mobile phone A telephone, a videophone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.
[0109]
It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the various liquid crystal devices described above, but is also applicable to electroluminescence and plasma display devices.
[0110]
As described above, according to the present embodiment, various electronic devices including a liquid crystal device capable of displaying an excellent image can be realized by reliably preventing deterioration of display quality such as ghost.
[0111]
【The invention's effect】
As described above, according to the present invention, the selection means for controlling the selection period of the drive signal to the sampling circuit includes the output line of one output stage of the shift register and the output stage adjacent to the one output stage. Since the output line and the control signal line common to the respective selection means are constituted by the three-input logic circuit connected to the input terminal, the wiring can be routed easily and can be easily provided in the electro-optical device. In addition, a sufficient sampling period is ensured for each data line to enable reliable image signal writing, and to prevent generation of a ghost image without fail. An operable driving circuit of an electro-optical device, an electro-optical device, and an electronic device can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram of various wirings, peripheral circuits, and the like formed on a TFT array substrate in a first embodiment of a liquid crystal device.
FIG. 2 is a circuit diagram of a shift register included in the data line driving circuit of FIG.
FIG. 3 is a timing chart showing operations of a data line driving circuit and a sampling circuit in the liquid crystal device of FIG.
4 is a circuit diagram of a TFT constituting a sampling circuit provided in the liquid crystal device of FIG.
FIG. 5 is a block diagram illustrating a configuration of a data line driving circuit according to a second embodiment of the present invention.
FIG. 6 is a timing chart illustrating operations of a data line driving circuit and a sampling circuit according to a second embodiment of the present invention.
FIG. 7 is a conceptual diagram illustrating a prism optical system that combines RGB three-color lights of a liquid crystal projector using a liquid crystal device according to a second embodiment of the present invention.
FIG. 8 is a block diagram of a data line driving circuit according to a third embodiment of the present invention.
FIG. 9 is a timing chart illustrating operations of a data line driving circuit and a sampling circuit according to a third embodiment of the present invention.
FIG. 10 is a block diagram illustrating a mode of an image signal supplied to a liquid crystal device according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram of a shift register and a sampling circuit of a data line driving circuit according to a fourth embodiment of the present invention.
FIG. 12 is a timing chart illustrating operations of a data line driving circuit and a sampling circuit according to a fourth embodiment of the present invention.
FIG. 13 is a circuit diagram of a shift register and a sampling circuit of a data line driving circuit according to a fifth embodiment of the present invention.
FIG. 14 is a circuit diagram of another example of the shift register and the sampling circuit of the data line driving circuit according to the fifth embodiment of the present invention.
FIG. 15A is a circuit diagram of an example of a buffer circuit and a sampling circuit of a data line driving circuit according to a sixth embodiment of the present invention, and FIG. 15B is a data line driving circuit according to a sixth embodiment of the present invention; FIG. 4 is a circuit diagram of another example of the buffer circuit and the sampling circuit of FIG.
FIG. 16 is a plan view illustrating the overall configuration of the liquid crystal device of FIG. 1;
FIG. 17 is a cross-sectional view illustrating the overall configuration of the liquid crystal device of FIG.
FIG. 18 is a block diagram illustrating a schematic configuration of an electronic device according to an embodiment of the present invention.
FIG. 19 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.
FIG. 20 is a front view illustrating a personal computer as another example of the electronic apparatus.
FIG. 21 is a perspective view illustrating a liquid crystal device using TCP as an example of an electronic apparatus.
FIG. 22 is a circuit diagram of a data line driving circuit and a sampling circuit in a conventional liquid crystal device.
FIG. 23 is a timing chart showing operations of a data line driving circuit and a sampling circuit in the liquid crystal device of FIG.
FIG. 24 is a diagram illustrating a ghost image generated in the data line driving circuit and the sampling circuit of FIG. 22;
FIG. 25 is a timing chart showing the operation of a conventional data line driving circuit and a conventional sampling circuit in the case where image signals are expanded into multiple phases and sampling circuits are individually driven.
FIG. 26 is a circuit diagram of a conventional data line driving circuit and a conventional sampling circuit in which an image signal is expanded into six phases and a plurality of sampling circuits are driven at one time.
FIG. 27 is a timing chart showing the operation of the data line driving circuit and the sampling circuit of FIG. 26;
FIG. 28 is a diagram showing a ghost image generated in a liquid crystal device using the data line driving circuit and the sampling circuit of FIG. 26;
FIG. 29 is a circuit diagram of a conventional data line driving circuit and a conventional sampling circuit when an image signal is developed into 12 phases and a plurality of sampling circuits are driven at a time.
30 is a diagram illustrating a ghost image generated when the data line driving circuit and the sampling circuit in FIG. 29 are used.
[Explanation of symbols]
1: TFT array substrate
2: Counter substrate
10. Liquid crystal device
11: Pixel electrode
21 ... Common electrode
23 ... Light shielding film
30 ... TFT
31 ... Scanning line
35 ... data line
50 ... Liquid crystal layer
52 ... Seal material
53 ... Close-up
101: Data line drive circuit
102 mounting terminals
130, 132, 133, 134 ... clocked inverter
301 ... Sampling circuit
304: image signal line
306 ... Sampling circuit drive signal line
401 shift register
402 ... Buffer circuit
403 ... Selection circuit
404 ... 3-input NAND circuit
405: bidirectional shift register
406 ... 3-input NOR circuit
410 ... Transmission gate

Claims (7)

A driving circuit for an electro-optical device including a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, and switching means connected to each of the data lines and each of the scanning lines. So,
A sampling circuit that samples the image signal and supplies the image signal to the data line;
A shift register for supplying a drive signal to the sampling circuit;
A selector provided corresponding to each output stage of the shift register and controlling a selection period of the drive signal to the sampling circuit;
In each of the selectors, an output of one output stage of the shift register, an output of an output stage adjacent to one output stage, and an output from a control signal line common to the selectors are supplied to input terminals. Consisting of a three-input logic circuit,
A driving circuit for an electro-optical device, comprising: 2. The driving circuit according to claim 1, wherein the selection unit includes a three-input NAND circuit at each stage. 2. The driving circuit according to claim 1, wherein the selection unit includes a three-input OR circuit in each stage. 2. The shift register according to claim 1, wherein the shift register further includes a transfer direction control unit that limits a transfer direction of a signal to a predetermined direction based on a direction control signal supplied from the outside. A driving circuit for an electro-optical device according to claim 3. The sampling circuit is connected to a supply line for an image signal output in a phase-expanded manner, and the selection unit is connected to supply the drive signal to a plurality of stages of the sampling circuit at one time. The driving circuit for an electro-optical device according to claim 1, wherein 6. A driving circuit for an electro-optical device according to claim 1, further comprising: an image display unit having an electro-optical member for reversibly changing an optical characteristic by an electric signal in a pixel portion. An electro-optical device, comprising: An electronic apparatus comprising the electro-optical device according to claim 6.

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